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TOMOYO Linux Cross Reference
Linux/arch/powerpc/sysdev/mpic_u3msi.c

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  1 /*
  2  * Copyright 2006, Segher Boessenkool, IBM Corporation.
  3  * Copyright 2006-2007, Michael Ellerman, IBM Corporation.
  4  *
  5  * This program is free software; you can redistribute it and/or
  6  * modify it under the terms of the GNU General Public License
  7  * as published by the Free Software Foundation; version 2 of the
  8  * License.
  9  *
 10  */
 11 
 12 #include <linux/irq.h>
 13 #include <linux/msi.h>
 14 #include <asm/mpic.h>
 15 #include <asm/prom.h>
 16 #include <asm/hw_irq.h>
 17 #include <asm/ppc-pci.h>
 18 #include <asm/msi_bitmap.h>
 19 
 20 #include "mpic.h"
 21 
 22 /* A bit ugly, can we get this from the pci_dev somehow? */
 23 static struct mpic *msi_mpic;
 24 
 25 static void mpic_u3msi_mask_irq(struct irq_data *data)
 26 {
 27         pci_msi_mask_irq(data);
 28         mpic_mask_irq(data);
 29 }
 30 
 31 static void mpic_u3msi_unmask_irq(struct irq_data *data)
 32 {
 33         mpic_unmask_irq(data);
 34         pci_msi_unmask_irq(data);
 35 }
 36 
 37 static struct irq_chip mpic_u3msi_chip = {
 38         .irq_shutdown           = mpic_u3msi_mask_irq,
 39         .irq_mask               = mpic_u3msi_mask_irq,
 40         .irq_unmask             = mpic_u3msi_unmask_irq,
 41         .irq_eoi                = mpic_end_irq,
 42         .irq_set_type           = mpic_set_irq_type,
 43         .irq_set_affinity       = mpic_set_affinity,
 44         .name                   = "MPIC-U3MSI",
 45 };
 46 
 47 static u64 read_ht_magic_addr(struct pci_dev *pdev, unsigned int pos)
 48 {
 49         u8 flags;
 50         u32 tmp;
 51         u64 addr;
 52 
 53         pci_read_config_byte(pdev, pos + HT_MSI_FLAGS, &flags);
 54 
 55         if (flags & HT_MSI_FLAGS_FIXED)
 56                 return HT_MSI_FIXED_ADDR;
 57 
 58         pci_read_config_dword(pdev, pos + HT_MSI_ADDR_LO, &tmp);
 59         addr = tmp & HT_MSI_ADDR_LO_MASK;
 60         pci_read_config_dword(pdev, pos + HT_MSI_ADDR_HI, &tmp);
 61         addr = addr | ((u64)tmp << 32);
 62 
 63         return addr;
 64 }
 65 
 66 static u64 find_ht_magic_addr(struct pci_dev *pdev, unsigned int hwirq)
 67 {
 68         struct pci_bus *bus;
 69         unsigned int pos;
 70 
 71         for (bus = pdev->bus; bus && bus->self; bus = bus->parent) {
 72                 pos = pci_find_ht_capability(bus->self, HT_CAPTYPE_MSI_MAPPING);
 73                 if (pos)
 74                         return read_ht_magic_addr(bus->self, pos);
 75         }
 76 
 77         return 0;
 78 }
 79 
 80 static u64 find_u4_magic_addr(struct pci_dev *pdev, unsigned int hwirq)
 81 {
 82         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
 83 
 84         /* U4 PCIe MSIs need to write to the special register in
 85          * the bridge that generates interrupts. There should be
 86          * theorically a register at 0xf8005000 where you just write
 87          * the MSI number and that triggers the right interrupt, but
 88          * unfortunately, this is busted in HW, the bridge endian swaps
 89          * the value and hits the wrong nibble in the register.
 90          *
 91          * So instead we use another register set which is used normally
 92          * for converting HT interrupts to MPIC interrupts, which decodes
 93          * the interrupt number as part of the low address bits
 94          *
 95          * This will not work if we ever use more than one legacy MSI in
 96          * a block but we never do. For one MSI or multiple MSI-X where
 97          * each interrupt address can be specified separately, it works
 98          * just fine.
 99          */
100         if (of_device_is_compatible(hose->dn, "u4-pcie") ||
101             of_device_is_compatible(hose->dn, "U4-pcie"))
102                 return 0xf8004000 | (hwirq << 4);
103 
104         return 0;
105 }
106 
107 static void u3msi_teardown_msi_irqs(struct pci_dev *pdev)
108 {
109         struct msi_desc *entry;
110         irq_hw_number_t hwirq;
111 
112         list_for_each_entry(entry, &pdev->msi_list, list) {
113                 if (entry->irq == NO_IRQ)
114                         continue;
115 
116                 hwirq = virq_to_hw(entry->irq);
117                 irq_set_msi_desc(entry->irq, NULL);
118                 irq_dispose_mapping(entry->irq);
119                 msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap, hwirq, 1);
120         }
121 
122         return;
123 }
124 
125 static int u3msi_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
126 {
127         unsigned int virq;
128         struct msi_desc *entry;
129         struct msi_msg msg;
130         u64 addr;
131         int hwirq;
132 
133         if (type == PCI_CAP_ID_MSIX)
134                 pr_debug("u3msi: MSI-X untested, trying anyway.\n");
135 
136         /* If we can't find a magic address then MSI ain't gonna work */
137         if (find_ht_magic_addr(pdev, 0) == 0 &&
138             find_u4_magic_addr(pdev, 0) == 0) {
139                 pr_debug("u3msi: no magic address found for %s\n",
140                          pci_name(pdev));
141                 return -ENXIO;
142         }
143 
144         list_for_each_entry(entry, &pdev->msi_list, list) {
145                 hwirq = msi_bitmap_alloc_hwirqs(&msi_mpic->msi_bitmap, 1);
146                 if (hwirq < 0) {
147                         pr_debug("u3msi: failed allocating hwirq\n");
148                         return hwirq;
149                 }
150 
151                 addr = find_ht_magic_addr(pdev, hwirq);
152                 if (addr == 0)
153                         addr = find_u4_magic_addr(pdev, hwirq);
154                 msg.address_lo = addr & 0xFFFFFFFF;
155                 msg.address_hi = addr >> 32;
156 
157                 virq = irq_create_mapping(msi_mpic->irqhost, hwirq);
158                 if (virq == NO_IRQ) {
159                         pr_debug("u3msi: failed mapping hwirq 0x%x\n", hwirq);
160                         msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap, hwirq, 1);
161                         return -ENOSPC;
162                 }
163 
164                 irq_set_msi_desc(virq, entry);
165                 irq_set_chip(virq, &mpic_u3msi_chip);
166                 irq_set_irq_type(virq, IRQ_TYPE_EDGE_RISING);
167 
168                 pr_debug("u3msi: allocated virq 0x%x (hw 0x%x) addr 0x%lx\n",
169                           virq, hwirq, (unsigned long)addr);
170 
171                 printk("u3msi: allocated virq 0x%x (hw 0x%x) addr 0x%lx\n",
172                           virq, hwirq, (unsigned long)addr);
173                 msg.data = hwirq;
174                 pci_write_msi_msg(virq, &msg);
175 
176                 hwirq++;
177         }
178 
179         return 0;
180 }
181 
182 int mpic_u3msi_init(struct mpic *mpic)
183 {
184         int rc;
185 
186         rc = mpic_msi_init_allocator(mpic);
187         if (rc) {
188                 pr_debug("u3msi: Error allocating bitmap!\n");
189                 return rc;
190         }
191 
192         pr_debug("u3msi: Registering MPIC U3 MSI callbacks.\n");
193 
194         BUG_ON(msi_mpic);
195         msi_mpic = mpic;
196 
197         WARN_ON(ppc_md.setup_msi_irqs);
198         ppc_md.setup_msi_irqs = u3msi_setup_msi_irqs;
199         ppc_md.teardown_msi_irqs = u3msi_teardown_msi_irqs;
200 
201         return 0;
202 }
203 

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