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TOMOYO Linux Cross Reference
Linux/arch/ppc/8xx_io/fec.c

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  1 /*
  2  * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
  3  * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
  4  *
  5  * This version of the driver is specific to the FADS implementation,
  6  * since the board contains control registers external to the processor
  7  * for the control of the LevelOne LXT970 transceiver.  The MPC860T manual
  8  * describes connections using the internal parallel port I/O, which
  9  * is basically all of Port D.
 10  *
 11  * Includes support for the following PHYs: QS6612, LXT970, LXT971/2.
 12  *
 13  * Right now, I am very wasteful with the buffers.  I allocate memory
 14  * pages and then divide them into 2K frame buffers.  This way I know I
 15  * have buffers large enough to hold one frame within one buffer descriptor.
 16  * Once I get this working, I will use 64 or 128 byte CPM buffers, which
 17  * will be much more memory efficient and will easily handle lots of
 18  * small packets.
 19  *
 20  * Much better multiple PHY support by Magnus Damm.
 21  * Copyright (c) 2000 Ericsson Radio Systems AB.
 22  *
 23  * Make use of MII for PHY control configurable.
 24  * Some fixes.
 25  * Copyright (c) 2000-2002 Wolfgang Denk, DENX Software Engineering.
 26  *
 27  * Support for AMD AM79C874 added.
 28  * Thomas Lange, thomas@corelatus.com
 29  */
 30 
 31 #include <linux/config.h>
 32 #include <linux/kernel.h>
 33 #include <linux/sched.h>
 34 #include <linux/string.h>
 35 #include <linux/ptrace.h>
 36 #include <linux/errno.h>
 37 #include <linux/ioport.h>
 38 #include <linux/slab.h>
 39 #include <linux/interrupt.h>
 40 #include <linux/pci.h>
 41 #include <linux/init.h>
 42 #include <linux/delay.h>
 43 #include <linux/netdevice.h>
 44 #include <linux/etherdevice.h>
 45 #include <linux/skbuff.h>
 46 #include <linux/spinlock.h>
 47 #ifdef CONFIG_FEC_PACKETHOOK
 48 #include <linux/pkthook.h>
 49 #endif
 50 
 51 #include <asm/8xx_immap.h>
 52 #include <asm/pgtable.h>
 53 #include <asm/mpc8xx.h>
 54 #include <asm/irq.h>
 55 #include <asm/bitops.h>
 56 #include <asm/uaccess.h>
 57 #include <asm/commproc.h>
 58 
 59 #ifdef  CONFIG_USE_MDIO
 60 /* Forward declarations of some structures to support different PHYs
 61 */
 62 
 63 typedef struct {
 64         uint mii_data;
 65         void (*funct)(uint mii_reg, struct net_device *dev);
 66 } phy_cmd_t;
 67 
 68 typedef struct {
 69         uint id;
 70         char *name;
 71 
 72         const phy_cmd_t *config;
 73         const phy_cmd_t *startup;
 74         const phy_cmd_t *ack_int;
 75         const phy_cmd_t *shutdown;
 76 } phy_info_t;
 77 #endif  /* CONFIG_USE_MDIO */
 78 
 79 /* The number of Tx and Rx buffers.  These are allocated from the page
 80  * pool.  The code may assume these are power of two, so it is best
 81  * to keep them that size.
 82  * We don't need to allocate pages for the transmitter.  We just use
 83  * the skbuffer directly.
 84  */
 85 #ifdef CONFIG_ENET_BIG_BUFFERS
 86 #define FEC_ENET_RX_PAGES       16
 87 #define FEC_ENET_RX_FRSIZE      2048
 88 #define FEC_ENET_RX_FRPPG       (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
 89 #define RX_RING_SIZE            (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
 90 #define TX_RING_SIZE            16      /* Must be power of two */
 91 #define TX_RING_MOD_MASK        15      /*   for this to work */
 92 #else
 93 #define FEC_ENET_RX_PAGES       4
 94 #define FEC_ENET_RX_FRSIZE      2048
 95 #define FEC_ENET_RX_FRPPG       (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
 96 #define RX_RING_SIZE            (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
 97 #define TX_RING_SIZE            8       /* Must be power of two */
 98 #define TX_RING_MOD_MASK        7       /*   for this to work */
 99 #endif
100 
101 /* Interrupt events/masks.
102 */
103 #define FEC_ENET_HBERR  ((uint)0x80000000)      /* Heartbeat error */
104 #define FEC_ENET_BABR   ((uint)0x40000000)      /* Babbling receiver */
105 #define FEC_ENET_BABT   ((uint)0x20000000)      /* Babbling transmitter */
106 #define FEC_ENET_GRA    ((uint)0x10000000)      /* Graceful stop complete */
107 #define FEC_ENET_TXF    ((uint)0x08000000)      /* Full frame transmitted */
108 #define FEC_ENET_TXB    ((uint)0x04000000)      /* A buffer was transmitted */
109 #define FEC_ENET_RXF    ((uint)0x02000000)      /* Full frame received */
110 #define FEC_ENET_RXB    ((uint)0x01000000)      /* A buffer was received */
111 #define FEC_ENET_MII    ((uint)0x00800000)      /* MII interrupt */
112 #define FEC_ENET_EBERR  ((uint)0x00400000)      /* SDMA bus error */
113 
114 /*
115 */
116 #define FEC_ECNTRL_PINMUX       0x00000004
117 #define FEC_ECNTRL_ETHER_EN     0x00000002
118 #define FEC_ECNTRL_RESET        0x00000001
119 
120 #define FEC_RCNTRL_BC_REJ       0x00000010
121 #define FEC_RCNTRL_PROM         0x00000008
122 #define FEC_RCNTRL_MII_MODE     0x00000004
123 #define FEC_RCNTRL_DRT          0x00000002
124 #define FEC_RCNTRL_LOOP         0x00000001
125 
126 #define FEC_TCNTRL_FDEN         0x00000004
127 #define FEC_TCNTRL_HBC          0x00000002
128 #define FEC_TCNTRL_GTS          0x00000001
129 
130 /* Delay to wait for FEC reset command to complete (in us)
131 */
132 #define FEC_RESET_DELAY         50
133 
134 /* The FEC stores dest/src/type, data, and checksum for receive packets.
135  */
136 #define PKT_MAXBUF_SIZE         1518
137 #define PKT_MINBUF_SIZE         64
138 #define PKT_MAXBLR_SIZE         1520
139 
140 /* The FEC buffer descriptors track the ring buffers.  The rx_bd_base and
141  * tx_bd_base always point to the base of the buffer descriptors.  The
142  * cur_rx and cur_tx point to the currently available buffer.
143  * The dirty_tx tracks the current buffer that is being sent by the
144  * controller.  The cur_tx and dirty_tx are equal under both completely
145  * empty and completely full conditions.  The empty/ready indicator in
146  * the buffer descriptor determines the actual condition.
147  */
148 struct fec_enet_private {
149         /* The saved address of a sent-in-place packet/buffer, for skfree(). */
150         struct  sk_buff* tx_skbuff[TX_RING_SIZE];
151         ushort  skb_cur;
152         ushort  skb_dirty;
153 
154         /* CPM dual port RAM relative addresses.
155         */
156         cbd_t   *rx_bd_base;            /* Address of Rx and Tx buffers. */
157         cbd_t   *tx_bd_base;
158         cbd_t   *cur_rx, *cur_tx;               /* The next free ring entry */
159         cbd_t   *dirty_tx;      /* The ring entries to be free()ed. */
160 
161         /* Virtual addresses for the receive buffers because we can't
162          * do a __va() on them anymore.
163          */
164         unsigned char *rx_vaddr[RX_RING_SIZE];
165 
166         struct  net_device_stats stats;
167         uint    tx_full;
168         spinlock_t lock;
169 
170 #ifdef  CONFIG_USE_MDIO
171         uint    phy_id;
172         uint    phy_id_done;
173         uint    phy_status;
174         uint    phy_speed;
175         phy_info_t      *phy;
176         struct tq_struct phy_task;
177 
178         uint    sequence_done;
179 
180         uint    phy_addr;
181 #endif  /* CONFIG_USE_MDIO */
182 
183         int     link;
184         int     old_link;
185         int     full_duplex;
186 
187 #ifdef CONFIG_FEC_PACKETHOOK
188         unsigned long   ph_lock;
189         fec_ph_func     *ph_rxhandler;
190         fec_ph_func     *ph_txhandler;
191         __u16           ph_proto;
192         volatile __u32  *ph_regaddr;
193         void            *ph_priv;
194 #endif
195 };
196 
197 static int fec_enet_open(struct net_device *dev);
198 static int fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev);
199 #ifdef  CONFIG_USE_MDIO
200 static void fec_enet_mii(struct net_device *dev);
201 #endif  /* CONFIG_USE_MDIO */
202 static void fec_enet_interrupt(int irq, void * dev_id, struct pt_regs * regs);
203 #ifdef CONFIG_FEC_PACKETHOOK
204 static void  fec_enet_tx(struct net_device *dev, __u32 regval);
205 static void  fec_enet_rx(struct net_device *dev, __u32 regval);
206 #else
207 static void  fec_enet_tx(struct net_device *dev);
208 static void  fec_enet_rx(struct net_device *dev);
209 #endif
210 static int fec_enet_close(struct net_device *dev);
211 static struct net_device_stats *fec_enet_get_stats(struct net_device *dev);
212 static void set_multicast_list(struct net_device *dev);
213 static void fec_restart(struct net_device *dev, int duplex);
214 static void fec_stop(struct net_device *dev);
215 static  ushort  my_enet_addr[3];
216 
217 #ifdef  CONFIG_USE_MDIO
218 /* MII processing.  We keep this as simple as possible.  Requests are
219  * placed on the list (if there is room).  When the request is finished
220  * by the MII, an optional function may be called.
221  */
222 typedef struct mii_list {
223         uint    mii_regval;
224         void    (*mii_func)(uint val, struct net_device *dev);
225         struct  mii_list *mii_next;
226 } mii_list_t;
227 
228 #define         NMII    20
229 mii_list_t      mii_cmds[NMII];
230 mii_list_t      *mii_free;
231 mii_list_t      *mii_head;
232 mii_list_t      *mii_tail;
233 
234 static int      mii_queue(struct net_device *dev, int request,
235                                 void (*func)(uint, struct net_device *));
236 
237 /* Make MII read/write commands for the FEC.
238 */
239 #define mk_mii_read(REG)        (0x60020000 | ((REG & 0x1f) << 18))
240 #define mk_mii_write(REG, VAL)  (0x50020000 | ((REG & 0x1f) << 18) | \
241                                                 (VAL & 0xffff))
242 #define mk_mii_end      0
243 #endif  /* CONFIG_USE_MDIO */
244 
245 /* Transmitter timeout.
246 */
247 #define TX_TIMEOUT (2*HZ)
248 
249 #ifdef  CONFIG_USE_MDIO
250 /* Register definitions for the PHY.
251 */
252 
253 #define MII_REG_CR          0  /* Control Register                         */
254 #define MII_REG_SR          1  /* Status Register                          */
255 #define MII_REG_PHYIR1      2  /* PHY Identification Register 1            */
256 #define MII_REG_PHYIR2      3  /* PHY Identification Register 2            */
257 #define MII_REG_ANAR        4  /* A-N Advertisement Register               */
258 #define MII_REG_ANLPAR      5  /* A-N Link Partner Ability Register        */
259 #define MII_REG_ANER        6  /* A-N Expansion Register                   */
260 #define MII_REG_ANNPTR      7  /* A-N Next Page Transmit Register          */
261 #define MII_REG_ANLPRNPR    8  /* A-N Link Partner Received Next Page Reg. */
262 
263 /* values for phy_status */
264 
265 #define PHY_CONF_ANE    0x0001  /* 1 auto-negotiation enabled */
266 #define PHY_CONF_LOOP   0x0002  /* 1 loopback mode enabled */
267 #define PHY_CONF_SPMASK 0x00f0  /* mask for speed */
268 #define PHY_CONF_10HDX  0x0010  /* 10 Mbit half duplex supported */
269 #define PHY_CONF_10FDX  0x0020  /* 10 Mbit full duplex supported */
270 #define PHY_CONF_100HDX 0x0040  /* 100 Mbit half duplex supported */
271 #define PHY_CONF_100FDX 0x0080  /* 100 Mbit full duplex supported */
272 
273 #define PHY_STAT_LINK   0x0100  /* 1 up - 0 down */
274 #define PHY_STAT_FAULT  0x0200  /* 1 remote fault */
275 #define PHY_STAT_ANC    0x0400  /* 1 auto-negotiation complete  */
276 #define PHY_STAT_SPMASK 0xf000  /* mask for speed */
277 #define PHY_STAT_10HDX  0x1000  /* 10 Mbit half duplex selected */
278 #define PHY_STAT_10FDX  0x2000  /* 10 Mbit full duplex selected */
279 #define PHY_STAT_100HDX 0x4000  /* 100 Mbit half duplex selected */
280 #define PHY_STAT_100FDX 0x8000  /* 100 Mbit full duplex selected */
281 #endif  /* CONFIG_USE_MDIO */
282 
283 #ifdef CONFIG_FEC_PACKETHOOK
284 int
285 fec_register_ph(struct net_device *dev, fec_ph_func *rxfun, fec_ph_func *txfun,
286                 __u16 proto, volatile __u32 *regaddr, void *priv)
287 {
288         struct fec_enet_private *fep;
289         int retval = 0;
290 
291         fep = dev->priv;
292 
293         if (test_and_set_bit(0, (void*)&fep->ph_lock) != 0) {
294                 /* Someone is messing with the packet hook */
295                 return -EAGAIN;
296         }
297         if (fep->ph_rxhandler != NULL || fep->ph_txhandler != NULL) {
298                 retval = -EBUSY;
299                 goto out;
300         }
301         fep->ph_rxhandler = rxfun;
302         fep->ph_txhandler = txfun;
303         fep->ph_proto = proto;
304         fep->ph_regaddr = regaddr;
305         fep->ph_priv = priv;
306 
307         out:
308         fep->ph_lock = 0;
309 
310         return retval;
311 }
312 
313 
314 int
315 fec_unregister_ph(struct net_device *dev)
316 {
317         struct fec_enet_private *fep;
318         int retval = 0;
319 
320         fep = dev->priv;
321 
322         if (test_and_set_bit(0, (void*)&fep->ph_lock) != 0) {
323                 /* Someone is messing with the packet hook */
324                 return -EAGAIN;
325         }
326 
327         fep->ph_rxhandler = fep->ph_txhandler = NULL;
328         fep->ph_proto = 0;
329         fep->ph_regaddr = NULL;
330         fep->ph_priv = NULL;
331 
332         fep->ph_lock = 0;
333 
334         return retval;
335 }
336 
337 EXPORT_SYMBOL(fec_register_ph);
338 EXPORT_SYMBOL(fec_unregister_ph);
339 
340 #endif /* CONFIG_FEC_PACKETHOOK */
341 
342 static int
343 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
344 {
345         struct fec_enet_private *fep;
346         volatile fec_t  *fecp;
347         volatile cbd_t  *bdp;
348 
349         fep = dev->priv;
350         fecp = (volatile fec_t*)dev->base_addr;
351 
352         if (!fep->link) {
353                 /* Link is down or autonegotiation is in progress. */
354                 return 1;
355         }
356 
357         /* Fill in a Tx ring entry */
358         bdp = fep->cur_tx;
359 
360 #ifndef final_version
361         if (bdp->cbd_sc & BD_ENET_TX_READY) {
362                 /* Ooops.  All transmit buffers are full.  Bail out.
363                  * This should not happen, since dev->tbusy should be set.
364                  */
365                 printk("%s: tx queue full!.\n", dev->name);
366                 return 1;
367         }
368 #endif
369 
370         /* Clear all of the status flags.
371          */
372         bdp->cbd_sc &= ~BD_ENET_TX_STATS;
373 
374         /* Set buffer length and buffer pointer.
375         */
376         bdp->cbd_bufaddr = __pa(skb->data);
377         bdp->cbd_datlen = skb->len;
378 
379         /* Save skb pointer.
380         */
381         fep->tx_skbuff[fep->skb_cur] = skb;
382 
383         fep->stats.tx_bytes += skb->len;
384         fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK;
385 
386         /* Push the data cache so the CPM does not get stale memory
387          * data.
388          */
389         flush_dcache_range((unsigned long)skb->data,
390                            (unsigned long)skb->data + skb->len);
391 
392         spin_lock_irq(&fep->lock);
393 
394         /* Send it on its way.  Tell FEC its ready, interrupt when done,
395          * its the last BD of the frame, and to put the CRC on the end.
396          */
397 
398         bdp->cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
399                         | BD_ENET_TX_LAST | BD_ENET_TX_TC);
400 
401         dev->trans_start = jiffies;
402 
403         /* Trigger transmission start */
404         fecp->fec_x_des_active = 0x01000000;
405 
406         /* If this was the last BD in the ring, start at the beginning again.
407         */
408         if (bdp->cbd_sc & BD_ENET_TX_WRAP) {
409                 bdp = fep->tx_bd_base;
410         } else {
411                 bdp++;
412         }
413 
414         if (bdp->cbd_sc & BD_ENET_TX_READY) {
415                 netif_stop_queue(dev);
416                 fep->tx_full = 1;
417         }
418 
419         fep->cur_tx = (cbd_t *)bdp;
420 
421         spin_unlock_irq(&fep->lock);
422 
423         return 0;
424 }
425 
426 static void
427 fec_timeout(struct net_device *dev)
428 {
429         struct fec_enet_private *fep = dev->priv;
430 
431         printk("%s: transmit timed out.\n", dev->name);
432         fep->stats.tx_errors++;
433 #ifndef final_version
434         {
435         int     i;
436         cbd_t   *bdp;
437 
438         printk("Ring data dump: cur_tx %lx%s, dirty_tx %lx cur_rx: %lx\n",
439                (unsigned long)fep->cur_tx, fep->tx_full ? " (full)" : "",
440                (unsigned long)fep->dirty_tx,
441                (unsigned long)fep->cur_rx);
442 
443         bdp = fep->tx_bd_base;
444         printk(" tx: %u buffers\n",  TX_RING_SIZE);
445         for (i = 0 ; i < TX_RING_SIZE; i++) {
446                 printk("  %08x: %04x %04x %08x\n",
447                        (uint) bdp,
448                        bdp->cbd_sc,
449                        bdp->cbd_datlen,
450                        bdp->cbd_bufaddr);
451                 bdp++;
452         }
453 
454         bdp = fep->rx_bd_base;
455         printk(" rx: %lu buffers\n",  RX_RING_SIZE);
456         for (i = 0 ; i < RX_RING_SIZE; i++) {
457                 printk("  %08x: %04x %04x %08x\n",
458                        (uint) bdp,
459                        bdp->cbd_sc,
460                        bdp->cbd_datlen,
461                        bdp->cbd_bufaddr);
462                 bdp++;
463         }
464         }
465 #endif
466         if (!fep->tx_full)
467                 netif_wake_queue(dev);
468 }
469 
470 /* The interrupt handler.
471  * This is called from the MPC core interrupt.
472  */
473 static  void
474 fec_enet_interrupt(int irq, void * dev_id, struct pt_regs * regs)
475 {
476         struct  net_device *dev = dev_id;
477         volatile fec_t  *fecp;
478         uint    int_events;
479 #ifdef CONFIG_FEC_PACKETHOOK
480         struct  fec_enet_private *fep = dev->priv;
481         __u32 regval;
482 
483         if (fep->ph_regaddr) regval = *fep->ph_regaddr;
484 #endif
485         fecp = (volatile fec_t*)dev->base_addr;
486 
487         /* Get the interrupt events that caused us to be here.
488         */
489         while ((int_events = fecp->fec_ievent) != 0) {
490                 fecp->fec_ievent = int_events;
491                 if ((int_events & (FEC_ENET_HBERR | FEC_ENET_BABR |
492                                    FEC_ENET_BABT | FEC_ENET_EBERR)) != 0) {
493                         printk("FEC ERROR %x\n", int_events);
494                 }
495 
496                 /* Handle receive event in its own function.
497                  */
498                 if (int_events & FEC_ENET_RXF) {
499 #ifdef CONFIG_FEC_PACKETHOOK
500                         fec_enet_rx(dev, regval);
501 #else
502                         fec_enet_rx(dev);
503 #endif
504                 }
505 
506                 /* Transmit OK, or non-fatal error. Update the buffer
507                    descriptors. FEC handles all errors, we just discover
508                    them as part of the transmit process.
509                 */
510                 if (int_events & FEC_ENET_TXF) {
511 #ifdef CONFIG_FEC_PACKETHOOK
512                         fec_enet_tx(dev, regval);
513 #else
514                         fec_enet_tx(dev);
515 #endif
516                 }
517 
518                 if (int_events & FEC_ENET_MII) {
519 #ifdef  CONFIG_USE_MDIO
520                         fec_enet_mii(dev);
521 #else
522 printk("%s[%d] %s: unexpected FEC_ENET_MII event\n", __FILE__,__LINE__,__FUNCTION__);
523 #endif  /* CONFIG_USE_MDIO */
524                 }
525 
526         }
527 }
528 
529 
530 static void
531 #ifdef CONFIG_FEC_PACKETHOOK
532 fec_enet_tx(struct net_device *dev, __u32 regval)
533 #else
534 fec_enet_tx(struct net_device *dev)
535 #endif
536 {
537         struct  fec_enet_private *fep;
538         volatile cbd_t  *bdp;
539         struct  sk_buff *skb;
540 
541         fep = dev->priv;
542         spin_lock(&fep->lock);
543         bdp = fep->dirty_tx;
544 
545         while ((bdp->cbd_sc&BD_ENET_TX_READY) == 0) {
546                 if (bdp == fep->cur_tx && fep->tx_full == 0) break;
547 
548                 skb = fep->tx_skbuff[fep->skb_dirty];
549                 /* Check for errors. */
550                 if (bdp->cbd_sc & (BD_ENET_TX_HB | BD_ENET_TX_LC |
551                                    BD_ENET_TX_RL | BD_ENET_TX_UN |
552                                    BD_ENET_TX_CSL)) {
553                         fep->stats.tx_errors++;
554                         if (bdp->cbd_sc & BD_ENET_TX_HB)  /* No heartbeat */
555                                 fep->stats.tx_heartbeat_errors++;
556                         if (bdp->cbd_sc & BD_ENET_TX_LC)  /* Late collision */
557                                 fep->stats.tx_window_errors++;
558                         if (bdp->cbd_sc & BD_ENET_TX_RL)  /* Retrans limit */
559                                 fep->stats.tx_aborted_errors++;
560                         if (bdp->cbd_sc & BD_ENET_TX_UN)  /* Underrun */
561                                 fep->stats.tx_fifo_errors++;
562                         if (bdp->cbd_sc & BD_ENET_TX_CSL) /* Carrier lost */
563                                 fep->stats.tx_carrier_errors++;
564                 } else {
565 #ifdef CONFIG_FEC_PACKETHOOK
566                         /* Packet hook ... */
567                         if (fep->ph_txhandler &&
568                             ((struct ethhdr *)skb->data)->h_proto
569                             == fep->ph_proto) {
570                                 fep->ph_txhandler((__u8*)skb->data, skb->len,
571                                                   regval, fep->ph_priv);
572                         }
573 #endif
574                         fep->stats.tx_packets++;
575                 }
576 
577 #ifndef final_version
578                 if (bdp->cbd_sc & BD_ENET_TX_READY)
579                         printk("HEY! Enet xmit interrupt and TX_READY.\n");
580 #endif
581                 /* Deferred means some collisions occurred during transmit,
582                  * but we eventually sent the packet OK.
583                  */
584                 if (bdp->cbd_sc & BD_ENET_TX_DEF)
585                         fep->stats.collisions++;
586 
587                 /* Free the sk buffer associated with this last transmit.
588                  */
589 #if 0
590 printk("TXI: %x %x %x\n", bdp, skb, fep->skb_dirty);
591 #endif
592                 dev_kfree_skb_irq (skb/*, FREE_WRITE*/);
593                 fep->tx_skbuff[fep->skb_dirty] = NULL;
594                 fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK;
595 
596                 /* Update pointer to next buffer descriptor to be transmitted.
597                  */
598                 if (bdp->cbd_sc & BD_ENET_TX_WRAP)
599                         bdp = fep->tx_bd_base;
600                 else
601                         bdp++;
602 
603                 /* Since we have freed up a buffer, the ring is no longer
604                  * full.
605                  */
606                 if (fep->tx_full) {
607                         fep->tx_full = 0;
608                         if (netif_queue_stopped(dev))
609                                 netif_wake_queue(dev);
610                 }
611 #ifdef CONFIG_FEC_PACKETHOOK
612                 /* Re-read register. Not exactly guaranteed to be correct,
613                    but... */
614                 if (fep->ph_regaddr) regval = *fep->ph_regaddr;
615 #endif
616         }
617         fep->dirty_tx = (cbd_t *)bdp;
618         spin_unlock(&fep->lock);
619 }
620 
621 
622 /* During a receive, the cur_rx points to the current incoming buffer.
623  * When we update through the ring, if the next incoming buffer has
624  * not been given to the system, we just set the empty indicator,
625  * effectively tossing the packet.
626  */
627 static void
628 #ifdef CONFIG_FEC_PACKETHOOK
629 fec_enet_rx(struct net_device *dev, __u32 regval)
630 #else
631 fec_enet_rx(struct net_device *dev)
632 #endif
633 {
634         struct  fec_enet_private *fep;
635         volatile fec_t  *fecp;
636         volatile cbd_t *bdp;
637         struct  sk_buff *skb;
638         ushort  pkt_len;
639         __u8 *data;
640 
641         fep = dev->priv;
642         fecp = (volatile fec_t*)dev->base_addr;
643 
644         /* First, grab all of the stats for the incoming packet.
645          * These get messed up if we get called due to a busy condition.
646          */
647         bdp = fep->cur_rx;
648 
649 while (!(bdp->cbd_sc & BD_ENET_RX_EMPTY)) {
650 
651 #ifndef final_version
652         /* Since we have allocated space to hold a complete frame,
653          * the last indicator should be set.
654          */
655         if ((bdp->cbd_sc & BD_ENET_RX_LAST) == 0)
656                 printk("FEC ENET: rcv is not +last\n");
657 #endif
658 
659         /* Check for errors. */
660         if (bdp->cbd_sc & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
661                            BD_ENET_RX_CR | BD_ENET_RX_OV)) {
662                 fep->stats.rx_errors++;
663                 if (bdp->cbd_sc & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
664                 /* Frame too long or too short. */
665                         fep->stats.rx_length_errors++;
666                 }
667                 if (bdp->cbd_sc & BD_ENET_RX_NO)        /* Frame alignment */
668                         fep->stats.rx_frame_errors++;
669                 if (bdp->cbd_sc & BD_ENET_RX_CR)        /* CRC Error */
670                         fep->stats.rx_crc_errors++;
671                 if (bdp->cbd_sc & BD_ENET_RX_OV)        /* FIFO overrun */
672                         fep->stats.rx_crc_errors++;
673         }
674 
675         /* Report late collisions as a frame error.
676          * On this error, the BD is closed, but we don't know what we
677          * have in the buffer.  So, just drop this frame on the floor.
678          */
679         if (bdp->cbd_sc & BD_ENET_RX_CL) {
680                 fep->stats.rx_errors++;
681                 fep->stats.rx_frame_errors++;
682                 goto rx_processing_done;
683         }
684 
685         /* Process the incoming frame.
686          */
687         fep->stats.rx_packets++;
688         pkt_len = bdp->cbd_datlen;
689         fep->stats.rx_bytes += pkt_len;
690         data = fep->rx_vaddr[bdp - fep->rx_bd_base];
691 
692 #ifdef CONFIG_FEC_PACKETHOOK
693         /* Packet hook ... */
694         if (fep->ph_rxhandler) {
695                 if (((struct ethhdr *)data)->h_proto == fep->ph_proto) {
696                         switch (fep->ph_rxhandler(data, pkt_len, regval,
697                                                   fep->ph_priv)) {
698                         case 1:
699                                 goto rx_processing_done;
700                                 break;
701                         case 0:
702                                 break;
703                         default:
704                                 fep->stats.rx_errors++;
705                                 goto rx_processing_done;
706                         }
707                 }
708         }
709 
710         /* If it wasn't filtered - copy it to an sk buffer. */
711 #endif
712 
713         /* This does 16 byte alignment, exactly what we need.
714          * The packet length includes FCS, but we don't want to
715          * include that when passing upstream as it messes up
716          * bridging applications.
717          */
718         skb = dev_alloc_skb(pkt_len-4);
719 
720         if (skb == NULL) {
721                 printk("%s: Memory squeeze, dropping packet.\n", dev->name);
722                 fep->stats.rx_dropped++;
723         } else {
724                 skb->dev = dev;
725                 skb_put(skb,pkt_len-4); /* Make room */
726                 eth_copy_and_sum(skb, data, pkt_len-4, 0);
727                 skb->protocol=eth_type_trans(skb,dev);
728                 netif_rx(skb);
729         }
730   rx_processing_done:
731 
732         /* Clear the status flags for this buffer.
733         */
734         bdp->cbd_sc &= ~BD_ENET_RX_STATS;
735 
736         /* Mark the buffer empty.
737         */
738         bdp->cbd_sc |= BD_ENET_RX_EMPTY;
739 
740         /* Update BD pointer to next entry.
741         */
742         if (bdp->cbd_sc & BD_ENET_RX_WRAP)
743                 bdp = fep->rx_bd_base;
744         else
745                 bdp++;
746 
747 #if 1
748         /* Doing this here will keep the FEC running while we process
749          * incoming frames.  On a heavily loaded network, we should be
750          * able to keep up at the expense of system resources.
751          */
752         fecp->fec_r_des_active = 0x01000000;
753 #endif
754 #ifdef CONFIG_FEC_PACKETHOOK
755         /* Re-read register. Not exactly guaranteed to be correct,
756            but... */
757         if (fep->ph_regaddr) regval = *fep->ph_regaddr;
758 #endif
759    } /* while (!(bdp->cbd_sc & BD_ENET_RX_EMPTY)) */
760         fep->cur_rx = (cbd_t *)bdp;
761 
762 #if 0
763         /* Doing this here will allow us to process all frames in the
764          * ring before the FEC is allowed to put more there.  On a heavily
765          * loaded network, some frames may be lost.  Unfortunately, this
766          * increases the interrupt overhead since we can potentially work
767          * our way back to the interrupt return only to come right back
768          * here.
769          */
770         fecp->fec_r_des_active = 0x01000000;
771 #endif
772 }
773 
774 
775 #ifdef  CONFIG_USE_MDIO
776 static void
777 fec_enet_mii(struct net_device *dev)
778 {
779         struct  fec_enet_private *fep;
780         volatile fec_t  *ep;
781         mii_list_t      *mip;
782         uint            mii_reg;
783 
784         fep = (struct fec_enet_private *)dev->priv;
785         ep = &(((immap_t *)IMAP_ADDR)->im_cpm.cp_fec);
786         mii_reg = ep->fec_mii_data;
787 
788         if ((mip = mii_head) == NULL) {
789                 printk("MII and no head!\n");
790                 return;
791         }
792 
793         if (mip->mii_func != NULL)
794                 (*(mip->mii_func))(mii_reg, dev);
795 
796         mii_head = mip->mii_next;
797         mip->mii_next = mii_free;
798         mii_free = mip;
799 
800         if ((mip = mii_head) != NULL) {
801                 ep->fec_mii_data = mip->mii_regval;
802         }
803 }
804 
805 static int
806 mii_queue(struct net_device *dev, int regval, void (*func)(uint, struct net_device *))
807 {
808         struct fec_enet_private *fep;
809         unsigned long   flags;
810         mii_list_t      *mip;
811         int             retval;
812 
813         /* Add PHY address to register command.
814         */
815         fep = dev->priv;
816         regval |= fep->phy_addr << 23;
817 
818         retval = 0;
819 
820         save_flags(flags);
821         cli();
822 
823         if ((mip = mii_free) != NULL) {
824                 mii_free = mip->mii_next;
825                 mip->mii_regval = regval;
826                 mip->mii_func = func;
827                 mip->mii_next = NULL;
828                 if (mii_head) {
829                         mii_tail->mii_next = mip;
830                         mii_tail = mip;
831                 } else {
832                         mii_head = mii_tail = mip;
833                         (&(((immap_t *)IMAP_ADDR)->im_cpm.cp_fec))->fec_mii_data = regval;
834                 }
835         } else {
836                 retval = 1;
837         }
838 
839         restore_flags(flags);
840 
841         return(retval);
842 }
843 
844 static void mii_do_cmd(struct net_device *dev, const phy_cmd_t *c)
845 {
846         int k;
847 
848         if(!c)
849                 return;
850 
851         for(k = 0; (c+k)->mii_data != mk_mii_end; k++)
852                 mii_queue(dev, (c+k)->mii_data, (c+k)->funct);
853 }
854 
855 static void mii_parse_sr(uint mii_reg, struct net_device *dev)
856 {
857         struct fec_enet_private *fep = dev->priv;
858         volatile uint *s = &(fep->phy_status);
859 
860         *s &= ~(PHY_STAT_LINK | PHY_STAT_FAULT | PHY_STAT_ANC);
861 
862         if (mii_reg & 0x0004)
863                 *s |= PHY_STAT_LINK;
864         if (mii_reg & 0x0010)
865                 *s |= PHY_STAT_FAULT;
866         if (mii_reg & 0x0020)
867                 *s |= PHY_STAT_ANC;
868 
869         fep->link = (*s & PHY_STAT_LINK) ? 1 : 0;
870 }
871 
872 static void mii_parse_cr(uint mii_reg, struct net_device *dev)
873 {
874         struct fec_enet_private *fep = dev->priv;
875         volatile uint *s = &(fep->phy_status);
876 
877         *s &= ~(PHY_CONF_ANE | PHY_CONF_LOOP);
878 
879         if (mii_reg & 0x1000)
880                 *s |= PHY_CONF_ANE;
881         if (mii_reg & 0x4000)
882                 *s |= PHY_CONF_LOOP;
883 }
884 
885 static void mii_parse_anar(uint mii_reg, struct net_device *dev)
886 {
887         struct fec_enet_private *fep = dev->priv;
888         volatile uint *s = &(fep->phy_status);
889 
890         *s &= ~(PHY_CONF_SPMASK);
891 
892         if (mii_reg & 0x0020)
893                 *s |= PHY_CONF_10HDX;
894         if (mii_reg & 0x0040)
895                 *s |= PHY_CONF_10FDX;
896         if (mii_reg & 0x0080)
897                 *s |= PHY_CONF_100HDX;
898         if (mii_reg & 0x00100)
899                 *s |= PHY_CONF_100FDX;
900 }
901 #if 0
902 static void mii_disp_reg(uint mii_reg, struct net_device *dev)
903 {
904         printk("reg %u = 0x%04x\n", (mii_reg >> 18) & 0x1f, mii_reg & 0xffff);
905 }
906 #endif
907 
908 /* ------------------------------------------------------------------------- */
909 /* The Level one LXT970 is used by many boards                               */
910 
911 #ifdef CONFIG_FEC_LXT970
912 
913 #define MII_LXT970_MIRROR    16  /* Mirror register           */
914 #define MII_LXT970_IER       17  /* Interrupt Enable Register */
915 #define MII_LXT970_ISR       18  /* Interrupt Status Register */
916 #define MII_LXT970_CONFIG    19  /* Configuration Register    */
917 #define MII_LXT970_CSR       20  /* Chip Status Register      */
918 
919 static void mii_parse_lxt970_csr(uint mii_reg, struct net_device *dev)
920 {
921         struct fec_enet_private *fep = dev->priv;
922         volatile uint *s = &(fep->phy_status);
923 
924         *s &= ~(PHY_STAT_SPMASK);
925 
926         if (mii_reg & 0x0800) {
927                 if (mii_reg & 0x1000)
928                         *s |= PHY_STAT_100FDX;
929                 else
930                         *s |= PHY_STAT_100HDX;
931         }
932         else {
933                 if (mii_reg & 0x1000)
934                         *s |= PHY_STAT_10FDX;
935                 else
936                         *s |= PHY_STAT_10HDX;
937         }
938 }
939 
940 static phy_info_t phy_info_lxt970 = {
941         0x07810000,
942         "LXT970",
943 
944         (const phy_cmd_t []) {  /* config */
945 #if 0
946 //              { mk_mii_write(MII_REG_ANAR, 0x0021), NULL },
947 
948                 /* Set default operation of 100-TX....for some reason
949                  * some of these bits are set on power up, which is wrong.
950                  */
951                 { mk_mii_write(MII_LXT970_CONFIG, 0), NULL },
952 #endif
953                 { mk_mii_read(MII_REG_CR), mii_parse_cr },
954                 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
955                 { mk_mii_end, }
956         },
957         (const phy_cmd_t []) {  /* startup - enable interrupts */
958                 { mk_mii_write(MII_LXT970_IER, 0x0002), NULL },
959                 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
960                 { mk_mii_end, }
961         },
962         (const phy_cmd_t []) { /* ack_int */
963                 /* read SR and ISR to acknowledge */
964 
965                 { mk_mii_read(MII_REG_SR), mii_parse_sr },
966                 { mk_mii_read(MII_LXT970_ISR), NULL },
967 
968                 /* find out the current status */
969 
970                 { mk_mii_read(MII_LXT970_CSR), mii_parse_lxt970_csr },
971                 { mk_mii_end, }
972         },
973         (const phy_cmd_t []) {  /* shutdown - disable interrupts */
974                 { mk_mii_write(MII_LXT970_IER, 0x0000), NULL },
975                 { mk_mii_end, }
976         },
977 };
978 
979 #endif /* CONFIG_FEC_LXT970 */
980 
981 /* ------------------------------------------------------------------------- */
982 /* The Level one LXT971 is used on some of my custom boards                  */
983 
984 #ifdef CONFIG_FEC_LXT971
985 
986 /* register definitions for the 971 */
987 
988 #define MII_LXT971_PCR       16  /* Port Control Register     */
989 #define MII_LXT971_SR2       17  /* Status Register 2         */
990 #define MII_LXT971_IER       18  /* Interrupt Enable Register */
991 #define MII_LXT971_ISR       19  /* Interrupt Status Register */
992 #define MII_LXT971_LCR       20  /* LED Control Register      */
993 #define MII_LXT971_TCR       30  /* Transmit Control Register */
994 
995 /*
996  * I had some nice ideas of running the MDIO faster...
997  * The 971 should support 8MHz and I tried it, but things acted really
998  * weird, so 2.5 MHz ought to be enough for anyone...
999  */
1000 
1001 static void mii_parse_lxt971_sr2(uint mii_reg, struct net_device *dev)
1002 {
1003         struct fec_enet_private *fep = dev->priv;
1004         volatile uint *s = &(fep->phy_status);
1005 
1006         *s &= ~(PHY_STAT_SPMASK);
1007 
1008         if (mii_reg & 0x4000) {
1009                 if (mii_reg & 0x0200)
1010                         *s |= PHY_STAT_100FDX;
1011                 else
1012                         *s |= PHY_STAT_100HDX;
1013         }
1014         else {
1015                 if (mii_reg & 0x0200)
1016                         *s |= PHY_STAT_10FDX;
1017                 else
1018                         *s |= PHY_STAT_10HDX;
1019         }
1020         if (mii_reg & 0x0008)
1021                 *s |= PHY_STAT_FAULT;
1022 }
1023 
1024 static phy_info_t phy_info_lxt971 = {
1025         0x0001378e,
1026         "LXT971",
1027 
1028         (const phy_cmd_t []) {  /* config */
1029 //              { mk_mii_write(MII_REG_ANAR, 0x021), NULL }, /* 10  Mbps, HD */
1030                 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1031                 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1032                 { mk_mii_end, }
1033         },
1034         (const phy_cmd_t []) {  /* startup - enable interrupts */
1035                 { mk_mii_write(MII_LXT971_IER, 0x00f2), NULL },
1036                 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1037 
1038                 /* Somehow does the 971 tell me that the link is down
1039                  * the first read after power-up.
1040                  * read here to get a valid value in ack_int */
1041 
1042                 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1043                 { mk_mii_end, }
1044         },
1045         (const phy_cmd_t []) { /* ack_int */
1046                 /* find out the current status */
1047 
1048                 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1049                 { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 },
1050 
1051                 /* we only need to read ISR to acknowledge */
1052 
1053                 { mk_mii_read(MII_LXT971_ISR), NULL },
1054                 { mk_mii_end, }
1055         },
1056         (const phy_cmd_t []) {  /* shutdown - disable interrupts */
1057                 { mk_mii_write(MII_LXT971_IER, 0x0000), NULL },
1058                 { mk_mii_end, }
1059         },
1060 };
1061 
1062 #endif /* CONFIG_FEC_LXT970 */
1063 
1064 
1065 /* ------------------------------------------------------------------------- */
1066 /* The Quality Semiconductor QS6612 is used on the RPX CLLF                  */
1067 
1068 #ifdef CONFIG_FEC_QS6612
1069 
1070 /* register definitions */
1071 
1072 #define MII_QS6612_MCR       17  /* Mode Control Register      */
1073 #define MII_QS6612_FTR       27  /* Factory Test Register      */
1074 #define MII_QS6612_MCO       28  /* Misc. Control Register     */
1075 #define MII_QS6612_ISR       29  /* Interrupt Source Register  */
1076 #define MII_QS6612_IMR       30  /* Interrupt Mask Register    */
1077 #define MII_QS6612_PCR       31  /* 100BaseTx PHY Control Reg. */
1078 
1079 static void mii_parse_qs6612_pcr(uint mii_reg, struct net_device *dev)
1080 {
1081         struct fec_enet_private *fep = dev->priv;
1082         volatile uint *s = &(fep->phy_status);
1083 
1084         *s &= ~(PHY_STAT_SPMASK);
1085 
1086         switch((mii_reg >> 2) & 7) {
1087         case 1: *s |= PHY_STAT_10HDX; break;
1088         case 2: *s |= PHY_STAT_100HDX; break;
1089         case 5: *s |= PHY_STAT_10FDX; break;
1090         case 6: *s |= PHY_STAT_100FDX; break;
1091         }
1092 }
1093 
1094 static phy_info_t phy_info_qs6612 = {
1095         0x00181440,
1096         "QS6612",
1097 
1098         (const phy_cmd_t []) {  /* config */
1099 //      { mk_mii_write(MII_REG_ANAR, 0x061), NULL }, /* 10  Mbps */
1100 
1101                 /* The PHY powers up isolated on the RPX,
1102                  * so send a command to allow operation.
1103                  */
1104 
1105                 { mk_mii_write(MII_QS6612_PCR, 0x0dc0), NULL },
1106 
1107                 /* parse cr and anar to get some info */
1108 
1109                 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1110                 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1111                 { mk_mii_end, }
1112         },
1113         (const phy_cmd_t []) {  /* startup - enable interrupts */
1114                 { mk_mii_write(MII_QS6612_IMR, 0x003a), NULL },
1115                 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1116                 { mk_mii_end, }
1117         },
1118         (const phy_cmd_t []) { /* ack_int */
1119 
1120                 /* we need to read ISR, SR and ANER to acknowledge */
1121 
1122                 { mk_mii_read(MII_QS6612_ISR), NULL },
1123                 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1124                 { mk_mii_read(MII_REG_ANER), NULL },
1125 
1126                 /* read pcr to get info */
1127 
1128                 { mk_mii_read(MII_QS6612_PCR), mii_parse_qs6612_pcr },
1129                 { mk_mii_end, }
1130         },
1131         (const phy_cmd_t []) {  /* shutdown - disable interrupts */
1132                 { mk_mii_write(MII_QS6612_IMR, 0x0000), NULL },
1133                 { mk_mii_end, }
1134         },
1135 };
1136 
1137 #endif /* CONFIG_FEC_QS6612 */
1138 
1139 /* ------------------------------------------------------------------------- */
1140 /* The Advanced Micro Devices AM79C874 is used on the ICU862                 */
1141 
1142 #ifdef CONFIG_FEC_AM79C874
1143 
1144 /* register definitions for the 79C874 */
1145 
1146 #define MII_AM79C874_MFR        16  /* Miscellaneous Features Register      */
1147 #define MII_AM79C874_ICSR       17  /* Interrupt Control/Status Register    */
1148 #define MII_AM79C874_DR         18  /* Diagnostic Register                  */
1149 #define MII_AM79C874_PMLR       19  /* Power Management & Loopback Register */
1150 #define MII_AM79C874_MCR        21  /* Mode Control Register                */
1151 #define MII_AM79C874_DC         23  /* Disconnect Counter                   */
1152 #define MII_AM79C874_REC        24  /* Receiver Error Counter               */
1153 
1154 static void mii_parse_amd79c874_dr(uint mii_reg, struct net_device *dev, uint data)
1155 {
1156         volatile struct fec_enet_private *fep = dev->priv;
1157         uint s = fep->phy_status;
1158 
1159         s &= ~(PHY_STAT_SPMASK);
1160 
1161         /* Register 18: Bit 10 is data rate, 11 is Duplex */
1162         switch ((mii_reg >> 10) & 3) {
1163         case 0: s |= PHY_STAT_10HDX;    break;
1164         case 1: s |= PHY_STAT_100HDX;   break;
1165         case 2: s |= PHY_STAT_10FDX;    break;
1166         case 3: s |= PHY_STAT_100FDX;   break;
1167         }
1168 
1169         fep->phy_status = s;
1170 }
1171 
1172 static phy_info_t phy_info_amd79c874 = {
1173         0x00022561,
1174         "AM79C874",
1175 
1176         (const phy_cmd_t []) {  /* config */
1177 //              { mk_mii_write(MII_REG_ANAR, 0x021), NULL }, /* 10  Mbps, HD */
1178                 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1179                 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1180                 { mk_mii_end, }
1181         },
1182         (const phy_cmd_t []) {  /* startup - enable interrupts */
1183                 { mk_mii_write(MII_AM79C874_ICSR, 0xff00), NULL },
1184                 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1185                 { mk_mii_end, }
1186         },
1187         (const phy_cmd_t []) { /* ack_int */
1188                 /* find out the current status */
1189 
1190                 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1191                 { mk_mii_read(MII_AM79C874_DR), mii_parse_amd79c874_dr },
1192 
1193                 /* we only need to read ICSR to acknowledge */
1194 
1195                 { mk_mii_read(MII_AM79C874_ICSR), NULL },
1196                 { mk_mii_end, }
1197         },
1198         (const phy_cmd_t []) {  /* shutdown - disable interrupts */
1199                 { mk_mii_write(MII_AM79C874_ICSR, 0x0000), NULL },
1200                 { mk_mii_end, }
1201         },
1202 };
1203 
1204 #endif /* CONFIG_FEC_AM79C874 */
1205 
1206 static phy_info_t *phy_info[] = {
1207 
1208 #ifdef CONFIG_FEC_LXT970
1209         &phy_info_lxt970,
1210 #endif /* CONFIG_FEC_LXT970 */
1211 
1212 #ifdef CONFIG_FEC_LXT971
1213         &phy_info_lxt971,
1214 #endif /* CONFIG_FEC_LXT971 */
1215 
1216 #ifdef CONFIG_FEC_QS6612
1217         &phy_info_qs6612,
1218 #endif /* CONFIG_FEC_QS6612 */
1219 
1220 #ifdef CONFIG_FEC_AM79C874
1221         &phy_info_amd79c874,
1222 #endif /* CONFIG_FEC_AM79C874 */
1223 
1224         NULL
1225 };
1226 
1227 static void mii_display_status(struct net_device *dev)
1228 {
1229         struct fec_enet_private *fep = dev->priv;
1230         volatile uint *s = &(fep->phy_status);
1231 
1232         if (!fep->link && !fep->old_link) {
1233                 /* Link is still down - don't print anything */
1234                 return;
1235         }
1236 
1237         printk("%s: status: ", dev->name);
1238 
1239         if (!fep->link) {
1240                 printk("link down");
1241         } else {
1242                 printk("link up");
1243 
1244                 switch(*s & PHY_STAT_SPMASK) {
1245                 case PHY_STAT_100FDX: printk(", 100 Mbps Full Duplex"); break;
1246                 case PHY_STAT_100HDX: printk(", 100 Mbps Half Duplex"); break;
1247                 case PHY_STAT_10FDX: printk(", 10 Mbps Full Duplex"); break;
1248                 case PHY_STAT_10HDX: printk(", 10 Mbps Half Duplex"); break;
1249                 default:
1250                         printk(", Unknown speed/duplex");
1251                 }
1252 
1253                 if (*s & PHY_STAT_ANC)
1254                         printk(", auto-negotiation complete");
1255         }
1256 
1257         if (*s & PHY_STAT_FAULT)
1258                 printk(", remote fault");
1259 
1260         printk(".\n");
1261 }
1262 
1263 static void mii_display_config(struct net_device *dev)
1264 {
1265         struct fec_enet_private *fep = dev->priv;
1266         volatile uint *s = &(fep->phy_status);
1267 
1268         printk("%s: config: auto-negotiation ", dev->name);
1269 
1270         if (*s & PHY_CONF_ANE)
1271                 printk("on");
1272         else
1273                 printk("off");
1274 
1275         if (*s & PHY_CONF_100FDX)
1276                 printk(", 100FDX");
1277         if (*s & PHY_CONF_100HDX)
1278                 printk(", 100HDX");
1279         if (*s & PHY_CONF_10FDX)
1280                 printk(", 10FDX");
1281         if (*s & PHY_CONF_10HDX)
1282                 printk(", 10HDX");
1283         if (!(*s & PHY_CONF_SPMASK))
1284                 printk(", No speed/duplex selected?");
1285 
1286         if (*s & PHY_CONF_LOOP)
1287                 printk(", loopback enabled");
1288 
1289         printk(".\n");
1290 
1291         fep->sequence_done = 1;
1292 }
1293 
1294 static void mii_relink(struct net_device *dev)
1295 {
1296         struct fec_enet_private *fep = dev->priv;
1297         int duplex;
1298 
1299         fep->link = (fep->phy_status & PHY_STAT_LINK) ? 1 : 0;
1300         mii_display_status(dev);
1301         fep->old_link = fep->link;
1302 
1303         if (fep->link) {
1304                 duplex = 0;
1305                 if (fep->phy_status
1306                     & (PHY_STAT_100FDX | PHY_STAT_10FDX))
1307                         duplex = 1;
1308                 fec_restart(dev, duplex);
1309         }
1310         else
1311                 fec_stop(dev);
1312 
1313 #if 0
1314         enable_irq(fep->mii_irq);
1315 #endif
1316 
1317 }
1318 
1319 static void mii_queue_relink(uint mii_reg, struct net_device *dev)
1320 {
1321         struct fec_enet_private *fep = dev->priv;
1322 
1323         fep->phy_task.routine = (void *)mii_relink;
1324         fep->phy_task.data = dev;
1325         schedule_task(&fep->phy_task);
1326 }
1327 
1328 static void mii_queue_config(uint mii_reg, struct net_device *dev)
1329 {
1330         struct fec_enet_private *fep = dev->priv;
1331 
1332         fep->phy_task.routine = (void *)mii_display_config;
1333         fep->phy_task.data = dev;
1334         schedule_task(&fep->phy_task);
1335 }
1336 
1337 
1338 
1339 phy_cmd_t phy_cmd_relink[] = { { mk_mii_read(MII_REG_CR), mii_queue_relink },
1340                                { mk_mii_end, } };
1341 phy_cmd_t phy_cmd_config[] = { { mk_mii_read(MII_REG_CR), mii_queue_config },
1342                                { mk_mii_end, } };
1343 
1344 
1345 
1346 /* Read remainder of PHY ID.
1347 */
1348 static void
1349 mii_discover_phy3(uint mii_reg, struct net_device *dev)
1350 {
1351         struct fec_enet_private *fep;
1352         int     i;
1353 
1354         fep = dev->priv;
1355         fep->phy_id |= (mii_reg & 0xffff);
1356 
1357         for(i = 0; phy_info[i]; i++)
1358                 if(phy_info[i]->id == (fep->phy_id >> 4))
1359                         break;
1360 
1361         if(!phy_info[i])
1362                 panic("%s: PHY id 0x%08x is not supported!\n",
1363                       dev->name, fep->phy_id);
1364 
1365         fep->phy = phy_info[i];
1366         fep->phy_id_done = 1;
1367 
1368         printk("%s: Phy @ 0x%x, type %s (0x%08x)\n",
1369                 dev->name, fep->phy_addr, fep->phy->name, fep->phy_id);
1370 }
1371 
1372 /* Scan all of the MII PHY addresses looking for someone to respond
1373  * with a valid ID.  This usually happens quickly.
1374  */
1375 static void
1376 mii_discover_phy(uint mii_reg, struct net_device *dev)
1377 {
1378         struct fec_enet_private *fep;
1379         uint    phytype;
1380 
1381         fep = dev->priv;
1382 
1383         if ((phytype = (mii_reg & 0xffff)) != 0xffff) {
1384 
1385                 /* Got first part of ID, now get remainder.
1386                 */
1387                 fep->phy_id = phytype << 16;
1388                 mii_queue(dev, mk_mii_read(MII_REG_PHYIR2), mii_discover_phy3);
1389         } else {
1390                 fep->phy_addr++;
1391                 if (fep->phy_addr < 32) {
1392                         mii_queue(dev, mk_mii_read(MII_REG_PHYIR1),
1393                                                         mii_discover_phy);
1394                 } else {
1395                         printk("fec: No PHY device found.\n");
1396                 }
1397         }
1398 }
1399 #endif  /* CONFIG_USE_MDIO */
1400 
1401 /* This interrupt occurs when the PHY detects a link change.
1402 */
1403 static void
1404 #ifdef CONFIG_RPXCLASSIC
1405 mii_link_interrupt(void *dev_id)
1406 #else
1407 mii_link_interrupt(int irq, void * dev_id, struct pt_regs * regs)
1408 #endif
1409 {
1410 #ifdef  CONFIG_USE_MDIO
1411         struct  net_device *dev = dev_id;
1412         struct fec_enet_private *fep = dev->priv;
1413         volatile immap_t *immap = (immap_t *)IMAP_ADDR;
1414         volatile fec_t *fecp = &(immap->im_cpm.cp_fec);
1415         unsigned int ecntrl = fecp->fec_ecntrl;
1416 
1417         /* We need the FEC enabled to access the MII
1418         */
1419         if ((ecntrl & FEC_ECNTRL_ETHER_EN) == 0) {
1420                 fecp->fec_ecntrl |= FEC_ECNTRL_ETHER_EN;
1421         }
1422 #endif  /* CONFIG_USE_MDIO */
1423 
1424 #if 0
1425         disable_irq(fep->mii_irq);  /* disable now, enable later */
1426 #endif
1427 
1428 
1429 #ifdef  CONFIG_USE_MDIO
1430         mii_do_cmd(dev, fep->phy->ack_int);
1431         mii_do_cmd(dev, phy_cmd_relink);  /* restart and display status */
1432 
1433         if ((ecntrl & FEC_ECNTRL_ETHER_EN) == 0) {
1434                 fecp->fec_ecntrl = ecntrl;      /* restore old settings */
1435         }
1436 #else
1437 printk("%s[%d] %s: unexpected Link interrupt\n", __FILE__,__LINE__,__FUNCTION__);
1438 #endif  /* CONFIG_USE_MDIO */
1439 
1440 }
1441 
1442 static int
1443 fec_enet_open(struct net_device *dev)
1444 {
1445         struct fec_enet_private *fep = dev->priv;
1446 
1447         /* I should reset the ring buffers here, but I don't yet know
1448          * a simple way to do that.
1449          */
1450 
1451 #ifdef  CONFIG_USE_MDIO
1452         fep->sequence_done = 0;
1453         fep->link = 0;
1454 
1455         if (fep->phy) {
1456                 mii_do_cmd(dev, fep->phy->ack_int);
1457                 mii_do_cmd(dev, fep->phy->config);
1458                 mii_do_cmd(dev, phy_cmd_config);  /* display configuration */
1459                 while(!fep->sequence_done)
1460                         schedule();
1461 
1462                 mii_do_cmd(dev, fep->phy->startup);
1463                 netif_start_queue(dev);
1464                 return 0;               /* Success */
1465         }
1466         return -ENODEV;         /* No PHY we understand */
1467 #else
1468         fep->link = 1;
1469         netif_start_queue(dev);
1470         return 0;       /* Success */
1471 #endif  /* CONFIG_USE_MDIO */
1472 
1473 }
1474 
1475 static int
1476 fec_enet_close(struct net_device *dev)
1477 {
1478         /* Don't know what to do yet.
1479         */
1480         netif_stop_queue(dev);
1481         fec_stop(dev);
1482 
1483         return 0;
1484 }
1485 
1486 static struct net_device_stats *fec_enet_get_stats(struct net_device *dev)
1487 {
1488         struct fec_enet_private *fep = (struct fec_enet_private *)dev->priv;
1489 
1490         return &fep->stats;
1491 }
1492 
1493 /* Set or clear the multicast filter for this adaptor.
1494  * Skeleton taken from sunlance driver.
1495  * The CPM Ethernet implementation allows Multicast as well as individual
1496  * MAC address filtering.  Some of the drivers check to make sure it is
1497  * a group multicast address, and discard those that are not.  I guess I
1498  * will do the same for now, but just remove the test if you want
1499  * individual filtering as well (do the upper net layers want or support
1500  * this kind of feature?).
1501  */
1502 
1503 static void set_multicast_list(struct net_device *dev)
1504 {
1505         struct  fec_enet_private *fep;
1506         volatile fec_t *ep;
1507 
1508         fep = (struct fec_enet_private *)dev->priv;
1509         ep = &(((immap_t *)IMAP_ADDR)->im_cpm.cp_fec);
1510 
1511         if (dev->flags&IFF_PROMISC) {
1512 
1513                 /* Log any net taps. */
1514                 printk("%s: Promiscuous mode enabled.\n", dev->name);
1515                 ep->fec_r_cntrl |= FEC_RCNTRL_PROM;
1516         } else {
1517 
1518                 ep->fec_r_cntrl &= ~FEC_RCNTRL_PROM;
1519 
1520                 if (dev->flags & IFF_ALLMULTI) {
1521                         /* Catch all multicast addresses, so set the
1522                          * filter to all 1's.
1523                          */
1524                         ep->fec_hash_table_high = 0xffffffff;
1525                         ep->fec_hash_table_low = 0xffffffff;
1526                 }
1527 #if 0
1528                 else {
1529                         /* Clear filter and add the addresses in the list.
1530                         */
1531                         ep->sen_gaddr1 = 0;
1532                         ep->sen_gaddr2 = 0;
1533                         ep->sen_gaddr3 = 0;
1534                         ep->sen_gaddr4 = 0;
1535 
1536                         dmi = dev->mc_list;
1537 
1538                         for (i=0; i<dev->mc_count; i++) {
1539 
1540                                 /* Only support group multicast for now.
1541                                 */
1542                                 if (!(dmi->dmi_addr[0] & 1))
1543                                         continue;
1544 
1545                                 /* The address in dmi_addr is LSB first,
1546                                  * and taddr is MSB first.  We have to
1547                                  * copy bytes MSB first from dmi_addr.
1548                                  */
1549                                 mcptr = (u_char *)dmi->dmi_addr + 5;
1550                                 tdptr = (u_char *)&ep->sen_taddrh;
1551                                 for (j=0; j<6; j++)
1552                                         *tdptr++ = *mcptr--;
1553 
1554                                 /* Ask CPM to run CRC and set bit in
1555                                  * filter mask.
1556                                  */
1557                                 cpmp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SCC1, CPM_CR_SET_GADDR) | CPM_CR_FLG;
1558                                 /* this delay is necessary here -- Cort */
1559                                 udelay(10);
1560                                 while (cpmp->cp_cpcr & CPM_CR_FLG);
1561                         }
1562                 }
1563 #endif
1564         }
1565 }
1566 
1567 /* Initialize the FEC Ethernet on 860T.
1568  */
1569 static int __init fec_enet_init(void)
1570 {
1571         struct net_device *dev;
1572         struct fec_enet_private *fep;
1573         int i, j, k, err;
1574         unsigned char   *eap, *iap, *ba;
1575         unsigned long   mem_addr;
1576         volatile        cbd_t   *bdp;
1577         cbd_t           *cbd_base;
1578         volatile        immap_t *immap;
1579         volatile        fec_t   *fecp;
1580         bd_t            *bd;
1581 #ifdef CONFIG_SCC_ENET
1582         unsigned char   tmpaddr[6];
1583 #endif
1584 
1585         immap = (immap_t *)IMAP_ADDR;   /* pointer to internal registers */
1586 
1587         bd = (bd_t *)__res;
1588 
1589         dev = alloc_etherdev(sizeof(*fep));
1590         if (!dev)
1591                 return -ENOMEM;
1592 
1593         fep = dev->priv;
1594 
1595         fecp = &(immap->im_cpm.cp_fec);
1596 
1597         /* Whack a reset.  We should wait for this.
1598         */
1599         fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET;
1600         for (i = 0;
1601              (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
1602              ++i) {
1603                 udelay(1);
1604         }
1605         if (i == FEC_RESET_DELAY) {
1606                 printk ("FEC Reset timeout!\n");
1607         }
1608 
1609         /* Set the Ethernet address.  If using multiple Enets on the 8xx,
1610          * this needs some work to get unique addresses.
1611          */
1612         eap = (unsigned char *)my_enet_addr;
1613         iap = bd->bi_enetaddr;
1614 
1615 #ifdef CONFIG_SCC_ENET
1616         /*
1617          * If a board has Ethernet configured both on a SCC and the
1618          * FEC, it needs (at least) 2 MAC addresses (we know that Sun
1619          * disagrees, but anyway). For the FEC port, we create
1620          * another address by setting one of the address bits above
1621          * something that would have (up to now) been allocated.
1622          */
1623         for (i=0; i<6; i++)
1624                 tmpaddr[i] = *iap++;
1625         tmpaddr[3] |= 0x80;
1626         iap = tmpaddr;
1627 #endif
1628 
1629         for (i=0; i<6; i++) {
1630                 dev->dev_addr[i] = *eap++ = *iap++;
1631         }
1632 
1633         /* Allocate memory for buffer descriptors.
1634         */
1635         if (((RX_RING_SIZE + TX_RING_SIZE) * sizeof(cbd_t)) > PAGE_SIZE) {
1636                 printk("FEC init error.  Need more space.\n");
1637                 printk("FEC initialization failed.\n");
1638                 return 1;
1639         }
1640         cbd_base = (cbd_t *)consistent_alloc(GFP_KERNEL, PAGE_SIZE, &mem_addr);
1641 
1642         /* Set receive and transmit descriptor base.
1643         */
1644         fep->rx_bd_base = cbd_base;
1645         fep->tx_bd_base = cbd_base + RX_RING_SIZE;
1646 
1647         fep->skb_cur = fep->skb_dirty = 0;
1648 
1649         /* Initialize the receive buffer descriptors.
1650         */
1651         bdp = fep->rx_bd_base;
1652         k = 0;
1653         for (i=0; i<FEC_ENET_RX_PAGES; i++) {
1654 
1655                 /* Allocate a page.
1656                 */
1657                 ba = (unsigned char *)consistent_alloc(GFP_KERNEL, PAGE_SIZE, &mem_addr);
1658                 /* BUG: no check for failure */
1659 
1660                 /* Initialize the BD for every fragment in the page.
1661                 */
1662                 for (j=0; j<FEC_ENET_RX_FRPPG; j++) {
1663                         bdp->cbd_sc = BD_ENET_RX_EMPTY;
1664                         bdp->cbd_bufaddr = mem_addr;
1665                         fep->rx_vaddr[k++] = ba;
1666                         mem_addr += FEC_ENET_RX_FRSIZE;
1667                         ba += FEC_ENET_RX_FRSIZE;
1668                         bdp++;
1669                 }
1670         }
1671 
1672         /* Set the last buffer to wrap.
1673         */
1674         bdp--;
1675         bdp->cbd_sc |= BD_SC_WRAP;
1676 
1677 #ifdef CONFIG_FEC_PACKETHOOK
1678         fep->ph_lock = 0;
1679         fep->ph_rxhandler = fep->ph_txhandler = NULL;
1680         fep->ph_proto = 0;
1681         fep->ph_regaddr = NULL;
1682         fep->ph_priv = NULL;
1683 #endif
1684 
1685         /* Install our interrupt handler.
1686         */
1687         if (request_8xxirq(FEC_INTERRUPT, fec_enet_interrupt, 0, "fec", dev) != 0)
1688                 panic("Could not allocate FEC IRQ!");
1689 
1690 #ifdef CONFIG_RPXCLASSIC
1691         /* Make Port C, bit 15 an input that causes interrupts.
1692         */
1693         immap->im_ioport.iop_pcpar &= ~0x0001;
1694         immap->im_ioport.iop_pcdir &= ~0x0001;
1695         immap->im_ioport.iop_pcso  &= ~0x0001;
1696         immap->im_ioport.iop_pcint |=  0x0001;
1697         cpm_install_handler(CPMVEC_PIO_PC15, mii_link_interrupt, dev);
1698 
1699         /* Make LEDS reflect Link status.
1700         */
1701         *((uint *) RPX_CSR_ADDR) &= ~BCSR2_FETHLEDMODE;
1702 #endif
1703 
1704 #ifdef PHY_INTERRUPT
1705         ((immap_t *)IMAP_ADDR)->im_siu_conf.sc_siel |=
1706                 (0x80000000 >> PHY_INTERRUPT);
1707 
1708         if (request_8xxirq(PHY_INTERRUPT, mii_link_interrupt, 0, "mii", dev) != 0)
1709                 panic("Could not allocate MII IRQ!");
1710 #endif
1711 
1712         dev->base_addr = (unsigned long)fecp;
1713 
1714         /* The FEC Ethernet specific entries in the device structure. */
1715         dev->open = fec_enet_open;
1716         dev->hard_start_xmit = fec_enet_start_xmit;
1717         dev->tx_timeout = fec_timeout;
1718         dev->watchdog_timeo = TX_TIMEOUT;
1719         dev->stop = fec_enet_close;
1720         dev->get_stats = fec_enet_get_stats;
1721         dev->set_multicast_list = set_multicast_list;
1722 
1723 #ifdef  CONFIG_USE_MDIO
1724         for (i=0; i<NMII-1; i++)
1725                 mii_cmds[i].mii_next = &mii_cmds[i+1];
1726         mii_free = mii_cmds;
1727 #endif  /* CONFIG_USE_MDIO */
1728 
1729         /* Configure all of port D for MII.
1730         */
1731         immap->im_ioport.iop_pdpar = 0x1fff;
1732 
1733         /* Bits moved from Rev. D onward.
1734         */
1735         if ((mfspr(IMMR) & 0xffff) < 0x0501)
1736                 immap->im_ioport.iop_pddir = 0x1c58;    /* Pre rev. D */
1737         else
1738                 immap->im_ioport.iop_pddir = 0x1fff;    /* Rev. D and later */
1739 
1740 #ifdef  CONFIG_USE_MDIO
1741         /* Set MII speed to 2.5 MHz
1742         */
1743         fecp->fec_mii_speed = fep->phy_speed =
1744                 (( (bd->bi_intfreq + 500000) / 2500000 / 2 ) & 0x3F ) << 1;
1745 #else
1746         fecp->fec_mii_speed = 0;        /* turn off MDIO */
1747 #endif  /* CONFIG_USE_MDIO */
1748 
1749         err = register_netdev(dev);
1750         if (err) {
1751                 kfree(dev);
1752                 return err;
1753         }
1754 
1755         printk ("%s: FEC ENET Version 0.2, FEC irq %d"
1756 #ifdef PHY_INTERRUPT
1757                 ", MII irq %d"
1758 #endif
1759                 ", addr ",
1760                 dev->name, FEC_INTERRUPT
1761 #ifdef PHY_INTERRUPT
1762                 , PHY_INTERRUPT
1763 #endif
1764         );
1765         for (i=0; i<6; i++)
1766                 printk("%02x%c", dev->dev_addr[i], (i==5) ? '\n' : ':');
1767 
1768 #ifdef  CONFIG_USE_MDIO /* start in full duplex mode, and negotiate speed */
1769         fec_restart (dev, 1);
1770 #else                   /* always use half duplex mode only */
1771         fec_restart (dev, 0);
1772 #endif
1773 
1774 #ifdef  CONFIG_USE_MDIO
1775         /* Queue up command to detect the PHY and initialize the
1776          * remainder of the interface.
1777          */
1778         fep->phy_id_done = 0;
1779         fep->phy_addr = 0;
1780         mii_queue(dev, mk_mii_read(MII_REG_PHYIR1), mii_discover_phy);
1781 #endif  /* CONFIG_USE_MDIO */
1782 
1783         return 0;
1784 }
1785 module_init(fec_enet_init);
1786 
1787 /* This function is called to start or restart the FEC during a link
1788  * change.  This only happens when switching between half and full
1789  * duplex.
1790  */
1791 static void
1792 fec_restart(struct net_device *dev, int duplex)
1793 {
1794         struct fec_enet_private *fep;
1795         int i;
1796         volatile        cbd_t   *bdp;
1797         volatile        immap_t *immap;
1798         volatile        fec_t   *fecp;
1799 
1800         immap = (immap_t *)IMAP_ADDR;   /* pointer to internal registers */
1801 
1802         fecp = &(immap->im_cpm.cp_fec);
1803 
1804         fep = dev->priv;
1805 
1806         /* Whack a reset.  We should wait for this.
1807         */
1808         fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET;
1809         for (i = 0;
1810              (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
1811              ++i) {
1812                 udelay(1);
1813         }
1814         if (i == FEC_RESET_DELAY) {
1815                 printk ("FEC Reset timeout!\n");
1816         }
1817 
1818         /* Set station address.
1819         */
1820         fecp->fec_addr_low  = (my_enet_addr[0] << 16) | my_enet_addr[1];
1821         fecp->fec_addr_high =  my_enet_addr[2];
1822 
1823         /* Reset all multicast.
1824         */
1825         fecp->fec_hash_table_high = 0;
1826         fecp->fec_hash_table_low  = 0;
1827 
1828         /* Set maximum receive buffer size.
1829         */
1830         fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
1831         fecp->fec_r_hash = PKT_MAXBUF_SIZE;
1832 
1833         /* Set receive and transmit descriptor base.
1834         */
1835         fecp->fec_r_des_start = iopa((uint)(fep->rx_bd_base));
1836         fecp->fec_x_des_start = iopa((uint)(fep->tx_bd_base));
1837 
1838         fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
1839         fep->cur_rx = fep->rx_bd_base;
1840 
1841         /* Reset SKB transmit buffers.
1842         */
1843         fep->skb_cur = fep->skb_dirty = 0;
1844         for (i=0; i<=TX_RING_MOD_MASK; i++) {
1845                 if (fep->tx_skbuff[i] != NULL) {
1846                         dev_kfree_skb(fep->tx_skbuff[i]);
1847                         fep->tx_skbuff[i] = NULL;
1848                 }
1849         }
1850 
1851         /* Initialize the receive buffer descriptors.
1852         */
1853         bdp = fep->rx_bd_base;
1854         for (i=0; i<RX_RING_SIZE; i++) {
1855 
1856                 /* Initialize the BD for every fragment in the page.
1857                 */
1858                 bdp->cbd_sc = BD_ENET_RX_EMPTY;
1859                 bdp++;
1860         }
1861 
1862         /* Set the last buffer to wrap.
1863         */
1864         bdp--;
1865         bdp->cbd_sc |= BD_SC_WRAP;
1866 
1867         /* ...and the same for transmmit.
1868         */
1869         bdp = fep->tx_bd_base;
1870         for (i=0; i<TX_RING_SIZE; i++) {
1871 
1872                 /* Initialize the BD for every fragment in the page.
1873                 */
1874                 bdp->cbd_sc = 0;
1875                 bdp->cbd_bufaddr = 0;
1876                 bdp++;
1877         }
1878 
1879         /* Set the last buffer to wrap.
1880         */
1881         bdp--;
1882         bdp->cbd_sc |= BD_SC_WRAP;
1883 
1884         /* Enable MII mode.
1885         */
1886         if (duplex) {
1887                 fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE;        /* MII enable */
1888                 fecp->fec_x_cntrl = FEC_TCNTRL_FDEN;            /* FD enable */
1889         }
1890         else {
1891                 fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT;
1892                 fecp->fec_x_cntrl = 0;
1893         }
1894         fep->full_duplex = duplex;
1895 
1896         /* Enable big endian and don't care about SDMA FC.
1897         */
1898         fecp->fec_fun_code = 0x78000000;
1899 
1900 #ifdef  CONFIG_USE_MDIO
1901         /* Set MII speed.
1902         */
1903         fecp->fec_mii_speed = fep->phy_speed;
1904 #endif  /* CONFIG_USE_MDIO */
1905 
1906         /* Clear any outstanding interrupt.
1907         */
1908         fecp->fec_ievent = 0xffc0;
1909 
1910         fecp->fec_ivec = (FEC_INTERRUPT/2) << 29;
1911 
1912         /* Enable interrupts we wish to service.
1913         */
1914         fecp->fec_imask = ( FEC_ENET_TXF | FEC_ENET_TXB |
1915                             FEC_ENET_RXF | FEC_ENET_RXB | FEC_ENET_MII );
1916 
1917         /* And last, enable the transmit and receive processing.
1918         */
1919         fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN;
1920         fecp->fec_r_des_active = 0x01000000;
1921 }
1922 
1923 static void
1924 fec_stop(struct net_device *dev)
1925 {
1926         volatile        immap_t *immap;
1927         volatile        fec_t   *fecp;
1928         struct fec_enet_private *fep;
1929         int i;
1930 
1931         immap = (immap_t *)IMAP_ADDR;   /* pointer to internal registers */
1932 
1933         fecp = &(immap->im_cpm.cp_fec);
1934 
1935         if ((fecp->fec_ecntrl & FEC_ECNTRL_ETHER_EN) == 0)
1936                 return; /* already down */
1937 
1938         fep = dev->priv;
1939 
1940 
1941         fecp->fec_x_cntrl = 0x01;       /* Graceful transmit stop */
1942 
1943         for (i = 0;
1944              ((fecp->fec_ievent & 0x10000000) == 0) && (i < FEC_RESET_DELAY);
1945              ++i) {
1946                 udelay(1);
1947         }
1948         if (i == FEC_RESET_DELAY) {
1949                 printk ("FEC timeout on graceful transmit stop\n");
1950         }
1951 
1952         /* Clear outstanding MII command interrupts.
1953         */
1954         fecp->fec_ievent = FEC_ENET_MII;
1955 
1956         /* Enable MII command finished interrupt
1957         */
1958         fecp->fec_ivec = (FEC_INTERRUPT/2) << 29;
1959         fecp->fec_imask = FEC_ENET_MII;
1960 
1961 #ifdef  CONFIG_USE_MDIO
1962         /* Set MII speed.
1963         */
1964         fecp->fec_mii_speed = fep->phy_speed;
1965 #endif  /* CONFIG_USE_MDIO */
1966 
1967         /* Disable FEC
1968         */
1969         fecp->fec_ecntrl &= ~(FEC_ECNTRL_ETHER_EN);
1970 }
1971 

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