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Linux/arch/ppc/platforms/4xx/ocotea.c

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  1 /*
  2  * arch/ppc/platforms/ocotea.c
  3  *
  4  * Ocotea board specific routines
  5  *
  6  * Matt Porter <mporter@mvista.com>
  7  *
  8  * Copyright 2003 MontaVista Software Inc.
  9  *
 10  * This program is free software; you can redistribute  it and/or modify it
 11  * under  the terms of  the GNU General  Public License as published by the
 12  * Free Software Foundation;  either version 2 of the  License, or (at your
 13  * option) any later version.
 14  */
 15 
 16 #include <linux/config.h>
 17 #include <linux/stddef.h>
 18 #include <linux/kernel.h>
 19 #include <linux/init.h>
 20 #include <linux/errno.h>
 21 #include <linux/reboot.h>
 22 #include <linux/pci.h>
 23 #include <linux/kdev_t.h>
 24 #include <linux/types.h>
 25 #include <linux/major.h>
 26 #include <linux/blkdev.h>
 27 #include <linux/console.h>
 28 #include <linux/delay.h>
 29 #include <linux/ide.h>
 30 #include <linux/initrd.h>
 31 #include <linux/irq.h>
 32 #include <linux/seq_file.h>
 33 #include <linux/root_dev.h>
 34 #include <linux/tty.h>
 35 #include <linux/serial.h>
 36 #include <linux/serial_core.h>
 37 
 38 #include <asm/system.h>
 39 #include <asm/pgtable.h>
 40 #include <asm/page.h>
 41 #include <asm/dma.h>
 42 #include <asm/io.h>
 43 #include <asm/machdep.h>
 44 #include <asm/pci-bridge.h>
 45 #include <asm/time.h>
 46 #include <asm/todc.h>
 47 #include <asm/bootinfo.h>
 48 #include <asm/ppc4xx_pic.h>
 49 
 50 extern void abort(void);
 51 
 52 /* Global Variables */
 53 bd_t __res;
 54 
 55 static void __init
 56 ocotea_calibrate_decr(void)
 57 {
 58         unsigned int freq;
 59 
 60         freq = OCOTEA_SYSCLK;
 61 
 62         tb_ticks_per_jiffy = freq / HZ;
 63         tb_to_us = mulhwu_scale_factor(freq, 1000000);
 64 
 65         /* Set the time base to zero */
 66         mtspr(SPRN_TBWL, 0);
 67         mtspr(SPRN_TBWU, 0);
 68 
 69         /* Clear any pending timer interrupts */
 70         mtspr(SPRN_TSR, TSR_ENW | TSR_WIS | TSR_DIS | TSR_FIS);
 71 
 72         /* Enable decrementer interrupt */
 73         mtspr(SPRN_TCR, TCR_DIE);
 74 }
 75 
 76 static int
 77 ocotea_show_cpuinfo(struct seq_file *m)
 78 {
 79         seq_printf(m, "vendor\t\t: IBM\n");
 80         seq_printf(m, "machine\t\t: PPC440GX EVB (Ocotea)\n");
 81 
 82         return 0;
 83 }
 84 static inline int
 85 ocotea_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
 86 {
 87         static char pci_irq_table[][4] =
 88         /*
 89          *      PCI IDSEL/INTPIN->INTLINE
 90          *         A   B   C   D
 91          */
 92         {
 93                 { 23, 23, 23, 23 },     /* IDSEL 1 - PCI Slot 0 */
 94                 { 24, 24, 24, 24 },     /* IDSEL 2 - PCI Slot 1 */
 95                 { 25, 25, 25, 25 },     /* IDSEL 3 - PCI Slot 2 */
 96                 { 26, 26, 26, 26 },     /* IDSEL 4 - PCI Slot 3 */
 97         };
 98 
 99         const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
100         return PCI_IRQ_TABLE_LOOKUP;
101 }
102 
103 #define PCIX_READW(offset) \
104         (readw((u32)pcix_reg_base+offset))
105 
106 #define PCIX_WRITEW(value, offset) \
107         (writew(value, (u32)pcix_reg_base+offset))
108 
109 #define PCIX_WRITEL(value, offset) \
110         (writel(value, (u32)pcix_reg_base+offset))
111 
112 /*
113  * FIXME: This is only here to "make it work".  This will move
114  * to a ibm_pcix.c which will contain a generic IBM PCIX bridge
115  * configuration library. -Matt
116  */
117 static void __init
118 ocotea_setup_pcix(void)
119 {
120         void *pcix_reg_base;
121 
122         pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX0_REG_SIZE);
123 
124         /* Enable PCIX0 I/O, Mem, and Busmaster cycles */
125         PCIX_WRITEW(PCIX_READW(PCIX0_COMMAND) | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, PCIX0_COMMAND);
126 
127         /* Disable all windows */
128         PCIX_WRITEL(0, PCIX0_POM0SA);
129         PCIX_WRITEL(0, PCIX0_POM1SA);
130         PCIX_WRITEL(0, PCIX0_POM2SA);
131         PCIX_WRITEL(0, PCIX0_PIM0SA);
132         PCIX_WRITEL(0, PCIX0_PIM0SAH);
133         PCIX_WRITEL(0, PCIX0_PIM1SA);
134         PCIX_WRITEL(0, PCIX0_PIM2SA);
135         PCIX_WRITEL(0, PCIX0_PIM2SAH);
136 
137         /* Setup 2GB PLB->PCI outbound mem window (3_8000_0000->0_8000_0000) */
138         PCIX_WRITEL(0x00000003, PCIX0_POM0LAH);
139         PCIX_WRITEL(0x80000000, PCIX0_POM0LAL);
140         PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH);
141         PCIX_WRITEL(0x80000000, PCIX0_POM0PCIAL);
142         PCIX_WRITEL(0x80000001, PCIX0_POM0SA);
143 
144         /* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */
145         PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH);
146         PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL);
147         PCIX_WRITEL(0xe0000007, PCIX0_PIM0SA);
148 
149         eieio();
150 }
151 
152 static void __init
153 ocotea_setup_hose(void)
154 {
155         struct pci_controller *hose;
156 
157         /* Configure windows on the PCI-X host bridge */
158         ocotea_setup_pcix();
159 
160         hose = pcibios_alloc_controller();
161 
162         if (!hose)
163                 return;
164 
165         hose->first_busno = 0;
166         hose->last_busno = 0xff;
167 
168         hose->pci_mem_offset = OCOTEA_PCI_MEM_OFFSET;
169 
170         pci_init_resource(&hose->io_resource,
171                         OCOTEA_PCI_LOWER_IO,
172                         OCOTEA_PCI_UPPER_IO,
173                         IORESOURCE_IO,
174                         "PCI host bridge");
175 
176         pci_init_resource(&hose->mem_resources[0],
177                         OCOTEA_PCI_LOWER_MEM,
178                         OCOTEA_PCI_UPPER_MEM,
179                         IORESOURCE_MEM,
180                         "PCI host bridge");
181 
182         hose->io_space.start = OCOTEA_PCI_LOWER_IO;
183         hose->io_space.end = OCOTEA_PCI_UPPER_IO;
184         hose->mem_space.start = OCOTEA_PCI_LOWER_MEM;
185         hose->mem_space.end = OCOTEA_PCI_UPPER_MEM;
186         isa_io_base =
187                 (unsigned long)ioremap64(OCOTEA_PCI_IO_BASE, OCOTEA_PCI_IO_SIZE);
188         hose->io_base_virt = (void *)isa_io_base;
189 
190         setup_indirect_pci(hose,
191                         OCOTEA_PCI_CFGA_PLB32,
192                         OCOTEA_PCI_CFGD_PLB32);
193         hose->set_cfg_type = 1;
194 
195         hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
196 
197         ppc_md.pci_swizzle = common_swizzle;
198         ppc_md.pci_map_irq = ocotea_map_irq;
199 }
200 
201 
202 TODC_ALLOC();
203 
204 static void __init
205 ocotea_early_serial_map(void)
206 {
207         struct uart_port port;
208 
209         /* Setup ioremapped serial port access */
210         memset(&port, 0, sizeof(port));
211         port.membase = ioremap64(PPC440GX_UART0_ADDR, 8);
212         port.irq = 0;
213         port.uartclk = BASE_BAUD * 16;
214         port.regshift = 0;
215         port.iotype = SERIAL_IO_MEM;
216         port.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
217         port.line = 0;
218 
219         if (early_serial_setup(&port) != 0) {
220                 printk("Early serial init of port 0 failed\n");
221         }
222 
223         port.membase = ioremap64(PPC440GX_UART1_ADDR, 8);
224         port.irq = 1;
225         port.line = 1;
226 
227         if (early_serial_setup(&port) != 0) {
228                 printk("Early serial init of port 1 failed\n");
229         }
230 }
231 
232 static void __init
233 ocotea_setup_arch(void)
234 {
235         unsigned char *addr;
236         unsigned long long mac64;
237 
238         /* Retrieve MAC addresses from flash */
239         addr = ioremap64(OCOTEA_MAC_BASE, OCOTEA_MAC_SIZE);
240         mac64 = simple_strtoull(addr, 0, 16);
241         memcpy(__res.bi_enetaddr[0], (char *)&mac64+2, 6);
242         mac64 = simple_strtoull(addr+OCOTEA_MAC1_OFFSET, 0, 16);
243         memcpy(__res.bi_enetaddr[1], (char *)&mac64+2, 6);
244         iounmap(addr);
245 
246 #if !defined(CONFIG_BDI_SWITCH)
247         /*
248          * The Abatron BDI JTAG debugger does not tolerate others
249          * mucking with the debug registers.
250          */
251         mtspr(SPRN_DBCR0, (DBCR0_TDE | DBCR0_IDM));
252 #endif
253 
254         /* Setup TODC access */
255         TODC_INIT(TODC_TYPE_DS1743,
256                         0,
257                         0,
258                         ioremap64(OCOTEA_RTC_ADDR, OCOTEA_RTC_SIZE),
259                         8);
260 
261         /* init to some ~sane value until calibrate_delay() runs */
262         loops_per_jiffy = 50000000/HZ;
263 
264         /* Setup PCI host bridge */
265         ocotea_setup_hose();
266 
267 #ifdef CONFIG_BLK_DEV_INITRD
268         if (initrd_start)
269                 ROOT_DEV = Root_RAM0;
270         else
271 #endif
272 #ifdef CONFIG_ROOT_NFS
273                 ROOT_DEV = Root_NFS;
274 #else
275                 ROOT_DEV = Root_HDA1;
276 #endif
277 
278 #ifdef CONFIG_DUMMY_CONSOLE
279         conswitchp = &dummy_con;
280 #endif
281 
282         ocotea_early_serial_map();
283 
284         /* Identify the system */
285         printk("IBM Ocotea port (MontaVista Software, Inc. <source@mvista.com>)\n");
286 }
287 
288 static void
289 ocotea_restart(char *cmd)
290 {
291         local_irq_disable();
292         abort();
293 }
294 
295 static void
296 ocotea_power_off(void)
297 {
298         local_irq_disable();
299         for(;;);
300 }
301 
302 static void
303 ocotea_halt(void)
304 {
305         local_irq_disable();
306         for(;;);
307 }
308 
309 /*
310  * Read the 440GX memory controller to get size of system memory.
311  */
312 static unsigned long __init
313 ocotea_find_end_of_memory(void)
314 {
315         u32 i, bank_config;
316         u32 mem_size = 0;
317 
318         for (i=0; i<4; i++)
319         {
320                 switch (i)
321                 {
322                         case 0:
323                                 mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B0CR);
324                                 break;
325                         case 1:
326                                 mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B1CR);
327                                 break;
328                         case 2:
329                                 mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B2CR);
330                                 break;
331                         case 3:
332                                 mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B3CR);
333                                 break;
334                 }
335 
336                 bank_config = mfdcr(DCRN_SDRAM0_CFGDATA);
337 
338                 if (!(bank_config & SDRAM_CONFIG_BANK_ENABLE))
339                         continue;
340                 switch (SDRAM_CONFIG_BANK_SIZE(bank_config))
341                 {
342                         case SDRAM_CONFIG_SIZE_8M:
343                                 mem_size += PPC44x_MEM_SIZE_8M;
344                                 break;
345                         case SDRAM_CONFIG_SIZE_16M:
346                                 mem_size += PPC44x_MEM_SIZE_16M;
347                                 break;
348                         case SDRAM_CONFIG_SIZE_32M:
349                                 mem_size += PPC44x_MEM_SIZE_32M;
350                                 break;
351                         case SDRAM_CONFIG_SIZE_64M:
352                                 mem_size += PPC44x_MEM_SIZE_64M;
353                                 break;
354                         case SDRAM_CONFIG_SIZE_128M:
355                                 mem_size += PPC44x_MEM_SIZE_128M;
356                                 break;
357                         case SDRAM_CONFIG_SIZE_256M:
358                                 mem_size += PPC44x_MEM_SIZE_256M;
359                                 break;
360                         case SDRAM_CONFIG_SIZE_512M:
361                                 mem_size += PPC44x_MEM_SIZE_512M;
362                                 break;
363                 }
364         }
365         return mem_size;
366 }
367 
368 static void __init
369 ocotea_init_irq(void)
370 {
371         int i;
372 
373         /* Enable PPC440GP interrupt compatibility mode */
374         SDR_WRITE(DCRN_SDR_MFR,SDR_READ(DCRN_SDR_MFR) | DCRN_SDR_MFR_PCM);
375 
376         ppc4xx_pic_init();
377 
378         for (i = 0; i < NR_IRQS; i++)
379                 irq_desc[i].handler = ppc4xx_pic;
380 }
381 
382 #ifdef CONFIG_SERIAL_TEXT_DEBUG
383 #include <linux/serialP.h>
384 #include <linux/serial_reg.h>
385 #include <asm/serial.h>
386 struct serial_state rs_table[RS_TABLE_SIZE] = {
387         SERIAL_PORT_DFNS        /* Defined in <asm/serial.h> */
388 };
389 
390 static void
391 ocotea_progress(char *s, unsigned short hex)
392 {
393         volatile char c;
394         volatile unsigned long com_port;
395         u16 shift;
396 
397         com_port = (unsigned long)rs_table[0].iomem_base;
398         shift = rs_table[0].iomem_reg_shift;
399 
400         while ((c = *s++) != 0) {
401                 while ((*((volatile unsigned char *)com_port +
402                                 (UART_LSR << shift)) & UART_LSR_THRE) == 0)
403                         ;
404                 *(volatile unsigned char *)com_port = c;
405 
406         }
407 
408         /* Send LF/CR to pretty up output */
409         while ((*((volatile unsigned char *)com_port +
410                 (UART_LSR << shift)) & UART_LSR_THRE) == 0)
411                 ;
412         *(volatile unsigned char *)com_port = '\r';
413         while ((*((volatile unsigned char *)com_port +
414                 (UART_LSR << shift)) & UART_LSR_THRE) == 0)
415                 ;
416         *(volatile unsigned char *)com_port = '\n';
417 }
418 #endif /* CONFIG_SERIAL_TEXT_DEBUG */
419 
420 #if 0
421 static void __init
422 ocotea_map_io(void)
423 {
424         io_block_mapping(0xe0000000, 0x0000000140000000,
425                          0x00001000, _PAGE_IO);
426 }
427 #endif
428 
429 void __init platform_init(unsigned long r3, unsigned long r4,
430                 unsigned long r5, unsigned long r6, unsigned long r7)
431 {
432         parse_bootinfo((struct bi_record *) (r3 + KERNELBASE));
433 
434         ppc_md.setup_arch = ocotea_setup_arch;
435         ppc_md.show_cpuinfo = ocotea_show_cpuinfo;
436         ppc_md.init_IRQ = ocotea_init_irq;
437         ppc_md.get_irq = NULL;          /* Set in ppc4xx_pic_init() */
438 
439         ppc_md.find_end_of_memory = ocotea_find_end_of_memory;
440 
441         ppc_md.restart = ocotea_restart;
442         ppc_md.power_off = ocotea_power_off;
443         ppc_md.halt = ocotea_halt;
444 
445         ppc_md.calibrate_decr = ocotea_calibrate_decr;
446         ppc_md.time_init = todc_time_init;
447         ppc_md.set_rtc_time = todc_set_rtc_time;
448         ppc_md.get_rtc_time = todc_get_rtc_time;
449 
450         ppc_md.nvram_read_val = todc_direct_read_val;
451         ppc_md.nvram_write_val = todc_direct_write_val;
452 
453 #ifdef CONFIG_SERIAL_TEXT_DEBUG
454         ppc_md.progress = ocotea_progress;
455 #endif /* CONFIG_SERIAL_TEXT_DEBUG */
456 #ifdef CONFIG_KGDB
457         ppc_md.early_serial_map = ocotea_early_serial_map;
458 #endif
459 }
460 

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