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Linux/arch/sh/include/asm/pgtable.h

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  1 /*
  2  * This file contains the functions and defines necessary to modify and
  3  * use the SuperH page table tree.
  4  *
  5  * Copyright (C) 1999 Niibe Yutaka
  6  * Copyright (C) 2002 - 2007 Paul Mundt
  7  *
  8  * This file is subject to the terms and conditions of the GNU General
  9  * Public License.  See the file "COPYING" in the main directory of this
 10  * archive for more details.
 11  */
 12 #ifndef __ASM_SH_PGTABLE_H
 13 #define __ASM_SH_PGTABLE_H
 14 
 15 #ifdef CONFIG_X2TLB
 16 #include <asm/pgtable-3level.h>
 17 #else
 18 #include <asm/pgtable-2level.h>
 19 #endif
 20 #include <asm/page.h>
 21 #include <asm/mmu.h>
 22 
 23 #ifndef __ASSEMBLY__
 24 #include <asm/addrspace.h>
 25 #include <asm/fixmap.h>
 26 
 27 /*
 28  * ZERO_PAGE is a global shared page that is always zero: used
 29  * for zero-mapped memory areas etc..
 30  */
 31 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
 32 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
 33 
 34 #endif /* !__ASSEMBLY__ */
 35 
 36 /*
 37  * Effective and physical address definitions, to aid with sign
 38  * extension.
 39  */
 40 #define NEFF            32
 41 #define NEFF_SIGN       (1LL << (NEFF - 1))
 42 #define NEFF_MASK       (-1LL << NEFF)
 43 
 44 static inline unsigned long long neff_sign_extend(unsigned long val)
 45 {
 46         unsigned long long extended = val;
 47         return (extended & NEFF_SIGN) ? (extended | NEFF_MASK) : extended;
 48 }
 49 
 50 #ifdef CONFIG_29BIT
 51 #define NPHYS           29
 52 #else
 53 #define NPHYS           32
 54 #endif
 55 
 56 #define NPHYS_SIGN      (1LL << (NPHYS - 1))
 57 #define NPHYS_MASK      (-1LL << NPHYS)
 58 
 59 #define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
 60 #define PGDIR_MASK      (~(PGDIR_SIZE-1))
 61 
 62 /* Entries per level */
 63 #define PTRS_PER_PTE    (PAGE_SIZE / (1 << PTE_MAGNITUDE))
 64 
 65 #define FIRST_USER_ADDRESS      0UL
 66 
 67 #define PHYS_ADDR_MASK29                0x1fffffff
 68 #define PHYS_ADDR_MASK32                0xffffffff
 69 
 70 static inline unsigned long phys_addr_mask(void)
 71 {
 72         /* Is the MMU in 29bit mode? */
 73         if (__in_29bit_mode())
 74                 return PHYS_ADDR_MASK29;
 75 
 76         return PHYS_ADDR_MASK32;
 77 }
 78 
 79 #define PTE_PHYS_MASK           (phys_addr_mask() & PAGE_MASK)
 80 #define PTE_FLAGS_MASK          (~(PTE_PHYS_MASK) << PAGE_SHIFT)
 81 
 82 #ifdef CONFIG_SUPERH32
 83 #define VMALLOC_START   (P3SEG)
 84 #else
 85 #define VMALLOC_START   (0xf0000000)
 86 #endif
 87 #define VMALLOC_END     (FIXADDR_START-2*PAGE_SIZE)
 88 
 89 #if defined(CONFIG_SUPERH32)
 90 #include <asm/pgtable_32.h>
 91 #else
 92 #include <asm/pgtable_64.h>
 93 #endif
 94 
 95 /*
 96  * SH-X and lower (legacy) SuperH parts (SH-3, SH-4, some SH-4A) can't do page
 97  * protection for execute, and considers it the same as a read. Also, write
 98  * permission implies read permission. This is the closest we can get..
 99  *
100  * SH-X2 (SH7785) and later parts take this to the opposite end of the extreme,
101  * not only supporting separate execute, read, and write bits, but having
102  * completely separate permission bits for user and kernel space.
103  */
104          /*xwr*/
105 #define __P000  PAGE_NONE
106 #define __P001  PAGE_READONLY
107 #define __P010  PAGE_COPY
108 #define __P011  PAGE_COPY
109 #define __P100  PAGE_EXECREAD
110 #define __P101  PAGE_EXECREAD
111 #define __P110  PAGE_COPY
112 #define __P111  PAGE_COPY
113 
114 #define __S000  PAGE_NONE
115 #define __S001  PAGE_READONLY
116 #define __S010  PAGE_WRITEONLY
117 #define __S011  PAGE_SHARED
118 #define __S100  PAGE_EXECREAD
119 #define __S101  PAGE_EXECREAD
120 #define __S110  PAGE_RWX
121 #define __S111  PAGE_RWX
122 
123 typedef pte_t *pte_addr_t;
124 
125 #define kern_addr_valid(addr)   (1)
126 
127 #define pte_pfn(x)              ((unsigned long)(((x).pte_low >> PAGE_SHIFT)))
128 
129 /*
130  * Initialise the page table caches
131  */
132 extern void pgtable_cache_init(void);
133 
134 struct vm_area_struct;
135 struct mm_struct;
136 
137 extern void __update_cache(struct vm_area_struct *vma,
138                            unsigned long address, pte_t pte);
139 extern void __update_tlb(struct vm_area_struct *vma,
140                          unsigned long address, pte_t pte);
141 
142 static inline void
143 update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
144 {
145         pte_t pte = *ptep;
146         __update_cache(vma, address, pte);
147         __update_tlb(vma, address, pte);
148 }
149 
150 extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
151 extern void paging_init(void);
152 extern void page_table_range_init(unsigned long start, unsigned long end,
153                                   pgd_t *pgd);
154 
155 /* arch/sh/mm/mmap.c */
156 #define HAVE_ARCH_UNMAPPED_AREA
157 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
158 
159 #define __HAVE_ARCH_PTE_SPECIAL
160 
161 #include <asm-generic/pgtable.h>
162 
163 #endif /* __ASM_SH_PGTABLE_H */
164 

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