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TOMOYO Linux Cross Reference
Linux/arch/sh/kernel/cpu/sh4a/setup-sh7723.c

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  1 /*
  2  * SH7723 Setup
  3  *
  4  *  Copyright (C) 2008  Paul Mundt
  5  *
  6  * This file is subject to the terms and conditions of the GNU General Public
  7  * License.  See the file "COPYING" in the main directory of this archive
  8  * for more details.
  9  */
 10 #include <linux/platform_device.h>
 11 #include <linux/init.h>
 12 #include <linux/serial.h>
 13 #include <linux/mm.h>
 14 #include <linux/serial_sci.h>
 15 #include <linux/uio_driver.h>
 16 #include <linux/usb/r8a66597.h>
 17 #include <linux/sh_timer.h>
 18 #include <linux/sh_intc.h>
 19 #include <linux/io.h>
 20 #include <asm/clock.h>
 21 #include <asm/mmzone.h>
 22 #include <cpu/sh7723.h>
 23 
 24 /* Serial */
 25 static struct plat_sci_port scif0_platform_data = {
 26         .port_reg       = 0xa4050160,
 27         .flags          = UPF_BOOT_AUTOCONF,
 28         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
 29         .type           = PORT_SCIF,
 30         .regtype        = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
 31 };
 32 
 33 static struct resource scif0_resources[] = {
 34         DEFINE_RES_MEM(0xffe00000, 0x100),
 35         DEFINE_RES_IRQ(evt2irq(0xc00)),
 36 };
 37 
 38 static struct platform_device scif0_device = {
 39         .name           = "sh-sci",
 40         .id             = 0,
 41         .resource       = scif0_resources,
 42         .num_resources  = ARRAY_SIZE(scif0_resources),
 43         .dev            = {
 44                 .platform_data  = &scif0_platform_data,
 45         },
 46 };
 47 
 48 static struct plat_sci_port scif1_platform_data = {
 49         .port_reg       = SCIx_NOT_SUPPORTED,
 50         .flags          = UPF_BOOT_AUTOCONF,
 51         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
 52         .type           = PORT_SCIF,
 53         .regtype        = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
 54 };
 55 
 56 static struct resource scif1_resources[] = {
 57         DEFINE_RES_MEM(0xffe10000, 0x100),
 58         DEFINE_RES_IRQ(evt2irq(0xc20)),
 59 };
 60 
 61 static struct platform_device scif1_device = {
 62         .name           = "sh-sci",
 63         .id             = 1,
 64         .resource       = scif1_resources,
 65         .num_resources  = ARRAY_SIZE(scif1_resources),
 66         .dev            = {
 67                 .platform_data  = &scif1_platform_data,
 68         },
 69 };
 70 
 71 static struct plat_sci_port scif2_platform_data = {
 72         .port_reg       = SCIx_NOT_SUPPORTED,
 73         .flags          = UPF_BOOT_AUTOCONF,
 74         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
 75         .type           = PORT_SCIF,
 76         .regtype        = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
 77 };
 78 
 79 static struct resource scif2_resources[] = {
 80         DEFINE_RES_MEM(0xffe20000, 0x100),
 81         DEFINE_RES_IRQ(evt2irq(0xc40)),
 82 };
 83 
 84 static struct platform_device scif2_device = {
 85         .name           = "sh-sci",
 86         .id             = 2,
 87         .resource       = scif2_resources,
 88         .num_resources  = ARRAY_SIZE(scif2_resources),
 89         .dev            = {
 90                 .platform_data  = &scif2_platform_data,
 91         },
 92 };
 93 
 94 static struct plat_sci_port scif3_platform_data = {
 95         .flags          = UPF_BOOT_AUTOCONF,
 96         .port_reg       = SCIx_NOT_SUPPORTED,
 97         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
 98         .sampling_rate  = 8,
 99         .type           = PORT_SCIFA,
100 };
101 
102 static struct resource scif3_resources[] = {
103         DEFINE_RES_MEM(0xa4e30000, 0x100),
104         DEFINE_RES_IRQ(evt2irq(0x900)),
105 };
106 
107 static struct platform_device scif3_device = {
108         .name           = "sh-sci",
109         .id             = 3,
110         .resource       = scif3_resources,
111         .num_resources  = ARRAY_SIZE(scif3_resources),
112         .dev            = {
113                 .platform_data  = &scif3_platform_data,
114         },
115 };
116 
117 static struct plat_sci_port scif4_platform_data = {
118         .port_reg       = SCIx_NOT_SUPPORTED,
119         .flags          = UPF_BOOT_AUTOCONF,
120         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
121         .sampling_rate  = 8,
122         .type           = PORT_SCIFA,
123 };
124 
125 static struct resource scif4_resources[] = {
126         DEFINE_RES_MEM(0xa4e40000, 0x100),
127         DEFINE_RES_IRQ(evt2irq(0xd00)),
128 };
129 
130 static struct platform_device scif4_device = {
131         .name           = "sh-sci",
132         .id             = 4,
133         .resource       = scif4_resources,
134         .num_resources  = ARRAY_SIZE(scif4_resources),
135         .dev            = {
136                 .platform_data  = &scif4_platform_data,
137         },
138 };
139 
140 static struct plat_sci_port scif5_platform_data = {
141         .port_reg       = SCIx_NOT_SUPPORTED,
142         .flags          = UPF_BOOT_AUTOCONF,
143         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
144         .sampling_rate  = 8,
145         .type           = PORT_SCIFA,
146 };
147 
148 static struct resource scif5_resources[] = {
149         DEFINE_RES_MEM(0xa4e50000, 0x100),
150         DEFINE_RES_IRQ(evt2irq(0xfa0)),
151 };
152 
153 static struct platform_device scif5_device = {
154         .name           = "sh-sci",
155         .id             = 5,
156         .resource       = scif5_resources,
157         .num_resources  = ARRAY_SIZE(scif5_resources),
158         .dev            = {
159                 .platform_data  = &scif5_platform_data,
160         },
161 };
162 
163 static struct uio_info vpu_platform_data = {
164         .name = "VPU5",
165         .version = "",
166         .irq = evt2irq(0x980),
167 };
168 
169 static struct resource vpu_resources[] = {
170         [0] = {
171                 .name   = "VPU",
172                 .start  = 0xfe900000,
173                 .end    = 0xfe902807,
174                 .flags  = IORESOURCE_MEM,
175         },
176         [1] = {
177                 /* place holder for contiguous memory */
178         },
179 };
180 
181 static struct platform_device vpu_device = {
182         .name           = "uio_pdrv_genirq",
183         .id             = 0,
184         .dev = {
185                 .platform_data  = &vpu_platform_data,
186         },
187         .resource       = vpu_resources,
188         .num_resources  = ARRAY_SIZE(vpu_resources),
189 };
190 
191 static struct uio_info veu0_platform_data = {
192         .name = "VEU2H",
193         .version = "",
194         .irq = evt2irq(0x8c0),
195 };
196 
197 static struct resource veu0_resources[] = {
198         [0] = {
199                 .name   = "VEU2H0",
200                 .start  = 0xfe920000,
201                 .end    = 0xfe92027b,
202                 .flags  = IORESOURCE_MEM,
203         },
204         [1] = {
205                 /* place holder for contiguous memory */
206         },
207 };
208 
209 static struct platform_device veu0_device = {
210         .name           = "uio_pdrv_genirq",
211         .id             = 1,
212         .dev = {
213                 .platform_data  = &veu0_platform_data,
214         },
215         .resource       = veu0_resources,
216         .num_resources  = ARRAY_SIZE(veu0_resources),
217 };
218 
219 static struct uio_info veu1_platform_data = {
220         .name = "VEU2H",
221         .version = "",
222         .irq = evt2irq(0x560),
223 };
224 
225 static struct resource veu1_resources[] = {
226         [0] = {
227                 .name   = "VEU2H1",
228                 .start  = 0xfe924000,
229                 .end    = 0xfe92427b,
230                 .flags  = IORESOURCE_MEM,
231         },
232         [1] = {
233                 /* place holder for contiguous memory */
234         },
235 };
236 
237 static struct platform_device veu1_device = {
238         .name           = "uio_pdrv_genirq",
239         .id             = 2,
240         .dev = {
241                 .platform_data  = &veu1_platform_data,
242         },
243         .resource       = veu1_resources,
244         .num_resources  = ARRAY_SIZE(veu1_resources),
245 };
246 
247 static struct sh_timer_config cmt_platform_data = {
248         .channels_mask = 0x20,
249 };
250 
251 static struct resource cmt_resources[] = {
252         DEFINE_RES_MEM(0x044a0000, 0x70),
253         DEFINE_RES_IRQ(evt2irq(0xf00)),
254 };
255 
256 static struct platform_device cmt_device = {
257         .name           = "sh-cmt-32",
258         .id             = 0,
259         .dev = {
260                 .platform_data  = &cmt_platform_data,
261         },
262         .resource       = cmt_resources,
263         .num_resources  = ARRAY_SIZE(cmt_resources),
264 };
265 
266 static struct sh_timer_config tmu0_platform_data = {
267         .channels_mask = 7,
268 };
269 
270 static struct resource tmu0_resources[] = {
271         DEFINE_RES_MEM(0xffd80000, 0x2c),
272         DEFINE_RES_IRQ(evt2irq(0x400)),
273         DEFINE_RES_IRQ(evt2irq(0x420)),
274         DEFINE_RES_IRQ(evt2irq(0x440)),
275 };
276 
277 static struct platform_device tmu0_device = {
278         .name           = "sh-tmu",
279         .id             = 0,
280         .dev = {
281                 .platform_data  = &tmu0_platform_data,
282         },
283         .resource       = tmu0_resources,
284         .num_resources  = ARRAY_SIZE(tmu0_resources),
285 };
286 
287 static struct sh_timer_config tmu1_platform_data = {
288         .channels_mask = 7,
289 };
290 
291 static struct resource tmu1_resources[] = {
292         DEFINE_RES_MEM(0xffd90000, 0x2c),
293         DEFINE_RES_IRQ(evt2irq(0x920)),
294         DEFINE_RES_IRQ(evt2irq(0x940)),
295         DEFINE_RES_IRQ(evt2irq(0x960)),
296 };
297 
298 static struct platform_device tmu1_device = {
299         .name           = "sh-tmu",
300         .id             = 1,
301         .dev = {
302                 .platform_data  = &tmu1_platform_data,
303         },
304         .resource       = tmu1_resources,
305         .num_resources  = ARRAY_SIZE(tmu1_resources),
306 };
307 
308 static struct resource rtc_resources[] = {
309         [0] = {
310                 .start  = 0xa465fec0,
311                 .end    = 0xa465fec0 + 0x58 - 1,
312                 .flags  = IORESOURCE_IO,
313         },
314         [1] = {
315                 /* Period IRQ */
316                 .start  = evt2irq(0xaa0),
317                 .flags  = IORESOURCE_IRQ,
318         },
319         [2] = {
320                 /* Carry IRQ */
321                 .start  = evt2irq(0xac0),
322                 .flags  = IORESOURCE_IRQ,
323         },
324         [3] = {
325                 /* Alarm IRQ */
326                 .start  = evt2irq(0xa80),
327                 .flags  = IORESOURCE_IRQ,
328         },
329 };
330 
331 static struct platform_device rtc_device = {
332         .name           = "sh-rtc",
333         .id             = -1,
334         .num_resources  = ARRAY_SIZE(rtc_resources),
335         .resource       = rtc_resources,
336 };
337 
338 static struct r8a66597_platdata r8a66597_data = {
339         .on_chip = 1,
340 };
341 
342 static struct resource sh7723_usb_host_resources[] = {
343         [0] = {
344                 .start  = 0xa4d80000,
345                 .end    = 0xa4d800ff,
346                 .flags  = IORESOURCE_MEM,
347         },
348         [1] = {
349                 .start  = evt2irq(0xa20),
350                 .end    = evt2irq(0xa20),
351                 .flags  = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
352         },
353 };
354 
355 static struct platform_device sh7723_usb_host_device = {
356         .name           = "r8a66597_hcd",
357         .id             = 0,
358         .dev = {
359                 .dma_mask               = NULL,         /*  not use dma */
360                 .coherent_dma_mask      = 0xffffffff,
361                 .platform_data          = &r8a66597_data,
362         },
363         .num_resources  = ARRAY_SIZE(sh7723_usb_host_resources),
364         .resource       = sh7723_usb_host_resources,
365 };
366 
367 static struct resource iic_resources[] = {
368         [0] = {
369                 .name   = "IIC",
370                 .start  = 0x04470000,
371                 .end    = 0x04470017,
372                 .flags  = IORESOURCE_MEM,
373         },
374         [1] = {
375                 .start  = evt2irq(0xe00),
376                 .end    = evt2irq(0xe60),
377                 .flags  = IORESOURCE_IRQ,
378        },
379 };
380 
381 static struct platform_device iic_device = {
382         .name           = "i2c-sh_mobile",
383         .id             = 0, /* "i2c0" clock */
384         .num_resources  = ARRAY_SIZE(iic_resources),
385         .resource       = iic_resources,
386 };
387 
388 static struct platform_device *sh7723_devices[] __initdata = {
389         &scif0_device,
390         &scif1_device,
391         &scif2_device,
392         &scif3_device,
393         &scif4_device,
394         &scif5_device,
395         &cmt_device,
396         &tmu0_device,
397         &tmu1_device,
398         &rtc_device,
399         &iic_device,
400         &sh7723_usb_host_device,
401         &vpu_device,
402         &veu0_device,
403         &veu1_device,
404 };
405 
406 static int __init sh7723_devices_setup(void)
407 {
408         platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
409         platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
410         platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);
411 
412         return platform_add_devices(sh7723_devices,
413                                     ARRAY_SIZE(sh7723_devices));
414 }
415 arch_initcall(sh7723_devices_setup);
416 
417 static struct platform_device *sh7723_early_devices[] __initdata = {
418         &scif0_device,
419         &scif1_device,
420         &scif2_device,
421         &scif3_device,
422         &scif4_device,
423         &scif5_device,
424         &cmt_device,
425         &tmu0_device,
426         &tmu1_device,
427 };
428 
429 void __init plat_early_device_setup(void)
430 {
431         early_platform_add_devices(sh7723_early_devices,
432                                    ARRAY_SIZE(sh7723_early_devices));
433 }
434 
435 #define RAMCR_CACHE_L2FC        0x0002
436 #define RAMCR_CACHE_L2E         0x0001
437 #define L2_CACHE_ENABLE         (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC)
438 
439 void l2_cache_init(void)
440 {
441         /* Enable L2 cache */
442         __raw_writel(L2_CACHE_ENABLE, RAMCR);
443 }
444 
445 enum {
446         UNUSED=0,
447         ENABLED,
448         DISABLED,
449 
450         /* interrupt sources */
451         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
452         HUDI,
453         DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3,
454         _2DG_TRI,_2DG_INI,_2DG_CEI,
455         DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3,
456         VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI,
457         SCIFA_SCIFA0,
458         VPU_VPUI,
459         TPU_TPUI,
460         ADC_ADI,
461         USB_USI0,
462         RTC_ATI,RTC_PRI,RTC_CUI,
463         DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR,
464         DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR,
465         KEYSC_KEYI,
466         SCIF_SCIF0,SCIF_SCIF1,SCIF_SCIF2,
467         MSIOF_MSIOFI0,MSIOF_MSIOFI1,
468         SCIFA_SCIFA1,
469         FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I,
470         I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI,
471         CMT_CMTI,
472         TSIF_TSIFI,
473         SIU_SIUI,
474         SCIFA_SCIFA2,
475         TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2,
476         IRDA_IRDAI,
477         ATAPI_ATAPII,
478         VEU2H1_VEU2HI,
479         LCDC_LCDCI,
480         TMU1_TUNI0,TMU1_TUNI1,TMU1_TUNI2,
481 
482         /* interrupt groups */
483         DMAC1A, DMAC0A, VIO, DMAC0B, FLCTL, I2C, _2DG,
484         SDHI1, RTC, DMAC1B, SDHI0,
485 };
486 
487 static struct intc_vect vectors[] __initdata = {
488         INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
489         INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
490         INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
491         INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
492 
493         INTC_VECT(DMAC1A_DEI0,0x700),
494         INTC_VECT(DMAC1A_DEI1,0x720),
495         INTC_VECT(DMAC1A_DEI2,0x740),
496         INTC_VECT(DMAC1A_DEI3,0x760),
497 
498         INTC_VECT(_2DG_TRI, 0x780),
499         INTC_VECT(_2DG_INI, 0x7A0),
500         INTC_VECT(_2DG_CEI, 0x7C0),
501 
502         INTC_VECT(DMAC0A_DEI0,0x800),
503         INTC_VECT(DMAC0A_DEI1,0x820),
504         INTC_VECT(DMAC0A_DEI2,0x840),
505         INTC_VECT(DMAC0A_DEI3,0x860),
506 
507         INTC_VECT(VIO_CEUI,0x880),
508         INTC_VECT(VIO_BEUI,0x8A0),
509         INTC_VECT(VIO_VEU2HI,0x8C0),
510         INTC_VECT(VIO_VOUI,0x8E0),
511 
512         INTC_VECT(SCIFA_SCIFA0,0x900),
513         INTC_VECT(VPU_VPUI,0x980),
514         INTC_VECT(TPU_TPUI,0x9A0),
515         INTC_VECT(ADC_ADI,0x9E0),
516         INTC_VECT(USB_USI0,0xA20),
517 
518         INTC_VECT(RTC_ATI,0xA80),
519         INTC_VECT(RTC_PRI,0xAA0),
520         INTC_VECT(RTC_CUI,0xAC0),
521 
522         INTC_VECT(DMAC1B_DEI4,0xB00),
523         INTC_VECT(DMAC1B_DEI5,0xB20),
524         INTC_VECT(DMAC1B_DADERR,0xB40),
525 
526         INTC_VECT(DMAC0B_DEI4,0xB80),
527         INTC_VECT(DMAC0B_DEI5,0xBA0),
528         INTC_VECT(DMAC0B_DADERR,0xBC0),
529 
530         INTC_VECT(KEYSC_KEYI,0xBE0),
531         INTC_VECT(SCIF_SCIF0,0xC00),
532         INTC_VECT(SCIF_SCIF1,0xC20),
533         INTC_VECT(SCIF_SCIF2,0xC40),
534         INTC_VECT(MSIOF_MSIOFI0,0xC80),
535         INTC_VECT(MSIOF_MSIOFI1,0xCA0),
536         INTC_VECT(SCIFA_SCIFA1,0xD00),
537 
538         INTC_VECT(FLCTL_FLSTEI,0xD80),
539         INTC_VECT(FLCTL_FLTENDI,0xDA0),
540         INTC_VECT(FLCTL_FLTREQ0I,0xDC0),
541         INTC_VECT(FLCTL_FLTREQ1I,0xDE0),
542 
543         INTC_VECT(I2C_ALI,0xE00),
544         INTC_VECT(I2C_TACKI,0xE20),
545         INTC_VECT(I2C_WAITI,0xE40),
546         INTC_VECT(I2C_DTEI,0xE60),
547 
548         INTC_VECT(SDHI0, 0xE80),
549         INTC_VECT(SDHI0, 0xEA0),
550         INTC_VECT(SDHI0, 0xEC0),
551 
552         INTC_VECT(CMT_CMTI,0xF00),
553         INTC_VECT(TSIF_TSIFI,0xF20),
554         INTC_VECT(SIU_SIUI,0xF80),
555         INTC_VECT(SCIFA_SCIFA2,0xFA0),
556 
557         INTC_VECT(TMU0_TUNI0,0x400),
558         INTC_VECT(TMU0_TUNI1,0x420),
559         INTC_VECT(TMU0_TUNI2,0x440),
560 
561         INTC_VECT(IRDA_IRDAI,0x480),
562         INTC_VECT(ATAPI_ATAPII,0x4A0),
563 
564         INTC_VECT(SDHI1, 0x4E0),
565         INTC_VECT(SDHI1, 0x500),
566         INTC_VECT(SDHI1, 0x520),
567 
568         INTC_VECT(VEU2H1_VEU2HI,0x560),
569         INTC_VECT(LCDC_LCDCI,0x580),
570 
571         INTC_VECT(TMU1_TUNI0,0x920),
572         INTC_VECT(TMU1_TUNI1,0x940),
573         INTC_VECT(TMU1_TUNI2,0x960),
574 
575 };
576 
577 static struct intc_group groups[] __initdata = {
578         INTC_GROUP(DMAC1A,DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3),
579         INTC_GROUP(DMAC0A,DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3),
580         INTC_GROUP(VIO, VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI),
581         INTC_GROUP(DMAC0B, DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR),
582         INTC_GROUP(FLCTL,FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I),
583         INTC_GROUP(I2C,I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI),
584         INTC_GROUP(_2DG, _2DG_TRI,_2DG_INI,_2DG_CEI),
585         INTC_GROUP(RTC, RTC_ATI,RTC_PRI,RTC_CUI),
586         INTC_GROUP(DMAC1B, DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR),
587 };
588 
589 static struct intc_mask_reg mask_registers[] __initdata = {
590         { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
591           { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0,
592             0, ENABLED, ENABLED, ENABLED } },
593         { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
594           { VIO_VOUI, VIO_VEU2HI,VIO_BEUI,VIO_CEUI,DMAC0A_DEI3,DMAC0A_DEI2,DMAC0A_DEI1,DMAC0A_DEI0 } },
595         { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
596           { 0, 0, 0, VPU_VPUI,0,0,0,SCIFA_SCIFA0 } },
597         { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
598           { DMAC1A_DEI3,DMAC1A_DEI2,DMAC1A_DEI1,DMAC1A_DEI0,0,0,0,IRDA_IRDAI } },
599         { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
600           { 0,TMU0_TUNI2,TMU0_TUNI1,TMU0_TUNI0,VEU2H1_VEU2HI,0,0,LCDC_LCDCI } },
601         { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
602           { KEYSC_KEYI,DMAC0B_DADERR,DMAC0B_DEI5,DMAC0B_DEI4,0,SCIF_SCIF2,SCIF_SCIF1,SCIF_SCIF0 } },
603         { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
604           { 0,0,0,SCIFA_SCIFA1,ADC_ADI,0,MSIOF_MSIOFI1,MSIOF_MSIOFI0 } },
605         { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
606           { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
607             FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
608         { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
609           { 0, ENABLED, ENABLED, ENABLED,
610             0, 0, SCIFA_SCIFA2, SIU_SIUI } },
611         { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
612           { 0, 0, 0, CMT_CMTI, 0, 0, USB_USI0,0 } },
613         { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
614           { 0, DMAC1B_DADERR,DMAC1B_DEI5,DMAC1B_DEI4,0,RTC_ATI,RTC_PRI,RTC_CUI } },
615         { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
616           { 0,_2DG_CEI,_2DG_INI,_2DG_TRI,0,TPU_TPUI,0,TSIF_TSIFI } },
617         { 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */
618           { 0,0,0,0,0,0,0,ATAPI_ATAPII } },
619         { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
620           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
621 };
622 
623 static struct intc_prio_reg prio_registers[] __initdata = {
624         { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2, IRDA_IRDAI } },
625         { 0xa4080004, 0, 16, 4, /* IPRB */ { VEU2H1_VEU2HI, LCDC_LCDCI, DMAC1A, 0} },
626         { 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2, 0} },
627         { 0xa408000c, 0, 16, 4, /* IPRD */ { } },
628         { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0A, VIO, SCIFA_SCIFA0, VPU_VPUI } },
629         { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC_KEYI, DMAC0B, USB_USI0, CMT_CMTI } },
630         { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2,0 } },
631         { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0,MSIOF_MSIOFI1, FLCTL, I2C } },
632         { 0xa4080020, 0, 16, 4, /* IPRI */ { SCIFA_SCIFA1,0,TSIF_TSIFI,_2DG } },
633         { 0xa4080024, 0, 16, 4, /* IPRJ */ { ADC_ADI,0,SIU_SIUI,SDHI1 } },
634         { 0xa4080028, 0, 16, 4, /* IPRK */ { RTC,DMAC1B,0,SDHI0 } },
635         { 0xa408002c, 0, 16, 4, /* IPRL */ { SCIFA_SCIFA2,0,TPU_TPUI,ATAPI_ATAPII } },
636         { 0xa4140010, 0, 32, 4, /* INTPRI00 */
637           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
638 };
639 
640 static struct intc_sense_reg sense_registers[] __initdata = {
641         { 0xa414001c, 16, 2, /* ICR1 */
642           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
643 };
644 
645 static struct intc_mask_reg ack_registers[] __initdata = {
646         { 0xa4140024, 0, 8, /* INTREQ00 */
647           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
648 };
649 
650 static struct intc_desc intc_desc __initdata = {
651         .name = "sh7723",
652         .force_enable = ENABLED,
653         .force_disable = DISABLED,
654         .hw = INTC_HW_DESC(vectors, groups, mask_registers,
655                            prio_registers, sense_registers, ack_registers),
656 };
657 
658 void __init plat_irq_setup(void)
659 {
660         register_intc_controller(&intc_desc);
661 }
662 

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