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TOMOYO Linux Cross Reference
Linux/arch/sh/kernel/cpu/sh4a/setup-sh7724.c

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  1 /*
  2  * SH7724 Setup
  3  *
  4  * Copyright (C) 2009 Renesas Solutions Corp.
  5  *
  6  * Kuninori Morimoto <morimoto.kuninori@renesas.com>
  7  *
  8  * Based on SH7723 Setup
  9  * Copyright (C) 2008  Paul Mundt
 10  *
 11  * This file is subject to the terms and conditions of the GNU General Public
 12  * License.  See the file "COPYING" in the main directory of this archive
 13  * for more details.
 14  */
 15 #include <linux/platform_device.h>
 16 #include <linux/init.h>
 17 #include <linux/serial.h>
 18 #include <linux/mm.h>
 19 #include <linux/serial_sci.h>
 20 #include <linux/uio_driver.h>
 21 #include <linux/sh_dma.h>
 22 #include <linux/sh_timer.h>
 23 #include <linux/sh_intc.h>
 24 #include <linux/io.h>
 25 #include <linux/notifier.h>
 26 
 27 #include <asm/suspend.h>
 28 #include <asm/clock.h>
 29 #include <asm/mmzone.h>
 30 
 31 #include <cpu/dma-register.h>
 32 #include <cpu/sh7724.h>
 33 
 34 /* DMA */
 35 static const struct sh_dmae_slave_config sh7724_dmae_slaves[] = {
 36         {
 37                 .slave_id       = SHDMA_SLAVE_SCIF0_TX,
 38                 .addr           = 0xffe0000c,
 39                 .chcr           = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
 40                 .mid_rid        = 0x21,
 41         }, {
 42                 .slave_id       = SHDMA_SLAVE_SCIF0_RX,
 43                 .addr           = 0xffe00014,
 44                 .chcr           = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
 45                 .mid_rid        = 0x22,
 46         }, {
 47                 .slave_id       = SHDMA_SLAVE_SCIF1_TX,
 48                 .addr           = 0xffe1000c,
 49                 .chcr           = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
 50                 .mid_rid        = 0x25,
 51         }, {
 52                 .slave_id       = SHDMA_SLAVE_SCIF1_RX,
 53                 .addr           = 0xffe10014,
 54                 .chcr           = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
 55                 .mid_rid        = 0x26,
 56         }, {
 57                 .slave_id       = SHDMA_SLAVE_SCIF2_TX,
 58                 .addr           = 0xffe2000c,
 59                 .chcr           = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
 60                 .mid_rid        = 0x29,
 61         }, {
 62                 .slave_id       = SHDMA_SLAVE_SCIF2_RX,
 63                 .addr           = 0xffe20014,
 64                 .chcr           = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
 65                 .mid_rid        = 0x2a,
 66         }, {
 67                 .slave_id       = SHDMA_SLAVE_SCIF3_TX,
 68                 .addr           = 0xa4e30020,
 69                 .chcr           = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
 70                 .mid_rid        = 0x2d,
 71         }, {
 72                 .slave_id       = SHDMA_SLAVE_SCIF3_RX,
 73                 .addr           = 0xa4e30024,
 74                 .chcr           = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
 75                 .mid_rid        = 0x2e,
 76         }, {
 77                 .slave_id       = SHDMA_SLAVE_SCIF4_TX,
 78                 .addr           = 0xa4e40020,
 79                 .chcr           = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
 80                 .mid_rid        = 0x31,
 81         }, {
 82                 .slave_id       = SHDMA_SLAVE_SCIF4_RX,
 83                 .addr           = 0xa4e40024,
 84                 .chcr           = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
 85                 .mid_rid        = 0x32,
 86         }, {
 87                 .slave_id       = SHDMA_SLAVE_SCIF5_TX,
 88                 .addr           = 0xa4e50020,
 89                 .chcr           = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
 90                 .mid_rid        = 0x35,
 91         }, {
 92                 .slave_id       = SHDMA_SLAVE_SCIF5_RX,
 93                 .addr           = 0xa4e50024,
 94                 .chcr           = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
 95                 .mid_rid        = 0x36,
 96         }, {
 97                 .slave_id       = SHDMA_SLAVE_USB0D0_TX,
 98                 .addr           = 0xA4D80100,
 99                 .chcr           = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
100                 .mid_rid        = 0x73,
101         }, {
102                 .slave_id       = SHDMA_SLAVE_USB0D0_RX,
103                 .addr           = 0xA4D80100,
104                 .chcr           = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
105                 .mid_rid        = 0x73,
106         }, {
107                 .slave_id       = SHDMA_SLAVE_USB0D1_TX,
108                 .addr           = 0xA4D80120,
109                 .chcr           = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
110                 .mid_rid        = 0x77,
111         }, {
112                 .slave_id       = SHDMA_SLAVE_USB0D1_RX,
113                 .addr           = 0xA4D80120,
114                 .chcr           = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
115                 .mid_rid        = 0x77,
116         }, {
117                 .slave_id       = SHDMA_SLAVE_USB1D0_TX,
118                 .addr           = 0xA4D90100,
119                 .chcr           = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
120                 .mid_rid        = 0xab,
121         }, {
122                 .slave_id       = SHDMA_SLAVE_USB1D0_RX,
123                 .addr           = 0xA4D90100,
124                 .chcr           = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
125                 .mid_rid        = 0xab,
126         }, {
127                 .slave_id       = SHDMA_SLAVE_USB1D1_TX,
128                 .addr           = 0xA4D90120,
129                 .chcr           = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
130                 .mid_rid        = 0xaf,
131         }, {
132                 .slave_id       = SHDMA_SLAVE_USB1D1_RX,
133                 .addr           = 0xA4D90120,
134                 .chcr           = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
135                 .mid_rid        = 0xaf,
136         }, {
137                 .slave_id       = SHDMA_SLAVE_SDHI0_TX,
138                 .addr           = 0x04ce0030,
139                 .chcr           = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_16BIT),
140                 .mid_rid        = 0xc1,
141         }, {
142                 .slave_id       = SHDMA_SLAVE_SDHI0_RX,
143                 .addr           = 0x04ce0030,
144                 .chcr           = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_16BIT),
145                 .mid_rid        = 0xc2,
146         }, {
147                 .slave_id       = SHDMA_SLAVE_SDHI1_TX,
148                 .addr           = 0x04cf0030,
149                 .chcr           = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_16BIT),
150                 .mid_rid        = 0xc9,
151         }, {
152                 .slave_id       = SHDMA_SLAVE_SDHI1_RX,
153                 .addr           = 0x04cf0030,
154                 .chcr           = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_16BIT),
155                 .mid_rid        = 0xca,
156         },
157 };
158 
159 static const struct sh_dmae_channel sh7724_dmae_channels[] = {
160         {
161                 .offset = 0,
162                 .dmars = 0,
163                 .dmars_bit = 0,
164         }, {
165                 .offset = 0x10,
166                 .dmars = 0,
167                 .dmars_bit = 8,
168         }, {
169                 .offset = 0x20,
170                 .dmars = 4,
171                 .dmars_bit = 0,
172         }, {
173                 .offset = 0x30,
174                 .dmars = 4,
175                 .dmars_bit = 8,
176         }, {
177                 .offset = 0x50,
178                 .dmars = 8,
179                 .dmars_bit = 0,
180         }, {
181                 .offset = 0x60,
182                 .dmars = 8,
183                 .dmars_bit = 8,
184         }
185 };
186 
187 static const unsigned int ts_shift[] = TS_SHIFT;
188 
189 static struct sh_dmae_pdata dma_platform_data = {
190         .slave          = sh7724_dmae_slaves,
191         .slave_num      = ARRAY_SIZE(sh7724_dmae_slaves),
192         .channel        = sh7724_dmae_channels,
193         .channel_num    = ARRAY_SIZE(sh7724_dmae_channels),
194         .ts_low_shift   = CHCR_TS_LOW_SHIFT,
195         .ts_low_mask    = CHCR_TS_LOW_MASK,
196         .ts_high_shift  = CHCR_TS_HIGH_SHIFT,
197         .ts_high_mask   = CHCR_TS_HIGH_MASK,
198         .ts_shift       = ts_shift,
199         .ts_shift_num   = ARRAY_SIZE(ts_shift),
200         .dmaor_init     = DMAOR_INIT,
201 };
202 
203 /* Resource order important! */
204 static struct resource sh7724_dmae0_resources[] = {
205         {
206                 /* Channel registers and DMAOR */
207                 .start  = 0xfe008020,
208                 .end    = 0xfe00808f,
209                 .flags  = IORESOURCE_MEM,
210         },
211         {
212                 /* DMARSx */
213                 .start  = 0xfe009000,
214                 .end    = 0xfe00900b,
215                 .flags  = IORESOURCE_MEM,
216         },
217         {
218                 .name   = "error_irq",
219                 .start  = evt2irq(0xbc0),
220                 .end    = evt2irq(0xbc0),
221                 .flags  = IORESOURCE_IRQ,
222         },
223         {
224                 /* IRQ for channels 0-3 */
225                 .start  = evt2irq(0x800),
226                 .end    = evt2irq(0x860),
227                 .flags  = IORESOURCE_IRQ,
228         },
229         {
230                 /* IRQ for channels 4-5 */
231                 .start  = evt2irq(0xb80),
232                 .end    = evt2irq(0xba0),
233                 .flags  = IORESOURCE_IRQ,
234         },
235 };
236 
237 /* Resource order important! */
238 static struct resource sh7724_dmae1_resources[] = {
239         {
240                 /* Channel registers and DMAOR */
241                 .start  = 0xfdc08020,
242                 .end    = 0xfdc0808f,
243                 .flags  = IORESOURCE_MEM,
244         },
245         {
246                 /* DMARSx */
247                 .start  = 0xfdc09000,
248                 .end    = 0xfdc0900b,
249                 .flags  = IORESOURCE_MEM,
250         },
251         {
252                 .name   = "error_irq",
253                 .start  = evt2irq(0xb40),
254                 .end    = evt2irq(0xb40),
255                 .flags  = IORESOURCE_IRQ,
256         },
257         {
258                 /* IRQ for channels 0-3 */
259                 .start  = evt2irq(0x700),
260                 .end    = evt2irq(0x760),
261                 .flags  = IORESOURCE_IRQ,
262         },
263         {
264                 /* IRQ for channels 4-5 */
265                 .start  = evt2irq(0xb00),
266                 .end    = evt2irq(0xb20),
267                 .flags  = IORESOURCE_IRQ,
268         },
269 };
270 
271 static struct platform_device dma0_device = {
272         .name           = "sh-dma-engine",
273         .id             = 0,
274         .resource       = sh7724_dmae0_resources,
275         .num_resources  = ARRAY_SIZE(sh7724_dmae0_resources),
276         .dev            = {
277                 .platform_data  = &dma_platform_data,
278         },
279 };
280 
281 static struct platform_device dma1_device = {
282         .name           = "sh-dma-engine",
283         .id             = 1,
284         .resource       = sh7724_dmae1_resources,
285         .num_resources  = ARRAY_SIZE(sh7724_dmae1_resources),
286         .dev            = {
287                 .platform_data  = &dma_platform_data,
288         },
289 };
290 
291 /* Serial */
292 static struct plat_sci_port scif0_platform_data = {
293         .port_reg       = SCIx_NOT_SUPPORTED,
294         .flags          = UPF_BOOT_AUTOCONF,
295         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
296         .type           = PORT_SCIF,
297         .regtype        = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
298 };
299 
300 static struct resource scif0_resources[] = {
301         DEFINE_RES_MEM(0xffe00000, 0x100),
302         DEFINE_RES_IRQ(evt2irq(0xc00)),
303 };
304 
305 static struct platform_device scif0_device = {
306         .name           = "sh-sci",
307         .id             = 0,
308         .resource       = scif0_resources,
309         .num_resources  = ARRAY_SIZE(scif0_resources),
310         .dev            = {
311                 .platform_data  = &scif0_platform_data,
312         },
313 };
314 
315 static struct plat_sci_port scif1_platform_data = {
316         .port_reg       = SCIx_NOT_SUPPORTED,
317         .flags          = UPF_BOOT_AUTOCONF,
318         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
319         .type           = PORT_SCIF,
320         .regtype        = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
321 };
322 
323 static struct resource scif1_resources[] = {
324         DEFINE_RES_MEM(0xffe10000, 0x100),
325         DEFINE_RES_IRQ(evt2irq(0xc20)),
326 };
327 
328 static struct platform_device scif1_device = {
329         .name           = "sh-sci",
330         .id             = 1,
331         .resource       = scif1_resources,
332         .num_resources  = ARRAY_SIZE(scif1_resources),
333         .dev            = {
334                 .platform_data  = &scif1_platform_data,
335         },
336 };
337 
338 static struct plat_sci_port scif2_platform_data = {
339         .port_reg       = SCIx_NOT_SUPPORTED,
340         .flags          = UPF_BOOT_AUTOCONF,
341         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
342         .type           = PORT_SCIF,
343         .regtype        = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
344 };
345 
346 static struct resource scif2_resources[] = {
347         DEFINE_RES_MEM(0xffe20000, 0x100),
348         DEFINE_RES_IRQ(evt2irq(0xc40)),
349 };
350 
351 static struct platform_device scif2_device = {
352         .name           = "sh-sci",
353         .id             = 2,
354         .resource       = scif2_resources,
355         .num_resources  = ARRAY_SIZE(scif2_resources),
356         .dev            = {
357                 .platform_data  = &scif2_platform_data,
358         },
359 };
360 
361 static struct plat_sci_port scif3_platform_data = {
362         .port_reg       = SCIx_NOT_SUPPORTED,
363         .flags          = UPF_BOOT_AUTOCONF,
364         .scscr          = SCSCR_RE | SCSCR_TE,
365         .sampling_rate  = 8,
366         .type           = PORT_SCIFA,
367 };
368 
369 static struct resource scif3_resources[] = {
370         DEFINE_RES_MEM(0xa4e30000, 0x100),
371         DEFINE_RES_IRQ(evt2irq(0x900)),
372 };
373 
374 static struct platform_device scif3_device = {
375         .name           = "sh-sci",
376         .id             = 3,
377         .resource       = scif3_resources,
378         .num_resources  = ARRAY_SIZE(scif3_resources),
379         .dev            = {
380                 .platform_data  = &scif3_platform_data,
381         },
382 };
383 
384 static struct plat_sci_port scif4_platform_data = {
385         .port_reg       = SCIx_NOT_SUPPORTED,
386         .flags          = UPF_BOOT_AUTOCONF,
387         .scscr          = SCSCR_RE | SCSCR_TE,
388         .sampling_rate  = 8,
389         .type           = PORT_SCIFA,
390 };
391 
392 static struct resource scif4_resources[] = {
393         DEFINE_RES_MEM(0xa4e40000, 0x100),
394         DEFINE_RES_IRQ(evt2irq(0xd00)),
395 };
396 
397 static struct platform_device scif4_device = {
398         .name           = "sh-sci",
399         .id             = 4,
400         .resource       = scif4_resources,
401         .num_resources  = ARRAY_SIZE(scif4_resources),
402         .dev            = {
403                 .platform_data  = &scif4_platform_data,
404         },
405 };
406 
407 static struct plat_sci_port scif5_platform_data = {
408         .port_reg       = SCIx_NOT_SUPPORTED,
409         .flags          = UPF_BOOT_AUTOCONF,
410         .scscr          = SCSCR_RE | SCSCR_TE,
411         .sampling_rate  = 8,
412         .type           = PORT_SCIFA,
413 };
414 
415 static struct resource scif5_resources[] = {
416         DEFINE_RES_MEM(0xa4e50000, 0x100),
417         DEFINE_RES_IRQ(evt2irq(0xfa0)),
418 };
419 
420 static struct platform_device scif5_device = {
421         .name           = "sh-sci",
422         .id             = 5,
423         .resource       = scif5_resources,
424         .num_resources  = ARRAY_SIZE(scif5_resources),
425         .dev            = {
426                 .platform_data  = &scif5_platform_data,
427         },
428 };
429 
430 /* RTC */
431 static struct resource rtc_resources[] = {
432         [0] = {
433                 .start  = 0xa465fec0,
434                 .end    = 0xa465fec0 + 0x58 - 1,
435                 .flags  = IORESOURCE_IO,
436         },
437         [1] = {
438                 /* Period IRQ */
439                 .start  = evt2irq(0xaa0),
440                 .flags  = IORESOURCE_IRQ,
441         },
442         [2] = {
443                 /* Carry IRQ */
444                 .start  = evt2irq(0xac0),
445                 .flags  = IORESOURCE_IRQ,
446         },
447         [3] = {
448                 /* Alarm IRQ */
449                 .start  = evt2irq(0xa80),
450                 .flags  = IORESOURCE_IRQ,
451         },
452 };
453 
454 static struct platform_device rtc_device = {
455         .name           = "sh-rtc",
456         .id             = -1,
457         .num_resources  = ARRAY_SIZE(rtc_resources),
458         .resource       = rtc_resources,
459 };
460 
461 /* I2C0 */
462 static struct resource iic0_resources[] = {
463         [0] = {
464                 .name   = "IIC0",
465                 .start  = 0x04470000,
466                 .end    = 0x04470018 - 1,
467                 .flags  = IORESOURCE_MEM,
468         },
469         [1] = {
470                 .start  = evt2irq(0xe00),
471                 .end    = evt2irq(0xe60),
472                 .flags  = IORESOURCE_IRQ,
473         },
474 };
475 
476 static struct platform_device iic0_device = {
477         .name           = "i2c-sh_mobile",
478         .id             = 0, /* "i2c0" clock */
479         .num_resources  = ARRAY_SIZE(iic0_resources),
480         .resource       = iic0_resources,
481 };
482 
483 /* I2C1 */
484 static struct resource iic1_resources[] = {
485         [0] = {
486                 .name   = "IIC1",
487                 .start  = 0x04750000,
488                 .end    = 0x04750018 - 1,
489                 .flags  = IORESOURCE_MEM,
490         },
491         [1] = {
492                 .start  = evt2irq(0xd80),
493                 .end    = evt2irq(0xde0),
494                 .flags  = IORESOURCE_IRQ,
495         },
496 };
497 
498 static struct platform_device iic1_device = {
499         .name           = "i2c-sh_mobile",
500         .id             = 1, /* "i2c1" clock */
501         .num_resources  = ARRAY_SIZE(iic1_resources),
502         .resource       = iic1_resources,
503 };
504 
505 /* VPU */
506 static struct uio_info vpu_platform_data = {
507         .name = "VPU5F",
508         .version = "",
509         .irq = evt2irq(0x980),
510 };
511 
512 static struct resource vpu_resources[] = {
513         [0] = {
514                 .name   = "VPU",
515                 .start  = 0xfe900000,
516                 .end    = 0xfe902807,
517                 .flags  = IORESOURCE_MEM,
518         },
519         [1] = {
520                 /* place holder for contiguous memory */
521         },
522 };
523 
524 static struct platform_device vpu_device = {
525         .name           = "uio_pdrv_genirq",
526         .id             = 0,
527         .dev = {
528                 .platform_data  = &vpu_platform_data,
529         },
530         .resource       = vpu_resources,
531         .num_resources  = ARRAY_SIZE(vpu_resources),
532 };
533 
534 /* VEU0 */
535 static struct uio_info veu0_platform_data = {
536         .name = "VEU3F0",
537         .version = "",
538         .irq = evt2irq(0xc60),
539 };
540 
541 static struct resource veu0_resources[] = {
542         [0] = {
543                 .name   = "VEU3F0",
544                 .start  = 0xfe920000,
545                 .end    = 0xfe9200cb,
546                 .flags  = IORESOURCE_MEM,
547         },
548         [1] = {
549                 /* place holder for contiguous memory */
550         },
551 };
552 
553 static struct platform_device veu0_device = {
554         .name           = "uio_pdrv_genirq",
555         .id             = 1,
556         .dev = {
557                 .platform_data  = &veu0_platform_data,
558         },
559         .resource       = veu0_resources,
560         .num_resources  = ARRAY_SIZE(veu0_resources),
561 };
562 
563 /* VEU1 */
564 static struct uio_info veu1_platform_data = {
565         .name = "VEU3F1",
566         .version = "",
567         .irq = evt2irq(0x8c0),
568 };
569 
570 static struct resource veu1_resources[] = {
571         [0] = {
572                 .name   = "VEU3F1",
573                 .start  = 0xfe924000,
574                 .end    = 0xfe9240cb,
575                 .flags  = IORESOURCE_MEM,
576         },
577         [1] = {
578                 /* place holder for contiguous memory */
579         },
580 };
581 
582 static struct platform_device veu1_device = {
583         .name           = "uio_pdrv_genirq",
584         .id             = 2,
585         .dev = {
586                 .platform_data  = &veu1_platform_data,
587         },
588         .resource       = veu1_resources,
589         .num_resources  = ARRAY_SIZE(veu1_resources),
590 };
591 
592 /* BEU0 */
593 static struct uio_info beu0_platform_data = {
594         .name = "BEU0",
595         .version = "",
596         .irq = evt2irq(0x8A0),
597 };
598 
599 static struct resource beu0_resources[] = {
600         [0] = {
601                 .name   = "BEU0",
602                 .start  = 0xfe930000,
603                 .end    = 0xfe933400,
604                 .flags  = IORESOURCE_MEM,
605         },
606         [1] = {
607                 /* place holder for contiguous memory */
608         },
609 };
610 
611 static struct platform_device beu0_device = {
612         .name           = "uio_pdrv_genirq",
613         .id             = 6,
614         .dev = {
615                 .platform_data  = &beu0_platform_data,
616         },
617         .resource       = beu0_resources,
618         .num_resources  = ARRAY_SIZE(beu0_resources),
619 };
620 
621 /* BEU1 */
622 static struct uio_info beu1_platform_data = {
623         .name = "BEU1",
624         .version = "",
625         .irq = evt2irq(0xA00),
626 };
627 
628 static struct resource beu1_resources[] = {
629         [0] = {
630                 .name   = "BEU1",
631                 .start  = 0xfe940000,
632                 .end    = 0xfe943400,
633                 .flags  = IORESOURCE_MEM,
634         },
635         [1] = {
636                 /* place holder for contiguous memory */
637         },
638 };
639 
640 static struct platform_device beu1_device = {
641         .name           = "uio_pdrv_genirq",
642         .id             = 7,
643         .dev = {
644                 .platform_data  = &beu1_platform_data,
645         },
646         .resource       = beu1_resources,
647         .num_resources  = ARRAY_SIZE(beu1_resources),
648 };
649 
650 static struct sh_timer_config cmt_platform_data = {
651         .channels_mask = 0x20,
652 };
653 
654 static struct resource cmt_resources[] = {
655         DEFINE_RES_MEM(0x044a0000, 0x70),
656         DEFINE_RES_IRQ(evt2irq(0xf00)),
657 };
658 
659 static struct platform_device cmt_device = {
660         .name           = "sh-cmt-32",
661         .id             = 0,
662         .dev = {
663                 .platform_data  = &cmt_platform_data,
664         },
665         .resource       = cmt_resources,
666         .num_resources  = ARRAY_SIZE(cmt_resources),
667 };
668 
669 static struct sh_timer_config tmu0_platform_data = {
670         .channels_mask = 7,
671 };
672 
673 static struct resource tmu0_resources[] = {
674         DEFINE_RES_MEM(0xffd80000, 0x2c),
675         DEFINE_RES_IRQ(evt2irq(0x400)),
676         DEFINE_RES_IRQ(evt2irq(0x420)),
677         DEFINE_RES_IRQ(evt2irq(0x440)),
678 };
679 
680 static struct platform_device tmu0_device = {
681         .name           = "sh-tmu",
682         .id             = 0,
683         .dev = {
684                 .platform_data  = &tmu0_platform_data,
685         },
686         .resource       = tmu0_resources,
687         .num_resources  = ARRAY_SIZE(tmu0_resources),
688 };
689 
690 static struct sh_timer_config tmu1_platform_data = {
691         .channels_mask = 7,
692 };
693 
694 static struct resource tmu1_resources[] = {
695         DEFINE_RES_MEM(0xffd90000, 0x2c),
696         DEFINE_RES_IRQ(evt2irq(0x920)),
697         DEFINE_RES_IRQ(evt2irq(0x940)),
698         DEFINE_RES_IRQ(evt2irq(0x960)),
699 };
700 
701 static struct platform_device tmu1_device = {
702         .name           = "sh-tmu",
703         .id             = 1,
704         .dev = {
705                 .platform_data  = &tmu1_platform_data,
706         },
707         .resource       = tmu1_resources,
708         .num_resources  = ARRAY_SIZE(tmu1_resources),
709 };
710 
711 /* JPU */
712 static struct uio_info jpu_platform_data = {
713         .name = "JPU",
714         .version = "",
715         .irq = evt2irq(0x560),
716 };
717 
718 static struct resource jpu_resources[] = {
719         [0] = {
720                 .name   = "JPU",
721                 .start  = 0xfe980000,
722                 .end    = 0xfe9902d3,
723                 .flags  = IORESOURCE_MEM,
724         },
725         [1] = {
726                 /* place holder for contiguous memory */
727         },
728 };
729 
730 static struct platform_device jpu_device = {
731         .name           = "uio_pdrv_genirq",
732         .id             = 3,
733         .dev = {
734                 .platform_data  = &jpu_platform_data,
735         },
736         .resource       = jpu_resources,
737         .num_resources  = ARRAY_SIZE(jpu_resources),
738 };
739 
740 /* SPU2DSP0 */
741 static struct uio_info spu0_platform_data = {
742         .name = "SPU2DSP0",
743         .version = "",
744         .irq = evt2irq(0xcc0),
745 };
746 
747 static struct resource spu0_resources[] = {
748         [0] = {
749                 .name   = "SPU2DSP0",
750                 .start  = 0xFE200000,
751                 .end    = 0xFE2FFFFF,
752                 .flags  = IORESOURCE_MEM,
753         },
754         [1] = {
755                 /* place holder for contiguous memory */
756         },
757 };
758 
759 static struct platform_device spu0_device = {
760         .name           = "uio_pdrv_genirq",
761         .id             = 4,
762         .dev = {
763                 .platform_data  = &spu0_platform_data,
764         },
765         .resource       = spu0_resources,
766         .num_resources  = ARRAY_SIZE(spu0_resources),
767 };
768 
769 /* SPU2DSP1 */
770 static struct uio_info spu1_platform_data = {
771         .name = "SPU2DSP1",
772         .version = "",
773         .irq = evt2irq(0xce0),
774 };
775 
776 static struct resource spu1_resources[] = {
777         [0] = {
778                 .name   = "SPU2DSP1",
779                 .start  = 0xFE300000,
780                 .end    = 0xFE3FFFFF,
781                 .flags  = IORESOURCE_MEM,
782         },
783         [1] = {
784                 /* place holder for contiguous memory */
785         },
786 };
787 
788 static struct platform_device spu1_device = {
789         .name           = "uio_pdrv_genirq",
790         .id             = 5,
791         .dev = {
792                 .platform_data  = &spu1_platform_data,
793         },
794         .resource       = spu1_resources,
795         .num_resources  = ARRAY_SIZE(spu1_resources),
796 };
797 
798 static struct platform_device *sh7724_devices[] __initdata = {
799         &scif0_device,
800         &scif1_device,
801         &scif2_device,
802         &scif3_device,
803         &scif4_device,
804         &scif5_device,
805         &cmt_device,
806         &tmu0_device,
807         &tmu1_device,
808         &dma0_device,
809         &dma1_device,
810         &rtc_device,
811         &iic0_device,
812         &iic1_device,
813         &vpu_device,
814         &veu0_device,
815         &veu1_device,
816         &beu0_device,
817         &beu1_device,
818         &jpu_device,
819         &spu0_device,
820         &spu1_device,
821 };
822 
823 static int __init sh7724_devices_setup(void)
824 {
825         platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
826         platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
827         platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);
828         platform_resource_setup_memory(&jpu_device,  "jpu",  2 << 20);
829         platform_resource_setup_memory(&spu0_device, "spu0", 2 << 20);
830         platform_resource_setup_memory(&spu1_device, "spu1", 2 << 20);
831 
832         return platform_add_devices(sh7724_devices,
833                                     ARRAY_SIZE(sh7724_devices));
834 }
835 arch_initcall(sh7724_devices_setup);
836 
837 static struct platform_device *sh7724_early_devices[] __initdata = {
838         &scif0_device,
839         &scif1_device,
840         &scif2_device,
841         &scif3_device,
842         &scif4_device,
843         &scif5_device,
844         &cmt_device,
845         &tmu0_device,
846         &tmu1_device,
847 };
848 
849 void __init plat_early_device_setup(void)
850 {
851         early_platform_add_devices(sh7724_early_devices,
852                                    ARRAY_SIZE(sh7724_early_devices));
853 }
854 
855 #define RAMCR_CACHE_L2FC        0x0002
856 #define RAMCR_CACHE_L2E         0x0001
857 #define L2_CACHE_ENABLE         (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC)
858 
859 void l2_cache_init(void)
860 {
861         /* Enable L2 cache */
862         __raw_writel(L2_CACHE_ENABLE, RAMCR);
863 }
864 
865 enum {
866         UNUSED = 0,
867         ENABLED,
868         DISABLED,
869 
870         /* interrupt sources */
871         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
872         HUDI,
873         DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3,
874         _2DG_TRI, _2DG_INI, _2DG_CEI,
875         DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3,
876         VIO_CEU0, VIO_BEU0, VIO_VEU1, VIO_VOU,
877         SCIFA3,
878         VPU,
879         TPU,
880         CEU1,
881         BEU1,
882         USB0, USB1,
883         ATAPI,
884         RTC_ATI, RTC_PRI, RTC_CUI,
885         DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR,
886         DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR,
887         KEYSC,
888         SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2,
889         VEU0,
890         MSIOF_MSIOFI0, MSIOF_MSIOFI1,
891         SPU_SPUI0, SPU_SPUI1,
892         SCIFA4,
893         ICB,
894         ETHI,
895         I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI,
896         I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI,
897         CMT,
898         TSIF,
899         FSI,
900         SCIFA5,
901         TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2,
902         IRDA,
903         JPU,
904         _2DDMAC,
905         MMC_MMC2I, MMC_MMC3I,
906         LCDC,
907         TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2,
908 
909         /* interrupt groups */
910         DMAC1A, _2DG, DMAC0A, VIO, USB, RTC,
911         DMAC1B, DMAC0B, I2C0, I2C1, SDHI0, SDHI1, SPU, MMCIF,
912 };
913 
914 static struct intc_vect vectors[] __initdata = {
915         INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
916         INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
917         INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
918         INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
919 
920         INTC_VECT(DMAC1A_DEI0, 0x700),
921         INTC_VECT(DMAC1A_DEI1, 0x720),
922         INTC_VECT(DMAC1A_DEI2, 0x740),
923         INTC_VECT(DMAC1A_DEI3, 0x760),
924 
925         INTC_VECT(_2DG_TRI, 0x780),
926         INTC_VECT(_2DG_INI, 0x7A0),
927         INTC_VECT(_2DG_CEI, 0x7C0),
928 
929         INTC_VECT(DMAC0A_DEI0, 0x800),
930         INTC_VECT(DMAC0A_DEI1, 0x820),
931         INTC_VECT(DMAC0A_DEI2, 0x840),
932         INTC_VECT(DMAC0A_DEI3, 0x860),
933 
934         INTC_VECT(VIO_CEU0, 0x880),
935         INTC_VECT(VIO_BEU0, 0x8A0),
936         INTC_VECT(VIO_VEU1, 0x8C0),
937         INTC_VECT(VIO_VOU,  0x8E0),
938 
939         INTC_VECT(SCIFA3, 0x900),
940         INTC_VECT(VPU,    0x980),
941         INTC_VECT(TPU,    0x9A0),
942         INTC_VECT(CEU1,   0x9E0),
943         INTC_VECT(BEU1,   0xA00),
944         INTC_VECT(USB0,   0xA20),
945         INTC_VECT(USB1,   0xA40),
946         INTC_VECT(ATAPI,  0xA60),
947 
948         INTC_VECT(RTC_ATI, 0xA80),
949         INTC_VECT(RTC_PRI, 0xAA0),
950         INTC_VECT(RTC_CUI, 0xAC0),
951 
952         INTC_VECT(DMAC1B_DEI4, 0xB00),
953         INTC_VECT(DMAC1B_DEI5, 0xB20),
954         INTC_VECT(DMAC1B_DADERR, 0xB40),
955 
956         INTC_VECT(DMAC0B_DEI4, 0xB80),
957         INTC_VECT(DMAC0B_DEI5, 0xBA0),
958         INTC_VECT(DMAC0B_DADERR, 0xBC0),
959 
960         INTC_VECT(KEYSC,      0xBE0),
961         INTC_VECT(SCIF_SCIF0, 0xC00),
962         INTC_VECT(SCIF_SCIF1, 0xC20),
963         INTC_VECT(SCIF_SCIF2, 0xC40),
964         INTC_VECT(VEU0,       0xC60),
965         INTC_VECT(MSIOF_MSIOFI0, 0xC80),
966         INTC_VECT(MSIOF_MSIOFI1, 0xCA0),
967         INTC_VECT(SPU_SPUI0, 0xCC0),
968         INTC_VECT(SPU_SPUI1, 0xCE0),
969         INTC_VECT(SCIFA4,    0xD00),
970 
971         INTC_VECT(ICB,  0xD20),
972         INTC_VECT(ETHI, 0xD60),
973 
974         INTC_VECT(I2C1_ALI, 0xD80),
975         INTC_VECT(I2C1_TACKI, 0xDA0),
976         INTC_VECT(I2C1_WAITI, 0xDC0),
977         INTC_VECT(I2C1_DTEI, 0xDE0),
978 
979         INTC_VECT(I2C0_ALI, 0xE00),
980         INTC_VECT(I2C0_TACKI, 0xE20),
981         INTC_VECT(I2C0_WAITI, 0xE40),
982         INTC_VECT(I2C0_DTEI, 0xE60),
983 
984         INTC_VECT(SDHI0, 0xE80),
985         INTC_VECT(SDHI0, 0xEA0),
986         INTC_VECT(SDHI0, 0xEC0),
987         INTC_VECT(SDHI0, 0xEE0),
988 
989         INTC_VECT(CMT,    0xF00),
990         INTC_VECT(TSIF,   0xF20),
991         INTC_VECT(FSI,    0xF80),
992         INTC_VECT(SCIFA5, 0xFA0),
993 
994         INTC_VECT(TMU0_TUNI0, 0x400),
995         INTC_VECT(TMU0_TUNI1, 0x420),
996         INTC_VECT(TMU0_TUNI2, 0x440),
997 
998         INTC_VECT(IRDA,    0x480),
999 
1000         INTC_VECT(SDHI1, 0x4E0),
1001         INTC_VECT(SDHI1, 0x500),
1002         INTC_VECT(SDHI1, 0x520),
1003 
1004         INTC_VECT(JPU, 0x560),
1005         INTC_VECT(_2DDMAC, 0x4A0),
1006 
1007         INTC_VECT(MMC_MMC2I, 0x5A0),
1008         INTC_VECT(MMC_MMC3I, 0x5C0),
1009 
1010         INTC_VECT(LCDC, 0xF40),
1011 
1012         INTC_VECT(TMU1_TUNI0, 0x920),
1013         INTC_VECT(TMU1_TUNI1, 0x940),
1014         INTC_VECT(TMU1_TUNI2, 0x960),
1015 };
1016 
1017 static struct intc_group groups[] __initdata = {
1018         INTC_GROUP(DMAC1A, DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3),
1019         INTC_GROUP(_2DG, _2DG_TRI, _2DG_INI, _2DG_CEI),
1020         INTC_GROUP(DMAC0A, DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3),
1021         INTC_GROUP(VIO, VIO_CEU0, VIO_BEU0, VIO_VEU1, VIO_VOU),
1022         INTC_GROUP(USB, USB0, USB1),
1023         INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
1024         INTC_GROUP(DMAC1B, DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR),
1025         INTC_GROUP(DMAC0B, DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR),
1026         INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI),
1027         INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI),
1028         INTC_GROUP(SPU, SPU_SPUI0, SPU_SPUI1),
1029         INTC_GROUP(MMCIF, MMC_MMC2I, MMC_MMC3I),
1030 };
1031 
1032 static struct intc_mask_reg mask_registers[] __initdata = {
1033         { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
1034           { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0,
1035             0, ENABLED, ENABLED, ENABLED } },
1036         { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
1037           { VIO_VOU, VIO_VEU1, VIO_BEU0, VIO_CEU0,
1038             DMAC0A_DEI3, DMAC0A_DEI2, DMAC0A_DEI1, DMAC0A_DEI0 } },
1039         { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
1040           { 0, 0, 0, VPU, ATAPI, ETHI, 0, SCIFA3 } },
1041         { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
1042           { DMAC1A_DEI3, DMAC1A_DEI2, DMAC1A_DEI1, DMAC1A_DEI0,
1043             SPU_SPUI1, SPU_SPUI0, BEU1, IRDA } },
1044         { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
1045           { 0, TMU0_TUNI2, TMU0_TUNI1, TMU0_TUNI0,
1046             JPU, 0, 0, LCDC } },
1047         { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
1048           { KEYSC, DMAC0B_DADERR, DMAC0B_DEI5, DMAC0B_DEI4,
1049             VEU0, SCIF_SCIF2, SCIF_SCIF1, SCIF_SCIF0 } },
1050         { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
1051           { 0, 0, ICB, SCIFA4,
1052             CEU1, 0, MSIOF_MSIOFI1, MSIOF_MSIOFI0 } },
1053         { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
1054           { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI,
1055             I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI } },
1056         { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
1057           { DISABLED, ENABLED, ENABLED, ENABLED,
1058             0, 0, SCIFA5, FSI } },
1059         { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
1060           { 0, 0, 0, CMT, 0, USB1, USB0, 0 } },
1061         { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
1062           { 0, DMAC1B_DADERR, DMAC1B_DEI5, DMAC1B_DEI4,
1063             0, RTC_CUI, RTC_PRI, RTC_ATI } },
1064         { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
1065           { 0, _2DG_CEI, _2DG_INI, _2DG_TRI,
1066             0, TPU, 0, TSIF } },
1067         { 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */
1068           { 0, 0, MMC_MMC3I, MMC_MMC2I, 0, 0, 0, _2DDMAC } },
1069         { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
1070           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
1071 };
1072 
1073 static struct intc_prio_reg prio_registers[] __initdata = {
1074         { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1,
1075                                              TMU0_TUNI2, IRDA } },
1076         { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, DMAC1A, BEU1 } },
1077         { 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1,
1078                                              TMU1_TUNI2, SPU } },
1079         { 0xa408000c, 0, 16, 4, /* IPRD */ { 0, MMCIF, 0, ATAPI } },
1080         { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0A, VIO, SCIFA3, VPU } },
1081         { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC0B, USB, CMT } },
1082         { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1,
1083                                              SCIF_SCIF2, VEU0 } },
1084         { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0, MSIOF_MSIOFI1,
1085                                              I2C1, I2C0 } },
1086         { 0xa4080020, 0, 16, 4, /* IPRI */ { SCIFA4, ICB, TSIF, _2DG } },
1087         { 0xa4080024, 0, 16, 4, /* IPRJ */ { CEU1, ETHI, FSI, SDHI1 } },
1088         { 0xa4080028, 0, 16, 4, /* IPRK */ { RTC, DMAC1B, 0, SDHI0 } },
1089         { 0xa408002c, 0, 16, 4, /* IPRL */ { SCIFA5, 0, TPU, _2DDMAC } },
1090         { 0xa4140010, 0, 32, 4, /* INTPRI00 */
1091           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
1092 };
1093 
1094 static struct intc_sense_reg sense_registers[] __initdata = {
1095         { 0xa414001c, 16, 2, /* ICR1 */
1096           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
1097 };
1098 
1099 static struct intc_mask_reg ack_registers[] __initdata = {
1100         { 0xa4140024, 0, 8, /* INTREQ00 */
1101           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
1102 };
1103 
1104 static struct intc_desc intc_desc __initdata = {
1105         .name = "sh7724",
1106         .force_enable = ENABLED,
1107         .force_disable = DISABLED,
1108         .hw = INTC_HW_DESC(vectors, groups, mask_registers,
1109                            prio_registers, sense_registers, ack_registers),
1110 };
1111 
1112 void __init plat_irq_setup(void)
1113 {
1114         register_intc_controller(&intc_desc);
1115 }
1116 
1117 static struct {
1118         /* BSC */
1119         unsigned long mmselr;
1120         unsigned long cs0bcr;
1121         unsigned long cs4bcr;
1122         unsigned long cs5abcr;
1123         unsigned long cs5bbcr;
1124         unsigned long cs6abcr;
1125         unsigned long cs6bbcr;
1126         unsigned long cs4wcr;
1127         unsigned long cs5awcr;
1128         unsigned long cs5bwcr;
1129         unsigned long cs6awcr;
1130         unsigned long cs6bwcr;
1131         /* INTC */
1132         unsigned short ipra;
1133         unsigned short iprb;
1134         unsigned short iprc;
1135         unsigned short iprd;
1136         unsigned short ipre;
1137         unsigned short iprf;
1138         unsigned short iprg;
1139         unsigned short iprh;
1140         unsigned short ipri;
1141         unsigned short iprj;
1142         unsigned short iprk;
1143         unsigned short iprl;
1144         unsigned char imr0;
1145         unsigned char imr1;
1146         unsigned char imr2;
1147         unsigned char imr3;
1148         unsigned char imr4;
1149         unsigned char imr5;
1150         unsigned char imr6;
1151         unsigned char imr7;
1152         unsigned char imr8;
1153         unsigned char imr9;
1154         unsigned char imr10;
1155         unsigned char imr11;
1156         unsigned char imr12;
1157         /* RWDT */
1158         unsigned short rwtcnt;
1159         unsigned short rwtcsr;
1160         /* CPG */
1161         unsigned long irdaclk;
1162         unsigned long spuclk;
1163 } sh7724_rstandby_state;
1164 
1165 static int sh7724_pre_sleep_notifier_call(struct notifier_block *nb,
1166                                           unsigned long flags, void *unused)
1167 {
1168         if (!(flags & SUSP_SH_RSTANDBY))
1169                 return NOTIFY_DONE;
1170 
1171         /* BCR */
1172         sh7724_rstandby_state.mmselr = __raw_readl(0xff800020); /* MMSELR */
1173         sh7724_rstandby_state.mmselr |= 0xa5a50000;
1174         sh7724_rstandby_state.cs0bcr = __raw_readl(0xfec10004); /* CS0BCR */
1175         sh7724_rstandby_state.cs4bcr = __raw_readl(0xfec10010); /* CS4BCR */
1176         sh7724_rstandby_state.cs5abcr = __raw_readl(0xfec10014); /* CS5ABCR */
1177         sh7724_rstandby_state.cs5bbcr = __raw_readl(0xfec10018); /* CS5BBCR */
1178         sh7724_rstandby_state.cs6abcr = __raw_readl(0xfec1001c); /* CS6ABCR */
1179         sh7724_rstandby_state.cs6bbcr = __raw_readl(0xfec10020); /* CS6BBCR */
1180         sh7724_rstandby_state.cs4wcr = __raw_readl(0xfec10030); /* CS4WCR */
1181         sh7724_rstandby_state.cs5awcr = __raw_readl(0xfec10034); /* CS5AWCR */
1182         sh7724_rstandby_state.cs5bwcr = __raw_readl(0xfec10038); /* CS5BWCR */
1183         sh7724_rstandby_state.cs6awcr = __raw_readl(0xfec1003c); /* CS6AWCR */
1184         sh7724_rstandby_state.cs6bwcr = __raw_readl(0xfec10040); /* CS6BWCR */
1185 
1186         /* INTC */
1187         sh7724_rstandby_state.ipra = __raw_readw(0xa4080000); /* IPRA */
1188         sh7724_rstandby_state.iprb = __raw_readw(0xa4080004); /* IPRB */
1189         sh7724_rstandby_state.iprc = __raw_readw(0xa4080008); /* IPRC */
1190         sh7724_rstandby_state.iprd = __raw_readw(0xa408000c); /* IPRD */
1191         sh7724_rstandby_state.ipre = __raw_readw(0xa4080010); /* IPRE */
1192         sh7724_rstandby_state.iprf = __raw_readw(0xa4080014); /* IPRF */
1193         sh7724_rstandby_state.iprg = __raw_readw(0xa4080018); /* IPRG */
1194         sh7724_rstandby_state.iprh = __raw_readw(0xa408001c); /* IPRH */
1195         sh7724_rstandby_state.ipri = __raw_readw(0xa4080020); /* IPRI */
1196         sh7724_rstandby_state.iprj = __raw_readw(0xa4080024); /* IPRJ */
1197         sh7724_rstandby_state.iprk = __raw_readw(0xa4080028); /* IPRK */
1198         sh7724_rstandby_state.iprl = __raw_readw(0xa408002c); /* IPRL */
1199         sh7724_rstandby_state.imr0 = __raw_readb(0xa4080080); /* IMR0 */
1200         sh7724_rstandby_state.imr1 = __raw_readb(0xa4080084); /* IMR1 */
1201         sh7724_rstandby_state.imr2 = __raw_readb(0xa4080088); /* IMR2 */
1202         sh7724_rstandby_state.imr3 = __raw_readb(0xa408008c); /* IMR3 */
1203         sh7724_rstandby_state.imr4 = __raw_readb(0xa4080090); /* IMR4 */
1204         sh7724_rstandby_state.imr5 = __raw_readb(0xa4080094); /* IMR5 */
1205         sh7724_rstandby_state.imr6 = __raw_readb(0xa4080098); /* IMR6 */
1206         sh7724_rstandby_state.imr7 = __raw_readb(0xa408009c); /* IMR7 */
1207         sh7724_rstandby_state.imr8 = __raw_readb(0xa40800a0); /* IMR8 */
1208         sh7724_rstandby_state.imr9 = __raw_readb(0xa40800a4); /* IMR9 */
1209         sh7724_rstandby_state.imr10 = __raw_readb(0xa40800a8); /* IMR10 */
1210         sh7724_rstandby_state.imr11 = __raw_readb(0xa40800ac); /* IMR11 */
1211         sh7724_rstandby_state.imr12 = __raw_readb(0xa40800b0); /* IMR12 */
1212 
1213         /* RWDT */
1214         sh7724_rstandby_state.rwtcnt = __raw_readb(0xa4520000); /* RWTCNT */
1215         sh7724_rstandby_state.rwtcnt |= 0x5a00;
1216         sh7724_rstandby_state.rwtcsr = __raw_readb(0xa4520004); /* RWTCSR */
1217         sh7724_rstandby_state.rwtcsr |= 0xa500;
1218         __raw_writew(sh7724_rstandby_state.rwtcsr & 0x07, 0xa4520004);
1219 
1220         /* CPG */
1221         sh7724_rstandby_state.irdaclk = __raw_readl(0xa4150018); /* IRDACLKCR */
1222         sh7724_rstandby_state.spuclk = __raw_readl(0xa415003c); /* SPUCLKCR */
1223 
1224         return NOTIFY_DONE;
1225 }
1226 
1227 static int sh7724_post_sleep_notifier_call(struct notifier_block *nb,
1228                                            unsigned long flags, void *unused)
1229 {
1230         if (!(flags & SUSP_SH_RSTANDBY))
1231                 return NOTIFY_DONE;
1232 
1233         /* BCR */
1234         __raw_writel(sh7724_rstandby_state.mmselr, 0xff800020); /* MMSELR */
1235         __raw_writel(sh7724_rstandby_state.cs0bcr, 0xfec10004); /* CS0BCR */
1236         __raw_writel(sh7724_rstandby_state.cs4bcr, 0xfec10010); /* CS4BCR */
1237         __raw_writel(sh7724_rstandby_state.cs5abcr, 0xfec10014); /* CS5ABCR */
1238         __raw_writel(sh7724_rstandby_state.cs5bbcr, 0xfec10018); /* CS5BBCR */
1239         __raw_writel(sh7724_rstandby_state.cs6abcr, 0xfec1001c); /* CS6ABCR */
1240         __raw_writel(sh7724_rstandby_state.cs6bbcr, 0xfec10020); /* CS6BBCR */
1241         __raw_writel(sh7724_rstandby_state.cs4wcr, 0xfec10030); /* CS4WCR */
1242         __raw_writel(sh7724_rstandby_state.cs5awcr, 0xfec10034); /* CS5AWCR */
1243         __raw_writel(sh7724_rstandby_state.cs5bwcr, 0xfec10038); /* CS5BWCR */
1244         __raw_writel(sh7724_rstandby_state.cs6awcr, 0xfec1003c); /* CS6AWCR */
1245         __raw_writel(sh7724_rstandby_state.cs6bwcr, 0xfec10040); /* CS6BWCR */
1246 
1247         /* INTC */
1248         __raw_writew(sh7724_rstandby_state.ipra, 0xa4080000); /* IPRA */
1249         __raw_writew(sh7724_rstandby_state.iprb, 0xa4080004); /* IPRB */
1250         __raw_writew(sh7724_rstandby_state.iprc, 0xa4080008); /* IPRC */
1251         __raw_writew(sh7724_rstandby_state.iprd, 0xa408000c); /* IPRD */
1252         __raw_writew(sh7724_rstandby_state.ipre, 0xa4080010); /* IPRE */
1253         __raw_writew(sh7724_rstandby_state.iprf, 0xa4080014); /* IPRF */
1254         __raw_writew(sh7724_rstandby_state.iprg, 0xa4080018); /* IPRG */
1255         __raw_writew(sh7724_rstandby_state.iprh, 0xa408001c); /* IPRH */
1256         __raw_writew(sh7724_rstandby_state.ipri, 0xa4080020); /* IPRI */
1257         __raw_writew(sh7724_rstandby_state.iprj, 0xa4080024); /* IPRJ */
1258         __raw_writew(sh7724_rstandby_state.iprk, 0xa4080028); /* IPRK */
1259         __raw_writew(sh7724_rstandby_state.iprl, 0xa408002c); /* IPRL */
1260         __raw_writeb(sh7724_rstandby_state.imr0, 0xa4080080); /* IMR0 */
1261         __raw_writeb(sh7724_rstandby_state.imr1, 0xa4080084); /* IMR1 */
1262         __raw_writeb(sh7724_rstandby_state.imr2, 0xa4080088); /* IMR2 */
1263         __raw_writeb(sh7724_rstandby_state.imr3, 0xa408008c); /* IMR3 */
1264         __raw_writeb(sh7724_rstandby_state.imr4, 0xa4080090); /* IMR4 */
1265         __raw_writeb(sh7724_rstandby_state.imr5, 0xa4080094); /* IMR5 */
1266         __raw_writeb(sh7724_rstandby_state.imr6, 0xa4080098); /* IMR6 */
1267         __raw_writeb(sh7724_rstandby_state.imr7, 0xa408009c); /* IMR7 */
1268         __raw_writeb(sh7724_rstandby_state.imr8, 0xa40800a0); /* IMR8 */
1269         __raw_writeb(sh7724_rstandby_state.imr9, 0xa40800a4); /* IMR9 */
1270         __raw_writeb(sh7724_rstandby_state.imr10, 0xa40800a8); /* IMR10 */
1271         __raw_writeb(sh7724_rstandby_state.imr11, 0xa40800ac); /* IMR11 */
1272         __raw_writeb(sh7724_rstandby_state.imr12, 0xa40800b0); /* IMR12 */
1273 
1274         /* RWDT */
1275         __raw_writew(sh7724_rstandby_state.rwtcnt, 0xa4520000); /* RWTCNT */
1276         __raw_writew(sh7724_rstandby_state.rwtcsr, 0xa4520004); /* RWTCSR */
1277 
1278         /* CPG */
1279         __raw_writel(sh7724_rstandby_state.irdaclk, 0xa4150018); /* IRDACLKCR */
1280         __raw_writel(sh7724_rstandby_state.spuclk, 0xa415003c); /* SPUCLKCR */
1281 
1282         return NOTIFY_DONE;
1283 }
1284 
1285 static struct notifier_block sh7724_pre_sleep_notifier = {
1286         .notifier_call = sh7724_pre_sleep_notifier_call,
1287         .priority = SH_MOBILE_PRE(SH_MOBILE_SLEEP_CPU),
1288 };
1289 
1290 static struct notifier_block sh7724_post_sleep_notifier = {
1291         .notifier_call = sh7724_post_sleep_notifier_call,
1292         .priority = SH_MOBILE_POST(SH_MOBILE_SLEEP_CPU),
1293 };
1294 
1295 static int __init sh7724_sleep_setup(void)
1296 {
1297         atomic_notifier_chain_register(&sh_mobile_pre_sleep_notifier_list,
1298                                        &sh7724_pre_sleep_notifier);
1299 
1300         atomic_notifier_chain_register(&sh_mobile_post_sleep_notifier_list,
1301                                        &sh7724_post_sleep_notifier);
1302         return 0;
1303 }
1304 arch_initcall(sh7724_sleep_setup);
1305 
1306 

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