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TOMOYO Linux Cross Reference
Linux/arch/sh/kernel/cpu/sh4a/setup-sh7780.c

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  1 /*
  2  * SH7780 Setup
  3  *
  4  *  Copyright (C) 2006  Paul Mundt
  5  *
  6  * This file is subject to the terms and conditions of the GNU General Public
  7  * License.  See the file "COPYING" in the main directory of this archive
  8  * for more details.
  9  */
 10 #include <linux/platform_device.h>
 11 #include <linux/init.h>
 12 #include <linux/serial.h>
 13 #include <linux/io.h>
 14 #include <linux/serial_sci.h>
 15 #include <linux/sh_dma.h>
 16 #include <linux/sh_timer.h>
 17 #include <linux/sh_intc.h>
 18 #include <cpu/dma-register.h>
 19 
 20 static struct plat_sci_port scif0_platform_data = {
 21         .scscr          = SCSCR_REIE | SCSCR_CKE1,
 22         .type           = PORT_SCIF,
 23         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
 24 };
 25 
 26 static struct resource scif0_resources[] = {
 27         DEFINE_RES_MEM(0xffe00000, 0x100),
 28         DEFINE_RES_IRQ(evt2irq(0x700)),
 29 };
 30 
 31 static struct platform_device scif0_device = {
 32         .name           = "sh-sci",
 33         .id             = 0,
 34         .resource       = scif0_resources,
 35         .num_resources  = ARRAY_SIZE(scif0_resources),
 36         .dev            = {
 37                 .platform_data  = &scif0_platform_data,
 38         },
 39 };
 40 
 41 static struct plat_sci_port scif1_platform_data = {
 42         .scscr          = SCSCR_REIE | SCSCR_CKE1,
 43         .type           = PORT_SCIF,
 44         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
 45 };
 46 
 47 static struct resource scif1_resources[] = {
 48         DEFINE_RES_MEM(0xffe10000, 0x100),
 49         DEFINE_RES_IRQ(evt2irq(0xb80)),
 50 };
 51 
 52 static struct platform_device scif1_device = {
 53         .name           = "sh-sci",
 54         .id             = 1,
 55         .resource       = scif1_resources,
 56         .num_resources  = ARRAY_SIZE(scif1_resources),
 57         .dev            = {
 58                 .platform_data  = &scif1_platform_data,
 59         },
 60 };
 61 
 62 static struct sh_timer_config tmu0_platform_data = {
 63         .channels_mask = 7,
 64 };
 65 
 66 static struct resource tmu0_resources[] = {
 67         DEFINE_RES_MEM(0xffd80000, 0x30),
 68         DEFINE_RES_IRQ(evt2irq(0x580)),
 69         DEFINE_RES_IRQ(evt2irq(0x5a0)),
 70         DEFINE_RES_IRQ(evt2irq(0x5c0)),
 71 };
 72 
 73 static struct platform_device tmu0_device = {
 74         .name           = "sh-tmu",
 75         .id             = 0,
 76         .dev = {
 77                 .platform_data  = &tmu0_platform_data,
 78         },
 79         .resource       = tmu0_resources,
 80         .num_resources  = ARRAY_SIZE(tmu0_resources),
 81 };
 82 
 83 static struct sh_timer_config tmu1_platform_data = {
 84         .channels_mask = 7,
 85 };
 86 
 87 static struct resource tmu1_resources[] = {
 88         DEFINE_RES_MEM(0xffdc0000, 0x2c),
 89         DEFINE_RES_IRQ(evt2irq(0xe00)),
 90         DEFINE_RES_IRQ(evt2irq(0xe20)),
 91         DEFINE_RES_IRQ(evt2irq(0xe40)),
 92 };
 93 
 94 static struct platform_device tmu1_device = {
 95         .name           = "sh-tmu",
 96         .id             = 1,
 97         .dev = {
 98                 .platform_data  = &tmu1_platform_data,
 99         },
100         .resource       = tmu1_resources,
101         .num_resources  = ARRAY_SIZE(tmu1_resources),
102 };
103 
104 static struct resource rtc_resources[] = {
105         [0] = {
106                 .start  = 0xffe80000,
107                 .end    = 0xffe80000 + 0x58 - 1,
108                 .flags  = IORESOURCE_IO,
109         },
110         [1] = {
111                 /* Shared Period/Carry/Alarm IRQ */
112                 .start  = evt2irq(0x480),
113                 .flags  = IORESOURCE_IRQ,
114         },
115 };
116 
117 static struct platform_device rtc_device = {
118         .name           = "sh-rtc",
119         .id             = -1,
120         .num_resources  = ARRAY_SIZE(rtc_resources),
121         .resource       = rtc_resources,
122 };
123 
124 /* DMA */
125 static const struct sh_dmae_channel sh7780_dmae0_channels[] = {
126         {
127                 .offset = 0,
128                 .dmars = 0,
129                 .dmars_bit = 0,
130         }, {
131                 .offset = 0x10,
132                 .dmars = 0,
133                 .dmars_bit = 8,
134         }, {
135                 .offset = 0x20,
136                 .dmars = 4,
137                 .dmars_bit = 0,
138         }, {
139                 .offset = 0x30,
140                 .dmars = 4,
141                 .dmars_bit = 8,
142         }, {
143                 .offset = 0x50,
144                 .dmars = 8,
145                 .dmars_bit = 0,
146         }, {
147                 .offset = 0x60,
148                 .dmars = 8,
149                 .dmars_bit = 8,
150         }
151 };
152 
153 static const struct sh_dmae_channel sh7780_dmae1_channels[] = {
154         {
155                 .offset = 0,
156         }, {
157                 .offset = 0x10,
158         }, {
159                 .offset = 0x20,
160         }, {
161                 .offset = 0x30,
162         }, {
163                 .offset = 0x50,
164         }, {
165                 .offset = 0x60,
166         }
167 };
168 
169 static const unsigned int ts_shift[] = TS_SHIFT;
170 
171 static struct sh_dmae_pdata dma0_platform_data = {
172         .channel        = sh7780_dmae0_channels,
173         .channel_num    = ARRAY_SIZE(sh7780_dmae0_channels),
174         .ts_low_shift   = CHCR_TS_LOW_SHIFT,
175         .ts_low_mask    = CHCR_TS_LOW_MASK,
176         .ts_high_shift  = CHCR_TS_HIGH_SHIFT,
177         .ts_high_mask   = CHCR_TS_HIGH_MASK,
178         .ts_shift       = ts_shift,
179         .ts_shift_num   = ARRAY_SIZE(ts_shift),
180         .dmaor_init     = DMAOR_INIT,
181 };
182 
183 static struct sh_dmae_pdata dma1_platform_data = {
184         .channel        = sh7780_dmae1_channels,
185         .channel_num    = ARRAY_SIZE(sh7780_dmae1_channels),
186         .ts_low_shift   = CHCR_TS_LOW_SHIFT,
187         .ts_low_mask    = CHCR_TS_LOW_MASK,
188         .ts_high_shift  = CHCR_TS_HIGH_SHIFT,
189         .ts_high_mask   = CHCR_TS_HIGH_MASK,
190         .ts_shift       = ts_shift,
191         .ts_shift_num   = ARRAY_SIZE(ts_shift),
192         .dmaor_init     = DMAOR_INIT,
193 };
194 
195 static struct resource sh7780_dmae0_resources[] = {
196         [0] = {
197                 /* Channel registers and DMAOR */
198                 .start  = 0xfc808020,
199                 .end    = 0xfc80808f,
200                 .flags  = IORESOURCE_MEM,
201         },
202         [1] = {
203                 /* DMARSx */
204                 .start  = 0xfc809000,
205                 .end    = 0xfc80900b,
206                 .flags  = IORESOURCE_MEM,
207         },
208         {
209                 /*
210                  * Real DMA error vector is 0x6c0, and channel
211                  * vectors are 0x640-0x6a0, 0x780-0x7a0
212                  */
213                 .name   = "error_irq",
214                 .start  = evt2irq(0x640),
215                 .end    = evt2irq(0x640),
216                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
217         },
218 };
219 
220 static struct resource sh7780_dmae1_resources[] = {
221         [0] = {
222                 /* Channel registers and DMAOR */
223                 .start  = 0xfc818020,
224                 .end    = 0xfc81808f,
225                 .flags  = IORESOURCE_MEM,
226         },
227         /* DMAC1 has no DMARS */
228         {
229                 /*
230                  * Real DMA error vector is 0x6c0, and channel
231                  * vectors are 0x7c0-0x7e0, 0xd80-0xde0
232                  */
233                 .name   = "error_irq",
234                 .start  = evt2irq(0x7c0),
235                 .end    = evt2irq(0x7c0),
236                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
237         },
238 };
239 
240 static struct platform_device dma0_device = {
241         .name           = "sh-dma-engine",
242         .id             = 0,
243         .resource       = sh7780_dmae0_resources,
244         .num_resources  = ARRAY_SIZE(sh7780_dmae0_resources),
245         .dev            = {
246                 .platform_data  = &dma0_platform_data,
247         },
248 };
249 
250 static struct platform_device dma1_device = {
251         .name           = "sh-dma-engine",
252         .id             = 1,
253         .resource       = sh7780_dmae1_resources,
254         .num_resources  = ARRAY_SIZE(sh7780_dmae1_resources),
255         .dev            = {
256                 .platform_data  = &dma1_platform_data,
257         },
258 };
259 
260 static struct platform_device *sh7780_devices[] __initdata = {
261         &scif0_device,
262         &scif1_device,
263         &tmu0_device,
264         &tmu1_device,
265         &rtc_device,
266         &dma0_device,
267         &dma1_device,
268 };
269 
270 static int __init sh7780_devices_setup(void)
271 {
272         return platform_add_devices(sh7780_devices,
273                                     ARRAY_SIZE(sh7780_devices));
274 }
275 arch_initcall(sh7780_devices_setup);
276 
277 static struct platform_device *sh7780_early_devices[] __initdata = {
278         &scif0_device,
279         &scif1_device,
280         &tmu0_device,
281         &tmu1_device,
282 };
283 
284 void __init plat_early_device_setup(void)
285 {
286         if (mach_is_sh2007()) {
287                 scif0_platform_data.scscr &= ~SCSCR_CKE1;
288                 scif1_platform_data.scscr &= ~SCSCR_CKE1;
289         }
290 
291         early_platform_add_devices(sh7780_early_devices,
292                                    ARRAY_SIZE(sh7780_early_devices));
293 }
294 
295 enum {
296         UNUSED = 0,
297 
298         /* interrupt sources */
299 
300         IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
301         IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
302         IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
303         IRL_HHLL, IRL_HHLH, IRL_HHHL,
304 
305         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
306         RTC, WDT, TMU0, TMU1, TMU2, TMU2_TICPI,
307         HUDI, DMAC0, SCIF0, DMAC1, CMT, HAC,
308         PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5,
309         SCIF1, SIOF, HSPI, MMCIF, TMU3, TMU4, TMU5, SSI, FLCTL, GPIO,
310 
311         /* interrupt groups */
312 
313         TMU012, TMU345,
314 };
315 
316 static struct intc_vect vectors[] __initdata = {
317         INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
318         INTC_VECT(RTC, 0x4c0),
319         INTC_VECT(WDT, 0x560),
320         INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
321         INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
322         INTC_VECT(HUDI, 0x600),
323         INTC_VECT(DMAC0, 0x640), INTC_VECT(DMAC0, 0x660),
324         INTC_VECT(DMAC0, 0x680), INTC_VECT(DMAC0, 0x6a0),
325         INTC_VECT(DMAC0, 0x6c0),
326         INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720),
327         INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760),
328         INTC_VECT(DMAC0, 0x780), INTC_VECT(DMAC0, 0x7a0),
329         INTC_VECT(DMAC1, 0x7c0), INTC_VECT(DMAC1, 0x7e0),
330         INTC_VECT(CMT, 0x900), INTC_VECT(HAC, 0x980),
331         INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
332         INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
333         INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0),
334         INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0),
335         INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20),
336         INTC_VECT(SCIF1, 0xb80), INTC_VECT(SCIF1, 0xba0),
337         INTC_VECT(SCIF1, 0xbc0), INTC_VECT(SCIF1, 0xbe0),
338         INTC_VECT(SIOF, 0xc00), INTC_VECT(HSPI, 0xc80),
339         INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20),
340         INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60),
341         INTC_VECT(DMAC1, 0xd80), INTC_VECT(DMAC1, 0xda0),
342         INTC_VECT(DMAC1, 0xdc0), INTC_VECT(DMAC1, 0xde0),
343         INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
344         INTC_VECT(TMU5, 0xe40),
345         INTC_VECT(SSI, 0xe80),
346         INTC_VECT(FLCTL, 0xf00), INTC_VECT(FLCTL, 0xf20),
347         INTC_VECT(FLCTL, 0xf40), INTC_VECT(FLCTL, 0xf60),
348         INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0),
349         INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0),
350 };
351 
352 static struct intc_group groups[] __initdata = {
353         INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
354         INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
355 };
356 
357 static struct intc_mask_reg mask_registers[] __initdata = {
358         { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
359           { 0, 0, 0, 0, 0, 0, GPIO, FLCTL,
360             SSI, MMCIF, HSPI, SIOF, PCIC5, PCIINTD, PCIINTC, PCIINTB,
361             PCIINTA, PCISERR, HAC, CMT, 0, 0, DMAC1, DMAC0,
362             HUDI, 0, WDT, SCIF1, SCIF0, RTC, TMU345, TMU012 } },
363 };
364 
365 static struct intc_prio_reg prio_registers[] __initdata = {
366         { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
367                                                  TMU2, TMU2_TICPI } },
368         { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, RTC } },
369         { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1, WDT } },
370         { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { HUDI, DMAC0, DMAC1 } },
371         { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { CMT, HAC,
372                                                  PCISERR, PCIINTA, } },
373         { 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { PCIINTB, PCIINTC,
374                                                  PCIINTD, PCIC5 } },
375         { 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { SIOF, HSPI, MMCIF, SSI } },
376         { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { FLCTL, GPIO } },
377 };
378 
379 static DECLARE_INTC_DESC(intc_desc, "sh7780", vectors, groups,
380                          mask_registers, prio_registers, NULL);
381 
382 /* Support for external interrupt pins in IRQ mode */
383 
384 static struct intc_vect irq_vectors[] __initdata = {
385         INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
386         INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
387         INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
388         INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
389 };
390 
391 static struct intc_mask_reg irq_mask_registers[] __initdata = {
392         { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
393           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
394 };
395 
396 static struct intc_prio_reg irq_prio_registers[] __initdata = {
397         { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
398                                                IRQ4, IRQ5, IRQ6, IRQ7 } },
399 };
400 
401 static struct intc_sense_reg irq_sense_registers[] __initdata = {
402         { 0xffd0001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
403                                             IRQ4, IRQ5, IRQ6, IRQ7 } },
404 };
405 
406 static struct intc_mask_reg irq_ack_registers[] __initdata = {
407         { 0xffd00024, 0, 32, /* INTREQ */
408           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
409 };
410 
411 static DECLARE_INTC_DESC_ACK(intc_irq_desc, "sh7780-irq", irq_vectors,
412                              NULL, irq_mask_registers, irq_prio_registers,
413                              irq_sense_registers, irq_ack_registers);
414 
415 /* External interrupt pins in IRL mode */
416 
417 static struct intc_vect irl_vectors[] __initdata = {
418         INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
419         INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
420         INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
421         INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0),
422         INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320),
423         INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360),
424         INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0),
425         INTC_VECT(IRL_HHHL, 0x3c0),
426 };
427 
428 static struct intc_mask_reg irl3210_mask_registers[] __initdata = {
429         { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
430           { IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
431             IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
432             IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
433             IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
434 };
435 
436 static struct intc_mask_reg irl7654_mask_registers[] __initdata = {
437         { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
438           { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
439             IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
440             IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
441             IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
442             IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
443 };
444 
445 static DECLARE_INTC_DESC(intc_irl7654_desc, "sh7780-irl7654", irl_vectors,
446                          NULL, irl7654_mask_registers, NULL, NULL);
447 
448 static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7780-irl3210", irl_vectors,
449                          NULL, irl3210_mask_registers, NULL, NULL);
450 
451 #define INTC_ICR0       0xffd00000
452 #define INTC_INTMSK0    0xffd00044
453 #define INTC_INTMSK1    0xffd00048
454 #define INTC_INTMSK2    0xffd40080
455 #define INTC_INTMSKCLR1 0xffd00068
456 #define INTC_INTMSKCLR2 0xffd40084
457 
458 void __init plat_irq_setup(void)
459 {
460         /* disable IRQ7-0 */
461         __raw_writel(0xff000000, INTC_INTMSK0);
462 
463         /* disable IRL3-0 + IRL7-4 */
464         __raw_writel(0xc0000000, INTC_INTMSK1);
465         __raw_writel(0xfffefffe, INTC_INTMSK2);
466 
467         /* select IRL mode for IRL3-0 + IRL7-4 */
468         __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
469 
470         /* disable holding function, ie enable "SH-4 Mode" */
471         __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
472 
473         register_intc_controller(&intc_desc);
474 }
475 
476 void __init plat_irq_setup_pins(int mode)
477 {
478         switch (mode) {
479         case IRQ_MODE_IRQ:
480                 /* select IRQ mode for IRL3-0 + IRL7-4 */
481                 __raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
482                 register_intc_controller(&intc_irq_desc);
483                 break;
484         case IRQ_MODE_IRL7654:
485                 /* enable IRL7-4 but don't provide any masking */
486                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
487                 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
488                 break;
489         case IRQ_MODE_IRL3210:
490                 /* enable IRL0-3 but don't provide any masking */
491                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
492                 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
493                 break;
494         case IRQ_MODE_IRL7654_MASK:
495                 /* enable IRL7-4 and mask using cpu intc controller */
496                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
497                 register_intc_controller(&intc_irl7654_desc);
498                 break;
499         case IRQ_MODE_IRL3210_MASK:
500                 /* enable IRL0-3 and mask using cpu intc controller */
501                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
502                 register_intc_controller(&intc_irl3210_desc);
503                 break;
504         default:
505                 BUG();
506         }
507 }
508 

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