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TOMOYO Linux Cross Reference
Linux/arch/sh/kernel/cpu/sh4a/setup-sh7786.c

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  1 /*
  2  * SH7786 Setup
  3  *
  4  * Copyright (C) 2009 - 2011  Renesas Solutions Corp.
  5  * Kuninori Morimoto <morimoto.kuninori@renesas.com>
  6  * Paul Mundt <paul.mundt@renesas.com>
  7  *
  8  * Based on SH7785 Setup
  9  *
 10  *  Copyright (C) 2007  Paul Mundt
 11  *
 12  * This file is subject to the terms and conditions of the GNU General Public
 13  * License.  See the file "COPYING" in the main directory of this archive
 14  * for more details.
 15  */
 16 #include <linux/platform_device.h>
 17 #include <linux/init.h>
 18 #include <linux/serial.h>
 19 #include <linux/serial_sci.h>
 20 #include <linux/io.h>
 21 #include <linux/mm.h>
 22 #include <linux/dma-mapping.h>
 23 #include <linux/sh_timer.h>
 24 #include <linux/sh_dma.h>
 25 #include <linux/sh_intc.h>
 26 #include <linux/usb/ohci_pdriver.h>
 27 #include <cpu/dma-register.h>
 28 #include <asm/mmzone.h>
 29 
 30 static struct plat_sci_port scif0_platform_data = {
 31         .mapbase        = 0xffea0000,
 32         .flags          = UPF_BOOT_AUTOCONF,
 33         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
 34         .scbrr_algo_id  = SCBRR_ALGO_1,
 35         .type           = PORT_SCIF,
 36         .irqs           = { evt2irq(0x700),
 37                             evt2irq(0x720),
 38                             evt2irq(0x760),
 39                             evt2irq(0x740) },
 40         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
 41 };
 42 
 43 static struct platform_device scif0_device = {
 44         .name           = "sh-sci",
 45         .id             = 0,
 46         .dev            = {
 47                 .platform_data  = &scif0_platform_data,
 48         },
 49 };
 50 
 51 /*
 52  * The rest of these all have multiplexed IRQs
 53  */
 54 static struct plat_sci_port scif1_platform_data = {
 55         .mapbase        = 0xffeb0000,
 56         .flags          = UPF_BOOT_AUTOCONF,
 57         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
 58         .scbrr_algo_id  = SCBRR_ALGO_1,
 59         .type           = PORT_SCIF,
 60         .irqs           = SCIx_IRQ_MUXED(evt2irq(0x780)),
 61         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
 62 };
 63 
 64 static struct platform_device scif1_device = {
 65         .name           = "sh-sci",
 66         .id             = 1,
 67         .dev            = {
 68                 .platform_data  = &scif1_platform_data,
 69         },
 70 };
 71 
 72 static struct plat_sci_port scif2_platform_data = {
 73         .mapbase        = 0xffec0000,
 74         .flags          = UPF_BOOT_AUTOCONF,
 75         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
 76         .scbrr_algo_id  = SCBRR_ALGO_1,
 77         .type           = PORT_SCIF,
 78         .irqs           = SCIx_IRQ_MUXED(evt2irq(0x840)),
 79         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
 80 };
 81 
 82 static struct platform_device scif2_device = {
 83         .name           = "sh-sci",
 84         .id             = 2,
 85         .dev            = {
 86                 .platform_data  = &scif2_platform_data,
 87         },
 88 };
 89 
 90 static struct plat_sci_port scif3_platform_data = {
 91         .mapbase        = 0xffed0000,
 92         .flags          = UPF_BOOT_AUTOCONF,
 93         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
 94         .scbrr_algo_id  = SCBRR_ALGO_1,
 95         .type           = PORT_SCIF,
 96         .irqs           = SCIx_IRQ_MUXED(evt2irq(0x860)),
 97         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
 98 };
 99 
100 static struct platform_device scif3_device = {
101         .name           = "sh-sci",
102         .id             = 3,
103         .dev            = {
104                 .platform_data  = &scif3_platform_data,
105         },
106 };
107 
108 static struct plat_sci_port scif4_platform_data = {
109         .mapbase        = 0xffee0000,
110         .flags          = UPF_BOOT_AUTOCONF,
111         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
112         .scbrr_algo_id  = SCBRR_ALGO_1,
113         .type           = PORT_SCIF,
114         .irqs           = SCIx_IRQ_MUXED(evt2irq(0x880)),
115         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
116 };
117 
118 static struct platform_device scif4_device = {
119         .name           = "sh-sci",
120         .id             = 4,
121         .dev            = {
122                 .platform_data  = &scif4_platform_data,
123         },
124 };
125 
126 static struct plat_sci_port scif5_platform_data = {
127         .mapbase        = 0xffef0000,
128         .flags          = UPF_BOOT_AUTOCONF,
129         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
130         .scbrr_algo_id  = SCBRR_ALGO_1,
131         .type           = PORT_SCIF,
132         .irqs           = SCIx_IRQ_MUXED(evt2irq(0x8a0)),
133         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
134 };
135 
136 static struct platform_device scif5_device = {
137         .name           = "sh-sci",
138         .id             = 5,
139         .dev            = {
140                 .platform_data  = &scif5_platform_data,
141         },
142 };
143 
144 static struct sh_timer_config tmu0_platform_data = {
145         .channel_offset = 0x04,
146         .timer_bit = 0,
147         .clockevent_rating = 200,
148 };
149 
150 static struct resource tmu0_resources[] = {
151         [0] = {
152                 .start  = 0xffd80008,
153                 .end    = 0xffd80013,
154                 .flags  = IORESOURCE_MEM,
155         },
156         [1] = {
157                 .start  = evt2irq(0x400),
158                 .flags  = IORESOURCE_IRQ,
159         },
160 };
161 
162 static struct platform_device tmu0_device = {
163         .name           = "sh_tmu",
164         .id             = 0,
165         .dev = {
166                 .platform_data  = &tmu0_platform_data,
167         },
168         .resource       = tmu0_resources,
169         .num_resources  = ARRAY_SIZE(tmu0_resources),
170 };
171 
172 static struct sh_timer_config tmu1_platform_data = {
173         .channel_offset = 0x10,
174         .timer_bit = 1,
175         .clocksource_rating = 200,
176 };
177 
178 static struct resource tmu1_resources[] = {
179         [0] = {
180                 .start  = 0xffd80014,
181                 .end    = 0xffd8001f,
182                 .flags  = IORESOURCE_MEM,
183         },
184         [1] = {
185                 .start  = evt2irq(0x420),
186                 .flags  = IORESOURCE_IRQ,
187         },
188 };
189 
190 static struct platform_device tmu1_device = {
191         .name           = "sh_tmu",
192         .id             = 1,
193         .dev = {
194                 .platform_data  = &tmu1_platform_data,
195         },
196         .resource       = tmu1_resources,
197         .num_resources  = ARRAY_SIZE(tmu1_resources),
198 };
199 
200 static struct sh_timer_config tmu2_platform_data = {
201         .channel_offset = 0x1c,
202         .timer_bit = 2,
203 };
204 
205 static struct resource tmu2_resources[] = {
206         [0] = {
207                 .start  = 0xffd80020,
208                 .end    = 0xffd8002f,
209                 .flags  = IORESOURCE_MEM,
210         },
211         [1] = {
212                 .start  = evt2irq(0x440),
213                 .flags  = IORESOURCE_IRQ,
214         },
215 };
216 
217 static struct platform_device tmu2_device = {
218         .name           = "sh_tmu",
219         .id             = 2,
220         .dev = {
221                 .platform_data  = &tmu2_platform_data,
222         },
223         .resource       = tmu2_resources,
224         .num_resources  = ARRAY_SIZE(tmu2_resources),
225 };
226 
227 static struct sh_timer_config tmu3_platform_data = {
228         .channel_offset = 0x04,
229         .timer_bit = 0,
230 };
231 
232 static struct resource tmu3_resources[] = {
233         [0] = {
234                 .start  = 0xffda0008,
235                 .end    = 0xffda0013,
236                 .flags  = IORESOURCE_MEM,
237         },
238         [1] = {
239                 .start  = evt2irq(0x480),
240                 .flags  = IORESOURCE_IRQ,
241         },
242 };
243 
244 static struct platform_device tmu3_device = {
245         .name           = "sh_tmu",
246         .id             = 3,
247         .dev = {
248                 .platform_data  = &tmu3_platform_data,
249         },
250         .resource       = tmu3_resources,
251         .num_resources  = ARRAY_SIZE(tmu3_resources),
252 };
253 
254 static struct sh_timer_config tmu4_platform_data = {
255         .channel_offset = 0x10,
256         .timer_bit = 1,
257 };
258 
259 static struct resource tmu4_resources[] = {
260         [0] = {
261                 .start  = 0xffda0014,
262                 .end    = 0xffda001f,
263                 .flags  = IORESOURCE_MEM,
264         },
265         [1] = {
266                 .start  = evt2irq(0x4a0),
267                 .flags  = IORESOURCE_IRQ,
268         },
269 };
270 
271 static struct platform_device tmu4_device = {
272         .name           = "sh_tmu",
273         .id             = 4,
274         .dev = {
275                 .platform_data  = &tmu4_platform_data,
276         },
277         .resource       = tmu4_resources,
278         .num_resources  = ARRAY_SIZE(tmu4_resources),
279 };
280 
281 static struct sh_timer_config tmu5_platform_data = {
282         .channel_offset = 0x1c,
283         .timer_bit = 2,
284 };
285 
286 static struct resource tmu5_resources[] = {
287         [0] = {
288                 .start  = 0xffda0020,
289                 .end    = 0xffda002b,
290                 .flags  = IORESOURCE_MEM,
291         },
292         [1] = {
293                 .start  = evt2irq(0x4c0),
294                 .flags  = IORESOURCE_IRQ,
295         },
296 };
297 
298 static struct platform_device tmu5_device = {
299         .name           = "sh_tmu",
300         .id             = 5,
301         .dev = {
302                 .platform_data  = &tmu5_platform_data,
303         },
304         .resource       = tmu5_resources,
305         .num_resources  = ARRAY_SIZE(tmu5_resources),
306 };
307 
308 static struct sh_timer_config tmu6_platform_data = {
309         .channel_offset = 0x04,
310         .timer_bit = 0,
311 };
312 
313 static struct resource tmu6_resources[] = {
314         [0] = {
315                 .start  = 0xffdc0008,
316                 .end    = 0xffdc0013,
317                 .flags  = IORESOURCE_MEM,
318         },
319         [1] = {
320                 .start  = evt2irq(0x7a0),
321                 .flags  = IORESOURCE_IRQ,
322         },
323 };
324 
325 static struct platform_device tmu6_device = {
326         .name           = "sh_tmu",
327         .id             = 6,
328         .dev = {
329                 .platform_data  = &tmu6_platform_data,
330         },
331         .resource       = tmu6_resources,
332         .num_resources  = ARRAY_SIZE(tmu6_resources),
333 };
334 
335 static struct sh_timer_config tmu7_platform_data = {
336         .channel_offset = 0x10,
337         .timer_bit = 1,
338 };
339 
340 static struct resource tmu7_resources[] = {
341         [0] = {
342                 .start  = 0xffdc0014,
343                 .end    = 0xffdc001f,
344                 .flags  = IORESOURCE_MEM,
345         },
346         [1] = {
347                 .start  = evt2irq(0x7a0),
348                 .flags  = IORESOURCE_IRQ,
349         },
350 };
351 
352 static struct platform_device tmu7_device = {
353         .name           = "sh_tmu",
354         .id             = 7,
355         .dev = {
356                 .platform_data  = &tmu7_platform_data,
357         },
358         .resource       = tmu7_resources,
359         .num_resources  = ARRAY_SIZE(tmu7_resources),
360 };
361 
362 static struct sh_timer_config tmu8_platform_data = {
363         .channel_offset = 0x1c,
364         .timer_bit = 2,
365 };
366 
367 static struct resource tmu8_resources[] = {
368         [0] = {
369                 .start  = 0xffdc0020,
370                 .end    = 0xffdc002b,
371                 .flags  = IORESOURCE_MEM,
372         },
373         [1] = {
374                 .start  = evt2irq(0x7a0),
375                 .flags  = IORESOURCE_IRQ,
376         },
377 };
378 
379 static struct platform_device tmu8_device = {
380         .name           = "sh_tmu",
381         .id             = 8,
382         .dev = {
383                 .platform_data  = &tmu8_platform_data,
384         },
385         .resource       = tmu8_resources,
386         .num_resources  = ARRAY_SIZE(tmu8_resources),
387 };
388 
389 static struct sh_timer_config tmu9_platform_data = {
390         .channel_offset = 0x04,
391         .timer_bit = 0,
392 };
393 
394 static struct resource tmu9_resources[] = {
395         [0] = {
396                 .start  = 0xffde0008,
397                 .end    = 0xffde0013,
398                 .flags  = IORESOURCE_MEM,
399         },
400         [1] = {
401                 .start  = evt2irq(0x7c0),
402                 .flags  = IORESOURCE_IRQ,
403         },
404 };
405 
406 static struct platform_device tmu9_device = {
407         .name           = "sh_tmu",
408         .id             = 9,
409         .dev = {
410                 .platform_data  = &tmu9_platform_data,
411         },
412         .resource       = tmu9_resources,
413         .num_resources  = ARRAY_SIZE(tmu9_resources),
414 };
415 
416 static struct sh_timer_config tmu10_platform_data = {
417         .channel_offset = 0x10,
418         .timer_bit = 1,
419 };
420 
421 static struct resource tmu10_resources[] = {
422         [0] = {
423                 .start  = 0xffde0014,
424                 .end    = 0xffde001f,
425                 .flags  = IORESOURCE_MEM,
426         },
427         [1] = {
428                 .start  = evt2irq(0x7c0),
429                 .flags  = IORESOURCE_IRQ,
430         },
431 };
432 
433 static struct platform_device tmu10_device = {
434         .name           = "sh_tmu",
435         .id             = 10,
436         .dev = {
437                 .platform_data  = &tmu10_platform_data,
438         },
439         .resource       = tmu10_resources,
440         .num_resources  = ARRAY_SIZE(tmu10_resources),
441 };
442 
443 static struct sh_timer_config tmu11_platform_data = {
444         .channel_offset = 0x1c,
445         .timer_bit = 2,
446 };
447 
448 static struct resource tmu11_resources[] = {
449         [0] = {
450                 .start  = 0xffde0020,
451                 .end    = 0xffde002b,
452                 .flags  = IORESOURCE_MEM,
453         },
454         [1] = {
455                 .start  = evt2irq(0x7c0),
456                 .flags  = IORESOURCE_IRQ,
457         },
458 };
459 
460 static struct platform_device tmu11_device = {
461         .name           = "sh_tmu",
462         .id             = 11,
463         .dev = {
464                 .platform_data  = &tmu11_platform_data,
465         },
466         .resource       = tmu11_resources,
467         .num_resources  = ARRAY_SIZE(tmu11_resources),
468 };
469 
470 static const struct sh_dmae_channel dmac0_channels[] = {
471         {
472                 .offset = 0,
473                 .dmars = 0,
474                 .dmars_bit = 0,
475         }, {
476                 .offset = 0x10,
477                 .dmars = 0,
478                 .dmars_bit = 8,
479         }, {
480                 .offset = 0x20,
481                 .dmars = 4,
482                 .dmars_bit = 0,
483         }, {
484                 .offset = 0x30,
485                 .dmars = 4,
486                 .dmars_bit = 8,
487         }, {
488                 .offset = 0x50,
489                 .dmars = 8,
490                 .dmars_bit = 0,
491         }, {
492                 .offset = 0x60,
493                 .dmars = 8,
494                 .dmars_bit = 8,
495         }
496 };
497 
498 static const unsigned int ts_shift[] = TS_SHIFT;
499 
500 static struct sh_dmae_pdata dma0_platform_data = {
501         .channel        = dmac0_channels,
502         .channel_num    = ARRAY_SIZE(dmac0_channels),
503         .ts_low_shift   = CHCR_TS_LOW_SHIFT,
504         .ts_low_mask    = CHCR_TS_LOW_MASK,
505         .ts_high_shift  = CHCR_TS_HIGH_SHIFT,
506         .ts_high_mask   = CHCR_TS_HIGH_MASK,
507         .ts_shift       = ts_shift,
508         .ts_shift_num   = ARRAY_SIZE(ts_shift),
509         .dmaor_init     = DMAOR_INIT,
510 };
511 
512 /* Resource order important! */
513 static struct resource dmac0_resources[] = {
514         {
515                 /* Channel registers and DMAOR */
516                 .start  = 0xfe008020,
517                 .end    = 0xfe00808f,
518                 .flags  = IORESOURCE_MEM,
519         }, {
520                 /* DMARSx */
521                 .start  = 0xfe009000,
522                 .end    = 0xfe00900b,
523                 .flags  = IORESOURCE_MEM,
524         }, {
525                 .name   = "error_irq",
526                 .start  = evt2irq(0x5c0),
527                 .end    = evt2irq(0x5c0),
528                 .flags  = IORESOURCE_IRQ,
529         }, {
530                 /* IRQ for channels 0-5 */
531                 .start  = evt2irq(0x500),
532                 .end    = evt2irq(0x5a0),
533                 .flags  = IORESOURCE_IRQ,
534         },
535 };
536 
537 static struct platform_device dma0_device = {
538         .name           = "sh-dma-engine",
539         .id             = 0,
540         .resource       = dmac0_resources,
541         .num_resources  = ARRAY_SIZE(dmac0_resources),
542         .dev            = {
543                 .platform_data  = &dma0_platform_data,
544         },
545 };
546 
547 #define USB_EHCI_START 0xffe70000
548 #define USB_OHCI_START 0xffe70400
549 
550 static struct resource usb_ehci_resources[] = {
551         [0] = {
552                 .start  = USB_EHCI_START,
553                 .end    = USB_EHCI_START + 0x3ff,
554                 .flags  = IORESOURCE_MEM,
555         },
556         [1] = {
557                 .start  = evt2irq(0xba0),
558                 .end    = evt2irq(0xba0),
559                 .flags  = IORESOURCE_IRQ,
560         },
561 };
562 
563 static struct platform_device usb_ehci_device = {
564         .name           = "sh_ehci",
565         .id             = -1,
566         .dev = {
567                 .dma_mask               = &usb_ehci_device.dev.coherent_dma_mask,
568                 .coherent_dma_mask      = DMA_BIT_MASK(32),
569         },
570         .num_resources  = ARRAY_SIZE(usb_ehci_resources),
571         .resource       = usb_ehci_resources,
572 };
573 
574 static struct resource usb_ohci_resources[] = {
575         [0] = {
576                 .start  = USB_OHCI_START,
577                 .end    = USB_OHCI_START + 0x3ff,
578                 .flags  = IORESOURCE_MEM,
579         },
580         [1] = {
581                 .start  = evt2irq(0xba0),
582                 .end    = evt2irq(0xba0),
583                 .flags  = IORESOURCE_IRQ,
584         },
585 };
586 
587 static struct usb_ohci_pdata usb_ohci_pdata;
588 
589 static struct platform_device usb_ohci_device = {
590         .name           = "ohci-platform",
591         .id             = -1,
592         .dev = {
593                 .dma_mask               = &usb_ohci_device.dev.coherent_dma_mask,
594                 .coherent_dma_mask      = DMA_BIT_MASK(32),
595                 .platform_data          = &usb_ohci_pdata,
596         },
597         .num_resources  = ARRAY_SIZE(usb_ohci_resources),
598         .resource       = usb_ohci_resources,
599 };
600 
601 static struct platform_device *sh7786_early_devices[] __initdata = {
602         &scif0_device,
603         &scif1_device,
604         &scif2_device,
605         &scif3_device,
606         &scif4_device,
607         &scif5_device,
608         &tmu0_device,
609         &tmu1_device,
610         &tmu2_device,
611         &tmu3_device,
612         &tmu4_device,
613         &tmu5_device,
614         &tmu6_device,
615         &tmu7_device,
616         &tmu8_device,
617         &tmu9_device,
618         &tmu10_device,
619         &tmu11_device,
620 };
621 
622 static struct platform_device *sh7786_devices[] __initdata = {
623         &dma0_device,
624         &usb_ehci_device,
625         &usb_ohci_device,
626 };
627 
628 /*
629  * Please call this function if your platform board
630  * use external clock for USB
631  * */
632 #define USBCTL0         0xffe70858
633 #define CLOCK_MODE_MASK 0xffffff7f
634 #define EXT_CLOCK_MODE  0x00000080
635 
636 void __init sh7786_usb_use_exclock(void)
637 {
638         u32 val = __raw_readl(USBCTL0) & CLOCK_MODE_MASK;
639         __raw_writel(val | EXT_CLOCK_MODE, USBCTL0);
640 }
641 
642 #define USBINITREG1     0xffe70094
643 #define USBINITREG2     0xffe7009c
644 #define USBINITVAL1     0x00ff0040
645 #define USBINITVAL2     0x00000001
646 
647 #define USBPCTL1        0xffe70804
648 #define USBST           0xffe70808
649 #define PHY_ENB         0x00000001
650 #define PLL_ENB         0x00000002
651 #define PHY_RST         0x00000004
652 #define ACT_PLL_STATUS  0xc0000000
653 
654 static void __init sh7786_usb_setup(void)
655 {
656         int i = 1000000;
657 
658         /*
659          * USB initial settings
660          *
661          * The following settings are necessary
662          * for using the USB modules.
663          *
664          * see "USB Initial Settings" for detail
665          */
666         __raw_writel(USBINITVAL1, USBINITREG1);
667         __raw_writel(USBINITVAL2, USBINITREG2);
668 
669         /*
670          * Set the PHY and PLL enable bit
671          */
672         __raw_writel(PHY_ENB | PLL_ENB, USBPCTL1);
673         while (i--) {
674                 if (ACT_PLL_STATUS == (__raw_readl(USBST) & ACT_PLL_STATUS)) {
675                         /* Set the PHY RST bit */
676                         __raw_writel(PHY_ENB | PLL_ENB | PHY_RST, USBPCTL1);
677                         printk(KERN_INFO "sh7786 usb setup done\n");
678                         break;
679                 }
680                 cpu_relax();
681         }
682 }
683 
684 enum {
685         UNUSED = 0,
686 
687         /* interrupt sources */
688         IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
689         IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
690         IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
691         IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
692 
693         IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
694         IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
695         IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
696         IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
697 
698         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
699         WDT,
700         TMU0_0, TMU0_1, TMU0_2, TMU0_3,
701         TMU1_0, TMU1_1, TMU1_2,
702         DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6,
703         HUDI1, HUDI0,
704         DMAC1_0, DMAC1_1, DMAC1_2, DMAC1_3,
705         HPB_0, HPB_1, HPB_2,
706         SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3,
707         SCIF1,
708         TMU2, TMU3,
709         SCIF2, SCIF3, SCIF4, SCIF5,
710         Eth_0, Eth_1,
711         PCIeC0_0, PCIeC0_1, PCIeC0_2,
712         PCIeC1_0, PCIeC1_1, PCIeC1_2,
713         USB,
714         I2C0, I2C1,
715         DU,
716         SSI0, SSI1, SSI2, SSI3,
717         PCIeC2_0, PCIeC2_1, PCIeC2_2,
718         HAC0, HAC1,
719         FLCTL,
720         HSPI,
721         GPIO0, GPIO1,
722         Thermal,
723         INTICI0, INTICI1, INTICI2, INTICI3,
724         INTICI4, INTICI5, INTICI6, INTICI7,
725 
726         /* Muxed sub-events */
727         TXI1, BRI1, RXI1, ERI1,
728 };
729 
730 static struct intc_vect sh7786_vectors[] __initdata = {
731         INTC_VECT(WDT, 0x3e0),
732         INTC_VECT(TMU0_0, 0x400), INTC_VECT(TMU0_1, 0x420),
733         INTC_VECT(TMU0_2, 0x440), INTC_VECT(TMU0_3, 0x460),
734         INTC_VECT(TMU1_0, 0x480), INTC_VECT(TMU1_1, 0x4a0),
735         INTC_VECT(TMU1_2, 0x4c0),
736         INTC_VECT(DMAC0_0, 0x500), INTC_VECT(DMAC0_1, 0x520),
737         INTC_VECT(DMAC0_2, 0x540), INTC_VECT(DMAC0_3, 0x560),
738         INTC_VECT(DMAC0_4, 0x580), INTC_VECT(DMAC0_5, 0x5a0),
739         INTC_VECT(DMAC0_6, 0x5c0),
740         INTC_VECT(HUDI1, 0x5e0), INTC_VECT(HUDI0, 0x600),
741         INTC_VECT(DMAC1_0, 0x620), INTC_VECT(DMAC1_1, 0x640),
742         INTC_VECT(DMAC1_2, 0x660), INTC_VECT(DMAC1_3, 0x680),
743         INTC_VECT(HPB_0, 0x6a0), INTC_VECT(HPB_1, 0x6c0),
744         INTC_VECT(HPB_2, 0x6e0),
745         INTC_VECT(SCIF0_0, 0x700), INTC_VECT(SCIF0_1, 0x720),
746         INTC_VECT(SCIF0_2, 0x740), INTC_VECT(SCIF0_3, 0x760),
747         INTC_VECT(SCIF1, 0x780),
748         INTC_VECT(TMU2, 0x7a0), INTC_VECT(TMU3, 0x7c0),
749         INTC_VECT(SCIF2, 0x840), INTC_VECT(SCIF3, 0x860),
750         INTC_VECT(SCIF4, 0x880), INTC_VECT(SCIF5, 0x8a0),
751         INTC_VECT(Eth_0, 0x8c0), INTC_VECT(Eth_1, 0x8e0),
752         INTC_VECT(PCIeC0_0, 0xae0), INTC_VECT(PCIeC0_1, 0xb00),
753         INTC_VECT(PCIeC0_2, 0xb20),
754         INTC_VECT(PCIeC1_0, 0xb40), INTC_VECT(PCIeC1_1, 0xb60),
755         INTC_VECT(PCIeC1_2, 0xb80),
756         INTC_VECT(USB, 0xba0),
757         INTC_VECT(I2C0, 0xcc0), INTC_VECT(I2C1, 0xce0),
758         INTC_VECT(DU, 0xd00),
759         INTC_VECT(SSI0, 0xd20), INTC_VECT(SSI1, 0xd40),
760         INTC_VECT(SSI2, 0xd60), INTC_VECT(SSI3, 0xd80),
761         INTC_VECT(PCIeC2_0, 0xda0), INTC_VECT(PCIeC2_1, 0xdc0),
762         INTC_VECT(PCIeC2_2, 0xde0),
763         INTC_VECT(HAC0, 0xe00), INTC_VECT(HAC1, 0xe20),
764         INTC_VECT(FLCTL, 0xe40),
765         INTC_VECT(HSPI, 0xe80),
766         INTC_VECT(GPIO0, 0xea0), INTC_VECT(GPIO1, 0xec0),
767         INTC_VECT(Thermal, 0xee0),
768         INTC_VECT(INTICI0, 0xf00), INTC_VECT(INTICI1, 0xf20),
769         INTC_VECT(INTICI2, 0xf40), INTC_VECT(INTICI3, 0xf60),
770         INTC_VECT(INTICI4, 0xf80), INTC_VECT(INTICI5, 0xfa0),
771         INTC_VECT(INTICI6, 0xfc0), INTC_VECT(INTICI7, 0xfe0),
772 };
773 
774 #define CnINTMSK0       0xfe410030
775 #define CnINTMSK1       0xfe410040
776 #define CnINTMSKCLR0    0xfe410050
777 #define CnINTMSKCLR1    0xfe410060
778 #define CnINT2MSKR0     0xfe410a20
779 #define CnINT2MSKR1     0xfe410a24
780 #define CnINT2MSKR2     0xfe410a28
781 #define CnINT2MSKR3     0xfe410a2c
782 #define CnINT2MSKCR0    0xfe410a30
783 #define CnINT2MSKCR1    0xfe410a34
784 #define CnINT2MSKCR2    0xfe410a38
785 #define CnINT2MSKCR3    0xfe410a3c
786 #define INTMSK2         0xfe410068
787 #define INTMSKCLR2      0xfe41006c
788 
789 #define INTDISTCR0      0xfe4100b0
790 #define INTDISTCR1      0xfe4100b4
791 #define INT2DISTCR0     0xfe410900
792 #define INT2DISTCR1     0xfe410904
793 #define INT2DISTCR2     0xfe410908
794 #define INT2DISTCR3     0xfe41090c
795 
796 static struct intc_mask_reg sh7786_mask_registers[] __initdata = {
797         { CnINTMSK0, CnINTMSKCLR0, 32,
798           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 },
799             INTC_SMP_BALANCING(INTDISTCR0) },
800         { INTMSK2, INTMSKCLR2, 32,
801           { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
802             IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
803             IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
804             IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
805             IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
806             IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
807             IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
808             IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
809         { CnINT2MSKR0, CnINT2MSKCR0 , 32,
810           { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
811             0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, WDT },
812             INTC_SMP_BALANCING(INT2DISTCR0) },
813         { CnINT2MSKR1, CnINT2MSKCR1, 32,
814           { TMU0_0, TMU0_1, TMU0_2, TMU0_3, TMU1_0, TMU1_1, TMU1_2, 0,
815             DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6,
816             HUDI1, HUDI0,
817             DMAC1_0, DMAC1_1, DMAC1_2, DMAC1_3,
818             HPB_0, HPB_1, HPB_2,
819             SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3,
820             SCIF1,
821             TMU2, TMU3, 0, }, INTC_SMP_BALANCING(INT2DISTCR1) },
822         { CnINT2MSKR2, CnINT2MSKCR2, 32,
823           { 0, 0, SCIF2, SCIF3, SCIF4, SCIF5,
824             Eth_0, Eth_1,
825             0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
826             PCIeC0_0, PCIeC0_1, PCIeC0_2,
827             PCIeC1_0, PCIeC1_1, PCIeC1_2,
828             USB, 0, 0 }, INTC_SMP_BALANCING(INT2DISTCR2) },
829         { CnINT2MSKR3, CnINT2MSKCR3, 32,
830           { 0, 0, 0, 0, 0, 0,
831             I2C0, I2C1,
832             DU, SSI0, SSI1, SSI2, SSI3,
833             PCIeC2_0, PCIeC2_1, PCIeC2_2,
834             HAC0, HAC1,
835             FLCTL, 0,
836             HSPI, GPIO0, GPIO1, Thermal,
837             0, 0, 0, 0, 0, 0, 0, 0 }, INTC_SMP_BALANCING(INT2DISTCR3) },
838 };
839 
840 static struct intc_prio_reg sh7786_prio_registers[] __initdata = {
841         { 0xfe410010, 0, 32, 4, /* INTPRI */   { IRQ0, IRQ1, IRQ2, IRQ3,
842                                                  IRQ4, IRQ5, IRQ6, IRQ7 } },
843         { 0xfe410800, 0, 32, 8, /* INT2PRI0 */ { 0, 0, 0, WDT } },
844         { 0xfe410804, 0, 32, 8, /* INT2PRI1 */ { TMU0_0, TMU0_1,
845                                                  TMU0_2, TMU0_3 } },
846         { 0xfe410808, 0, 32, 8, /* INT2PRI2 */ { TMU1_0, TMU1_1,
847                                                  TMU1_2, 0 } },
848         { 0xfe41080c, 0, 32, 8, /* INT2PRI3 */ { DMAC0_0, DMAC0_1,
849                                                  DMAC0_2, DMAC0_3 } },
850         { 0xfe410810, 0, 32, 8, /* INT2PRI4 */ { DMAC0_4, DMAC0_5,
851                                                  DMAC0_6, HUDI1 } },
852         { 0xfe410814, 0, 32, 8, /* INT2PRI5 */ { HUDI0, DMAC1_0,
853                                                  DMAC1_1, DMAC1_2 } },
854         { 0xfe410818, 0, 32, 8, /* INT2PRI6 */ { DMAC1_3, HPB_0,
855                                                  HPB_1, HPB_2 } },
856         { 0xfe41081c, 0, 32, 8, /* INT2PRI7 */ { SCIF0_0, SCIF0_1,
857                                                  SCIF0_2, SCIF0_3 } },
858         { 0xfe410820, 0, 32, 8, /* INT2PRI8 */ { SCIF1, TMU2, TMU3, 0 } },
859         { 0xfe410824, 0, 32, 8, /* INT2PRI9 */ { 0, 0, SCIF2, SCIF3 } },
860         { 0xfe410828, 0, 32, 8, /* INT2PRI10 */ { SCIF4, SCIF5,
861                                                   Eth_0, Eth_1 } },
862         { 0xfe41082c, 0, 32, 8, /* INT2PRI11 */ { 0, 0, 0, 0 } },
863         { 0xfe410830, 0, 32, 8, /* INT2PRI12 */ { 0, 0, 0, 0 } },
864         { 0xfe410834, 0, 32, 8, /* INT2PRI13 */ { 0, 0, 0, 0 } },
865         { 0xfe410838, 0, 32, 8, /* INT2PRI14 */ { 0, 0, 0, PCIeC0_0 } },
866         { 0xfe41083c, 0, 32, 8, /* INT2PRI15 */ { PCIeC0_1, PCIeC0_2,
867                                                   PCIeC1_0, PCIeC1_1 } },
868         { 0xfe410840, 0, 32, 8, /* INT2PRI16 */ { PCIeC1_2, USB, 0, 0 } },
869         { 0xfe410844, 0, 32, 8, /* INT2PRI17 */ { 0, 0, 0, 0 } },
870         { 0xfe410848, 0, 32, 8, /* INT2PRI18 */ { 0, 0, I2C0, I2C1 } },
871         { 0xfe41084c, 0, 32, 8, /* INT2PRI19 */ { DU, SSI0, SSI1, SSI2 } },
872         { 0xfe410850, 0, 32, 8, /* INT2PRI20 */ { SSI3, PCIeC2_0,
873                                                   PCIeC2_1, PCIeC2_2 } },
874         { 0xfe410854, 0, 32, 8, /* INT2PRI21 */ { HAC0, HAC1, FLCTL, 0 } },
875         { 0xfe410858, 0, 32, 8, /* INT2PRI22 */ { HSPI, GPIO0,
876                                                   GPIO1, Thermal } },
877         { 0xfe41085c, 0, 32, 8, /* INT2PRI23 */ { 0, 0, 0, 0 } },
878         { 0xfe410860, 0, 32, 8, /* INT2PRI24 */ { 0, 0, 0, 0 } },
879         { 0xfe410090, 0xfe4100a0, 32, 4, /* CnICIPRI / CnICIPRICLR */
880           { INTICI7, INTICI6, INTICI5, INTICI4,
881             INTICI3, INTICI2, INTICI1, INTICI0 }, INTC_SMP(4, 2) },
882 };
883 
884 static struct intc_subgroup sh7786_subgroups[] __initdata = {
885         { 0xfe410c20, 32, SCIF1,
886           { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
887             0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, TXI1, BRI1, RXI1, ERI1 } },
888 };
889 
890 static struct intc_desc sh7786_intc_desc __initdata = {
891         .name           = "sh7786",
892         .hw             = {
893                 .vectors        = sh7786_vectors,
894                 .nr_vectors     = ARRAY_SIZE(sh7786_vectors),
895                 .mask_regs      = sh7786_mask_registers,
896                 .nr_mask_regs   = ARRAY_SIZE(sh7786_mask_registers),
897                 .subgroups      = sh7786_subgroups,
898                 .nr_subgroups   = ARRAY_SIZE(sh7786_subgroups),
899                 .prio_regs      = sh7786_prio_registers,
900                 .nr_prio_regs   = ARRAY_SIZE(sh7786_prio_registers),
901         },
902 };
903 
904 /* Support for external interrupt pins in IRQ mode */
905 static struct intc_vect vectors_irq0123[] __initdata = {
906         INTC_VECT(IRQ0, 0x200), INTC_VECT(IRQ1, 0x240),
907         INTC_VECT(IRQ2, 0x280), INTC_VECT(IRQ3, 0x2c0),
908 };
909 
910 static struct intc_vect vectors_irq4567[] __initdata = {
911         INTC_VECT(IRQ4, 0x300), INTC_VECT(IRQ5, 0x340),
912         INTC_VECT(IRQ6, 0x380), INTC_VECT(IRQ7, 0x3c0),
913 };
914 
915 static struct intc_sense_reg sh7786_sense_registers[] __initdata = {
916         { 0xfe41001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
917                                             IRQ4, IRQ5, IRQ6, IRQ7 } },
918 };
919 
920 static struct intc_mask_reg sh7786_ack_registers[] __initdata = {
921         { 0xfe410024, 0, 32, /* INTREQ */
922           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
923 };
924 
925 static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7786-irq0123",
926                              vectors_irq0123, NULL, sh7786_mask_registers,
927                              sh7786_prio_registers, sh7786_sense_registers,
928                              sh7786_ack_registers);
929 
930 static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7786-irq4567",
931                              vectors_irq4567, NULL, sh7786_mask_registers,
932                              sh7786_prio_registers, sh7786_sense_registers,
933                              sh7786_ack_registers);
934 
935 /* External interrupt pins in IRL mode */
936 
937 static struct intc_vect vectors_irl0123[] __initdata = {
938         INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
939         INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
940         INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
941         INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
942         INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
943         INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
944         INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
945         INTC_VECT(IRL0_HHHL, 0x3c0),
946 };
947 
948 static struct intc_vect vectors_irl4567[] __initdata = {
949         INTC_VECT(IRL4_LLLL, 0x900), INTC_VECT(IRL4_LLLH, 0x920),
950         INTC_VECT(IRL4_LLHL, 0x940), INTC_VECT(IRL4_LLHH, 0x960),
951         INTC_VECT(IRL4_LHLL, 0x980), INTC_VECT(IRL4_LHLH, 0x9a0),
952         INTC_VECT(IRL4_LHHL, 0x9c0), INTC_VECT(IRL4_LHHH, 0x9e0),
953         INTC_VECT(IRL4_HLLL, 0xa00), INTC_VECT(IRL4_HLLH, 0xa20),
954         INTC_VECT(IRL4_HLHL, 0xa40), INTC_VECT(IRL4_HLHH, 0xa60),
955         INTC_VECT(IRL4_HHLL, 0xa80), INTC_VECT(IRL4_HHLH, 0xaa0),
956         INTC_VECT(IRL4_HHHL, 0xac0),
957 };
958 
959 static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7786-irl0123", vectors_irl0123,
960                          NULL, sh7786_mask_registers, NULL, NULL);
961 
962 static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7786-irl4567", vectors_irl4567,
963                          NULL, sh7786_mask_registers, NULL, NULL);
964 
965 #define INTC_ICR0       0xfe410000
966 #define INTC_INTMSK0    CnINTMSK0
967 #define INTC_INTMSK1    CnINTMSK1
968 #define INTC_INTMSK2    INTMSK2
969 #define INTC_INTMSKCLR1 CnINTMSKCLR1
970 #define INTC_INTMSKCLR2 INTMSKCLR2
971 
972 void __init plat_irq_setup(void)
973 {
974         /* disable IRQ3-0 + IRQ7-4 */
975         __raw_writel(0xff000000, INTC_INTMSK0);
976 
977         /* disable IRL3-0 + IRL7-4 */
978         __raw_writel(0xc0000000, INTC_INTMSK1);
979         __raw_writel(0xfffefffe, INTC_INTMSK2);
980 
981         /* select IRL mode for IRL3-0 + IRL7-4 */
982         __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
983 
984         register_intc_controller(&sh7786_intc_desc);
985 }
986 
987 void __init plat_irq_setup_pins(int mode)
988 {
989         switch (mode) {
990         case IRQ_MODE_IRQ7654:
991                 /* select IRQ mode for IRL7-4 */
992                 __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
993                 register_intc_controller(&intc_desc_irq4567);
994                 break;
995         case IRQ_MODE_IRQ3210:
996                 /* select IRQ mode for IRL3-0 */
997                 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
998                 register_intc_controller(&intc_desc_irq0123);
999                 break;
1000         case IRQ_MODE_IRL7654:
1001                 /* enable IRL7-4 but don't provide any masking */
1002                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
1003                 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
1004                 break;
1005         case IRQ_MODE_IRL3210:
1006                 /* enable IRL0-3 but don't provide any masking */
1007                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
1008                 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
1009                 break;
1010         case IRQ_MODE_IRL7654_MASK:
1011                 /* enable IRL7-4 and mask using cpu intc controller */
1012                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
1013                 register_intc_controller(&intc_desc_irl4567);
1014                 break;
1015         case IRQ_MODE_IRL3210_MASK:
1016                 /* enable IRL0-3 and mask using cpu intc controller */
1017                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
1018                 register_intc_controller(&intc_desc_irl0123);
1019                 break;
1020         default:
1021                 BUG();
1022         }
1023 }
1024 
1025 void __init plat_mem_setup(void)
1026 {
1027 }
1028 
1029 static int __init sh7786_devices_setup(void)
1030 {
1031         int ret, irq;
1032 
1033         sh7786_usb_setup();
1034 
1035         /*
1036          * De-mux SCIF1 IRQs if possible
1037          */
1038         irq = intc_irq_lookup(sh7786_intc_desc.name, TXI1);
1039         if (irq > 0) {
1040                 scif1_platform_data.irqs[SCIx_TXI_IRQ] = irq;
1041                 scif1_platform_data.irqs[SCIx_ERI_IRQ] =
1042                         intc_irq_lookup(sh7786_intc_desc.name, ERI1);
1043                 scif1_platform_data.irqs[SCIx_BRI_IRQ] =
1044                         intc_irq_lookup(sh7786_intc_desc.name, BRI1);
1045                 scif1_platform_data.irqs[SCIx_RXI_IRQ] =
1046                         intc_irq_lookup(sh7786_intc_desc.name, RXI1);
1047         }
1048 
1049         ret = platform_add_devices(sh7786_early_devices,
1050                                    ARRAY_SIZE(sh7786_early_devices));
1051         if (unlikely(ret != 0))
1052                 return ret;
1053 
1054         return platform_add_devices(sh7786_devices,
1055                                     ARRAY_SIZE(sh7786_devices));
1056 }
1057 arch_initcall(sh7786_devices_setup);
1058 
1059 void __init plat_early_device_setup(void)
1060 {
1061         early_platform_add_devices(sh7786_early_devices,
1062                                    ARRAY_SIZE(sh7786_early_devices));
1063 }
1064 

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