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Linux/arch/sh/kernel/cpu/sh4a/smp-shx3.c

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  1 /*
  2  * SH-X3 SMP
  3  *
  4  *  Copyright (C) 2007 - 2010  Paul Mundt
  5  *  Copyright (C) 2007  Magnus Damm
  6  *
  7  * This file is subject to the terms and conditions of the GNU General Public
  8  * License.  See the file "COPYING" in the main directory of this archive
  9  * for more details.
 10  */
 11 #include <linux/init.h>
 12 #include <linux/kernel.h>
 13 #include <linux/cpumask.h>
 14 #include <linux/smp.h>
 15 #include <linux/interrupt.h>
 16 #include <linux/io.h>
 17 #include <linux/sched.h>
 18 #include <linux/delay.h>
 19 #include <linux/cpu.h>
 20 #include <asm/sections.h>
 21 
 22 #define STBCR_REG(phys_id) (0xfe400004 | (phys_id << 12))
 23 #define RESET_REG(phys_id) (0xfe400008 | (phys_id << 12))
 24 
 25 #define STBCR_MSTP      0x00000001
 26 #define STBCR_RESET     0x00000002
 27 #define STBCR_SLEEP     0x00000004
 28 #define STBCR_LTSLP     0x80000000
 29 
 30 static irqreturn_t ipi_interrupt_handler(int irq, void *arg)
 31 {
 32         unsigned int message = (unsigned int)(long)arg;
 33         unsigned int cpu = hard_smp_processor_id();
 34         unsigned int offs = 4 * cpu;
 35         unsigned int x;
 36 
 37         x = __raw_readl(0xfe410070 + offs); /* C0INITICI..CnINTICI */
 38         x &= (1 << (message << 2));
 39         __raw_writel(x, 0xfe410080 + offs); /* C0INTICICLR..CnINTICICLR */
 40 
 41         smp_message_recv(message);
 42 
 43         return IRQ_HANDLED;
 44 }
 45 
 46 static void shx3_smp_setup(void)
 47 {
 48         unsigned int cpu = 0;
 49         int i, num;
 50 
 51         init_cpu_possible(cpumask_of(cpu));
 52 
 53         /* Enable light sleep for the boot CPU */
 54         __raw_writel(__raw_readl(STBCR_REG(cpu)) | STBCR_LTSLP, STBCR_REG(cpu));
 55 
 56         __cpu_number_map[0] = 0;
 57         __cpu_logical_map[0] = 0;
 58 
 59         /*
 60          * Do this stupidly for now.. we don't have an easy way to probe
 61          * for the total number of cores.
 62          */
 63         for (i = 1, num = 0; i < NR_CPUS; i++) {
 64                 set_cpu_possible(i, true);
 65                 __cpu_number_map[i] = ++num;
 66                 __cpu_logical_map[num] = i;
 67         }
 68 
 69         printk(KERN_INFO "Detected %i available secondary CPU(s)\n", num);
 70 }
 71 
 72 static void shx3_prepare_cpus(unsigned int max_cpus)
 73 {
 74         int i;
 75 
 76         BUILD_BUG_ON(SMP_MSG_NR >= 8);
 77 
 78         for (i = 0; i < SMP_MSG_NR; i++)
 79                 request_irq(104 + i, ipi_interrupt_handler,
 80                             IRQF_PERCPU, "IPI", (void *)(long)i);
 81 
 82         for (i = 0; i < max_cpus; i++)
 83                 set_cpu_present(i, true);
 84 }
 85 
 86 static void shx3_start_cpu(unsigned int cpu, unsigned long entry_point)
 87 {
 88         if (__in_29bit_mode())
 89                 __raw_writel(entry_point, RESET_REG(cpu));
 90         else
 91                 __raw_writel(virt_to_phys(entry_point), RESET_REG(cpu));
 92 
 93         if (!(__raw_readl(STBCR_REG(cpu)) & STBCR_MSTP))
 94                 __raw_writel(STBCR_MSTP, STBCR_REG(cpu));
 95 
 96         while (!(__raw_readl(STBCR_REG(cpu)) & STBCR_MSTP))
 97                 cpu_relax();
 98 
 99         /* Start up secondary processor by sending a reset */
100         __raw_writel(STBCR_RESET | STBCR_LTSLP, STBCR_REG(cpu));
101 }
102 
103 static unsigned int shx3_smp_processor_id(void)
104 {
105         return __raw_readl(0xff000048); /* CPIDR */
106 }
107 
108 static void shx3_send_ipi(unsigned int cpu, unsigned int message)
109 {
110         unsigned long addr = 0xfe410070 + (cpu * 4);
111 
112         BUG_ON(cpu >= 4);
113 
114         __raw_writel(1 << (message << 2), addr); /* C0INTICI..CnINTICI */
115 }
116 
117 static void shx3_update_boot_vector(unsigned int cpu)
118 {
119         __raw_writel(STBCR_MSTP, STBCR_REG(cpu));
120         while (!(__raw_readl(STBCR_REG(cpu)) & STBCR_MSTP))
121                 cpu_relax();
122         __raw_writel(STBCR_RESET, STBCR_REG(cpu));
123 }
124 
125 static int
126 shx3_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
127 {
128         unsigned int cpu = (unsigned int)hcpu;
129 
130         switch (action) {
131         case CPU_UP_PREPARE:
132                 shx3_update_boot_vector(cpu);
133                 break;
134         case CPU_ONLINE:
135                 pr_info("CPU %u is now online\n", cpu);
136                 break;
137         case CPU_DEAD:
138                 break;
139         }
140 
141         return NOTIFY_OK;
142 }
143 
144 static struct notifier_block shx3_cpu_notifier = {
145         .notifier_call          = shx3_cpu_callback,
146 };
147 
148 static int register_shx3_cpu_notifier(void)
149 {
150         register_hotcpu_notifier(&shx3_cpu_notifier);
151         return 0;
152 }
153 late_initcall(register_shx3_cpu_notifier);
154 
155 struct plat_smp_ops shx3_smp_ops = {
156         .smp_setup              = shx3_smp_setup,
157         .prepare_cpus           = shx3_prepare_cpus,
158         .start_cpu              = shx3_start_cpu,
159         .smp_processor_id       = shx3_smp_processor_id,
160         .send_ipi               = shx3_send_ipi,
161         .cpu_die                = native_cpu_die,
162         .cpu_disable            = native_cpu_disable,
163         .play_dead              = native_play_dead,
164 };
165 

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