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Linux/arch/sh/mm/tlb-sh3.c

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  1 /*
  2  * arch/sh/mm/tlb-sh3.c
  3  *
  4  * SH-3 specific TLB operations
  5  *
  6  * Copyright (C) 1999  Niibe Yutaka
  7  * Copyright (C) 2002  Paul Mundt
  8  *
  9  * Released under the terms of the GNU GPL v2.0.
 10  */
 11 #include <linux/signal.h>
 12 #include <linux/sched.h>
 13 #include <linux/kernel.h>
 14 #include <linux/errno.h>
 15 #include <linux/string.h>
 16 #include <linux/types.h>
 17 #include <linux/ptrace.h>
 18 #include <linux/mman.h>
 19 #include <linux/mm.h>
 20 #include <linux/smp.h>
 21 #include <linux/interrupt.h>
 22 
 23 #include <asm/io.h>
 24 #include <linux/uaccess.h>
 25 #include <asm/pgalloc.h>
 26 #include <asm/mmu_context.h>
 27 #include <asm/cacheflush.h>
 28 
 29 void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
 30 {
 31         unsigned long flags, pteval, vpn;
 32 
 33         /*
 34          * Handle debugger faulting in for debugee.
 35          */
 36         if (vma && current->active_mm != vma->vm_mm)
 37                 return;
 38 
 39         local_irq_save(flags);
 40 
 41         /* Set PTEH register */
 42         vpn = (address & MMU_VPN_MASK) | get_asid();
 43         __raw_writel(vpn, MMU_PTEH);
 44 
 45         pteval = pte_val(pte);
 46 
 47         /* Set PTEL register */
 48         pteval &= _PAGE_FLAGS_HARDWARE_MASK; /* drop software flags */
 49         /* conveniently, we want all the software flags to be 0 anyway */
 50         __raw_writel(pteval, MMU_PTEL);
 51 
 52         /* Load the TLB */
 53         asm volatile("ldtlb": /* no output */ : /* no input */ : "memory");
 54         local_irq_restore(flags);
 55 }
 56 
 57 void local_flush_tlb_one(unsigned long asid, unsigned long page)
 58 {
 59         unsigned long addr, data;
 60         int i, ways = MMU_NTLB_WAYS;
 61 
 62         /*
 63          * NOTE: PTEH.ASID should be set to this MM
 64          *       _AND_ we need to write ASID to the array.
 65          *
 66          * It would be simple if we didn't need to set PTEH.ASID...
 67          */
 68         addr = MMU_TLB_ADDRESS_ARRAY | (page & 0x1F000);
 69         data = (page & 0xfffe0000) | asid; /* VALID bit is off */
 70 
 71         if ((current_cpu_data.flags & CPU_HAS_MMU_PAGE_ASSOC)) {
 72                 addr |= MMU_PAGE_ASSOC_BIT;
 73                 ways = 1;       /* we already know the way .. */
 74         }
 75 
 76         for (i = 0; i < ways; i++)
 77                 __raw_writel(data, addr + (i << 8));
 78 }
 79 
 80 void local_flush_tlb_all(void)
 81 {
 82         unsigned long flags, status;
 83 
 84         /*
 85          * Flush all the TLB.
 86          *
 87          * Write to the MMU control register's bit:
 88          *      TF-bit for SH-3, TI-bit for SH-4.
 89          *      It's same position, bit #2.
 90          */
 91         local_irq_save(flags);
 92         status = __raw_readl(MMUCR);
 93         status |= 0x04;
 94         __raw_writel(status, MMUCR);
 95         ctrl_barrier();
 96         local_irq_restore(flags);
 97 }
 98 

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