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TOMOYO Linux Cross Reference
Linux/arch/sparc/include/asm/hypervisor.h

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Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 /* SPDX-License-Identifier: GPL-2.0 */
  2 #ifndef _SPARC64_HYPERVISOR_H
  3 #define _SPARC64_HYPERVISOR_H
  4 
  5 /* Sun4v hypervisor interfaces and defines.
  6  *
  7  * Hypervisor calls are made via traps to software traps number 0x80
  8  * and above.  Registers %o0 to %o5 serve as argument, status, and
  9  * return value registers.
 10  *
 11  * There are two kinds of these traps.  First there are the normal
 12  * "fast traps" which use software trap 0x80 and encode the function
 13  * to invoke by number in register %o5.  Argument and return value
 14  * handling is as follows:
 15  *
 16  * -----------------------------------------------
 17  * |  %o5  | function number |     undefined     |
 18  * |  %o0  |   argument 0    |   return status   |
 19  * |  %o1  |   argument 1    |   return value 1  |
 20  * |  %o2  |   argument 2    |   return value 2  |
 21  * |  %o3  |   argument 3    |   return value 3  |
 22  * |  %o4  |   argument 4    |   return value 4  |
 23  * -----------------------------------------------
 24  *
 25  * The second type are "hyper-fast traps" which encode the function
 26  * number in the software trap number itself.  So these use trap
 27  * numbers > 0x80.  The register usage for hyper-fast traps is as
 28  * follows:
 29  *
 30  * -----------------------------------------------
 31  * |  %o0  |   argument 0    |   return status   |
 32  * |  %o1  |   argument 1    |   return value 1  |
 33  * |  %o2  |   argument 2    |   return value 2  |
 34  * |  %o3  |   argument 3    |   return value 3  |
 35  * |  %o4  |   argument 4    |   return value 4  |
 36  * -----------------------------------------------
 37  *
 38  * Registers providing explicit arguments to the hypervisor calls
 39  * are volatile across the call.  Upon return their values are
 40  * undefined unless explicitly specified as containing a particular
 41  * return value by the specific call.  The return status is always
 42  * returned in register %o0, zero indicates a successful execution of
 43  * the hypervisor call and other values indicate an error status as
 44  * defined below.  So, for example, if a hyper-fast trap takes
 45  * arguments 0, 1, and 2, then %o0, %o1, and %o2 are volatile across
 46  * the call and %o3, %o4, and %o5 would be preserved.
 47  *
 48  * If the hypervisor trap is invalid, or the fast trap function number
 49  * is invalid, HV_EBADTRAP will be returned in %o0.  Also, all 64-bits
 50  * of the argument and return values are significant.
 51  */
 52 
 53 /* Trap numbers.  */
 54 #define HV_FAST_TRAP            0x80
 55 #define HV_MMU_MAP_ADDR_TRAP    0x83
 56 #define HV_MMU_UNMAP_ADDR_TRAP  0x84
 57 #define HV_TTRACE_ADDENTRY_TRAP 0x85
 58 #define HV_CORE_TRAP            0xff
 59 
 60 /* Error codes.  */
 61 #define HV_EOK                          0  /* Successful return            */
 62 #define HV_ENOCPU                       1  /* Invalid CPU id               */
 63 #define HV_ENORADDR                     2  /* Invalid real address         */
 64 #define HV_ENOINTR                      3  /* Invalid interrupt id         */
 65 #define HV_EBADPGSZ                     4  /* Invalid pagesize encoding    */
 66 #define HV_EBADTSB                      5  /* Invalid TSB description      */
 67 #define HV_EINVAL                       6  /* Invalid argument             */
 68 #define HV_EBADTRAP                     7  /* Invalid function number      */
 69 #define HV_EBADALIGN                    8  /* Invalid address alignment    */
 70 #define HV_EWOULDBLOCK                  9  /* Cannot complete w/o blocking */
 71 #define HV_ENOACCESS                    10 /* No access to resource        */
 72 #define HV_EIO                          11 /* I/O error                    */
 73 #define HV_ECPUERROR                    12 /* CPU in error state           */
 74 #define HV_ENOTSUPPORTED                13 /* Function not supported       */
 75 #define HV_ENOMAP                       14 /* No mapping found             */
 76 #define HV_ETOOMANY                     15 /* Too many items specified     */
 77 #define HV_ECHANNEL                     16 /* Invalid LDC channel          */
 78 #define HV_EBUSY                        17 /* Resource busy                */
 79 #define HV_EUNAVAILABLE                 23 /* Resource or operation not
 80                                             * currently available, but may
 81                                             * become available in the future
 82                                             */
 83 
 84 /* mach_exit()
 85  * TRAP:        HV_FAST_TRAP
 86  * FUNCTION:    HV_FAST_MACH_EXIT
 87  * ARG0:        exit code
 88  * ERRORS:      This service does not return.
 89  *
 90  * Stop all CPUs in the virtual domain and place them into the stopped
 91  * state.  The 64-bit exit code may be passed to a service entity as
 92  * the domain's exit status.  On systems without a service entity, the
 93  * domain will undergo a reset, and the boot firmware will be
 94  * reloaded.
 95  *
 96  * This function will never return to the guest that invokes it.
 97  *
 98  * Note: By convention an exit code of zero denotes a successful exit by
 99  *       the guest code.  A non-zero exit code denotes a guest specific
100  *       error indication.
101  *
102  */
103 #define HV_FAST_MACH_EXIT               0x00
104 
105 #ifndef __ASSEMBLY__
106 void sun4v_mach_exit(unsigned long exit_code);
107 #endif
108 
109 /* Domain services.  */
110 
111 /* mach_desc()
112  * TRAP:        HV_FAST_TRAP
113  * FUNCTION:    HV_FAST_MACH_DESC
114  * ARG0:        buffer
115  * ARG1:        length
116  * RET0:        status
117  * RET1:        length
118  * ERRORS:      HV_EBADALIGN    Buffer is badly aligned
119  *              HV_ENORADDR     Buffer is to an illegal real address.
120  *              HV_EINVAL       Buffer length is too small for complete
121  *                              machine description.
122  *
123  * Copy the most current machine description into the buffer indicated
124  * by the real address in ARG0.  The buffer provided must be 16 byte
125  * aligned.  Upon success or HV_EINVAL, this service returns the
126  * actual size of the machine description in the RET1 return value.
127  *
128  * Note: A method of determining the appropriate buffer size for the
129  *       machine description is to first call this service with a buffer
130  *       length of 0 bytes.
131  */
132 #define HV_FAST_MACH_DESC               0x01
133 
134 #ifndef __ASSEMBLY__
135 unsigned long sun4v_mach_desc(unsigned long buffer_pa,
136                               unsigned long buf_len,
137                               unsigned long *real_buf_len);
138 #endif
139 
140 /* mach_sir()
141  * TRAP:        HV_FAST_TRAP
142  * FUNCTION:    HV_FAST_MACH_SIR
143  * ERRORS:      This service does not return.
144  *
145  * Perform a software initiated reset of the virtual machine domain.
146  * All CPUs are captured as soon as possible, all hardware devices are
147  * returned to the entry default state, and the domain is restarted at
148  * the SIR (trap type 0x04) real trap table (RTBA) entry point on one
149  * of the CPUs.  The single CPU restarted is selected as determined by
150  * platform specific policy.  Memory is preserved across this
151  * operation.
152  */
153 #define HV_FAST_MACH_SIR                0x02
154 
155 #ifndef __ASSEMBLY__
156 void sun4v_mach_sir(void);
157 #endif
158 
159 /* mach_set_watchdog()
160  * TRAP:        HV_FAST_TRAP
161  * FUNCTION:    HV_FAST_MACH_SET_WATCHDOG
162  * ARG0:        timeout in milliseconds
163  * RET0:        status
164  * RET1:        time remaining in milliseconds
165  *
166  * A guest uses this API to set a watchdog timer.  Once the gues has set
167  * the timer, it must call the timer service again either to disable or
168  * postpone the expiration.  If the timer expires before being reset or
169  * disabled, then the hypervisor take a platform specific action leading
170  * to guest termination within a bounded time period.  The platform action
171  * may include recovery actions such as reporting the expiration to a
172  * Service Processor, and/or automatically restarting the gues.
173  *
174  * The 'timeout' parameter is specified in milliseconds, however the
175  * implementated granularity is given by the 'watchdog-resolution'
176  * property in the 'platform' node of the guest's machine description.
177  * The largest allowed timeout value is specified by the
178  * 'watchdog-max-timeout' property of the 'platform' node.
179  *
180  * If the 'timeout' argument is not zero, the watchdog timer is set to
181  * expire after a minimum of 'timeout' milliseconds.
182  *
183  * If the 'timeout' argument is zero, the watchdog timer is disabled.
184  *
185  * If the 'timeout' value exceeds the value of the 'max-watchdog-timeout'
186  * property, the hypervisor leaves the watchdog timer state unchanged,
187  * and returns a status of EINVAL.
188  *
189  * The 'time remaining' return value is valid regardless of whether the
190  * return status is EOK or EINVAL.  A non-zero return value indicates the
191  * number of milliseconds that were remaining until the timer was to expire.
192  * If less than one millisecond remains, the return value is '1'.  If the
193  * watchdog timer was disabled at the time of the call, the return value is
194  * zero.
195  *
196  * If the hypervisor cannot support the exact timeout value requested, but
197  * can support a larger timeout value, the hypervisor may round the actual
198  * timeout to a value larger than the requested timeout, consequently the
199  * 'time remaining' return value may be larger than the previously requested
200  * timeout value.
201  *
202  * Any guest OS debugger should be aware that the watchdog service may be in
203  * use.  Consequently, it is recommended that the watchdog service is
204  * disabled upon debugger entry (e.g. reaching a breakpoint), and then
205  * re-enabled upon returning to normal execution.  The API has been designed
206  * with this in mind, and the 'time remaining' result of the disable call may
207  * be used directly as the timeout argument of the re-enable call.
208  */
209 #define HV_FAST_MACH_SET_WATCHDOG       0x05
210 
211 #ifndef __ASSEMBLY__
212 unsigned long sun4v_mach_set_watchdog(unsigned long timeout,
213                                       unsigned long *orig_timeout);
214 #endif
215 
216 /* CPU services.
217  *
218  * CPUs represent devices that can execute software threads.  A single
219  * chip that contains multiple cores or strands is represented as
220  * multiple CPUs with unique CPU identifiers.  CPUs are exported to
221  * OBP via the machine description (and to the OS via the OBP device
222  * tree).  CPUs are always in one of three states: stopped, running,
223  * or error.
224  *
225  * A CPU ID is a pre-assigned 16-bit value that uniquely identifies a
226  * CPU within a logical domain.  Operations that are to be performed
227  * on multiple CPUs specify them via a CPU list.  A CPU list is an
228  * array in real memory, of which each 16-bit word is a CPU ID.  CPU
229  * lists are passed through the API as two arguments.  The first is
230  * the number of entries (16-bit words) in the CPU list, and the
231  * second is the (real address) pointer to the CPU ID list.
232  */
233 
234 /* cpu_start()
235  * TRAP:        HV_FAST_TRAP
236  * FUNCTION:    HV_FAST_CPU_START
237  * ARG0:        CPU ID
238  * ARG1:        PC
239  * ARG2:        RTBA
240  * ARG3:        target ARG0
241  * RET0:        status
242  * ERRORS:      ENOCPU          Invalid CPU ID
243  *              EINVAL          Target CPU ID is not in the stopped state
244  *              ENORADDR        Invalid PC or RTBA real address
245  *              EBADALIGN       Unaligned PC or unaligned RTBA
246  *              EWOULDBLOCK     Starting resources are not available
247  *
248  * Start CPU with given CPU ID with PC in %pc and with a real trap
249  * base address value of RTBA.  The indicated CPU must be in the
250  * stopped state.  The supplied RTBA must be aligned on a 256 byte
251  * boundary.  On successful completion, the specified CPU will be in
252  * the running state and will be supplied with "target ARG0" in %o0
253  * and RTBA in %tba.
254  */
255 #define HV_FAST_CPU_START               0x10
256 
257 #ifndef __ASSEMBLY__
258 unsigned long sun4v_cpu_start(unsigned long cpuid,
259                               unsigned long pc,
260                               unsigned long rtba,
261                               unsigned long arg0);
262 #endif
263 
264 /* cpu_stop()
265  * TRAP:        HV_FAST_TRAP
266  * FUNCTION:    HV_FAST_CPU_STOP
267  * ARG0:        CPU ID
268  * RET0:        status
269  * ERRORS:      ENOCPU          Invalid CPU ID
270  *              EINVAL          Target CPU ID is the current cpu
271  *              EINVAL          Target CPU ID is not in the running state
272  *              EWOULDBLOCK     Stopping resources are not available
273  *              ENOTSUPPORTED   Not supported on this platform
274  *
275  * The specified CPU is stopped.  The indicated CPU must be in the
276  * running state.  On completion, it will be in the stopped state.  It
277  * is not legal to stop the current CPU.
278  *
279  * Note: As this service cannot be used to stop the current cpu, this service
280  *       may not be used to stop the last running CPU in a domain.  To stop
281  *       and exit a running domain, a guest must use the mach_exit() service.
282  */
283 #define HV_FAST_CPU_STOP                0x11
284 
285 #ifndef __ASSEMBLY__
286 unsigned long sun4v_cpu_stop(unsigned long cpuid);
287 #endif
288 
289 /* cpu_yield()
290  * TRAP:        HV_FAST_TRAP
291  * FUNCTION:    HV_FAST_CPU_YIELD
292  * RET0:        status
293  * ERRORS:      No possible error.
294  *
295  * Suspend execution on the current CPU.  Execution will resume when
296  * an interrupt (device, %stick_compare, or cross-call) is targeted to
297  * the CPU.  On some CPUs, this API may be used by the hypervisor to
298  * save power by disabling hardware strands.
299  */
300 #define HV_FAST_CPU_YIELD               0x12
301 
302 #ifndef __ASSEMBLY__
303 unsigned long sun4v_cpu_yield(void);
304 #endif
305 
306 /* cpu_poke()
307  * TRAP:        HV_FAST_TRAP
308  * FUNCTION:    HV_FAST_CPU_POKE
309  * RET0:        status
310  * ERRORS:      ENOCPU          cpuid refers to a CPU that does not exist
311  *              EINVAL          cpuid is current CPU
312  *
313  * Poke CPU cpuid. If the target CPU is currently suspended having
314  * invoked the cpu-yield service, that vCPU will be resumed.
315  * Poke interrupts may only be sent to valid, non-local CPUs.
316  * It is not legal to poke the current vCPU.
317  */
318 #define HV_FAST_CPU_POKE                0x13
319 
320 #ifndef __ASSEMBLY__
321 unsigned long sun4v_cpu_poke(unsigned long cpuid);
322 #endif
323 
324 /* cpu_qconf()
325  * TRAP:        HV_FAST_TRAP
326  * FUNCTION:    HV_FAST_CPU_QCONF
327  * ARG0:        queue
328  * ARG1:        base real address
329  * ARG2:        number of entries
330  * RET0:        status
331  * ERRORS:      ENORADDR        Invalid base real address
332  *              EINVAL          Invalid queue or number of entries is less
333  *                              than 2 or too large.
334  *              EBADALIGN       Base real address is not correctly aligned
335  *                              for size.
336  *
337  * Configure the given queue to be placed at the given base real
338  * address, with the given number of entries.  The number of entries
339  * must be a power of 2.  The base real address must be aligned
340  * exactly to match the queue size.  Each queue entry is 64 bytes
341  * long, so for example a 32 entry queue must be aligned on a 2048
342  * byte real address boundary.
343  *
344  * The specified queue is unconfigured if the number of entries is given
345  * as zero.
346  *
347  * For the current version of this API service, the argument queue is defined
348  * as follows:
349  *
350  *      queue           description
351  *      -----           -------------------------
352  *      0x3c            cpu mondo queue
353  *      0x3d            device mondo queue
354  *      0x3e            resumable error queue
355  *      0x3f            non-resumable error queue
356  *
357  * Note: The maximum number of entries for each queue for a specific cpu may
358  *       be determined from the machine description.
359  */
360 #define HV_FAST_CPU_QCONF               0x14
361 #define  HV_CPU_QUEUE_CPU_MONDO          0x3c
362 #define  HV_CPU_QUEUE_DEVICE_MONDO       0x3d
363 #define  HV_CPU_QUEUE_RES_ERROR          0x3e
364 #define  HV_CPU_QUEUE_NONRES_ERROR       0x3f
365 
366 #ifndef __ASSEMBLY__
367 unsigned long sun4v_cpu_qconf(unsigned long type,
368                               unsigned long queue_paddr,
369                               unsigned long num_queue_entries);
370 #endif
371 
372 /* cpu_qinfo()
373  * TRAP:        HV_FAST_TRAP
374  * FUNCTION:    HV_FAST_CPU_QINFO
375  * ARG0:        queue
376  * RET0:        status
377  * RET1:        base real address
378  * RET1:        number of entries
379  * ERRORS:      EINVAL          Invalid queue
380  *
381  * Return the configuration info for the given queue.  The base real
382  * address and number of entries of the defined queue are returned.
383  * The queue argument values are the same as for cpu_qconf() above.
384  *
385  * If the specified queue is a valid queue number, but no queue has
386  * been defined, the number of entries will be set to zero and the
387  * base real address returned is undefined.
388  */
389 #define HV_FAST_CPU_QINFO               0x15
390 
391 /* cpu_mondo_send()
392  * TRAP:        HV_FAST_TRAP
393  * FUNCTION:    HV_FAST_CPU_MONDO_SEND
394  * ARG0-1:      CPU list
395  * ARG2:        data real address
396  * RET0:        status
397  * ERRORS:      EBADALIGN       Mondo data is not 64-byte aligned or CPU list
398  *                              is not 2-byte aligned.
399  *              ENORADDR        Invalid data mondo address, or invalid cpu list
400  *                              address.
401  *              ENOCPU          Invalid cpu in CPU list
402  *              EWOULDBLOCK     Some or all of the listed CPUs did not receive
403  *                              the mondo
404  *              ECPUERROR       One or more of the listed CPUs are in error
405  *                              state, use HV_FAST_CPU_STATE to see which ones
406  *              EINVAL          CPU list includes caller's CPU ID
407  *
408  * Send a mondo interrupt to the CPUs in the given CPU list with the
409  * 64-bytes at the given data real address.  The data must be 64-byte
410  * aligned.  The mondo data will be delivered to the cpu_mondo queues
411  * of the recipient CPUs.
412  *
413  * In all cases, error or not, the CPUs in the CPU list to which the
414  * mondo has been successfully delivered will be indicated by having
415  * their entry in CPU list updated with the value 0xffff.
416  */
417 #define HV_FAST_CPU_MONDO_SEND          0x42
418 
419 #ifndef __ASSEMBLY__
420 unsigned long sun4v_cpu_mondo_send(unsigned long cpu_count,
421                                    unsigned long cpu_list_pa,
422                                    unsigned long mondo_block_pa);
423 #endif
424 
425 /* cpu_myid()
426  * TRAP:        HV_FAST_TRAP
427  * FUNCTION:    HV_FAST_CPU_MYID
428  * RET0:        status
429  * RET1:        CPU ID
430  * ERRORS:      No errors defined.
431  *
432  * Return the hypervisor ID handle for the current CPU.  Use by a
433  * virtual CPU to discover it's own identity.
434  */
435 #define HV_FAST_CPU_MYID                0x16
436 
437 /* cpu_state()
438  * TRAP:        HV_FAST_TRAP
439  * FUNCTION:    HV_FAST_CPU_STATE
440  * ARG0:        CPU ID
441  * RET0:        status
442  * RET1:        state
443  * ERRORS:      ENOCPU          Invalid CPU ID
444  *
445  * Retrieve the current state of the CPU with the given CPU ID.
446  */
447 #define HV_FAST_CPU_STATE               0x17
448 #define  HV_CPU_STATE_STOPPED            0x01
449 #define  HV_CPU_STATE_RUNNING            0x02
450 #define  HV_CPU_STATE_ERROR              0x03
451 
452 #ifndef __ASSEMBLY__
453 long sun4v_cpu_state(unsigned long cpuid);
454 #endif
455 
456 /* cpu_set_rtba()
457  * TRAP:        HV_FAST_TRAP
458  * FUNCTION:    HV_FAST_CPU_SET_RTBA
459  * ARG0:        RTBA
460  * RET0:        status
461  * RET1:        previous RTBA
462  * ERRORS:      ENORADDR        Invalid RTBA real address
463  *              EBADALIGN       RTBA is incorrectly aligned for a trap table
464  *
465  * Set the real trap base address of the local cpu to the given RTBA.
466  * The supplied RTBA must be aligned on a 256 byte boundary.  Upon
467  * success the previous value of the RTBA is returned in RET1.
468  *
469  * Note: This service does not affect %tba
470  */
471 #define HV_FAST_CPU_SET_RTBA            0x18
472 
473 /* cpu_set_rtba()
474  * TRAP:        HV_FAST_TRAP
475  * FUNCTION:    HV_FAST_CPU_GET_RTBA
476  * RET0:        status
477  * RET1:        previous RTBA
478  * ERRORS:      No possible error.
479  *
480  * Returns the current value of RTBA in RET1.
481  */
482 #define HV_FAST_CPU_GET_RTBA            0x19
483 
484 /* MMU services.
485  *
486  * Layout of a TSB description for mmu_tsb_ctx{,non}0() calls.
487  */
488 #ifndef __ASSEMBLY__
489 struct hv_tsb_descr {
490         unsigned short          pgsz_idx;
491         unsigned short          assoc;
492         unsigned int            num_ttes;       /* in TTEs */
493         unsigned int            ctx_idx;
494         unsigned int            pgsz_mask;
495         unsigned long           tsb_base;
496         unsigned long           resv;
497 };
498 #endif
499 #define HV_TSB_DESCR_PGSZ_IDX_OFFSET    0x00
500 #define HV_TSB_DESCR_ASSOC_OFFSET       0x02
501 #define HV_TSB_DESCR_NUM_TTES_OFFSET    0x04
502 #define HV_TSB_DESCR_CTX_IDX_OFFSET     0x08
503 #define HV_TSB_DESCR_PGSZ_MASK_OFFSET   0x0c
504 #define HV_TSB_DESCR_TSB_BASE_OFFSET    0x10
505 #define HV_TSB_DESCR_RESV_OFFSET        0x18
506 
507 /* Page size bitmask.  */
508 #define HV_PGSZ_MASK_8K                 (1 << 0)
509 #define HV_PGSZ_MASK_64K                (1 << 1)
510 #define HV_PGSZ_MASK_512K               (1 << 2)
511 #define HV_PGSZ_MASK_4MB                (1 << 3)
512 #define HV_PGSZ_MASK_32MB               (1 << 4)
513 #define HV_PGSZ_MASK_256MB              (1 << 5)
514 #define HV_PGSZ_MASK_2GB                (1 << 6)
515 #define HV_PGSZ_MASK_16GB               (1 << 7)
516 
517 /* Page size index.  The value given in the TSB descriptor must correspond
518  * to the smallest page size specified in the pgsz_mask page size bitmask.
519  */
520 #define HV_PGSZ_IDX_8K                  0
521 #define HV_PGSZ_IDX_64K                 1
522 #define HV_PGSZ_IDX_512K                2
523 #define HV_PGSZ_IDX_4MB                 3
524 #define HV_PGSZ_IDX_32MB                4
525 #define HV_PGSZ_IDX_256MB               5
526 #define HV_PGSZ_IDX_2GB                 6
527 #define HV_PGSZ_IDX_16GB                7
528 
529 /* MMU fault status area.
530  *
531  * MMU related faults have their status and fault address information
532  * placed into a memory region made available by privileged code.  Each
533  * virtual processor must make a mmu_fault_area_conf() call to tell the
534  * hypervisor where that processor's fault status should be stored.
535  *
536  * The fault status block is a multiple of 64-bytes and must be aligned
537  * on a 64-byte boundary.
538  */
539 #ifndef __ASSEMBLY__
540 struct hv_fault_status {
541         unsigned long           i_fault_type;
542         unsigned long           i_fault_addr;
543         unsigned long           i_fault_ctx;
544         unsigned long           i_reserved[5];
545         unsigned long           d_fault_type;
546         unsigned long           d_fault_addr;
547         unsigned long           d_fault_ctx;
548         unsigned long           d_reserved[5];
549 };
550 #endif
551 #define HV_FAULT_I_TYPE_OFFSET  0x00
552 #define HV_FAULT_I_ADDR_OFFSET  0x08
553 #define HV_FAULT_I_CTX_OFFSET   0x10
554 #define HV_FAULT_D_TYPE_OFFSET  0x40
555 #define HV_FAULT_D_ADDR_OFFSET  0x48
556 #define HV_FAULT_D_CTX_OFFSET   0x50
557 
558 #define HV_FAULT_TYPE_FAST_MISS 1
559 #define HV_FAULT_TYPE_FAST_PROT 2
560 #define HV_FAULT_TYPE_MMU_MISS  3
561 #define HV_FAULT_TYPE_INV_RA    4
562 #define HV_FAULT_TYPE_PRIV_VIOL 5
563 #define HV_FAULT_TYPE_PROT_VIOL 6
564 #define HV_FAULT_TYPE_NFO       7
565 #define HV_FAULT_TYPE_NFO_SEFF  8
566 #define HV_FAULT_TYPE_INV_VA    9
567 #define HV_FAULT_TYPE_INV_ASI   10
568 #define HV_FAULT_TYPE_NC_ATOMIC 11
569 #define HV_FAULT_TYPE_PRIV_ACT  12
570 #define HV_FAULT_TYPE_RESV1     13
571 #define HV_FAULT_TYPE_UNALIGNED 14
572 #define HV_FAULT_TYPE_INV_PGSZ  15
573 /* Values 16 --> -2 are reserved.  */
574 #define HV_FAULT_TYPE_MULTIPLE  -1
575 
576 /* Flags argument for mmu_{map,unmap}_addr(), mmu_demap_{page,context,all}(),
577  * and mmu_{map,unmap}_perm_addr().
578  */
579 #define HV_MMU_DMMU                     0x01
580 #define HV_MMU_IMMU                     0x02
581 #define HV_MMU_ALL                      (HV_MMU_DMMU | HV_MMU_IMMU)
582 
583 /* mmu_map_addr()
584  * TRAP:        HV_MMU_MAP_ADDR_TRAP
585  * ARG0:        virtual address
586  * ARG1:        mmu context
587  * ARG2:        TTE
588  * ARG3:        flags (HV_MMU_{IMMU,DMMU})
589  * ERRORS:      EINVAL          Invalid virtual address, mmu context, or flags
590  *              EBADPGSZ        Invalid page size value
591  *              ENORADDR        Invalid real address in TTE
592  *
593  * Create a non-permanent mapping using the given TTE, virtual
594  * address, and mmu context.  The flags argument determines which
595  * (data, or instruction, or both) TLB the mapping gets loaded into.
596  *
597  * The behavior is undefined if the valid bit is clear in the TTE.
598  *
599  * Note: This API call is for privileged code to specify temporary translation
600  *       mappings without the need to create and manage a TSB.
601  */
602 
603 /* mmu_unmap_addr()
604  * TRAP:        HV_MMU_UNMAP_ADDR_TRAP
605  * ARG0:        virtual address
606  * ARG1:        mmu context
607  * ARG2:        flags (HV_MMU_{IMMU,DMMU})
608  * ERRORS:      EINVAL          Invalid virtual address, mmu context, or flags
609  *
610  * Demaps the given virtual address in the given mmu context on this
611  * CPU.  This function is intended to be used to demap pages mapped
612  * with mmu_map_addr.  This service is equivalent to invoking
613  * mmu_demap_page() with only the current CPU in the CPU list. The
614  * flags argument determines which (data, or instruction, or both) TLB
615  * the mapping gets unmapped from.
616  *
617  * Attempting to perform an unmap operation for a previously defined
618  * permanent mapping will have undefined results.
619  */
620 
621 /* mmu_tsb_ctx0()
622  * TRAP:        HV_FAST_TRAP
623  * FUNCTION:    HV_FAST_MMU_TSB_CTX0
624  * ARG0:        number of TSB descriptions
625  * ARG1:        TSB descriptions pointer
626  * RET0:        status
627  * ERRORS:      ENORADDR                Invalid TSB descriptions pointer or
628  *                                      TSB base within a descriptor
629  *              EBADALIGN               TSB descriptions pointer is not aligned
630  *                                      to an 8-byte boundary, or TSB base
631  *                                      within a descriptor is not aligned for
632  *                                      the given TSB size
633  *              EBADPGSZ                Invalid page size in a TSB descriptor
634  *              EBADTSB                 Invalid associativity or size in a TSB
635  *                                      descriptor
636  *              EINVAL                  Invalid number of TSB descriptions, or
637  *                                      invalid context index in a TSB
638  *                                      descriptor, or index page size not
639  *                                      equal to smallest page size in page
640  *                                      size bitmask field.
641  *
642  * Configures the TSBs for the current CPU for virtual addresses with
643  * context zero.  The TSB descriptions pointer is a pointer to an
644  * array of the given number of TSB descriptions.
645  *
646  * Note: The maximum number of TSBs available to a virtual CPU is given by the
647  *       mmu-max-#tsbs property of the cpu's corresponding "cpu" node in the
648  *       machine description.
649  */
650 #define HV_FAST_MMU_TSB_CTX0            0x20
651 
652 #ifndef __ASSEMBLY__
653 unsigned long sun4v_mmu_tsb_ctx0(unsigned long num_descriptions,
654                                  unsigned long tsb_desc_ra);
655 #endif
656 
657 /* mmu_tsb_ctxnon0()
658  * TRAP:        HV_FAST_TRAP
659  * FUNCTION:    HV_FAST_MMU_TSB_CTXNON0
660  * ARG0:        number of TSB descriptions
661  * ARG1:        TSB descriptions pointer
662  * RET0:        status
663  * ERRORS:      Same as for mmu_tsb_ctx0() above.
664  *
665  * Configures the TSBs for the current CPU for virtual addresses with
666  * non-zero contexts.  The TSB descriptions pointer is a pointer to an
667  * array of the given number of TSB descriptions.
668  *
669  * Note: A maximum of 16 TSBs may be specified in the TSB description list.
670  */
671 #define HV_FAST_MMU_TSB_CTXNON0         0x21
672 
673 /* mmu_demap_page()
674  * TRAP:        HV_FAST_TRAP
675  * FUNCTION:    HV_FAST_MMU_DEMAP_PAGE
676  * ARG0:        reserved, must be zero
677  * ARG1:        reserved, must be zero
678  * ARG2:        virtual address
679  * ARG3:        mmu context
680  * ARG4:        flags (HV_MMU_{IMMU,DMMU})
681  * RET0:        status
682  * ERRORS:      EINVAL                  Invalid virtual address, context, or
683  *                                      flags value
684  *              ENOTSUPPORTED           ARG0 or ARG1 is non-zero
685  *
686  * Demaps any page mapping of the given virtual address in the given
687  * mmu context for the current virtual CPU.  Any virtually tagged
688  * caches are guaranteed to be kept consistent.  The flags argument
689  * determines which TLB (instruction, or data, or both) participate in
690  * the operation.
691  *
692  * ARG0 and ARG1 are both reserved and must be set to zero.
693  */
694 #define HV_FAST_MMU_DEMAP_PAGE          0x22
695 
696 /* mmu_demap_ctx()
697  * TRAP:        HV_FAST_TRAP
698  * FUNCTION:    HV_FAST_MMU_DEMAP_CTX
699  * ARG0:        reserved, must be zero
700  * ARG1:        reserved, must be zero
701  * ARG2:        mmu context
702  * ARG3:        flags (HV_MMU_{IMMU,DMMU})
703  * RET0:        status
704  * ERRORS:      EINVAL                  Invalid context or flags value
705  *              ENOTSUPPORTED           ARG0 or ARG1 is non-zero
706  *
707  * Demaps all non-permanent virtual page mappings previously specified
708  * for the given context for the current virtual CPU.  Any virtual
709  * tagged caches are guaranteed to be kept consistent.  The flags
710  * argument determines which TLB (instruction, or data, or both)
711  * participate in the operation.
712  *
713  * ARG0 and ARG1 are both reserved and must be set to zero.
714  */
715 #define HV_FAST_MMU_DEMAP_CTX           0x23
716 
717 /* mmu_demap_all()
718  * TRAP:        HV_FAST_TRAP
719  * FUNCTION:    HV_FAST_MMU_DEMAP_ALL
720  * ARG0:        reserved, must be zero
721  * ARG1:        reserved, must be zero
722  * ARG2:        flags (HV_MMU_{IMMU,DMMU})
723  * RET0:        status
724  * ERRORS:      EINVAL                  Invalid flags value
725  *              ENOTSUPPORTED           ARG0 or ARG1 is non-zero
726  *
727  * Demaps all non-permanent virtual page mappings previously specified
728  * for the current virtual CPU.  Any virtual tagged caches are
729  * guaranteed to be kept consistent.  The flags argument determines
730  * which TLB (instruction, or data, or both) participate in the
731  * operation.
732  *
733  * ARG0 and ARG1 are both reserved and must be set to zero.
734  */
735 #define HV_FAST_MMU_DEMAP_ALL           0x24
736 
737 #ifndef __ASSEMBLY__
738 void sun4v_mmu_demap_all(void);
739 #endif
740 
741 /* mmu_map_perm_addr()
742  * TRAP:        HV_FAST_TRAP
743  * FUNCTION:    HV_FAST_MMU_MAP_PERM_ADDR
744  * ARG0:        virtual address
745  * ARG1:        reserved, must be zero
746  * ARG2:        TTE
747  * ARG3:        flags (HV_MMU_{IMMU,DMMU})
748  * RET0:        status
749  * ERRORS:      EINVAL                  Invalid virtual address or flags value
750  *              EBADPGSZ                Invalid page size value
751  *              ENORADDR                Invalid real address in TTE
752  *              ETOOMANY                Too many mappings (max of 8 reached)
753  *
754  * Create a permanent mapping using the given TTE and virtual address
755  * for context 0 on the calling virtual CPU.  A maximum of 8 such
756  * permanent mappings may be specified by privileged code.  Mappings
757  * may be removed with mmu_unmap_perm_addr().
758  *
759  * The behavior is undefined if a TTE with the valid bit clear is given.
760  *
761  * Note: This call is used to specify address space mappings for which
762  *       privileged code does not expect to receive misses.  For example,
763  *       this mechanism can be used to map kernel nucleus code and data.
764  */
765 #define HV_FAST_MMU_MAP_PERM_ADDR       0x25
766 
767 #ifndef __ASSEMBLY__
768 unsigned long sun4v_mmu_map_perm_addr(unsigned long vaddr,
769                                       unsigned long set_to_zero,
770                                       unsigned long tte,
771                                       unsigned long flags);
772 #endif
773 
774 /* mmu_fault_area_conf()
775  * TRAP:        HV_FAST_TRAP
776  * FUNCTION:    HV_FAST_MMU_FAULT_AREA_CONF
777  * ARG0:        real address
778  * RET0:        status
779  * RET1:        previous mmu fault area real address
780  * ERRORS:      ENORADDR                Invalid real address
781  *              EBADALIGN               Invalid alignment for fault area
782  *
783  * Configure the MMU fault status area for the calling CPU.  A 64-byte
784  * aligned real address specifies where MMU fault status information
785  * is placed.  The return value is the previously specified area, or 0
786  * for the first invocation.  Specifying a fault area at real address
787  * 0 is not allowed.
788  */
789 #define HV_FAST_MMU_FAULT_AREA_CONF     0x26
790 
791 /* mmu_enable()
792  * TRAP:        HV_FAST_TRAP
793  * FUNCTION:    HV_FAST_MMU_ENABLE
794  * ARG0:        enable flag
795  * ARG1:        return target address
796  * RET0:        status
797  * ERRORS:      ENORADDR                Invalid real address when disabling
798  *                                      translation.
799  *              EBADALIGN               The return target address is not
800  *                                      aligned to an instruction.
801  *              EINVAL                  The enable flag request the current
802  *                                      operating mode (e.g. disable if already
803  *                                      disabled)
804  *
805  * Enable or disable virtual address translation for the calling CPU
806  * within the virtual machine domain.  If the enable flag is zero,
807  * translation is disabled, any non-zero value will enable
808  * translation.
809  *
810  * When this function returns, the newly selected translation mode
811  * will be active.  If the mmu is being enabled, then the return
812  * target address is a virtual address else it is a real address.
813  *
814  * Upon successful completion, control will be returned to the given
815  * return target address (ie. the cpu will jump to that address).  On
816  * failure, the previous mmu mode remains and the trap simply returns
817  * as normal with the appropriate error code in RET0.
818  */
819 #define HV_FAST_MMU_ENABLE              0x27
820 
821 /* mmu_unmap_perm_addr()
822  * TRAP:        HV_FAST_TRAP
823  * FUNCTION:    HV_FAST_MMU_UNMAP_PERM_ADDR
824  * ARG0:        virtual address
825  * ARG1:        reserved, must be zero
826  * ARG2:        flags (HV_MMU_{IMMU,DMMU})
827  * RET0:        status
828  * ERRORS:      EINVAL                  Invalid virtual address or flags value
829  *              ENOMAP                  Specified mapping was not found
830  *
831  * Demaps any permanent page mapping (established via
832  * mmu_map_perm_addr()) at the given virtual address for context 0 on
833  * the current virtual CPU.  Any virtual tagged caches are guaranteed
834  * to be kept consistent.
835  */
836 #define HV_FAST_MMU_UNMAP_PERM_ADDR     0x28
837 
838 /* mmu_tsb_ctx0_info()
839  * TRAP:        HV_FAST_TRAP
840  * FUNCTION:    HV_FAST_MMU_TSB_CTX0_INFO
841  * ARG0:        max TSBs
842  * ARG1:        buffer pointer
843  * RET0:        status
844  * RET1:        number of TSBs
845  * ERRORS:      EINVAL                  Supplied buffer is too small
846  *              EBADALIGN               The buffer pointer is badly aligned
847  *              ENORADDR                Invalid real address for buffer pointer
848  *
849  * Return the TSB configuration as previous defined by mmu_tsb_ctx0()
850  * into the provided buffer.  The size of the buffer is given in ARG1
851  * in terms of the number of TSB description entries.
852  *
853  * Upon return, RET1 always contains the number of TSB descriptions
854  * previously configured.  If zero TSBs were configured, EOK is
855  * returned with RET1 containing 0.
856  */
857 #define HV_FAST_MMU_TSB_CTX0_INFO       0x29
858 
859 /* mmu_tsb_ctxnon0_info()
860  * TRAP:        HV_FAST_TRAP
861  * FUNCTION:    HV_FAST_MMU_TSB_CTXNON0_INFO
862  * ARG0:        max TSBs
863  * ARG1:        buffer pointer
864  * RET0:        status
865  * RET1:        number of TSBs
866  * ERRORS:      EINVAL                  Supplied buffer is too small
867  *              EBADALIGN               The buffer pointer is badly aligned
868  *              ENORADDR                Invalid real address for buffer pointer
869  *
870  * Return the TSB configuration as previous defined by
871  * mmu_tsb_ctxnon0() into the provided buffer.  The size of the buffer
872  * is given in ARG1 in terms of the number of TSB description entries.
873  *
874  * Upon return, RET1 always contains the number of TSB descriptions
875  * previously configured.  If zero TSBs were configured, EOK is
876  * returned with RET1 containing 0.
877  */
878 #define HV_FAST_MMU_TSB_CTXNON0_INFO    0x2a
879 
880 /* mmu_fault_area_info()
881  * TRAP:        HV_FAST_TRAP
882  * FUNCTION:    HV_FAST_MMU_FAULT_AREA_INFO
883  * RET0:        status
884  * RET1:        fault area real address
885  * ERRORS:      No errors defined.
886  *
887  * Return the currently defined MMU fault status area for the current
888  * CPU.  The real address of the fault status area is returned in
889  * RET1, or 0 is returned in RET1 if no fault status area is defined.
890  *
891  * Note: mmu_fault_area_conf() may be called with the return value (RET1)
892  *       from this service if there is a need to save and restore the fault
893  *       area for a cpu.
894  */
895 #define HV_FAST_MMU_FAULT_AREA_INFO     0x2b
896 
897 /* Cache and Memory services. */
898 
899 /* mem_scrub()
900  * TRAP:        HV_FAST_TRAP
901  * FUNCTION:    HV_FAST_MEM_SCRUB
902  * ARG0:        real address
903  * ARG1:        length
904  * RET0:        status
905  * RET1:        length scrubbed
906  * ERRORS:      ENORADDR        Invalid real address
907  *              EBADALIGN       Start address or length are not correctly
908  *                              aligned
909  *              EINVAL          Length is zero
910  *
911  * Zero the memory contents in the range real address to real address
912  * plus length minus 1.  Also, valid ECC will be generated for that
913  * memory address range.  Scrubbing is started at the given real
914  * address, but may not scrub the entire given length.  The actual
915  * length scrubbed will be returned in RET1.
916  *
917  * The real address and length must be aligned on an 8K boundary, or
918  * contain the start address and length from a sun4v error report.
919  *
920  * Note: There are two uses for this function.  The first use is to block clear
921  *       and initialize memory and the second is to scrub an u ncorrectable
922  *       error reported via a resumable or non-resumable trap.  The second
923  *       use requires the arguments to be equal to the real address and length
924  *       provided in a sun4v memory error report.
925  */
926 #define HV_FAST_MEM_SCRUB               0x31
927 
928 /* mem_sync()
929  * TRAP:        HV_FAST_TRAP
930  * FUNCTION:    HV_FAST_MEM_SYNC
931  * ARG0:        real address
932  * ARG1:        length
933  * RET0:        status
934  * RET1:        length synced
935  * ERRORS:      ENORADDR        Invalid real address
936  *              EBADALIGN       Start address or length are not correctly
937  *                              aligned
938  *              EINVAL          Length is zero
939  *
940  * Force the next access within the real address to real address plus
941  * length minus 1 to be fetches from main system memory.  Less than
942  * the given length may be synced, the actual amount synced is
943  * returned in RET1.  The real address and length must be aligned on
944  * an 8K boundary.
945  */
946 #define HV_FAST_MEM_SYNC                0x32
947 
948 /* Coprocessor services
949  *
950  * M7 and later processors provide an on-chip coprocessor which
951  * accelerates database operations, and is known internally as
952  * DAX.
953  */
954 
955 /* ccb_submit()
956  * TRAP:        HV_FAST_TRAP
957  * FUNCTION:    HV_CCB_SUBMIT
958  * ARG0:        address of CCB array
959  * ARG1:        size (in bytes) of CCB array being submitted
960  * ARG2:        flags
961  * ARG3:        reserved
962  * RET0:        status (success or error code)
963  * RET1:        size (in bytes) of CCB array that was accepted (might be less
964  *              than arg1)
965  * RET2:        status data
966  *              if status == ENOMAP or ENOACCESS, identifies the VA in question
967  *              if status == EUNAVAILBLE, unavailable code
968  * RET3:        reserved
969  *
970  * ERRORS:      EOK             successful submission (check size)
971  *              EWOULDBLOCK     could not finish submissions, try again
972  *              EBADALIGN       array not 64B aligned or size not 64B multiple
973  *              ENORADDR        invalid RA for array or in CCB
974  *              ENOMAP          could not translate address (see status data)
975  *              EINVAL          invalid ccb or arguments
976  *              ETOOMANY        too many ccbs with all-or-nothing flag
977  *              ENOACCESS       guest has no access to submit ccbs or address
978  *                              in CCB does not have correct permissions (check
979  *                              status data)
980  *              EUNAVAILABLE    ccb operation could not be performed at this
981  *                              time (check status data)
982  *                              Status data codes:
983  *                                      0 - exact CCB could not be executed
984  *                                      1 - CCB opcode cannot be executed
985  *                                      2 - CCB version cannot be executed
986  *                                      3 - vcpu cannot execute CCBs
987  *                                      4 - no CCBs can be executed
988  */
989 
990 #define HV_CCB_SUBMIT               0x34
991 #ifndef __ASSEMBLY__
992 unsigned long sun4v_ccb_submit(unsigned long ccb_buf,
993                                unsigned long len,
994                                unsigned long flags,
995                                unsigned long reserved,
996                                void *submitted_len,
997                                void *status_data);
998 #endif
999 
1000 /* flags (ARG2) */
1001 #define HV_CCB_QUERY_CMD                BIT(1)
1002 #define HV_CCB_ARG0_TYPE_REAL           0UL
1003 #define HV_CCB_ARG0_TYPE_PRIMARY        BIT(4)
1004 #define HV_CCB_ARG0_TYPE_SECONDARY      BIT(5)
1005 #define HV_CCB_ARG0_TYPE_NUCLEUS        GENMASK(5, 4)
1006 #define HV_CCB_ARG0_PRIVILEGED          BIT(6)
1007 #define HV_CCB_ALL_OR_NOTHING           BIT(7)
1008 #define HV_CCB_QUEUE_INFO               BIT(8)
1009 #define HV_CCB_VA_REJECT                0UL
1010 #define HV_CCB_VA_SECONDARY             BIT(13)
1011 #define HV_CCB_VA_NUCLEUS               GENMASK(13, 12)
1012 #define HV_CCB_VA_PRIVILEGED            BIT(14)
1013 #define HV_CCB_VA_READ_ADI_DISABLE      BIT(15) /* DAX2 only */
1014 
1015 /* ccb_info()
1016  * TRAP:        HV_FAST_TRAP
1017  * FUNCTION:    HV_CCB_INFO
1018  * ARG0:        real address of CCB completion area
1019  * RET0:        status (success or error code)
1020  * RET1:        info array
1021  *                      - RET1[0]: CCB state
1022  *                      - RET1[1]: dax unit
1023  *                      - RET1[2]: queue number
1024  *                      - RET1[3]: queue position
1025  *
1026  * ERRORS:      EOK             operation successful
1027  *              EBADALIGN       address not 64B aligned
1028  *              ENORADDR        RA in address not valid
1029  *              EINVAL          CA not valid
1030  *              EWOULDBLOCK     info not available for this CCB currently, try
1031  *                              again
1032  *              ENOACCESS       guest cannot use dax
1033  */
1034 
1035 #define HV_CCB_INFO                 0x35
1036 #ifndef __ASSEMBLY__
1037 unsigned long sun4v_ccb_info(unsigned long ca,
1038                              void *info_arr);
1039 #endif
1040 
1041 /* info array byte offsets (RET1) */
1042 #define CCB_INFO_OFFSET_CCB_STATE       0
1043 #define CCB_INFO_OFFSET_DAX_UNIT        2
1044 #define CCB_INFO_OFFSET_QUEUE_NUM       4
1045 #define CCB_INFO_OFFSET_QUEUE_POS       6
1046 
1047 /* CCB state (RET1[0]) */
1048 #define HV_CCB_STATE_COMPLETED      0
1049 #define HV_CCB_STATE_ENQUEUED       1
1050 #define HV_CCB_STATE_INPROGRESS     2
1051 #define HV_CCB_STATE_NOTFOUND       3
1052 
1053 /* ccb_kill()
1054  * TRAP:        HV_FAST_TRAP
1055  * FUNCTION:    HV_CCB_KILL
1056  * ARG0:        real address of CCB completion area
1057  * RET0:        status (success or error code)
1058  * RET1:        CCB kill status
1059  *
1060  * ERRORS:      EOK             operation successful
1061  *              EBADALIGN       address not 64B aligned
1062  *              ENORADDR        RA in address not valid
1063  *              EINVAL          CA not valid
1064  *              EWOULDBLOCK     kill not available for this CCB currently, try
1065  *                              again
1066  *              ENOACCESS       guest cannot use dax
1067  */
1068 
1069 #define HV_CCB_KILL                 0x36
1070 #ifndef __ASSEMBLY__
1071 unsigned long sun4v_ccb_kill(unsigned long ca,
1072                              void *kill_status);
1073 #endif
1074 
1075 /* CCB kill status (RET1) */
1076 #define HV_CCB_KILL_COMPLETED       0
1077 #define HV_CCB_KILL_DEQUEUED        1
1078 #define HV_CCB_KILL_KILLED          2
1079 #define HV_CCB_KILL_NOTFOUND        3
1080 
1081 /* Time of day services.
1082  *
1083  * The hypervisor maintains the time of day on a per-domain basis.
1084  * Changing the time of day in one domain does not affect the time of
1085  * day on any other domain.
1086  *
1087  * Time is described by a single unsigned 64-bit word which is the
1088  * number of seconds since the UNIX Epoch (00:00:00 UTC, January 1,
1089  * 1970).
1090  */
1091 
1092 /* tod_get()
1093  * TRAP:        HV_FAST_TRAP
1094  * FUNCTION:    HV_FAST_TOD_GET
1095  * RET0:        status
1096  * RET1:        TOD
1097  * ERRORS:      EWOULDBLOCK     TOD resource is temporarily unavailable
1098  *              ENOTSUPPORTED   If TOD not supported on this platform
1099  *
1100  * Return the current time of day.  May block if TOD access is
1101  * temporarily not possible.
1102  */
1103 #define HV_FAST_TOD_GET                 0x50
1104 
1105 #ifndef __ASSEMBLY__
1106 unsigned long sun4v_tod_get(unsigned long *time);
1107 #endif
1108 
1109 /* tod_set()
1110  * TRAP:        HV_FAST_TRAP
1111  * FUNCTION:    HV_FAST_TOD_SET
1112  * ARG0:        TOD
1113  * RET0:        status
1114  * ERRORS:      EWOULDBLOCK     TOD resource is temporarily unavailable
1115  *              ENOTSUPPORTED   If TOD not supported on this platform
1116  *
1117  * The current time of day is set to the value specified in ARG0.  May
1118  * block if TOD access is temporarily not possible.
1119  */
1120 #define HV_FAST_TOD_SET                 0x51
1121 
1122 #ifndef __ASSEMBLY__
1123 unsigned long sun4v_tod_set(unsigned long time);
1124 #endif
1125 
1126 /* Console services */
1127 
1128 /* con_getchar()
1129  * TRAP:        HV_FAST_TRAP
1130  * FUNCTION:    HV_FAST_CONS_GETCHAR
1131  * RET0:        status
1132  * RET1:        character
1133  * ERRORS:      EWOULDBLOCK     No character available.
1134  *
1135  * Returns a character from the console device.  If no character is
1136  * available then an EWOULDBLOCK error is returned.  If a character is
1137  * available, then the returned status is EOK and the character value
1138  * is in RET1.
1139  *
1140  * A virtual BREAK is represented by the 64-bit value -1.
1141  *
1142  * A virtual HUP signal is represented by the 64-bit value -2.
1143  */
1144 #define HV_FAST_CONS_GETCHAR            0x60
1145 
1146 /* con_putchar()
1147  * TRAP:        HV_FAST_TRAP
1148  * FUNCTION:    HV_FAST_CONS_PUTCHAR
1149  * ARG0:        character
1150  * RET0:        status
1151  * ERRORS:      EINVAL          Illegal character
1152  *              EWOULDBLOCK     Output buffer currently full, would block
1153  *
1154  * Send a character to the console device.  Only character values
1155  * between 0 and 255 may be used.  Values outside this range are
1156  * invalid except for the 64-bit value -1 which is used to send a
1157  * virtual BREAK.
1158  */
1159 #define HV_FAST_CONS_PUTCHAR            0x61
1160 
1161 /* con_read()
1162  * TRAP:        HV_FAST_TRAP
1163  * FUNCTION:    HV_FAST_CONS_READ
1164  * ARG0:        buffer real address
1165  * ARG1:        buffer size in bytes
1166  * RET0:        status
1167  * RET1:        bytes read or BREAK or HUP
1168  * ERRORS:      EWOULDBLOCK     No character available.
1169  *
1170  * Reads characters into a buffer from the console device.  If no
1171  * character is available then an EWOULDBLOCK error is returned.
1172  * If a character is available, then the returned status is EOK
1173  * and the number of bytes read into the given buffer is provided
1174  * in RET1.
1175  *
1176  * A virtual BREAK is represented by the 64-bit RET1 value -1.
1177  *
1178  * A virtual HUP signal is represented by the 64-bit RET1 value -2.
1179  *
1180  * If BREAK or HUP are indicated, no bytes were read into buffer.
1181  */
1182 #define HV_FAST_CONS_READ               0x62
1183 
1184 /* con_write()
1185  * TRAP:        HV_FAST_TRAP
1186  * FUNCTION:    HV_FAST_CONS_WRITE
1187  * ARG0:        buffer real address
1188  * ARG1:        buffer size in bytes
1189  * RET0:        status
1190  * RET1:        bytes written
1191  * ERRORS:      EWOULDBLOCK     Output buffer currently full, would block
1192  *
1193  * Send a characters in buffer to the console device.  Breaks must be
1194  * sent using con_putchar().
1195  */
1196 #define HV_FAST_CONS_WRITE              0x63
1197 
1198 #ifndef __ASSEMBLY__
1199 long sun4v_con_getchar(long *status);
1200 long sun4v_con_putchar(long c);
1201 long sun4v_con_read(unsigned long buffer,
1202                     unsigned long size,
1203                     unsigned long *bytes_read);
1204 unsigned long sun4v_con_write(unsigned long buffer,
1205                               unsigned long size,
1206                               unsigned long *bytes_written);
1207 #endif
1208 
1209 /* mach_set_soft_state()
1210  * TRAP:        HV_FAST_TRAP
1211  * FUNCTION:    HV_FAST_MACH_SET_SOFT_STATE
1212  * ARG0:        software state
1213  * ARG1:        software state description pointer
1214  * RET0:        status
1215  * ERRORS:      EINVAL          software state not valid or software state
1216  *                              description is not NULL terminated
1217  *              ENORADDR        software state description pointer is not a
1218  *                              valid real address
1219  *              EBADALIGNED     software state description is not correctly
1220  *                              aligned
1221  *
1222  * This allows the guest to report it's soft state to the hypervisor.  There
1223  * are two primary components to this state.  The first part states whether
1224  * the guest software is running or not.  The second containts optional
1225  * details specific to the software.
1226  *
1227  * The software state argument is defined below in HV_SOFT_STATE_*, and
1228  * indicates whether the guest is operating normally or in a transitional
1229  * state.
1230  *
1231  * The software state description argument is a real address of a data buffer
1232  * of size 32-bytes aligned on a 32-byte boundary.  It is treated as a NULL
1233  * terminated 7-bit ASCII string of up to 31 characters not including the
1234  * NULL termination.
1235  */
1236 #define HV_FAST_MACH_SET_SOFT_STATE     0x70
1237 #define  HV_SOFT_STATE_NORMAL            0x01
1238 #define  HV_SOFT_STATE_TRANSITION        0x02
1239 
1240 #ifndef __ASSEMBLY__
1241 unsigned long sun4v_mach_set_soft_state(unsigned long soft_state,
1242                                         unsigned long msg_string_ra);
1243 #endif
1244 
1245 /* mach_get_soft_state()
1246  * TRAP:        HV_FAST_TRAP
1247  * FUNCTION:    HV_FAST_MACH_GET_SOFT_STATE
1248  * ARG0:        software state description pointer
1249  * RET0:        status
1250  * RET1:        software state
1251  * ERRORS:      ENORADDR        software state description pointer is not a
1252  *                              valid real address
1253  *              EBADALIGNED     software state description is not correctly
1254  *                              aligned
1255  *
1256  * Retrieve the current value of the guest's software state.  The rules
1257  * for the software state pointer are the same as for mach_set_soft_state()
1258  * above.
1259  */
1260 #define HV_FAST_MACH_GET_SOFT_STATE     0x71
1261 
1262 /* svc_send()
1263  * TRAP:        HV_FAST_TRAP
1264  * FUNCTION:    HV_FAST_SVC_SEND
1265  * ARG0:        service ID
1266  * ARG1:        buffer real address
1267  * ARG2:        buffer size
1268  * RET0:        STATUS
1269  * RET1:        sent_bytes
1270  *
1271  * Be careful, all output registers are clobbered by this operation,
1272  * so for example it is not possible to save away a value in %o4
1273  * across the trap.
1274  */
1275 #define HV_FAST_SVC_SEND                0x80
1276 
1277 /* svc_recv()
1278  * TRAP:        HV_FAST_TRAP
1279  * FUNCTION:    HV_FAST_SVC_RECV
1280  * ARG0:        service ID
1281  * ARG1:        buffer real address
1282  * ARG2:        buffer size
1283  * RET0:        STATUS
1284  * RET1:        recv_bytes
1285  *
1286  * Be careful, all output registers are clobbered by this operation,
1287  * so for example it is not possible to save away a value in %o4
1288  * across the trap.
1289  */
1290 #define HV_FAST_SVC_RECV                0x81
1291 
1292 /* svc_getstatus()
1293  * TRAP:        HV_FAST_TRAP
1294  * FUNCTION:    HV_FAST_SVC_GETSTATUS
1295  * ARG0:        service ID
1296  * RET0:        STATUS
1297  * RET1:        status bits
1298  */
1299 #define HV_FAST_SVC_GETSTATUS           0x82
1300 
1301 /* svc_setstatus()
1302  * TRAP:        HV_FAST_TRAP
1303  * FUNCTION:    HV_FAST_SVC_SETSTATUS
1304  * ARG0:        service ID
1305  * ARG1:        bits to set
1306  * RET0:        STATUS
1307  */
1308 #define HV_FAST_SVC_SETSTATUS           0x83
1309 
1310 /* svc_clrstatus()
1311  * TRAP:        HV_FAST_TRAP
1312  * FUNCTION:    HV_FAST_SVC_CLRSTATUS
1313  * ARG0:        service ID
1314  * ARG1:        bits to clear
1315  * RET0:        STATUS
1316  */
1317 #define HV_FAST_SVC_CLRSTATUS           0x84
1318 
1319 #ifndef __ASSEMBLY__
1320 unsigned long sun4v_svc_send(unsigned long svc_id,
1321                              unsigned long buffer,
1322                              unsigned long buffer_size,
1323                              unsigned long *sent_bytes);
1324 unsigned long sun4v_svc_recv(unsigned long svc_id,
1325                              unsigned long buffer,
1326                              unsigned long buffer_size,
1327                              unsigned long *recv_bytes);
1328 unsigned long sun4v_svc_getstatus(unsigned long svc_id,
1329                                   unsigned long *status_bits);
1330 unsigned long sun4v_svc_setstatus(unsigned long svc_id,
1331                                   unsigned long status_bits);
1332 unsigned long sun4v_svc_clrstatus(unsigned long svc_id,
1333                                   unsigned long status_bits);
1334 #endif
1335 
1336 /* Trap trace services.
1337  *
1338  * The hypervisor provides a trap tracing capability for privileged
1339  * code running on each virtual CPU.  Privileged code provides a
1340  * round-robin trap trace queue within which the hypervisor writes
1341  * 64-byte entries detailing hyperprivileged traps taken n behalf of
1342  * privileged code.  This is provided as a debugging capability for
1343  * privileged code.
1344  *
1345  * The trap trace control structure is 64-bytes long and placed at the
1346  * start (offset 0) of the trap trace buffer, and is described as
1347  * follows:
1348  */
1349 #ifndef __ASSEMBLY__
1350 struct hv_trap_trace_control {
1351         unsigned long           head_offset;
1352         unsigned long           tail_offset;
1353         unsigned long           __reserved[0x30 / sizeof(unsigned long)];
1354 };
1355 #endif
1356 #define HV_TRAP_TRACE_CTRL_HEAD_OFFSET  0x00
1357 #define HV_TRAP_TRACE_CTRL_TAIL_OFFSET  0x08
1358 
1359 /* The head offset is the offset of the most recently completed entry
1360  * in the trap-trace buffer.  The tail offset is the offset of the
1361  * next entry to be written.  The control structure is owned and
1362  * modified by the hypervisor.  A guest may not modify the control
1363  * structure contents.  Attempts to do so will result in undefined
1364  * behavior for the guest.
1365  *
1366  * Each trap trace buffer entry is laid out as follows:
1367  */
1368 #ifndef __ASSEMBLY__
1369 struct hv_trap_trace_entry {
1370         unsigned char   type;           /* Hypervisor or guest entry?   */
1371         unsigned char   hpstate;        /* Hyper-privileged state       */
1372         unsigned char   tl;             /* Trap level                   */
1373         unsigned char   gl;             /* Global register level        */
1374         unsigned short  tt;             /* Trap type                    */
1375         unsigned short  tag;            /* Extended trap identifier     */
1376         unsigned long   tstate;         /* Trap state                   */
1377         unsigned long   tick;           /* Tick                         */
1378         unsigned long   tpc;            /* Trap PC                      */
1379         unsigned long   f1;             /* Entry specific               */
1380         unsigned long   f2;             /* Entry specific               */
1381         unsigned long   f3;             /* Entry specific               */
1382         unsigned long   f4;             /* Entry specific               */
1383 };
1384 #endif
1385 #define HV_TRAP_TRACE_ENTRY_TYPE        0x00
1386 #define HV_TRAP_TRACE_ENTRY_HPSTATE     0x01
1387 #define HV_TRAP_TRACE_ENTRY_TL          0x02
1388 #define HV_TRAP_TRACE_ENTRY_GL          0x03
1389 #define HV_TRAP_TRACE_ENTRY_TT          0x04
1390 #define HV_TRAP_TRACE_ENTRY_TAG         0x06
1391 #define HV_TRAP_TRACE_ENTRY_TSTATE      0x08
1392 #define HV_TRAP_TRACE_ENTRY_TICK        0x10
1393 #define HV_TRAP_TRACE_ENTRY_TPC         0x18
1394 #define HV_TRAP_TRACE_ENTRY_F1          0x20
1395 #define HV_TRAP_TRACE_ENTRY_F2          0x28
1396 #define HV_TRAP_TRACE_ENTRY_F3          0x30
1397 #define HV_TRAP_TRACE_ENTRY_F4          0x38
1398 
1399 /* The type field is encoded as follows.  */
1400 #define HV_TRAP_TYPE_UNDEF              0x00 /* Entry content undefined     */
1401 #define HV_TRAP_TYPE_HV                 0x01 /* Hypervisor trap entry       */
1402 #define HV_TRAP_TYPE_GUEST              0xff /* Added via ttrace_addentry() */
1403 
1404 /* ttrace_buf_conf()
1405  * TRAP:        HV_FAST_TRAP
1406  * FUNCTION:    HV_FAST_TTRACE_BUF_CONF
1407  * ARG0:        real address
1408  * ARG1:        number of entries
1409  * RET0:        status
1410  * RET1:        number of entries
1411  * ERRORS:      ENORADDR        Invalid real address
1412  *              EINVAL          Size is too small
1413  *              EBADALIGN       Real address not aligned on 64-byte boundary
1414  *
1415  * Requests hypervisor trap tracing and declares a virtual CPU's trap
1416  * trace buffer to the hypervisor.  The real address supplies the real
1417  * base address of the trap trace queue and must be 64-byte aligned.
1418  * Specifying a value of 0 for the number of entries disables trap
1419  * tracing for the calling virtual CPU.  The buffer allocated must be
1420  * sized for a power of two number of 64-byte trap trace entries plus
1421  * an initial 64-byte control structure.
1422  *
1423  * This may be invoked any number of times so that a virtual CPU may
1424  * relocate a trap trace buffer or create "snapshots" of information.
1425  *
1426  * If the real address is illegal or badly aligned, then trap tracing
1427  * is disabled and an error is returned.
1428  *
1429  * Upon failure with EINVAL, this service call returns in RET1 the
1430  * minimum number of buffer entries required.  Upon other failures
1431  * RET1 is undefined.
1432  */
1433 #define HV_FAST_TTRACE_BUF_CONF         0x90
1434 
1435 /* ttrace_buf_info()
1436  * TRAP:        HV_FAST_TRAP
1437  * FUNCTION:    HV_FAST_TTRACE_BUF_INFO
1438  * RET0:        status
1439  * RET1:        real address
1440  * RET2:        size
1441  * ERRORS:      None defined.
1442  *
1443  * Returns the size and location of the previously declared trap-trace
1444  * buffer.  In the event that no buffer was previously defined, or the
1445  * buffer is disabled, this call will return a size of zero bytes.
1446  */
1447 #define HV_FAST_TTRACE_BUF_INFO         0x91
1448 
1449 /* ttrace_enable()
1450  * TRAP:        HV_FAST_TRAP
1451  * FUNCTION:    HV_FAST_TTRACE_ENABLE
1452  * ARG0:        enable
1453  * RET0:        status
1454  * RET1:        previous enable state
1455  * ERRORS:      EINVAL          No trap trace buffer currently defined
1456  *
1457  * Enable or disable trap tracing, and return the previous enabled
1458  * state in RET1.  Future systems may define various flags for the
1459  * enable argument (ARG0), for the moment a guest should pass
1460  * "(uint64_t) -1" to enable, and "(uint64_t) 0" to disable all
1461  * tracing - which will ensure future compatibility.
1462  */
1463 #define HV_FAST_TTRACE_ENABLE           0x92
1464 
1465 /* ttrace_freeze()
1466  * TRAP:        HV_FAST_TRAP
1467  * FUNCTION:    HV_FAST_TTRACE_FREEZE
1468  * ARG0:        freeze
1469  * RET0:        status
1470  * RET1:        previous freeze state
1471  * ERRORS:      EINVAL          No trap trace buffer currently defined
1472  *
1473  * Freeze or unfreeze trap tracing, returning the previous freeze
1474  * state in RET1.  A guest should pass a non-zero value to freeze and
1475  * a zero value to unfreeze all tracing.  The returned previous state
1476  * is 0 for not frozen and 1 for frozen.
1477  */
1478 #define HV_FAST_TTRACE_FREEZE           0x93
1479 
1480 /* ttrace_addentry()
1481  * TRAP:        HV_TTRACE_ADDENTRY_TRAP
1482  * ARG0:        tag (16-bits)
1483  * ARG1:        data word 0
1484  * ARG2:        data word 1
1485  * ARG3:        data word 2
1486  * ARG4:        data word 3
1487  * RET0:        status
1488  * ERRORS:      EINVAL          No trap trace buffer currently defined
1489  *
1490  * Add an entry to the trap trace buffer.  Upon return only ARG0/RET0
1491  * is modified - none of the other registers holding arguments are
1492  * volatile across this hypervisor service.
1493  */
1494 
1495 /* Core dump services.
1496  *
1497  * Since the hypervisor viraulizes and thus obscures a lot of the
1498  * physical machine layout and state, traditional OS crash dumps can
1499  * be difficult to diagnose especially when the problem is a
1500  * configuration error of some sort.
1501  *
1502  * The dump services provide an opaque buffer into which the
1503  * hypervisor can place it's internal state in order to assist in
1504  * debugging such situations.  The contents are opaque and extremely
1505  * platform and hypervisor implementation specific.  The guest, during
1506  * a core dump, requests that the hypervisor update any information in
1507  * the dump buffer in preparation to being dumped as part of the
1508  * domain's memory image.
1509  */
1510 
1511 /* dump_buf_update()
1512  * TRAP:        HV_FAST_TRAP
1513  * FUNCTION:    HV_FAST_DUMP_BUF_UPDATE
1514  * ARG0:        real address
1515  * ARG1:        size
1516  * RET0:        status
1517  * RET1:        required size of dump buffer
1518  * ERRORS:      ENORADDR        Invalid real address
1519  *              EBADALIGN       Real address is not aligned on a 64-byte
1520  *                              boundary
1521  *              EINVAL          Size is non-zero but less than minimum size
1522  *                              required
1523  *              ENOTSUPPORTED   Operation not supported on current logical
1524  *                              domain
1525  *
1526  * Declare a domain dump buffer to the hypervisor.  The real address
1527  * provided for the domain dump buffer must be 64-byte aligned.  The
1528  * size specifies the size of the dump buffer and may be larger than
1529  * the minimum size specified in the machine description.  The
1530  * hypervisor will fill the dump buffer with opaque data.
1531  *
1532  * Note: A guest may elect to include dump buffer contents as part of a crash
1533  *       dump to assist with debugging.  This function may be called any number
1534  *       of times so that a guest may relocate a dump buffer, or create
1535  *       "snapshots" of any dump-buffer information.  Each call to
1536  *       dump_buf_update() atomically declares the new dump buffer to the
1537  *       hypervisor.
1538  *
1539  * A specified size of 0 unconfigures the dump buffer.  If the real
1540  * address is illegal or badly aligned, then any currently active dump
1541  * buffer is disabled and an error is returned.
1542  *
1543  * In the event that the call fails with EINVAL, RET1 contains the
1544  * minimum size requires by the hypervisor for a valid dump buffer.
1545  */
1546 #define HV_FAST_DUMP_BUF_UPDATE         0x94
1547 
1548 /* dump_buf_info()
1549  * TRAP:        HV_FAST_TRAP
1550  * FUNCTION:    HV_FAST_DUMP_BUF_INFO
1551  * RET0:        status
1552  * RET1:        real address of current dump buffer
1553  * RET2:        size of current dump buffer
1554  * ERRORS:      No errors defined.
1555  *
1556  * Return the currently configures dump buffer description.  A
1557  * returned size of 0 bytes indicates an undefined dump buffer.  In
1558  * this case the return address in RET1 is undefined.
1559  */
1560 #define HV_FAST_DUMP_BUF_INFO           0x95
1561 
1562 /* Device interrupt services.
1563  *
1564  * Device interrupts are allocated to system bus bridges by the hypervisor,
1565  * and described to OBP in the machine description.  OBP then describes
1566  * these interrupts to the OS via properties in the device tree.
1567  *
1568  * Terminology:
1569  *
1570  *      cpuid           Unique opaque value which represents a target cpu.
1571  *
1572  *      devhandle       Device handle.  It uniquely identifies a device, and
1573  *                      consistes of the lower 28-bits of the hi-cell of the
1574  *                      first entry of the device's "reg" property in the
1575  *                      OBP device tree.
1576  *
1577  *      devino          Device interrupt number.  Specifies the relative
1578  *                      interrupt number within the device.  The unique
1579  *                      combination of devhandle and devino are used to
1580  *                      identify a specific device interrupt.
1581  *
1582  *                      Note: The devino value is the same as the values in the
1583  *                            "interrupts" property or "interrupt-map" property
1584  *                            in the OBP device tree for that device.
1585  *
1586  *      sysino          System interrupt number.  A 64-bit unsigned interger
1587  *                      representing a unique interrupt within a virtual
1588  *                      machine.
1589  *
1590  *      intr_state      A flag representing the interrupt state for a given
1591  *                      sysino.  The state values are defined below.
1592  *
1593  *      intr_enabled    A flag representing the 'enabled' state for a given
1594  *                      sysino.  The enable values are defined below.
1595  */
1596 
1597 #define HV_INTR_STATE_IDLE              0 /* Nothing pending */
1598 #define HV_INTR_STATE_RECEIVED          1 /* Interrupt received by hardware */
1599 #define HV_INTR_STATE_DELIVERED         2 /* Interrupt delivered to queue */
1600 
1601 #define HV_INTR_DISABLED                0 /* sysino not enabled */
1602 #define HV_INTR_ENABLED                 1 /* sysino enabled */
1603 
1604 /* intr_devino_to_sysino()
1605  * TRAP:        HV_FAST_TRAP
1606  * FUNCTION:    HV_FAST_INTR_DEVINO2SYSINO
1607  * ARG0:        devhandle
1608  * ARG1:        devino
1609  * RET0:        status
1610  * RET1:        sysino
1611  * ERRORS:      EINVAL          Invalid devhandle/devino
1612  *
1613  * Converts a device specific interrupt number of the given
1614  * devhandle/devino into a system specific ino (sysino).
1615  */
1616 #define HV_FAST_INTR_DEVINO2SYSINO      0xa0
1617 
1618 #ifndef __ASSEMBLY__
1619 unsigned long sun4v_devino_to_sysino(unsigned long devhandle,
1620                                      unsigned long devino);
1621 #endif
1622 
1623 /* intr_getenabled()
1624  * TRAP:        HV_FAST_TRAP
1625  * FUNCTION:    HV_FAST_INTR_GETENABLED
1626  * ARG0:        sysino
1627  * RET0:        status
1628  * RET1:        intr_enabled (HV_INTR_{DISABLED,ENABLED})
1629  * ERRORS:      EINVAL          Invalid sysino
1630  *
1631  * Returns interrupt enabled state in RET1 for the interrupt defined
1632  * by the given sysino.
1633  */
1634 #define HV_FAST_INTR_GETENABLED         0xa1
1635 
1636 #ifndef __ASSEMBLY__
1637 unsigned long sun4v_intr_getenabled(unsigned long sysino);
1638 #endif
1639 
1640 /* intr_setenabled()
1641  * TRAP:        HV_FAST_TRAP
1642  * FUNCTION:    HV_FAST_INTR_SETENABLED
1643  * ARG0:        sysino
1644  * ARG1:        intr_enabled (HV_INTR_{DISABLED,ENABLED})
1645  * RET0:        status
1646  * ERRORS:      EINVAL          Invalid sysino or intr_enabled value
1647  *
1648  * Set the 'enabled' state of the interrupt sysino.
1649  */
1650 #define HV_FAST_INTR_SETENABLED         0xa2
1651 
1652 #ifndef __ASSEMBLY__
1653 unsigned long sun4v_intr_setenabled(unsigned long sysino,
1654                                     unsigned long intr_enabled);
1655 #endif
1656 
1657 /* intr_getstate()
1658  * TRAP:        HV_FAST_TRAP
1659  * FUNCTION:    HV_FAST_INTR_GETSTATE
1660  * ARG0:        sysino
1661  * RET0:        status
1662  * RET1:        intr_state (HV_INTR_STATE_*)
1663  * ERRORS:      EINVAL          Invalid sysino
1664  *
1665  * Returns current state of the interrupt defined by the given sysino.
1666  */
1667 #define HV_FAST_INTR_GETSTATE           0xa3
1668 
1669 #ifndef __ASSEMBLY__
1670 unsigned long sun4v_intr_getstate(unsigned long sysino);
1671 #endif
1672 
1673 /* intr_setstate()
1674  * TRAP:        HV_FAST_TRAP
1675  * FUNCTION:    HV_FAST_INTR_SETSTATE
1676  * ARG0:        sysino
1677  * ARG1:        intr_state (HV_INTR_STATE_*)
1678  * RET0:        status
1679  * ERRORS:      EINVAL          Invalid sysino or intr_state value
1680  *
1681  * Sets the current state of the interrupt described by the given sysino
1682  * value.
1683  *
1684  * Note: Setting the state to HV_INTR_STATE_IDLE clears any pending
1685  *       interrupt for sysino.
1686  */
1687 #define HV_FAST_INTR_SETSTATE           0xa4
1688 
1689 #ifndef __ASSEMBLY__
1690 unsigned long sun4v_intr_setstate(unsigned long sysino, unsigned long intr_state);
1691 #endif
1692 
1693 /* intr_gettarget()
1694  * TRAP:        HV_FAST_TRAP
1695  * FUNCTION:    HV_FAST_INTR_GETTARGET
1696  * ARG0:        sysino
1697  * RET0:        status
1698  * RET1:        cpuid
1699  * ERRORS:      EINVAL          Invalid sysino
1700  *
1701  * Returns CPU that is the current target of the interrupt defined by
1702  * the given sysino.  The CPU value returned is undefined if the target
1703  * has not been set via intr_settarget().
1704  */
1705 #define HV_FAST_INTR_GETTARGET          0xa5
1706 
1707 #ifndef __ASSEMBLY__
1708 unsigned long sun4v_intr_gettarget(unsigned long sysino);
1709 #endif
1710 
1711 /* intr_settarget()
1712  * TRAP:        HV_FAST_TRAP
1713  * FUNCTION:    HV_FAST_INTR_SETTARGET
1714  * ARG0:        sysino
1715  * ARG1:        cpuid
1716  * RET0:        status
1717  * ERRORS:      EINVAL          Invalid sysino
1718  *              ENOCPU          Invalid cpuid
1719  *
1720  * Set the target CPU for the interrupt defined by the given sysino.
1721  */
1722 #define HV_FAST_INTR_SETTARGET          0xa6
1723 
1724 #ifndef __ASSEMBLY__
1725 unsigned long sun4v_intr_settarget(unsigned long sysino, unsigned long cpuid);
1726 #endif
1727 
1728 /* vintr_get_cookie()
1729  * TRAP:        HV_FAST_TRAP
1730  * FUNCTION:    HV_FAST_VINTR_GET_COOKIE
1731  * ARG0:        device handle
1732  * ARG1:        device ino
1733  * RET0:        status
1734  * RET1:        cookie
1735  */
1736 #define HV_FAST_VINTR_GET_COOKIE        0xa7
1737 
1738 /* vintr_set_cookie()
1739  * TRAP:        HV_FAST_TRAP
1740  * FUNCTION:    HV_FAST_VINTR_SET_COOKIE
1741  * ARG0:        device handle
1742  * ARG1:        device ino
1743  * ARG2:        cookie
1744  * RET0:        status
1745  */
1746 #define HV_FAST_VINTR_SET_COOKIE        0xa8
1747 
1748 /* vintr_get_valid()
1749  * TRAP:        HV_FAST_TRAP
1750  * FUNCTION:    HV_FAST_VINTR_GET_VALID
1751  * ARG0:        device handle
1752  * ARG1:        device ino
1753  * RET0:        status
1754  * RET1:        valid state
1755  */
1756 #define HV_FAST_VINTR_GET_VALID         0xa9
1757 
1758 /* vintr_set_valid()
1759  * TRAP:        HV_FAST_TRAP
1760  * FUNCTION:    HV_FAST_VINTR_SET_VALID
1761  * ARG0:        device handle
1762  * ARG1:        device ino
1763  * ARG2:        valid state
1764  * RET0:        status
1765  */
1766 #define HV_FAST_VINTR_SET_VALID         0xaa
1767 
1768 /* vintr_get_state()
1769  * TRAP:        HV_FAST_TRAP
1770  * FUNCTION:    HV_FAST_VINTR_GET_STATE
1771  * ARG0:        device handle
1772  * ARG1:        device ino
1773  * RET0:        status
1774  * RET1:        state
1775  */
1776 #define HV_FAST_VINTR_GET_STATE         0xab
1777 
1778 /* vintr_set_state()
1779  * TRAP:        HV_FAST_TRAP
1780  * FUNCTION:    HV_FAST_VINTR_SET_STATE
1781  * ARG0:        device handle
1782  * ARG1:        device ino
1783  * ARG2:        state
1784  * RET0:        status
1785  */
1786 #define HV_FAST_VINTR_SET_STATE         0xac
1787 
1788 /* vintr_get_target()
1789  * TRAP:        HV_FAST_TRAP
1790  * FUNCTION:    HV_FAST_VINTR_GET_TARGET
1791  * ARG0:        device handle
1792  * ARG1:        device ino
1793  * RET0:        status
1794  * RET1:        cpuid
1795  */
1796 #define HV_FAST_VINTR_GET_TARGET        0xad
1797 
1798 /* vintr_set_target()
1799  * TRAP:        HV_FAST_TRAP
1800  * FUNCTION:    HV_FAST_VINTR_SET_TARGET
1801  * ARG0:        device handle
1802  * ARG1:        device ino
1803  * ARG2:        cpuid
1804  * RET0:        status
1805  */
1806 #define HV_FAST_VINTR_SET_TARGET        0xae
1807 
1808 #ifndef __ASSEMBLY__
1809 unsigned long sun4v_vintr_get_cookie(unsigned long dev_handle,
1810                                      unsigned long dev_ino,
1811                                      unsigned long *cookie);
1812 unsigned long sun4v_vintr_set_cookie(unsigned long dev_handle,
1813                                      unsigned long dev_ino,
1814                                      unsigned long cookie);
1815 unsigned long sun4v_vintr_get_valid(unsigned long dev_handle,
1816                                     unsigned long dev_ino,
1817                                     unsigned long *valid);
1818 unsigned long sun4v_vintr_set_valid(unsigned long dev_handle,
1819                                     unsigned long dev_ino,
1820                                     unsigned long valid);
1821 unsigned long sun4v_vintr_get_state(unsigned long dev_handle,
1822                                     unsigned long dev_ino,
1823                                     unsigned long *state);
1824 unsigned long sun4v_vintr_set_state(unsigned long dev_handle,
1825                                     unsigned long dev_ino,
1826                                     unsigned long state);
1827 unsigned long sun4v_vintr_get_target(unsigned long dev_handle,
1828                                      unsigned long dev_ino,
1829                                      unsigned long *cpuid);
1830 unsigned long sun4v_vintr_set_target(unsigned long dev_handle,
1831                                      unsigned long dev_ino,
1832                                      unsigned long cpuid);
1833 #endif
1834 
1835 /* PCI IO services.
1836  *
1837  * See the terminology descriptions in the device interrupt services
1838  * section above as those apply here too.  Here are terminology
1839  * definitions specific to these PCI IO services:
1840  *
1841  *      tsbnum          TSB number.  Indentifies which io-tsb is used.
1842  *                      For this version of the specification, tsbnum
1843  *                      must be zero.
1844  *
1845  *      tsbindex        TSB index.  Identifies which entry in the TSB
1846  *                      is used.  The first entry is zero.
1847  *
1848  *      tsbid           A 64-bit aligned data structure which contains
1849  *                      a tsbnum and a tsbindex.  Bits 63:32 contain the
1850  *                      tsbnum and bits 31:00 contain the tsbindex.
1851  *
1852  *                      Use the HV_PCI_TSBID() macro to construct such
1853  *                      values.
1854  *
1855  *      io_attributes   IO attributes for IOMMU mappings.  One of more
1856  *                      of the attritbute bits are stores in a 64-bit
1857  *                      value.  The values are defined below.
1858  *
1859  *      r_addr          64-bit real address
1860  *
1861  *      pci_device      PCI device address.  A PCI device address identifies
1862  *                      a specific device on a specific PCI bus segment.
1863  *                      A PCI device address ia a 32-bit unsigned integer
1864  *                      with the following format:
1865  *
1866  *                              00000000.bbbbbbbb.dddddfff.00000000
1867  *
1868  *                      Use the HV_PCI_DEVICE_BUILD() macro to construct
1869  *                      such values.
1870  *
1871  *      pci_config_offset
1872  *                      PCI configureation space offset.  For conventional
1873  *                      PCI a value between 0 and 255.  For extended
1874  *                      configuration space, a value between 0 and 4095.
1875  *
1876  *                      Note: For PCI configuration space accesses, the offset
1877  *                            must be aligned to the access size.
1878  *
1879  *      error_flag      A return value which specifies if the action succeeded
1880  *                      or failed.  0 means no error, non-0 means some error
1881  *                      occurred while performing the service.
1882  *
1883  *      io_sync_direction
1884  *                      Direction definition for pci_dma_sync(), defined
1885  *                      below in HV_PCI_SYNC_*.
1886  *
1887  *      io_page_list    A list of io_page_addresses, an io_page_address is
1888  *                      a real address.
1889  *
1890  *      io_page_list_p  A pointer to an io_page_list.
1891  *
1892  *      "size based byte swap" - Some functions do size based byte swapping
1893  *                               which allows sw to access pointers and
1894  *                               counters in native form when the processor
1895  *                               operates in a different endianness than the
1896  *                               IO bus.  Size-based byte swapping converts a
1897  *                               multi-byte field between big-endian and
1898  *                               little-endian format.
1899  */
1900 
1901 #define HV_PCI_MAP_ATTR_READ            0x01
1902 #define HV_PCI_MAP_ATTR_WRITE           0x02
1903 #define HV_PCI_MAP_ATTR_RELAXED_ORDER   0x04
1904 
1905 #define HV_PCI_DEVICE_BUILD(b,d,f)      \
1906         ((((b) & 0xff) << 16) | \
1907          (((d) & 0x1f) << 11) | \
1908          (((f) & 0x07) <<  8))
1909 
1910 #define HV_PCI_TSBID(__tsb_num, __tsb_index) \
1911         ((((u64)(__tsb_num)) << 32UL) | ((u64)(__tsb_index)))
1912 
1913 #define HV_PCI_SYNC_FOR_DEVICE          0x01
1914 #define HV_PCI_SYNC_FOR_CPU             0x02
1915 
1916 /* pci_iommu_map()
1917  * TRAP:        HV_FAST_TRAP
1918  * FUNCTION:    HV_FAST_PCI_IOMMU_MAP
1919  * ARG0:        devhandle
1920  * ARG1:        tsbid
1921  * ARG2:        #ttes
1922  * ARG3:        io_attributes
1923  * ARG4:        io_page_list_p
1924  * RET0:        status
1925  * RET1:        #ttes mapped
1926  * ERRORS:      EINVAL          Invalid devhandle/tsbnum/tsbindex/io_attributes
1927  *              EBADALIGN       Improperly aligned real address
1928  *              ENORADDR        Invalid real address
1929  *
1930  * Create IOMMU mappings in the sun4v device defined by the given
1931  * devhandle.  The mappings are created in the TSB defined by the
1932  * tsbnum component of the given tsbid.  The first mapping is created
1933  * in the TSB i ndex defined by the tsbindex component of the given tsbid.
1934  * The call creates up to #ttes mappings, the first one at tsbnum, tsbindex,
1935  * the second at tsbnum, tsbindex + 1, etc.
1936  *
1937  * All mappings are created with the attributes defined by the io_attributes
1938  * argument.  The page mapping addresses are described in the io_page_list
1939  * defined by the given io_page_list_p, which is a pointer to the io_page_list.
1940  * The first entry in the io_page_list is the address for the first iotte, the
1941  * 2nd for the 2nd iotte, and so on.
1942  *
1943  * Each io_page_address in the io_page_list must be appropriately aligned.
1944  * #ttes must be greater than zero.  For this version of the spec, the tsbnum
1945  * component of the given tsbid must be zero.
1946  *
1947  * Returns the actual number of mappings creates, which may be less than
1948  * or equal to the argument #ttes.  If the function returns a value which
1949  * is less than the #ttes, the caller may continus to call the function with
1950  * an updated tsbid, #ttes, io_page_list_p arguments until all pages are
1951  * mapped.
1952  *
1953  * Note: This function does not imply an iotte cache flush.  The guest must
1954  *       demap an entry before re-mapping it.
1955  */
1956 #define HV_FAST_PCI_IOMMU_MAP           0xb0
1957 
1958 /* pci_iommu_demap()
1959  * TRAP:        HV_FAST_TRAP
1960  * FUNCTION:    HV_FAST_PCI_IOMMU_DEMAP
1961  * ARG0:        devhandle
1962  * ARG1:        tsbid
1963  * ARG2:        #ttes
1964  * RET0:        status
1965  * RET1:        #ttes demapped
1966  * ERRORS:      EINVAL          Invalid devhandle/tsbnum/tsbindex
1967  *
1968  * Demap and flush IOMMU mappings in the device defined by the given
1969  * devhandle.  Demaps up to #ttes entries in the TSB defined by the tsbnum
1970  * component of the given tsbid, starting at the TSB index defined by the
1971  * tsbindex component of the given tsbid.
1972  *
1973  * For this version of the spec, the tsbnum of the given tsbid must be zero.
1974  * #ttes must be greater than zero.
1975  *
1976  * Returns the actual number of ttes demapped, which may be less than or equal
1977  * to the argument #ttes.  If #ttes demapped is less than #ttes, the caller
1978  * may continue to call this function with updated tsbid and #ttes arguments
1979  * until all pages are demapped.
1980  *
1981  * Note: Entries do not have to be mapped to be demapped.  A demap of an
1982  *       unmapped page will flush the entry from the tte cache.
1983  */
1984 #define HV_FAST_PCI_IOMMU_DEMAP         0xb1
1985 
1986 /* pci_iommu_getmap()
1987  * TRAP:        HV_FAST_TRAP
1988  * FUNCTION:    HV_FAST_PCI_IOMMU_GETMAP
1989  * ARG0:        devhandle
1990  * ARG1:        tsbid
1991  * RET0:        status
1992  * RET1:        io_attributes
1993  * RET2:        real address
1994  * ERRORS:      EINVAL          Invalid devhandle/tsbnum/tsbindex
1995  *              ENOMAP          Mapping is not valid, no translation exists
1996  *
1997  * Read and return the mapping in the device described by the given devhandle
1998  * and tsbid.  If successful, the io_attributes shall be returned in RET1
1999  * and the page address of the mapping shall be returned in RET2.
2000  *
2001  * For this version of the spec, the tsbnum component of the given tsbid
2002  * must be zero.
2003  */
2004 #define HV_FAST_PCI_IOMMU_GETMAP        0xb2
2005 
2006 /* pci_iommu_getbypass()
2007  * TRAP:        HV_FAST_TRAP
2008  * FUNCTION:    HV_FAST_PCI_IOMMU_GETBYPASS
2009  * ARG0:        devhandle
2010  * ARG1:        real address
2011  * ARG2:        io_attributes
2012  * RET0:        status
2013  * RET1:        io_addr
2014  * ERRORS:      EINVAL          Invalid devhandle/io_attributes
2015  *              ENORADDR        Invalid real address
2016  *              ENOTSUPPORTED   Function not supported in this implementation.
2017  *
2018  * Create a "special" mapping in the device described by the given devhandle,
2019  * for the given real address and attributes.  Return the IO address in RET1
2020  * if successful.
2021  */
2022 #define HV_FAST_PCI_IOMMU_GETBYPASS     0xb3
2023 
2024 /* pci_config_get()
2025  * TRAP:        HV_FAST_TRAP
2026  * FUNCTION:    HV_FAST_PCI_CONFIG_GET
2027  * ARG0:        devhandle
2028  * ARG1:        pci_device
2029  * ARG2:        pci_config_offset
2030  * ARG3:        size
2031  * RET0:        status
2032  * RET1:        error_flag
2033  * RET2:        data
2034  * ERRORS:      EINVAL          Invalid devhandle/pci_device/offset/size
2035  *              EBADALIGN       pci_config_offset not size aligned
2036  *              ENOACCESS       Access to this offset is not permitted
2037  *
2038  * Read PCI configuration space for the adapter described by the given
2039  * devhandle.  Read size (1, 2, or 4) bytes of data from the given
2040  * pci_device, at pci_config_offset from the beginning of the device's
2041  * configuration space.  If there was no error, RET1 is set to zero and
2042  * RET2 is set to the data read.  Insignificant bits in RET2 are not
2043  * guaranteed to have any specific value and therefore must be ignored.
2044  *
2045  * The data returned in RET2 is size based byte swapped.
2046  *
2047  * If an error occurs during the read, set RET1 to a non-zero value.  The
2048  * given pci_config_offset must be 'size' aligned.
2049  */
2050 #define HV_FAST_PCI_CONFIG_GET          0xb4
2051 
2052 /* pci_config_put()
2053  * TRAP:        HV_FAST_TRAP
2054  * FUNCTION:    HV_FAST_PCI_CONFIG_PUT
2055  * ARG0:        devhandle
2056  * ARG1:        pci_device
2057  * ARG2:        pci_config_offset
2058  * ARG3:        size
2059  * ARG4:        data
2060  * RET0:        status
2061  * RET1:        error_flag
2062  * ERRORS:      EINVAL          Invalid devhandle/pci_device/offset/size
2063  *              EBADALIGN       pci_config_offset not size aligned
2064  *              ENOACCESS       Access to this offset is not permitted
2065  *
2066  * Write PCI configuration space for the adapter described by the given
2067  * devhandle.  Write size (1, 2, or 4) bytes of data in a single operation,
2068  * at pci_config_offset from the beginning of the device's configuration
2069  * space.  The data argument contains the data to be written to configuration
2070  * space.  Prior to writing, the data is size based byte swapped.
2071  *
2072  * If an error occurs during the write access, do not generate an error
2073  * report, do set RET1 to a non-zero value.  Otherwise RET1 is zero.
2074  * The given pci_config_offset must be 'size' aligned.
2075  *
2076  * This function is permitted to read from offset zero in the configuration
2077  * space described by the given pci_device if necessary to ensure that the
2078  * write access to config space completes.
2079  */
2080 #define HV_FAST_PCI_CONFIG_PUT          0xb5
2081 
2082 /* pci_peek()
2083  * TRAP:        HV_FAST_TRAP
2084  * FUNCTION:    HV_FAST_PCI_PEEK
2085  * ARG0:        devhandle
2086  * ARG1:        real address
2087  * ARG2:        size
2088  * RET0:        status
2089  * RET1:        error_flag
2090  * RET2:        data
2091  * ERRORS:      EINVAL          Invalid devhandle or size
2092  *              EBADALIGN       Improperly aligned real address
2093  *              ENORADDR        Bad real address
2094  *              ENOACCESS       Guest access prohibited
2095  *
2096  * Attempt to read the IO address given by the given devhandle, real address,
2097  * and size.  Size must be 1, 2, 4, or 8.  The read is performed as a single
2098  * access operation using the given size.  If an error occurs when reading
2099  * from the given location, do not generate an error report, but return a
2100  * non-zero value in RET1.  If the read was successful, return zero in RET1
2101  * and return the actual data read in RET2.  The data returned is size based
2102  * byte swapped.
2103  *
2104  * Non-significant bits in RET2 are not guaranteed to have any specific value
2105  * and therefore must be ignored.  If RET1 is returned as non-zero, the data
2106  * value is not guaranteed to have any specific value and should be ignored.
2107  *
2108  * The caller must have permission to read from the given devhandle, real
2109  * address, which must be an IO address.  The argument real address must be a
2110  * size aligned address.
2111  *
2112  * The hypervisor implementation of this function must block access to any
2113  * IO address that the guest does not have explicit permission to access.
2114  */
2115 #define HV_FAST_PCI_PEEK                0xb6
2116 
2117 /* pci_poke()
2118  * TRAP:        HV_FAST_TRAP
2119  * FUNCTION:    HV_FAST_PCI_POKE
2120  * ARG0:        devhandle
2121  * ARG1:        real address
2122  * ARG2:        size
2123  * ARG3:        data
2124  * ARG4:        pci_device
2125  * RET0:        status
2126  * RET1:        error_flag
2127  * ERRORS:      EINVAL          Invalid devhandle, size, or pci_device
2128  *              EBADALIGN       Improperly aligned real address
2129  *              ENORADDR        Bad real address
2130  *              ENOACCESS       Guest access prohibited
2131  *              ENOTSUPPORTED   Function is not supported by implementation
2132  *
2133  * Attempt to write data to the IO address given by the given devhandle,
2134  * real address, and size.  Size must be 1, 2, 4, or 8.  The write is
2135  * performed as a single access operation using the given size. Prior to
2136  * writing the data is size based swapped.
2137  *
2138  * If an error occurs when writing to the given location, do not generate an
2139  * error report, but return a non-zero value in RET1.  If the write was
2140  * successful, return zero in RET1.
2141  *
2142  * pci_device describes the configuration address of the device being
2143  * written to.  The implementation may safely read from offset 0 with
2144  * the configuration space of the device described by devhandle and
2145  * pci_device in order to guarantee that the write portion of the operation
2146  * completes
2147  *
2148  * Any error that occurs due to the read shall be reported using the normal
2149  * error reporting mechanisms .. the read error is not suppressed.
2150  *
2151  * The caller must have permission to write to the given devhandle, real
2152  * address, which must be an IO address.  The argument real address must be a
2153  * size aligned address.  The caller must have permission to read from
2154  * the given devhandle, pci_device cofiguration space offset 0.
2155  *
2156  * The hypervisor implementation of this function must block access to any
2157  * IO address that the guest does not have explicit permission to access.
2158  */
2159 #define HV_FAST_PCI_POKE                0xb7
2160 
2161 /* pci_dma_sync()
2162  * TRAP:        HV_FAST_TRAP
2163  * FUNCTION:    HV_FAST_PCI_DMA_SYNC
2164  * ARG0:        devhandle
2165  * ARG1:        real address
2166  * ARG2:        size
2167  * ARG3:        io_sync_direction
2168  * RET0:        status
2169  * RET1:        #synced
2170  * ERRORS:      EINVAL          Invalid devhandle or io_sync_direction
2171  *              ENORADDR        Bad real address
2172  *
2173  * Synchronize a memory region described by the given real address and size,
2174  * for the device defined by the given devhandle using the direction(s)
2175  * defined by the given io_sync_direction.  The argument size is the size of
2176  * the memory region in bytes.
2177  *
2178  * Return the actual number of bytes synchronized in the return value #synced,
2179  * which may be less than or equal to the argument size.  If the return
2180  * value #synced is less than size, the caller must continue to call this
2181  * function with updated real address and size arguments until the entire
2182  * memory region is synchronized.
2183  */
2184 #define HV_FAST_PCI_DMA_SYNC            0xb8
2185 
2186 /* PCI MSI services.  */
2187 
2188 #define HV_MSITYPE_MSI32                0x00
2189 #define HV_MSITYPE_MSI64                0x01
2190 
2191 #define HV_MSIQSTATE_IDLE               0x00
2192 #define HV_MSIQSTATE_ERROR              0x01
2193 
2194 #define HV_MSIQ_INVALID                 0x00
2195 #define HV_MSIQ_VALID                   0x01
2196 
2197 #define HV_MSISTATE_IDLE                0x00
2198 #define HV_MSISTATE_DELIVERED           0x01
2199 
2200 #define HV_MSIVALID_INVALID             0x00
2201 #define HV_MSIVALID_VALID               0x01
2202 
2203 #define HV_PCIE_MSGTYPE_PME_MSG         0x18
2204 #define HV_PCIE_MSGTYPE_PME_ACK_MSG     0x1b
2205 #define HV_PCIE_MSGTYPE_CORR_MSG        0x30
2206 #define HV_PCIE_MSGTYPE_NONFATAL_MSG    0x31
2207 #define HV_PCIE_MSGTYPE_FATAL_MSG       0x33
2208 
2209 #define HV_MSG_INVALID                  0x00
2210 #define HV_MSG_VALID                    0x01
2211 
2212 /* pci_msiq_conf()
2213  * TRAP:        HV_FAST_TRAP
2214  * FUNCTION:    HV_FAST_PCI_MSIQ_CONF
2215  * ARG0:        devhandle
2216  * ARG1:        msiqid
2217  * ARG2:        real address
2218  * ARG3:        number of entries
2219  * RET0:        status
2220  * ERRORS:      EINVAL          Invalid devhandle, msiqid or nentries
2221  *              EBADALIGN       Improperly aligned real address
2222  *              ENORADDR        Bad real address
2223  *
2224  * Configure the MSI queue given by the devhandle and msiqid arguments,
2225  * and to be placed at the given real address and be of the given
2226  * number of entries.  The real address must be aligned exactly to match
2227  * the queue size.  Each queue entry is 64-bytes long, so f.e. a 32 entry
2228  * queue must be aligned on a 2048 byte real address boundary.  The MSI-EQ
2229  * Head and Tail are initialized so that the MSI-EQ is 'empty'.
2230  *
2231  * Implementation Note: Certain implementations have fixed sized queues.  In
2232  *                      that case, number of entries must contain the correct
2233  *                      value.
2234  */
2235 #define HV_FAST_PCI_MSIQ_CONF           0xc0
2236 
2237 /* pci_msiq_info()
2238  * TRAP:        HV_FAST_TRAP
2239  * FUNCTION:    HV_FAST_PCI_MSIQ_INFO
2240  * ARG0:        devhandle
2241  * ARG1:        msiqid
2242  * RET0:        status
2243  * RET1:        real address
2244  * RET2:        number of entries
2245  * ERRORS:      EINVAL          Invalid devhandle or msiqid
2246  *
2247  * Return the configuration information for the MSI queue described
2248  * by the given devhandle and msiqid.  The base address of the queue
2249  * is returned in ARG1 and the number of entries is returned in ARG2.
2250  * If the queue is unconfigured, the real address is undefined and the
2251  * number of entries will be returned as zero.
2252  */
2253 #define HV_FAST_PCI_MSIQ_INFO           0xc1
2254 
2255 /* pci_msiq_getvalid()
2256  * TRAP:        HV_FAST_TRAP
2257  * FUNCTION:    HV_FAST_PCI_MSIQ_GETVALID
2258  * ARG0:        devhandle
2259  * ARG1:        msiqid
2260  * RET0:        status
2261  * RET1:        msiqvalid       (HV_MSIQ_VALID or HV_MSIQ_INVALID)
2262  * ERRORS:      EINVAL          Invalid devhandle or msiqid
2263  *
2264  * Get the valid state of the MSI-EQ described by the given devhandle and
2265  * msiqid.
2266  */
2267 #define HV_FAST_PCI_MSIQ_GETVALID       0xc2
2268 
2269 /* pci_msiq_setvalid()
2270  * TRAP:        HV_FAST_TRAP
2271  * FUNCTION:    HV_FAST_PCI_MSIQ_SETVALID
2272  * ARG0:        devhandle
2273  * ARG1:        msiqid
2274  * ARG2:        msiqvalid       (HV_MSIQ_VALID or HV_MSIQ_INVALID)
2275  * RET0:        status
2276  * ERRORS:      EINVAL          Invalid devhandle or msiqid or msiqvalid
2277  *                              value or MSI EQ is uninitialized
2278  *
2279  * Set the valid state of the MSI-EQ described by the given devhandle and
2280  * msiqid to the given msiqvalid.
2281  */
2282 #define HV_FAST_PCI_MSIQ_SETVALID       0xc3
2283 
2284 /* pci_msiq_getstate()
2285  * TRAP:        HV_FAST_TRAP
2286  * FUNCTION:    HV_FAST_PCI_MSIQ_GETSTATE
2287  * ARG0:        devhandle
2288  * ARG1:        msiqid
2289  * RET0:        status
2290  * RET1:        msiqstate       (HV_MSIQSTATE_IDLE or HV_MSIQSTATE_ERROR)
2291  * ERRORS:      EINVAL          Invalid devhandle or msiqid
2292  *
2293  * Get the state of the MSI-EQ described by the given devhandle and
2294  * msiqid.
2295  */
2296 #define HV_FAST_PCI_MSIQ_GETSTATE       0xc4
2297 
2298 /* pci_msiq_getvalid()
2299  * TRAP:        HV_FAST_TRAP
2300  * FUNCTION:    HV_FAST_PCI_MSIQ_GETVALID
2301  * ARG0:        devhandle
2302  * ARG1:        msiqid
2303  * ARG2:        msiqstate       (HV_MSIQSTATE_IDLE or HV_MSIQSTATE_ERROR)
2304  * RET0:        status
2305  * ERRORS:      EINVAL          Invalid devhandle or msiqid or msiqstate
2306  *                              value or MSI EQ is uninitialized
2307  *
2308  * Set the state of the MSI-EQ described by the given devhandle and
2309  * msiqid to the given msiqvalid.
2310  */
2311 #define HV_FAST_PCI_MSIQ_SETSTATE       0xc5
2312 
2313 /* pci_msiq_gethead()
2314  * TRAP:        HV_FAST_TRAP
2315  * FUNCTION:    HV_FAST_PCI_MSIQ_GETHEAD
2316  * ARG0:        devhandle
2317  * ARG1:        msiqid
2318  * RET0:        status
2319  * RET1:        msiqhead
2320  * ERRORS:      EINVAL          Invalid devhandle or msiqid
2321  *
2322  * Get the current MSI EQ queue head for the MSI-EQ described by the
2323  * given devhandle and msiqid.
2324  */
2325 #define HV_FAST_PCI_MSIQ_GETHEAD        0xc6
2326 
2327 /* pci_msiq_sethead()
2328  * TRAP:        HV_FAST_TRAP
2329  * FUNCTION:    HV_FAST_PCI_MSIQ_SETHEAD
2330  * ARG0:        devhandle
2331  * ARG1:        msiqid
2332  * ARG2:        msiqhead
2333  * RET0:        status
2334  * ERRORS:      EINVAL          Invalid devhandle or msiqid or msiqhead,
2335  *                              or MSI EQ is uninitialized
2336  *
2337  * Set the current MSI EQ queue head for the MSI-EQ described by the
2338  * given devhandle and msiqid.
2339  */
2340 #define HV_FAST_PCI_MSIQ_SETHEAD        0xc7
2341 
2342 /* pci_msiq_gettail()
2343  * TRAP:        HV_FAST_TRAP
2344  * FUNCTION:    HV_FAST_PCI_MSIQ_GETTAIL
2345  * ARG0:        devhandle
2346  * ARG1:        msiqid
2347  * RET0:        status
2348  * RET1:        msiqtail
2349  * ERRORS:      EINVAL          Invalid devhandle or msiqid
2350  *
2351  * Get the current MSI EQ queue tail for the MSI-EQ described by the
2352  * given devhandle and msiqid.
2353  */
2354 #define HV_FAST_PCI_MSIQ_GETTAIL        0xc8
2355 
2356 /* pci_msi_getvalid()
2357  * TRAP:        HV_FAST_TRAP
2358  * FUNCTION:    HV_FAST_PCI_MSI_GETVALID
2359  * ARG0:        devhandle
2360  * ARG1:        msinum
2361  * RET0:        status
2362  * RET1:        msivalidstate
2363  * ERRORS:      EINVAL          Invalid devhandle or msinum
2364  *
2365  * Get the current valid/enabled state for the MSI defined by the
2366  * given devhandle and msinum.
2367  */
2368 #define HV_FAST_PCI_MSI_GETVALID        0xc9
2369 
2370 /* pci_msi_setvalid()
2371  * TRAP:        HV_FAST_TRAP
2372  * FUNCTION:    HV_FAST_PCI_MSI_SETVALID
2373  * ARG0:        devhandle
2374  * ARG1:        msinum
2375  * ARG2:        msivalidstate
2376  * RET0:        status
2377  * ERRORS:      EINVAL          Invalid devhandle or msinum or msivalidstate
2378  *
2379  * Set the current valid/enabled state for the MSI defined by the
2380  * given devhandle and msinum.
2381  */
2382 #define HV_FAST_PCI_MSI_SETVALID        0xca
2383 
2384 /* pci_msi_getmsiq()
2385  * TRAP:        HV_FAST_TRAP
2386  * FUNCTION:    HV_FAST_PCI_MSI_GETMSIQ
2387  * ARG0:        devhandle
2388  * ARG1:        msinum
2389  * RET0:        status
2390  * RET1:        msiqid
2391  * ERRORS:      EINVAL          Invalid devhandle or msinum or MSI is unbound
2392  *
2393  * Get the MSI EQ that the MSI defined by the given devhandle and
2394  * msinum is bound to.
2395  */
2396 #define HV_FAST_PCI_MSI_GETMSIQ         0xcb
2397 
2398 /* pci_msi_setmsiq()
2399  * TRAP:        HV_FAST_TRAP
2400  * FUNCTION:    HV_FAST_PCI_MSI_SETMSIQ
2401  * ARG0:        devhandle
2402  * ARG1:        msinum
2403  * ARG2:        msitype
2404  * ARG3:        msiqid
2405  * RET0:        status
2406  * ERRORS:      EINVAL          Invalid devhandle or msinum or msiqid
2407  *
2408  * Set the MSI EQ that the MSI defined by the given devhandle and
2409  * msinum is bound to.
2410  */
2411 #define HV_FAST_PCI_MSI_SETMSIQ         0xcc
2412 
2413 /* pci_msi_getstate()
2414  * TRAP:        HV_FAST_TRAP
2415  * FUNCTION:    HV_FAST_PCI_MSI_GETSTATE
2416  * ARG0:        devhandle
2417  * ARG1:        msinum
2418  * RET0:        status
2419  * RET1:        msistate
2420  * ERRORS:      EINVAL          Invalid devhandle or msinum
2421  *
2422  * Get the state of the MSI defined by the given devhandle and msinum.
2423  * If not initialized, return HV_MSISTATE_IDLE.
2424  */
2425 #define HV_FAST_PCI_MSI_GETSTATE        0xcd
2426 
2427 /* pci_msi_setstate()
2428  * TRAP:        HV_FAST_TRAP
2429  * FUNCTION:    HV_FAST_PCI_MSI_SETSTATE
2430  * ARG0:        devhandle
2431  * ARG1:        msinum
2432  * ARG2:        msistate
2433  * RET0:        status
2434  * ERRORS:      EINVAL          Invalid devhandle or msinum or msistate
2435  *
2436  * Set the state of the MSI defined by the given devhandle and msinum.
2437  */
2438 #define HV_FAST_PCI_MSI_SETSTATE        0xce
2439 
2440 /* pci_msg_getmsiq()
2441  * TRAP:        HV_FAST_TRAP
2442  * FUNCTION:    HV_FAST_PCI_MSG_GETMSIQ
2443  * ARG0:        devhandle
2444  * ARG1:        msgtype
2445  * RET0:        status
2446  * RET1:        msiqid
2447  * ERRORS:      EINVAL          Invalid devhandle or msgtype
2448  *
2449  * Get the MSI EQ of the MSG defined by the given devhandle and msgtype.
2450  */
2451 #define HV_FAST_PCI_MSG_GETMSIQ         0xd0
2452 
2453 /* pci_msg_setmsiq()
2454  * TRAP:        HV_FAST_TRAP
2455  * FUNCTION:    HV_FAST_PCI_MSG_SETMSIQ
2456  * ARG0:        devhandle
2457  * ARG1:        msgtype
2458  * ARG2:        msiqid
2459  * RET0:        status
2460  * ERRORS:      EINVAL          Invalid devhandle, msgtype, or msiqid
2461  *
2462  * Set the MSI EQ of the MSG defined by the given devhandle and msgtype.
2463  */
2464 #define HV_FAST_PCI_MSG_SETMSIQ         0xd1
2465 
2466 /* pci_msg_getvalid()
2467  * TRAP:        HV_FAST_TRAP
2468  * FUNCTION:    HV_FAST_PCI_MSG_GETVALID
2469  * ARG0:        devhandle
2470  * ARG1:        msgtype
2471  * RET0:        status
2472  * RET1:        msgvalidstate
2473  * ERRORS:      EINVAL          Invalid devhandle or msgtype
2474  *
2475  * Get the valid/enabled state of the MSG defined by the given
2476  * devhandle and msgtype.
2477  */
2478 #define HV_FAST_PCI_MSG_GETVALID        0xd2
2479 
2480 /* pci_msg_setvalid()
2481  * TRAP:        HV_FAST_TRAP
2482  * FUNCTION:    HV_FAST_PCI_MSG_SETVALID
2483  * ARG0:        devhandle
2484  * ARG1:        msgtype
2485  * ARG2:        msgvalidstate
2486  * RET0:        status
2487  * ERRORS:      EINVAL          Invalid devhandle or msgtype or msgvalidstate
2488  *
2489  * Set the valid/enabled state of the MSG defined by the given
2490  * devhandle and msgtype.
2491  */
2492 #define HV_FAST_PCI_MSG_SETVALID        0xd3
2493 
2494 /* PCI IOMMU v2 definitions and services
2495  *
2496  * While the PCI IO definitions above is valid IOMMU v2 adds new PCI IO
2497  * definitions and services.
2498  *
2499  *      CTE             Clump Table Entry. First level table entry in the ATU.
2500  *
2501  *      pci_device_list
2502  *                      A 32-bit aligned list of pci_devices.
2503  *
2504  *      pci_device_listp
2505  *                      real address of a pci_device_list. 32-bit aligned.
2506  *
2507  *      iotte           IOMMU translation table entry.
2508  *
2509  *      iotte_attributes
2510  *                      IO Attributes for IOMMU v2 mappings. In addition to
2511  *                      read, write IOMMU v2 supports relax ordering
2512  *
2513  *      io_page_list    A 64-bit aligned list of real addresses. Each real
2514  *                      address in an io_page_list must be properly aligned
2515  *                      to the pagesize of the given IOTSB.
2516  *
2517  *      io_page_list_p  Real address of an io_page_list, 64-bit aligned.
2518  *
2519  *      IOTSB           IO Translation Storage Buffer. An aligned table of
2520  *                      IOTTEs. Each IOTSB has a pagesize, table size, and
2521  *                      virtual address associated with it that must match
2522  *                      a pagesize and table size supported by the un-derlying
2523  *                      hardware implementation. The alignment requirements
2524  *                      for an IOTSB depend on the pagesize used for that IOTSB.
2525  *                      Each IOTTE in an IOTSB maps one pagesize-sized page.
2526  *                      The size of the IOTSB dictates how large of a virtual
2527  *                      address space the IOTSB is capable of mapping.
2528  *
2529  *      iotsb_handle    An opaque identifier for an IOTSB. A devhandle plus
2530  *                      iotsb_handle represents a binding of an IOTSB to a
2531  *                      PCI root complex.
2532  *
2533  *      iotsb_index     Zero-based IOTTE number within an IOTSB.
2534  */
2535 
2536 /* The index_count argument consists of two fields:
2537  * bits 63:48 #iottes and bits 47:0 iotsb_index
2538  */
2539 #define HV_PCI_IOTSB_INDEX_COUNT(__iottes, __iotsb_index) \
2540         (((u64)(__iottes) << 48UL) | ((u64)(__iotsb_index)))
2541 
2542 /* pci_iotsb_conf()
2543  * TRAP:        HV_FAST_TRAP
2544  * FUNCTION:    HV_FAST_PCI_IOTSB_CONF
2545  * ARG0:        devhandle
2546  * ARG1:        r_addr
2547  * ARG2:        size
2548  * ARG3:        pagesize
2549  * ARG4:        iova
2550  * RET0:        status
2551  * RET1:        iotsb_handle
2552  * ERRORS:      EINVAL          Invalid devhandle, size, iova, or pagesize
2553  *              EBADALIGN       r_addr is not properly aligned
2554  *              ENORADDR        r_addr is not a valid real address
2555  *              ETOOMANY        No further IOTSBs may be configured
2556  *              EBUSY           Duplicate devhandle, raddir, iova combination
2557  *
2558  * Create an IOTSB suitable for the PCI root complex identified by devhandle,
2559  * for the DMA virtual address defined by the argument iova.
2560  *
2561  * r_addr is the properly aligned base address of the IOTSB and size is the
2562  * IOTSB (table) size in bytes.The IOTSB is required to be zeroed prior to
2563  * being configured. If it contains any values other than zeros then the
2564  * behavior is undefined.
2565  *
2566  * pagesize is the size of each page in the IOTSB. Note that the combination of
2567  * size (table size) and pagesize must be valid.
2568  *
2569  * virt is the DMA virtual address this IOTSB will map.
2570  *
2571  * If successful, the opaque 64-bit handle iotsb_handle is returned in ret1.
2572  * Once configured, privileged access to the IOTSB memory is prohibited and
2573  * creates undefined behavior. The only permitted access is indirect via these
2574  * services.
2575  */
2576 #define HV_FAST_PCI_IOTSB_CONF          0x190
2577 
2578 /* pci_iotsb_info()
2579  * TRAP:        HV_FAST_TRAP
2580  * FUNCTION:    HV_FAST_PCI_IOTSB_INFO
2581  * ARG0:        devhandle
2582  * ARG1:        iotsb_handle
2583  * RET0:        status
2584  * RET1:        r_addr
2585  * RET2:        size
2586  * RET3:        pagesize
2587  * RET4:        iova
2588  * RET5:        #bound
2589  * ERRORS:      EINVAL  Invalid devhandle or iotsb_handle
2590  *
2591  * This service returns configuration information about an IOTSB previously
2592  * created with pci_iotsb_conf.
2593  *
2594  * iotsb_handle value 0 may be used with this service to inquire about the
2595  * legacy IOTSB that may or may not exist. If the service succeeds, the return
2596  * values describe the legacy IOTSB and I/O virtual addresses mapped by that
2597  * table. However, the table base address r_addr may contain the value -1 which
2598  * indicates a memory range that cannot be accessed or be reclaimed.
2599  *
2600  * The return value #bound contains the number of PCI devices that iotsb_handle
2601  * is currently bound to.
2602  */
2603 #define HV_FAST_PCI_IOTSB_INFO          0x191
2604 
2605 /* pci_iotsb_unconf()
2606  * TRAP:        HV_FAST_TRAP
2607  * FUNCTION:    HV_FAST_PCI_IOTSB_UNCONF
2608  * ARG0:        devhandle
2609  * ARG1:        iotsb_handle
2610  * RET0:        status
2611  * ERRORS:      EINVAL  Invalid devhandle or iotsb_handle
2612  *              EBUSY   The IOTSB is bound and may not be unconfigured
2613  *
2614  * This service unconfigures the IOTSB identified by the devhandle and
2615  * iotsb_handle arguments, previously created with pci_iotsb_conf.
2616  * The IOTSB must not be currently bound to any device or the service will fail
2617  *
2618  * If the call succeeds, iotsb_handle is no longer valid.
2619  */
2620 #define HV_FAST_PCI_IOTSB_UNCONF        0x192
2621 
2622 /* pci_iotsb_bind()
2623  * TRAP:        HV_FAST_TRAP
2624  * FUNCTION:    HV_FAST_PCI_IOTSB_BIND
2625  * ARG0:        devhandle
2626  * ARG1:        iotsb_handle
2627  * ARG2:        pci_device
2628  * RET0:        status
2629  * ERRORS:      EINVAL  Invalid devhandle, iotsb_handle, or pci_device
2630  *              EBUSY   A PCI function is already bound to an IOTSB at the same
2631  *                      address range as specified by devhandle, iotsb_handle.
2632  *
2633  * This service binds the PCI function specified by the argument pci_device to
2634  * the IOTSB specified by the arguments devhandle and iotsb_handle.
2635  *
2636  * The PCI device function is bound to the specified IOTSB with the IOVA range
2637  * specified when the IOTSB was configured via pci_iotsb_conf. If the function
2638  * is already bound then it is unbound first.
2639  */
2640 #define HV_FAST_PCI_IOTSB_BIND          0x193
2641 
2642 /* pci_iotsb_unbind()
2643  * TRAP:        HV_FAST_TRAP
2644  * FUNCTION:    HV_FAST_PCI_IOTSB_UNBIND
2645  * ARG0:        devhandle
2646  * ARG1:        iotsb_handle
2647  * ARG2:        pci_device
2648  * RET0:        status
2649  * ERRORS:      EINVAL  Invalid devhandle, iotsb_handle, or pci_device
2650  *              ENOMAP  The PCI function was not bound to the specified IOTSB
2651  *
2652  * This service unbinds the PCI device specified by the argument pci_device
2653  * from the IOTSB identified  * by the arguments devhandle and iotsb_handle.
2654  *
2655  * If the PCI device is not bound to the specified IOTSB then this service will
2656  * fail with status ENOMAP
2657  */
2658 #define HV_FAST_PCI_IOTSB_UNBIND        0x194
2659 
2660 /* pci_iotsb_get_binding()
2661  * TRAP:        HV_FAST_TRAP
2662  * FUNCTION:    HV_FAST_PCI_IOTSB_GET_BINDING
2663  * ARG0:        devhandle
2664  * ARG1:        iotsb_handle
2665  * ARG2:        iova
2666  * RET0:        status
2667  * RET1:        iotsb_handle
2668  * ERRORS:      EINVAL  Invalid devhandle, pci_device, or iova
2669  *              ENOMAP  The PCI function is not bound to an IOTSB at iova
2670  *
2671  * This service returns the IOTSB binding, iotsb_handle, for a given pci_device
2672  * and DMA virtual address, iova.
2673  *
2674  * iova must be the base address of a DMA virtual address range as defined by
2675  * the iommu-address-ranges property in the root complex device node defined
2676  * by the argument devhandle.
2677  */
2678 #define HV_FAST_PCI_IOTSB_GET_BINDING   0x195
2679 
2680 /* pci_iotsb_map()
2681  * TRAP:        HV_FAST_TRAP
2682  * FUNCTION:    HV_FAST_PCI_IOTSB_MAP
2683  * ARG0:        devhandle
2684  * ARG1:        iotsb_handle
2685  * ARG2:        index_count
2686  * ARG3:        iotte_attributes
2687  * ARG4:        io_page_list_p
2688  * RET0:        status
2689  * RET1:        #mapped
2690  * ERRORS:      EINVAL          Invalid devhandle, iotsb_handle, #iottes,
2691  *                              iotsb_index or iotte_attributes
2692  *              EBADALIGN       Improperly aligned io_page_list_p or I/O page
2693  *                              address in the I/O page list.
2694  *              ENORADDR        Invalid io_page_list_p or I/O page address in
2695  *                              the I/O page list.
2696  *
2697  * This service creates and flushes mappings in the IOTSB defined by the
2698  * arguments devhandle, iotsb.
2699  *
2700  * The index_count argument consists of two fields. Bits 63:48 contain #iotte
2701  * and bits 47:0 contain iotsb_index
2702  *
2703  * The first mapping is created in the IOTSB index specified by iotsb_index.
2704  * Subsequent mappings are  created at iotsb_index+1 and so on.
2705  *
2706  * The attributes of each mapping are defined by the argument iotte_attributes.
2707  *
2708  * The io_page_list_p specifies the real address of the 64-bit-aligned list of
2709  * #iottes I/O page addresses. Each page address must be a properly aligned
2710  * real address of a page to be mapped in the IOTSB. The first entry in the I/O
2711  * page list contains the real address of the first page, the 2nd entry for the
2712  * 2nd page, and so on.
2713  *
2714  * #iottes must be greater than zero.
2715  *
2716  * The return value #mapped is the actual number of mappings created, which may
2717  * be less than or equal to the argument #iottes. If the function returns
2718  * successfully with a #mapped value less than the requested #iottes then the
2719  * caller should continue to invoke the service with updated iotsb_index,
2720  * #iottes, and io_page_list_p arguments until all pages are mapped.
2721  *
2722  * This service must not be used to demap a mapping. In other words, all
2723  * mappings must be valid and have  one or both of the RW attribute bits set.
2724  *
2725  * Note:
2726  * It is implementation-defined whether I/O page real address validity checking
2727  * is done at time mappings are established or deferred until they are
2728  * accessed.
2729  */
2730 #define HV_FAST_PCI_IOTSB_MAP           0x196
2731 
2732 /* pci_iotsb_map_one()
2733  * TRAP:        HV_FAST_TRAP
2734  * FUNCTION:    HV_FAST_PCI_IOTSB_MAP_ONE
2735  * ARG0:        devhandle
2736  * ARG1:        iotsb_handle
2737  * ARG2:        iotsb_index
2738  * ARG3:        iotte_attributes
2739  * ARG4:        r_addr
2740  * RET0:        status
2741  * ERRORS:      EINVAL          Invalid devhandle,iotsb_handle, iotsb_index
2742  *                              or iotte_attributes
2743  *              EBADALIGN       Improperly aligned r_addr
2744  *              ENORADDR        Invalid r_addr
2745  *
2746  * This service creates and flushes a single mapping in the IOTSB defined by the
2747  * arguments devhandle, iotsb.
2748  *
2749  * The mapping for the page at r_addr is created at the IOTSB index specified by
2750  * iotsb_index with  the attributes iotte_attributes.
2751  *
2752  * This service must not be used to demap a mapping. In other words, the mapping
2753  * must be valid and have one or both of the RW attribute bits set.
2754  *
2755  * Note:
2756  * It is implementation-defined whether I/O page real address validity checking
2757  * is done at time mappings are established or deferred until they are
2758  * accessed.
2759  */
2760 #define HV_FAST_PCI_IOTSB_MAP_ONE       0x197
2761 
2762 /* pci_iotsb_demap()
2763  * TRAP:        HV_FAST_TRAP
2764  * FUNCTION:    HV_FAST_PCI_IOTSB_DEMAP
2765  * ARG0:        devhandle
2766  * ARG1:        iotsb_handle
2767  * ARG2:        iotsb_index
2768  * ARG3:        #iottes
2769  * RET0:        status
2770  * RET1:        #unmapped
2771  * ERRORS:      EINVAL  Invalid devhandle, iotsb_handle, iotsb_index or #iottes
2772  *
2773  * This service unmaps and flushes up to #iottes mappings starting at index
2774  * iotsb_index from the IOTSB defined by the arguments devhandle, iotsb.
2775  *
2776  * #iottes must be greater than zero.
2777  *
2778  * The actual number of IOTTEs unmapped is returned in #unmapped and may be less
2779  * than or equal to the requested number of IOTTEs, #iottes.
2780  *
2781  * If #unmapped is less than #iottes, the caller should continue to invoke this
2782  * service with updated iotsb_index and #iottes arguments until all pages are
2783  * demapped.
2784  */
2785 #define HV_FAST_PCI_IOTSB_DEMAP         0x198
2786 
2787 /* pci_iotsb_getmap()
2788  * TRAP:        HV_FAST_TRAP
2789  * FUNCTION:    HV_FAST_PCI_IOTSB_GETMAP
2790  * ARG0:        devhandle
2791  * ARG1:        iotsb_handle
2792  * ARG2:        iotsb_index
2793  * RET0:        status
2794  * RET1:        r_addr
2795  * RET2:        iotte_attributes
2796  * ERRORS:      EINVAL  Invalid devhandle, iotsb_handle, or iotsb_index
2797  *              ENOMAP  No mapping was found
2798  *
2799  * This service returns the mapping specified by index iotsb_index from the
2800  * IOTSB defined by the arguments devhandle, iotsb.
2801  *
2802  * Upon success, the real address of the mapping shall be returned in
2803  * r_addr and thethe IOTTE mapping attributes shall be returned in
2804  * iotte_attributes.
2805  *
2806  * The return value iotte_attributes may not include optional features used in
2807  * the call to create the  mapping.
2808  */
2809 #define HV_FAST_PCI_IOTSB_GETMAP        0x199
2810 
2811 /* pci_iotsb_sync_mappings()
2812  * TRAP:        HV_FAST_TRAP
2813  * FUNCTION:    HV_FAST_PCI_IOTSB_SYNC_MAPPINGS
2814  * ARG0:        devhandle
2815  * ARG1:        iotsb_handle
2816  * ARG2:        iotsb_index
2817  * ARG3:        #iottes
2818  * RET0:        status
2819  * RET1:        #synced
2820  * ERROS:       EINVAL  Invalid devhandle, iotsb_handle, iotsb_index, or #iottes
2821  *
2822  * This service synchronizes #iottes mappings starting at index iotsb_index in
2823  * the IOTSB defined by the arguments devhandle, iotsb.
2824  *
2825  * #iottes must be greater than zero.
2826  *
2827  * The actual number of IOTTEs synchronized is returned in #synced, which may
2828  * be less than or equal to the requested number, #iottes.
2829  *
2830  * Upon a successful return, #synced is less than #iottes, the caller should
2831  * continue to invoke this service with updated iotsb_index and #iottes
2832  * arguments until all pages are synchronized.
2833  */
2834 #define HV_FAST_PCI_IOTSB_SYNC_MAPPINGS 0x19a
2835 
2836 /* Logical Domain Channel services.  */
2837 
2838 #define LDC_CHANNEL_DOWN                0
2839 #define LDC_CHANNEL_UP                  1
2840 #define LDC_CHANNEL_RESETTING           2
2841 
2842 /* ldc_tx_qconf()
2843  * TRAP:        HV_FAST_TRAP
2844  * FUNCTION:    HV_FAST_LDC_TX_QCONF
2845  * ARG0:        channel ID
2846  * ARG1:        real address base of queue
2847  * ARG2:        num entries in queue
2848  * RET0:        status
2849  *
2850  * Configure transmit queue for the LDC endpoint specified by the
2851  * given channel ID, to be placed at the given real address, and
2852  * be of the given num entries.  Num entries must be a power of two.
2853  * The real address base of the queue must be aligned on the queue
2854  * size.  Each queue entry is 64-bytes, so for example, a 32 entry
2855  * queue must be aligned on a 2048 byte real address boundary.
2856  *
2857  * Upon configuration of a valid transmit queue the head and tail
2858  * pointers are set to a hypervisor specific identical value indicating
2859  * that the queue initially is empty.
2860  *
2861  * The endpoint's transmit queue is un-configured if num entries is zero.
2862  *
2863  * The maximum number of entries for each queue for a specific cpu may be
2864  * determined from the machine description.  A transmit queue may be
2865  * specified even in the event that the LDC is down (peer endpoint has no
2866  * receive queue specified).  Transmission will begin as soon as the peer
2867  * endpoint defines a receive queue.
2868  *
2869  * It is recommended that a guest wait for a transmit queue to empty prior
2870  * to reconfiguring it, or un-configuring it.  Re or un-configuring of a
2871  * non-empty transmit queue behaves exactly as defined above, however it
2872  * is undefined as to how many of the pending entries in the original queue
2873  * will be delivered prior to the re-configuration taking effect.
2874  * Furthermore, as the queue configuration causes a reset of the head and
2875  * tail pointers there is no way for a guest to determine how many entries
2876  * have been sent after the configuration operation.
2877  */
2878 #define HV_FAST_LDC_TX_QCONF            0xe0
2879 
2880 /* ldc_tx_qinfo()
2881  * TRAP:        HV_FAST_TRAP
2882  * FUNCTION:    HV_FAST_LDC_TX_QINFO
2883  * ARG0:        channel ID
2884  * RET0:        status
2885  * RET1:        real address base of queue
2886  * RET2:        num entries in queue
2887  *
2888  * Return the configuration info for the transmit queue of LDC endpoint
2889  * defined by the given channel ID.  The real address is the currently
2890  * defined real address base of the defined queue, and num entries is the
2891  * size of the queue in terms of number of entries.
2892  *
2893  * If the specified channel ID is a valid endpoint number, but no transmit
2894  * queue has been defined this service will return success, but with num
2895  * entries set to zero and the real address will have an undefined value.
2896  */
2897 #define HV_FAST_LDC_TX_QINFO            0xe1
2898 
2899 /* ldc_tx_get_state()
2900  * TRAP:        HV_FAST_TRAP
2901  * FUNCTION:    HV_FAST_LDC_TX_GET_STATE
2902  * ARG0:        channel ID
2903  * RET0:        status
2904  * RET1:        head offset
2905  * RET2:        tail offset
2906  * RET3:        channel state
2907  *
2908  * Return the transmit state, and the head and tail queue pointers, for
2909  * the transmit queue of the LDC endpoint defined by the given channel ID.
2910  * The head and tail values are the byte offset of the head and tail
2911  * positions of the transmit queue for the specified endpoint.
2912  */
2913 #define HV_FAST_LDC_TX_GET_STATE        0xe2
2914 
2915 /* ldc_tx_set_qtail()
2916  * TRAP:        HV_FAST_TRAP
2917  * FUNCTION:    HV_FAST_LDC_TX_SET_QTAIL
2918  * ARG0:        channel ID
2919  * ARG1:        tail offset
2920  * RET0:        status
2921  *
2922  * Update the tail pointer for the transmit queue associated with the LDC
2923  * endpoint defined by the given channel ID.  The tail offset specified
2924  * must be aligned on a 64 byte boundary, and calculated so as to increase
2925  * the number of pending entries on the transmit queue.  Any attempt to
2926  * decrease the number of pending transmit queue entires is considered
2927  * an invalid tail offset and will result in an EINVAL error.
2928  *
2929  * Since the tail of the transmit queue may not be moved backwards, the
2930  * transmit queue may be flushed by configuring a new transmit queue,
2931  * whereupon the hypervisor will configure the initial transmit head and
2932  * tail pointers to be equal.
2933  */
2934 #define HV_FAST_LDC_TX_SET_QTAIL        0xe3
2935 
2936 /* ldc_rx_qconf()
2937  * TRAP:        HV_FAST_TRAP
2938  * FUNCTION:    HV_FAST_LDC_RX_QCONF
2939  * ARG0:        channel ID
2940  * ARG1:        real address base of queue
2941  * ARG2:        num entries in queue
2942  * RET0:        status
2943  *
2944  * Configure receive queue for the LDC endpoint specified by the
2945  * given channel ID, to be placed at the given real address, and
2946  * be of the given num entries.  Num entries must be a power of two.
2947  * The real address base of the queue must be aligned on the queue
2948  * size.  Each queue entry is 64-bytes, so for example, a 32 entry
2949  * queue must be aligned on a 2048 byte real address boundary.
2950  *
2951  * The endpoint's transmit queue is un-configured if num entries is zero.
2952  *
2953  * If a valid receive queue is specified for a local endpoint the LDC is
2954  * in the up state for the purpose of transmission to this endpoint.
2955  *
2956  * The maximum number of entries for each queue for a specific cpu may be
2957  * determined from the machine description.
2958  *
2959  * As receive queue configuration causes a reset of the queue's head and
2960  * tail pointers there is no way for a gues to determine how many entries
2961  * have been received between a preceding ldc_get_rx_state() API call
2962  * and the completion of the configuration operation.  It should be noted
2963  * that datagram delivery is not guaranteed via domain channels anyway,
2964  * and therefore any higher protocol should be resilient to datagram
2965  * loss if necessary.  However, to overcome this specific race potential
2966  * it is recommended, for example, that a higher level protocol be employed
2967  * to ensure either retransmission, or ensure that no datagrams are pending
2968  * on the peer endpoint's transmit queue prior to the configuration process.
2969  */
2970 #define HV_FAST_LDC_RX_QCONF            0xe4
2971 
2972 /* ldc_rx_qinfo()
2973  * TRAP:        HV_FAST_TRAP
2974  * FUNCTION:    HV_FAST_LDC_RX_QINFO
2975  * ARG0:        channel ID
2976  * RET0:        status
2977  * RET1:        real address base of queue
2978  * RET2:        num entries in queue
2979  *
2980  * Return the configuration info for the receive queue of LDC endpoint
2981  * defined by the given channel ID.  The real address is the currently
2982  * defined real address base of the defined queue, and num entries is the
2983  * size of the queue in terms of number of entries.
2984  *
2985  * If the specified channel ID is a valid endpoint number, but no receive
2986  * queue has been defined this service will return success, but with num
2987  * entries set to zero and the real address will have an undefined value.
2988  */
2989 #define HV_FAST_LDC_RX_QINFO            0xe5
2990 
2991 /* ldc_rx_get_state()
2992  * TRAP:        HV_FAST_TRAP
2993  * FUNCTION:    HV_FAST_LDC_RX_GET_STATE
2994  * ARG0:        channel ID
2995  * RET0:        status
2996  * RET1:        head offset
2997  * RET2:        tail offset
2998  * RET3:        channel state
2999  *
3000  * Return the receive state, and the head and tail queue pointers, for
3001  * the receive queue of the LDC endpoint defined by the given channel ID.
3002  * The head and tail values are the byte offset of the head and tail
3003  * positions of the receive queue for the specified endpoint.
3004  */
3005 #define HV_FAST_LDC_RX_GET_STATE        0xe6
3006 
3007 /* ldc_rx_set_qhead()
3008  * TRAP:        HV_FAST_TRAP
3009  * FUNCTION:    HV_FAST_LDC_RX_SET_QHEAD
3010  * ARG0:        channel ID
3011  * ARG1:        head offset
3012  * RET0:        status
3013  *
3014  * Update the head pointer for the receive queue associated with the LDC
3015  * endpoint defined by the given channel ID.  The head offset specified
3016  * must be aligned on a 64 byte boundary, and calculated so as to decrease
3017  * the number of pending entries on the receive queue.  Any attempt to
3018  * increase the number of pending receive queue entires is considered
3019  * an invalid head offset and will result in an EINVAL error.
3020  *
3021  * The receive queue may be flushed by setting the head offset equal
3022  * to the current tail offset.
3023  */
3024 #define HV_FAST_LDC_RX_SET_QHEAD        0xe7
3025 
3026 /* LDC Map Table Entry.  Each slot is defined by a translation table
3027  * entry, as specified by the LDC_MTE_* bits below, and a 64-bit
3028  * hypervisor invalidation cookie.
3029  */
3030 #define LDC_MTE_PADDR   0x0fffffffffffe000 /* pa[55:13]          */
3031 #define LDC_MTE_COPY_W  0x0000000000000400 /* copy write access  */
3032 #define LDC_MTE_COPY_R  0x0000000000000200 /* copy read access   */
3033 #define LDC_MTE_IOMMU_W 0x0000000000000100 /* IOMMU write access */
3034 #define LDC_MTE_IOMMU_R 0x0000000000000080 /* IOMMU read access  */
3035 #define LDC_MTE_EXEC    0x0000000000000040 /* execute            */
3036 #define LDC_MTE_WRITE   0x0000000000000020 /* read               */
3037 #define LDC_MTE_READ    0x0000000000000010 /* write              */
3038 #define LDC_MTE_SZALL   0x000000000000000f /* page size bits     */
3039 #define LDC_MTE_SZ16GB  0x0000000000000007 /* 16GB page          */
3040 #define LDC_MTE_SZ2GB   0x0000000000000006 /* 2GB page           */
3041 #define LDC_MTE_SZ256MB 0x0000000000000005 /* 256MB page         */
3042 #define LDC_MTE_SZ32MB  0x0000000000000004 /* 32MB page          */
3043 #define LDC_MTE_SZ4MB   0x0000000000000003 /* 4MB page           */
3044 #define LDC_MTE_SZ512K  0x0000000000000002 /* 512K page          */
3045 #define LDC_MTE_SZ64K   0x0000000000000001 /* 64K page           */
3046 #define LDC_MTE_SZ8K    0x0000000000000000 /* 8K page            */
3047 
3048 #ifndef __ASSEMBLY__
3049 struct ldc_mtable_entry {
3050         unsigned long   mte;
3051         unsigned long   cookie;
3052 };
3053 #endif
3054 
3055 /* ldc_set_map_table()
3056  * TRAP:        HV_FAST_TRAP
3057  * FUNCTION:    HV_FAST_LDC_SET_MAP_TABLE
3058  * ARG0:        channel ID
3059  * ARG1:        table real address
3060  * ARG2:        num entries
3061  * RET0:        status
3062  *
3063  * Register the MTE table at the given table real address, with the
3064  * specified num entries, for the LDC indicated by the given channel
3065  * ID.
3066  */
3067 #define HV_FAST_LDC_SET_MAP_TABLE       0xea
3068 
3069 /* ldc_get_map_table()
3070  * TRAP:        HV_FAST_TRAP
3071  * FUNCTION:    HV_FAST_LDC_GET_MAP_TABLE
3072  * ARG0:        channel ID
3073  * RET0:        status
3074  * RET1:        table real address
3075  * RET2:        num entries
3076  *
3077  * Return the configuration of the current mapping table registered
3078  * for the given channel ID.
3079  */
3080 #define HV_FAST_LDC_GET_MAP_TABLE       0xeb
3081 
3082 #define LDC_COPY_IN     0
3083 #define LDC_COPY_OUT    1
3084 
3085 /* ldc_copy()
3086  * TRAP:        HV_FAST_TRAP
3087  * FUNCTION:    HV_FAST_LDC_COPY
3088  * ARG0:        channel ID
3089  * ARG1:        LDC_COPY_* direction code
3090  * ARG2:        target real address
3091  * ARG3:        local real address
3092  * ARG4:        length in bytes
3093  * RET0:        status
3094  * RET1:        actual length in bytes
3095  */
3096 #define HV_FAST_LDC_COPY                0xec
3097 
3098 #define LDC_MEM_READ    1
3099 #define LDC_MEM_WRITE   2
3100 #define LDC_MEM_EXEC    4
3101 
3102 /* ldc_mapin()
3103  * TRAP:        HV_FAST_TRAP
3104  * FUNCTION:    HV_FAST_LDC_MAPIN
3105  * ARG0:        channel ID
3106  * ARG1:        cookie
3107  * RET0:        status
3108  * RET1:        real address
3109  * RET2:        LDC_MEM_* permissions
3110  */
3111 #define HV_FAST_LDC_MAPIN               0xed
3112 
3113 /* ldc_unmap()
3114  * TRAP:        HV_FAST_TRAP
3115  * FUNCTION:    HV_FAST_LDC_UNMAP
3116  * ARG0:        real address
3117  * RET0:        status
3118  */
3119 #define HV_FAST_LDC_UNMAP               0xee
3120 
3121 /* ldc_revoke()
3122  * TRAP:        HV_FAST_TRAP
3123  * FUNCTION:    HV_FAST_LDC_REVOKE
3124  * ARG0:        channel ID
3125  * ARG1:        cookie
3126  * ARG2:        ldc_mtable_entry cookie
3127  * RET0:        status
3128  */
3129 #define HV_FAST_LDC_REVOKE              0xef
3130 
3131 #ifndef __ASSEMBLY__
3132 unsigned long sun4v_ldc_tx_qconf(unsigned long channel,
3133                                  unsigned long ra,
3134                                  unsigned long num_entries);
3135 unsigned long sun4v_ldc_tx_qinfo(unsigned long channel,
3136                                  unsigned long *ra,
3137                                  unsigned long *num_entries);
3138 unsigned long sun4v_ldc_tx_get_state(unsigned long channel,
3139                                      unsigned long *head_off,
3140                                      unsigned long *tail_off,
3141                                      unsigned long *chan_state);
3142 unsigned long sun4v_ldc_tx_set_qtail(unsigned long channel,
3143                                      unsigned long tail_off);
3144 unsigned long sun4v_ldc_rx_qconf(unsigned long channel,
3145                                  unsigned long ra,
3146                                  unsigned long num_entries);
3147 unsigned long sun4v_ldc_rx_qinfo(unsigned long channel,
3148                                  unsigned long *ra,
3149                                  unsigned long *num_entries);
3150 unsigned long sun4v_ldc_rx_get_state(unsigned long channel,
3151                                      unsigned long *head_off,
3152                                      unsigned long *tail_off,
3153                                      unsigned long *chan_state);
3154 unsigned long sun4v_ldc_rx_set_qhead(unsigned long channel,
3155                                      unsigned long head_off);
3156 unsigned long sun4v_ldc_set_map_table(unsigned long channel,
3157                                       unsigned long ra,
3158                                       unsigned long num_entries);
3159 unsigned long sun4v_ldc_get_map_table(unsigned long channel,
3160                                       unsigned long *ra,
3161                                       unsigned long *num_entries);
3162 unsigned long sun4v_ldc_copy(unsigned long channel,
3163                              unsigned long dir_code,
3164                              unsigned long tgt_raddr,
3165                              unsigned long lcl_raddr,
3166                              unsigned long len,
3167                              unsigned long *actual_len);
3168 unsigned long sun4v_ldc_mapin(unsigned long channel,
3169                               unsigned long cookie,
3170                               unsigned long *ra,
3171                               unsigned long *perm);
3172 unsigned long sun4v_ldc_unmap(unsigned long ra);
3173 unsigned long sun4v_ldc_revoke(unsigned long channel,
3174                                unsigned long cookie,
3175                                unsigned long mte_cookie);
3176 #endif
3177 
3178 /* Performance counter services.  */
3179 
3180 #define HV_PERF_JBUS_PERF_CTRL_REG      0x00
3181 #define HV_PERF_JBUS_PERF_CNT_REG       0x01
3182 #define HV_PERF_DRAM_PERF_CTRL_REG_0    0x02
3183 #define HV_PERF_DRAM_PERF_CNT_REG_0     0x03
3184 #define HV_PERF_DRAM_PERF_CTRL_REG_1    0x04
3185 #define HV_PERF_DRAM_PERF_CNT_REG_1     0x05
3186 #define HV_PERF_DRAM_PERF_CTRL_REG_2    0x06
3187 #define HV_PERF_DRAM_PERF_CNT_REG_2     0x07
3188 #define HV_PERF_DRAM_PERF_CTRL_REG_3    0x08
3189 #define HV_PERF_DRAM_PERF_CNT_REG_3     0x09
3190 
3191 /* get_perfreg()
3192  * TRAP:        HV_FAST_TRAP
3193  * FUNCTION:    HV_FAST_GET_PERFREG
3194  * ARG0:        performance reg number
3195  * RET0:        status
3196  * RET1:        performance reg value
3197  * ERRORS:      EINVAL          Invalid performance register number
3198  *              ENOACCESS       No access allowed to performance counters
3199  *
3200  * Read the value of the given DRAM/JBUS performance counter/control register.
3201  */
3202 #define HV_FAST_GET_PERFREG             0x100
3203 
3204 /* set_perfreg()
3205  * TRAP:        HV_FAST_TRAP
3206  * FUNCTION:    HV_FAST_SET_PERFREG
3207  * ARG0:        performance reg number
3208  * ARG1:        performance reg value
3209  * RET0:        status
3210  * ERRORS:      EINVAL          Invalid performance register number
3211  *              ENOACCESS       No access allowed to performance counters
3212  *
3213  * Write the given performance reg value to the given DRAM/JBUS
3214  * performance counter/control register.
3215  */
3216 #define HV_FAST_SET_PERFREG             0x101
3217 
3218 #define HV_N2_PERF_SPARC_CTL            0x0
3219 #define HV_N2_PERF_DRAM_CTL0            0x1
3220 #define HV_N2_PERF_DRAM_CNT0            0x2
3221 #define HV_N2_PERF_DRAM_CTL1            0x3
3222 #define HV_N2_PERF_DRAM_CNT1            0x4
3223 #define HV_N2_PERF_DRAM_CTL2            0x5
3224 #define HV_N2_PERF_DRAM_CNT2            0x6
3225 #define HV_N2_PERF_DRAM_CTL3            0x7
3226 #define HV_N2_PERF_DRAM_CNT3            0x8
3227 
3228 #define HV_FAST_N2_GET_PERFREG          0x104
3229 #define HV_FAST_N2_SET_PERFREG          0x105
3230 
3231 #ifndef __ASSEMBLY__
3232 unsigned long sun4v_niagara_getperf(unsigned long reg,
3233                                     unsigned long *val);
3234 unsigned long sun4v_niagara_setperf(unsigned long reg,
3235                                     unsigned long val);
3236 unsigned long sun4v_niagara2_getperf(unsigned long reg,
3237                                      unsigned long *val);
3238 unsigned long sun4v_niagara2_setperf(unsigned long reg,
3239                                      unsigned long val);
3240 #endif
3241 
3242 /* MMU statistics services.
3243  *
3244  * The hypervisor maintains MMU statistics and privileged code provides
3245  * a buffer where these statistics can be collected.  It is continually
3246  * updated once configured.  The layout is as follows:
3247  */
3248 #ifndef __ASSEMBLY__
3249 struct hv_mmu_statistics {
3250         unsigned long immu_tsb_hits_ctx0_8k_tte;
3251         unsigned long immu_tsb_ticks_ctx0_8k_tte;
3252         unsigned long immu_tsb_hits_ctx0_64k_tte;
3253         unsigned long immu_tsb_ticks_ctx0_64k_tte;
3254         unsigned long __reserved1[2];
3255         unsigned long immu_tsb_hits_ctx0_4mb_tte;
3256         unsigned long immu_tsb_ticks_ctx0_4mb_tte;
3257         unsigned long __reserved2[2];
3258         unsigned long immu_tsb_hits_ctx0_256mb_tte;
3259         unsigned long immu_tsb_ticks_ctx0_256mb_tte;
3260         unsigned long __reserved3[4];
3261         unsigned long immu_tsb_hits_ctxnon0_8k_tte;
3262         unsigned long immu_tsb_ticks_ctxnon0_8k_tte;
3263         unsigned long immu_tsb_hits_ctxnon0_64k_tte;
3264         unsigned long immu_tsb_ticks_ctxnon0_64k_tte;
3265         unsigned long __reserved4[2];
3266         unsigned long immu_tsb_hits_ctxnon0_4mb_tte;
3267         unsigned long immu_tsb_ticks_ctxnon0_4mb_tte;
3268         unsigned long __reserved5[2];
3269         unsigned long immu_tsb_hits_ctxnon0_256mb_tte;
3270         unsigned long immu_tsb_ticks_ctxnon0_256mb_tte;
3271         unsigned long __reserved6[4];
3272         unsigned long dmmu_tsb_hits_ctx0_8k_tte;
3273         unsigned long dmmu_tsb_ticks_ctx0_8k_tte;
3274         unsigned long dmmu_tsb_hits_ctx0_64k_tte;
3275         unsigned long dmmu_tsb_ticks_ctx0_64k_tte;
3276         unsigned long __reserved7[2];
3277         unsigned long dmmu_tsb_hits_ctx0_4mb_tte;
3278         unsigned long dmmu_tsb_ticks_ctx0_4mb_tte;
3279         unsigned long __reserved8[2];
3280         unsigned long dmmu_tsb_hits_ctx0_256mb_tte;
3281         unsigned long dmmu_tsb_ticks_ctx0_256mb_tte;
3282         unsigned long __reserved9[4];
3283         unsigned long dmmu_tsb_hits_ctxnon0_8k_tte;
3284         unsigned long dmmu_tsb_ticks_ctxnon0_8k_tte;
3285         unsigned long dmmu_tsb_hits_ctxnon0_64k_tte;
3286         unsigned long dmmu_tsb_ticks_ctxnon0_64k_tte;
3287         unsigned long __reserved10[2];
3288         unsigned long dmmu_tsb_hits_ctxnon0_4mb_tte;
3289         unsigned long dmmu_tsb_ticks_ctxnon0_4mb_tte;
3290         unsigned long __reserved11[2];
3291         unsigned long dmmu_tsb_hits_ctxnon0_256mb_tte;
3292         unsigned long dmmu_tsb_ticks_ctxnon0_256mb_tte;
3293         unsigned long __reserved12[4];
3294 };
3295 #endif
3296 
3297 /* mmustat_conf()
3298  * TRAP:        HV_FAST_TRAP
3299  * FUNCTION:    HV_FAST_MMUSTAT_CONF
3300  * ARG0:        real address
3301  * RET0:        status
3302  * RET1:        real address
3303  * ERRORS:      ENORADDR        Invalid real address
3304  *              EBADALIGN       Real address not aligned on 64-byte boundary
3305  *              EBADTRAP        API not supported on this processor
3306  *
3307  * Enable MMU statistic gathering using the buffer at the given real
3308  * address on the current virtual CPU.  The new buffer real address
3309  * is given in ARG1, and the previously specified buffer real address
3310  * is returned in RET1, or is returned as zero for the first invocation.
3311  *
3312  * If the passed in real address argument is zero, this will disable
3313  * MMU statistic collection on the current virtual CPU.  If an error is
3314  * returned then no statistics are collected.
3315  *
3316  * The buffer contents should be initialized to all zeros before being
3317  * given to the hypervisor or else the statistics will be meaningless.
3318  */
3319 #define HV_FAST_MMUSTAT_CONF            0x102
3320 
3321 /* mmustat_info()
3322  * TRAP:        HV_FAST_TRAP
3323  * FUNCTION:    HV_FAST_MMUSTAT_INFO
3324  * RET0:        status
3325  * RET1:        real address
3326  * ERRORS:      EBADTRAP        API not supported on this processor
3327  *
3328  * Return the current state and real address of the currently configured
3329  * MMU statistics buffer on the current virtual CPU.
3330  */
3331 #define HV_FAST_MMUSTAT_INFO            0x103
3332 
3333 #ifndef __ASSEMBLY__
3334 unsigned long sun4v_mmustat_conf(unsigned long ra, unsigned long *orig_ra);
3335 unsigned long sun4v_mmustat_info(unsigned long *ra);
3336 #endif
3337 
3338 /* NCS crypto services  */
3339 
3340 /* ncs_request() sub-function numbers */
3341 #define HV_NCS_QCONF                    0x01
3342 #define HV_NCS_QTAIL_UPDATE             0x02
3343 
3344 #ifndef __ASSEMBLY__
3345 struct hv_ncs_queue_entry {
3346         /* MAU Control Register */
3347         unsigned long   mau_control;
3348 #define MAU_CONTROL_INV_PARITY  0x0000000000002000
3349 #define MAU_CONTROL_STRAND      0x0000000000001800
3350 #define MAU_CONTROL_BUSY        0x0000000000000400
3351 #define MAU_CONTROL_INT         0x0000000000000200
3352 #define MAU_CONTROL_OP          0x00000000000001c0
3353 #define MAU_CONTROL_OP_SHIFT    6
3354 #define MAU_OP_LOAD_MA_MEMORY   0x0
3355 #define MAU_OP_STORE_MA_MEMORY  0x1
3356 #define MAU_OP_MODULAR_MULT     0x2
3357 #define MAU_OP_MODULAR_REDUCE   0x3
3358 #define MAU_OP_MODULAR_EXP_LOOP 0x4
3359 #define MAU_CONTROL_LEN         0x000000000000003f
3360 #define MAU_CONTROL_LEN_SHIFT   0
3361 
3362         /* Real address of bytes to load or store bytes
3363          * into/out-of the MAU.
3364          */
3365         unsigned long   mau_mpa;
3366 
3367         /* Modular Arithmetic MA Offset Register.  */
3368         unsigned long   mau_ma;
3369 
3370         /* Modular Arithmetic N Prime Register.  */
3371         unsigned long   mau_np;
3372 };
3373 
3374 struct hv_ncs_qconf_arg {
3375         unsigned long   mid;      /* MAU ID, 1 per core on Niagara */
3376         unsigned long   base;     /* Real address base of queue */
3377         unsigned long   end;      /* Real address end of queue */
3378         unsigned long   num_ents; /* Number of entries in queue */
3379 };
3380 
3381 struct hv_ncs_qtail_update_arg {
3382         unsigned long   mid;      /* MAU ID, 1 per core on Niagara */
3383         unsigned long   tail;     /* New tail index to use */
3384         unsigned long   syncflag; /* only SYNCFLAG_SYNC is implemented */
3385 #define HV_NCS_SYNCFLAG_SYNC    0x00
3386 #define HV_NCS_SYNCFLAG_ASYNC   0x01
3387 };
3388 #endif
3389 
3390 /* ncs_request()
3391  * TRAP:        HV_FAST_TRAP
3392  * FUNCTION:    HV_FAST_NCS_REQUEST
3393  * ARG0:        NCS sub-function
3394  * ARG1:        sub-function argument real address
3395  * ARG2:        size in bytes of sub-function argument
3396  * RET0:        status
3397  *
3398  * The MAU chip of the Niagara processor is not directly accessible
3399  * to privileged code, instead it is programmed indirectly via this
3400  * hypervisor API.
3401  *
3402  * The interfaces defines a queue of MAU operations to perform.
3403  * Privileged code registers a queue with the hypervisor by invoking
3404  * this HVAPI with the HV_NCS_QCONF sub-function, which defines the
3405  * base, end, and number of entries of the queue.  Each queue entry
3406  * contains a MAU register struct block.
3407  *
3408  * The privileged code then proceeds to add entries to the queue and
3409  * then invoke the HV_NCS_QTAIL_UPDATE sub-function.  Since only
3410  * synchronous operations are supported by the current hypervisor,
3411  * HV_NCS_QTAIL_UPDATE will run all the pending queue entries to
3412  * completion and return HV_EOK, or return an error code.
3413  *
3414  * The real address of the sub-function argument must be aligned on at
3415  * least an 8-byte boundary.
3416  *
3417  * The tail argument of HV_NCS_QTAIL_UPDATE is an index, not a byte
3418  * offset, into the queue and must be less than or equal the 'num_ents'
3419  * argument given in the HV_NCS_QCONF call.
3420  */
3421 #define HV_FAST_NCS_REQUEST             0x110
3422 
3423 #ifndef __ASSEMBLY__
3424 unsigned long sun4v_ncs_request(unsigned long request,
3425                                 unsigned long arg_ra,
3426                                 unsigned long arg_size);
3427 #endif
3428 
3429 #define HV_FAST_FIRE_GET_PERFREG        0x120
3430 #define HV_FAST_FIRE_SET_PERFREG        0x121
3431 
3432 #define HV_FAST_REBOOT_DATA_SET         0x172
3433 
3434 #ifndef __ASSEMBLY__
3435 unsigned long sun4v_reboot_data_set(unsigned long ra,
3436                                     unsigned long len);
3437 #endif
3438 
3439 #define HV_FAST_VT_GET_PERFREG          0x184
3440 #define HV_FAST_VT_SET_PERFREG          0x185
3441 
3442 #ifndef __ASSEMBLY__
3443 unsigned long sun4v_vt_get_perfreg(unsigned long reg_num,
3444                                    unsigned long *reg_val);
3445 unsigned long sun4v_vt_set_perfreg(unsigned long reg_num,
3446                                    unsigned long reg_val);
3447 #endif
3448 
3449 #define HV_FAST_T5_GET_PERFREG          0x1a8
3450 #define HV_FAST_T5_SET_PERFREG          0x1a9
3451 
3452 #ifndef __ASSEMBLY__
3453 unsigned long sun4v_t5_get_perfreg(unsigned long reg_num,
3454                                    unsigned long *reg_val);
3455 unsigned long sun4v_t5_set_perfreg(unsigned long reg_num,
3456                                    unsigned long reg_val);
3457 #endif
3458 
3459 
3460 #define HV_FAST_M7_GET_PERFREG  0x43
3461 #define HV_FAST_M7_SET_PERFREG  0x44
3462 
3463 #ifndef __ASSEMBLY__
3464 unsigned long sun4v_m7_get_perfreg(unsigned long reg_num,
3465                                       unsigned long *reg_val);
3466 unsigned long sun4v_m7_set_perfreg(unsigned long reg_num,
3467                                       unsigned long reg_val);
3468 #endif
3469 
3470 /* Function numbers for HV_CORE_TRAP.  */
3471 #define HV_CORE_SET_VER                 0x00
3472 #define HV_CORE_PUTCHAR                 0x01
3473 #define HV_CORE_EXIT                    0x02
3474 #define HV_CORE_GET_VER                 0x03
3475 
3476 /* Hypervisor API groups for use with HV_CORE_SET_VER and
3477  * HV_CORE_GET_VER.
3478  */
3479 #define HV_GRP_SUN4V                    0x0000
3480 #define HV_GRP_CORE                     0x0001
3481 #define HV_GRP_INTR                     0x0002
3482 #define HV_GRP_SOFT_STATE               0x0003
3483 #define HV_GRP_TM                       0x0080
3484 #define HV_GRP_PCI                      0x0100
3485 #define HV_GRP_LDOM                     0x0101
3486 #define HV_GRP_SVC_CHAN                 0x0102
3487 #define HV_GRP_NCS                      0x0103
3488 #define HV_GRP_RNG                      0x0104
3489 #define HV_GRP_PBOOT                    0x0105
3490 #define HV_GRP_TPM                      0x0107
3491 #define HV_GRP_SDIO                     0x0108
3492 #define HV_GRP_SDIO_ERR                 0x0109
3493 #define HV_GRP_REBOOT_DATA              0x0110
3494 #define HV_GRP_ATU                      0x0111
3495 #define HV_GRP_DAX                      0x0113
3496 #define HV_GRP_M7_PERF                  0x0114
3497 #define HV_GRP_NIAG_PERF                0x0200
3498 #define HV_GRP_FIRE_PERF                0x0201
3499 #define HV_GRP_N2_CPU                   0x0202
3500 #define HV_GRP_NIU                      0x0204
3501 #define HV_GRP_VF_CPU                   0x0205
3502 #define HV_GRP_KT_CPU                   0x0209
3503 #define HV_GRP_VT_CPU                   0x020c
3504 #define HV_GRP_T5_CPU                   0x0211
3505 #define HV_GRP_DIAG                     0x0300
3506 
3507 #ifndef __ASSEMBLY__
3508 unsigned long sun4v_get_version(unsigned long group,
3509                                 unsigned long *major,
3510                                 unsigned long *minor);
3511 unsigned long sun4v_set_version(unsigned long group,
3512                                 unsigned long major,
3513                                 unsigned long minor,
3514                                 unsigned long *actual_minor);
3515 
3516 int sun4v_hvapi_register(unsigned long group, unsigned long major,
3517                          unsigned long *minor);
3518 void sun4v_hvapi_unregister(unsigned long group);
3519 int sun4v_hvapi_get(unsigned long group,
3520                     unsigned long *major,
3521                     unsigned long *minor);
3522 void sun4v_hvapi_init(void);
3523 #endif
3524 
3525 #endif /* !(_SPARC64_HYPERVISOR_H) */
3526 

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