1 #ifndef __SPARC64_IO_H
2 #define __SPARC64_IO_H
3
4 #include <linux/kernel.h>
5 #include <linux/compiler.h>
6 #include <linux/types.h>
7
8 #include <asm/page.h> /* IO address mapping routines need this */
9 #include <asm/asi.h>
10 #include <asm-generic/pci_iomap.h>
11
12 /* BIO layer definitions. */
13 extern unsigned long kern_base, kern_size;
14
15 /* __raw_{read,write}{b,w,l,q} uses direct access.
16 * Access the memory as big endian bypassing the cache
17 * by using ASI_PHYS_BYPASS_EC_E
18 */
19 #define __raw_readb __raw_readb
20 static inline u8 __raw_readb(const volatile void __iomem *addr)
21 {
22 u8 ret;
23
24 __asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_raw_readb */"
25 : "=r" (ret)
26 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
27
28 return ret;
29 }
30
31 #define __raw_readw __raw_readw
32 static inline u16 __raw_readw(const volatile void __iomem *addr)
33 {
34 u16 ret;
35
36 __asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_raw_readw */"
37 : "=r" (ret)
38 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
39
40 return ret;
41 }
42
43 #define __raw_readl __raw_readl
44 static inline u32 __raw_readl(const volatile void __iomem *addr)
45 {
46 u32 ret;
47
48 __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_raw_readl */"
49 : "=r" (ret)
50 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
51
52 return ret;
53 }
54
55 #define __raw_readq __raw_readq
56 static inline u64 __raw_readq(const volatile void __iomem *addr)
57 {
58 u64 ret;
59
60 __asm__ __volatile__("ldxa\t[%1] %2, %0\t/* pci_raw_readq */"
61 : "=r" (ret)
62 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
63
64 return ret;
65 }
66
67 #define __raw_writeb __raw_writeb
68 static inline void __raw_writeb(u8 b, const volatile void __iomem *addr)
69 {
70 __asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_raw_writeb */"
71 : /* no outputs */
72 : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
73 }
74
75 #define __raw_writew __raw_writew
76 static inline void __raw_writew(u16 w, const volatile void __iomem *addr)
77 {
78 __asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_raw_writew */"
79 : /* no outputs */
80 : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
81 }
82
83 #define __raw_writel __raw_writel
84 static inline void __raw_writel(u32 l, const volatile void __iomem *addr)
85 {
86 __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_raw_writel */"
87 : /* no outputs */
88 : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
89 }
90
91 #define __raw_writeq __raw_writeq
92 static inline void __raw_writeq(u64 q, const volatile void __iomem *addr)
93 {
94 __asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_raw_writeq */"
95 : /* no outputs */
96 : "Jr" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
97 }
98
99 /* Memory functions, same as I/O accesses on Ultra.
100 * Access memory as little endian bypassing
101 * the cache by using ASI_PHYS_BYPASS_EC_E_L
102 */
103 #define readb readb
104 #define readb_relaxed readb
105 static inline u8 readb(const volatile void __iomem *addr)
106 { u8 ret;
107
108 __asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_readb */"
109 : "=r" (ret)
110 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
111 : "memory");
112 return ret;
113 }
114
115 #define readw readw
116 #define readw_relaxed readw
117 static inline u16 readw(const volatile void __iomem *addr)
118 { u16 ret;
119
120 __asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_readw */"
121 : "=r" (ret)
122 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
123 : "memory");
124
125 return ret;
126 }
127
128 #define readl readl
129 #define readl_relaxed readl
130 static inline u32 readl(const volatile void __iomem *addr)
131 { u32 ret;
132
133 __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_readl */"
134 : "=r" (ret)
135 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
136 : "memory");
137
138 return ret;
139 }
140
141 #define readq readq
142 #define readq_relaxed readq
143 static inline u64 readq(const volatile void __iomem *addr)
144 { u64 ret;
145
146 __asm__ __volatile__("ldxa\t[%1] %2, %0\t/* pci_readq */"
147 : "=r" (ret)
148 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
149 : "memory");
150
151 return ret;
152 }
153
154 #define writeb writeb
155 #define writeb_relaxed writeb
156 static inline void writeb(u8 b, volatile void __iomem *addr)
157 {
158 __asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_writeb */"
159 : /* no outputs */
160 : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
161 : "memory");
162 }
163
164 #define writew writew
165 #define writew_relaxed writew
166 static inline void writew(u16 w, volatile void __iomem *addr)
167 {
168 __asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_writew */"
169 : /* no outputs */
170 : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
171 : "memory");
172 }
173
174 #define writel writel
175 #define writel_relaxed writel
176 static inline void writel(u32 l, volatile void __iomem *addr)
177 {
178 __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_writel */"
179 : /* no outputs */
180 : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
181 : "memory");
182 }
183
184 #define writeq writeq
185 #define writeq_relaxed writeq
186 static inline void writeq(u64 q, volatile void __iomem *addr)
187 {
188 __asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_writeq */"
189 : /* no outputs */
190 : "Jr" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
191 : "memory");
192 }
193
194 #define inb inb
195 static inline u8 inb(unsigned long addr)
196 {
197 return readb((volatile void __iomem *)addr);
198 }
199
200 #define inw inw
201 static inline u16 inw(unsigned long addr)
202 {
203 return readw((volatile void __iomem *)addr);
204 }
205
206 #define inl inl
207 static inline u32 inl(unsigned long addr)
208 {
209 return readl((volatile void __iomem *)addr);
210 }
211
212 #define outb outb
213 static inline void outb(u8 b, unsigned long addr)
214 {
215 writeb(b, (volatile void __iomem *)addr);
216 }
217
218 #define outw outw
219 static inline void outw(u16 w, unsigned long addr)
220 {
221 writew(w, (volatile void __iomem *)addr);
222 }
223
224 #define outl outl
225 static inline void outl(u32 l, unsigned long addr)
226 {
227 writel(l, (volatile void __iomem *)addr);
228 }
229
230
231 #define inb_p(__addr) inb(__addr)
232 #define outb_p(__b, __addr) outb(__b, __addr)
233 #define inw_p(__addr) inw(__addr)
234 #define outw_p(__w, __addr) outw(__w, __addr)
235 #define inl_p(__addr) inl(__addr)
236 #define outl_p(__l, __addr) outl(__l, __addr)
237
238 void outsb(unsigned long, const void *, unsigned long);
239 void outsw(unsigned long, const void *, unsigned long);
240 void outsl(unsigned long, const void *, unsigned long);
241 void insb(unsigned long, void *, unsigned long);
242 void insw(unsigned long, void *, unsigned long);
243 void insl(unsigned long, void *, unsigned long);
244
245 static inline void ioread8_rep(void __iomem *port, void *buf, unsigned long count)
246 {
247 insb((unsigned long __force)port, buf, count);
248 }
249 static inline void ioread16_rep(void __iomem *port, void *buf, unsigned long count)
250 {
251 insw((unsigned long __force)port, buf, count);
252 }
253
254 static inline void ioread32_rep(void __iomem *port, void *buf, unsigned long count)
255 {
256 insl((unsigned long __force)port, buf, count);
257 }
258
259 static inline void iowrite8_rep(void __iomem *port, const void *buf, unsigned long count)
260 {
261 outsb((unsigned long __force)port, buf, count);
262 }
263
264 static inline void iowrite16_rep(void __iomem *port, const void *buf, unsigned long count)
265 {
266 outsw((unsigned long __force)port, buf, count);
267 }
268
269 static inline void iowrite32_rep(void __iomem *port, const void *buf, unsigned long count)
270 {
271 outsl((unsigned long __force)port, buf, count);
272 }
273
274 /* Valid I/O Space regions are anywhere, because each PCI bus supported
275 * can live in an arbitrary area of the physical address range.
276 */
277 #define IO_SPACE_LIMIT 0xffffffffffffffffUL
278
279 /* Now, SBUS variants, only difference from PCI is that we do
280 * not use little-endian ASIs.
281 */
282 static inline u8 sbus_readb(const volatile void __iomem *addr)
283 {
284 return __raw_readb(addr);
285 }
286
287 static inline u16 sbus_readw(const volatile void __iomem *addr)
288 {
289 return __raw_readw(addr);
290 }
291
292 static inline u32 sbus_readl(const volatile void __iomem *addr)
293 {
294 return __raw_readl(addr);
295 }
296
297 static inline u64 sbus_readq(const volatile void __iomem *addr)
298 {
299 return __raw_readq(addr);
300 }
301
302 static inline void sbus_writeb(u8 b, volatile void __iomem *addr)
303 {
304 __raw_writeb(b, addr);
305 }
306
307 static inline void sbus_writew(u16 w, volatile void __iomem *addr)
308 {
309 __raw_writew(w, addr);
310 }
311
312 static inline void sbus_writel(u32 l, volatile void __iomem *addr)
313 {
314 __raw_writel(l, addr);
315 }
316
317 static inline void sbus_writeq(u64 q, volatile void __iomem *addr)
318 {
319 __raw_writeq(q, addr);
320 }
321
322 static inline void sbus_memset_io(volatile void __iomem *dst, int c, __kernel_size_t n)
323 {
324 while(n--) {
325 sbus_writeb(c, dst);
326 dst++;
327 }
328 }
329
330 static inline void memset_io(volatile void __iomem *dst, int c, __kernel_size_t n)
331 {
332 volatile void __iomem *d = dst;
333
334 while (n--) {
335 writeb(c, d);
336 d++;
337 }
338 }
339
340 static inline void sbus_memcpy_fromio(void *dst, const volatile void __iomem *src,
341 __kernel_size_t n)
342 {
343 char *d = dst;
344
345 while (n--) {
346 char tmp = sbus_readb(src);
347 *d++ = tmp;
348 src++;
349 }
350 }
351
352
353 static inline void memcpy_fromio(void *dst, const volatile void __iomem *src,
354 __kernel_size_t n)
355 {
356 char *d = dst;
357
358 while (n--) {
359 char tmp = readb(src);
360 *d++ = tmp;
361 src++;
362 }
363 }
364
365 static inline void sbus_memcpy_toio(volatile void __iomem *dst, const void *src,
366 __kernel_size_t n)
367 {
368 const char *s = src;
369 volatile void __iomem *d = dst;
370
371 while (n--) {
372 char tmp = *s++;
373 sbus_writeb(tmp, d);
374 d++;
375 }
376 }
377
378 static inline void memcpy_toio(volatile void __iomem *dst, const void *src,
379 __kernel_size_t n)
380 {
381 const char *s = src;
382 volatile void __iomem *d = dst;
383
384 while (n--) {
385 char tmp = *s++;
386 writeb(tmp, d);
387 d++;
388 }
389 }
390
391 #define mmiowb()
392
393 #ifdef __KERNEL__
394
395 /* On sparc64 we have the whole physical IO address space accessible
396 * using physically addressed loads and stores, so this does nothing.
397 */
398 static inline void __iomem *ioremap(unsigned long offset, unsigned long size)
399 {
400 return (void __iomem *)offset;
401 }
402
403 #define ioremap_nocache(X,Y) ioremap((X),(Y))
404 #define ioremap_wc(X,Y) ioremap((X),(Y))
405 #define ioremap_wt(X,Y) ioremap((X),(Y))
406
407 static inline void iounmap(volatile void __iomem *addr)
408 {
409 }
410
411 #define ioread8 readb
412 #define ioread16 readw
413 #define ioread16be __raw_readw
414 #define ioread32 readl
415 #define ioread32be __raw_readl
416 #define iowrite8 writeb
417 #define iowrite16 writew
418 #define iowrite16be __raw_writew
419 #define iowrite32 writel
420 #define iowrite32be __raw_writel
421
422 /* Create a virtual mapping cookie for an IO port range */
423 void __iomem *ioport_map(unsigned long port, unsigned int nr);
424 void ioport_unmap(void __iomem *);
425
426 /* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
427 struct pci_dev;
428 void pci_iounmap(struct pci_dev *dev, void __iomem *);
429
430 static inline int sbus_can_dma_64bit(void)
431 {
432 return 1;
433 }
434 static inline int sbus_can_burst64(void)
435 {
436 return 1;
437 }
438 struct device;
439 void sbus_set_sbus64(struct device *, int);
440
441 /*
442 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
443 * access
444 */
445 #define xlate_dev_mem_ptr(p) __va(p)
446
447 /*
448 * Convert a virtual cached pointer to an uncached pointer
449 */
450 #define xlate_dev_kmem_ptr(p) p
451
452 #endif
453
454 #endif /* !(__SPARC64_IO_H) */
455
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