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TOMOYO Linux Cross Reference
Linux/arch/sparc/kernel/perf_event.c

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Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 /* Performance event support for sparc64.
  2  *
  3  * Copyright (C) 2009, 2010 David S. Miller <davem@davemloft.net>
  4  *
  5  * This code is based almost entirely upon the x86 perf event
  6  * code, which is:
  7  *
  8  *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
  9  *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
 10  *  Copyright (C) 2009 Jaswinder Singh Rajput
 11  *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
 12  *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
 13  */
 14 
 15 #include <linux/perf_event.h>
 16 #include <linux/kprobes.h>
 17 #include <linux/ftrace.h>
 18 #include <linux/kernel.h>
 19 #include <linux/kdebug.h>
 20 #include <linux/mutex.h>
 21 
 22 #include <asm/stacktrace.h>
 23 #include <asm/cpudata.h>
 24 #include <asm/uaccess.h>
 25 #include <linux/atomic.h>
 26 #include <asm/nmi.h>
 27 #include <asm/pcr.h>
 28 #include <asm/cacheflush.h>
 29 
 30 #include "kernel.h"
 31 #include "kstack.h"
 32 
 33 /* Two classes of sparc64 chips currently exist.  All of which have
 34  * 32-bit counters which can generate overflow interrupts on the
 35  * transition from 0xffffffff to 0.
 36  *
 37  * All chips upto and including SPARC-T3 have two performance
 38  * counters.  The two 32-bit counters are accessed in one go using a
 39  * single 64-bit register.
 40  *
 41  * On these older chips both counters are controlled using a single
 42  * control register.  The only way to stop all sampling is to clear
 43  * all of the context (user, supervisor, hypervisor) sampling enable
 44  * bits.  But these bits apply to both counters, thus the two counters
 45  * can't be enabled/disabled individually.
 46  *
 47  * Furthermore, the control register on these older chips have two
 48  * event fields, one for each of the two counters.  It's thus nearly
 49  * impossible to have one counter going while keeping the other one
 50  * stopped.  Therefore it is possible to get overflow interrupts for
 51  * counters not currently "in use" and that condition must be checked
 52  * in the overflow interrupt handler.
 53  *
 54  * So we use a hack, in that we program inactive counters with the
 55  * "sw_count0" and "sw_count1" events.  These count how many times
 56  * the instruction "sethi %hi(0xfc000), %g0" is executed.  It's an
 57  * unusual way to encode a NOP and therefore will not trigger in
 58  * normal code.
 59  *
 60  * Starting with SPARC-T4 we have one control register per counter.
 61  * And the counters are stored in individual registers.  The registers
 62  * for the counters are 64-bit but only a 32-bit counter is
 63  * implemented.  The event selections on SPARC-T4 lack any
 64  * restrictions, therefore we can elide all of the complicated
 65  * conflict resolution code we have for SPARC-T3 and earlier chips.
 66  */
 67 
 68 #define MAX_HWEVENTS                    4
 69 #define MAX_PCRS                        4
 70 #define MAX_PERIOD                      ((1UL << 32) - 1)
 71 
 72 #define PIC_UPPER_INDEX                 0
 73 #define PIC_LOWER_INDEX                 1
 74 #define PIC_NO_INDEX                    -1
 75 
 76 struct cpu_hw_events {
 77         /* Number of events currently scheduled onto this cpu.
 78          * This tells how many entries in the arrays below
 79          * are valid.
 80          */
 81         int                     n_events;
 82 
 83         /* Number of new events added since the last hw_perf_disable().
 84          * This works because the perf event layer always adds new
 85          * events inside of a perf_{disable,enable}() sequence.
 86          */
 87         int                     n_added;
 88 
 89         /* Array of events current scheduled on this cpu.  */
 90         struct perf_event       *event[MAX_HWEVENTS];
 91 
 92         /* Array of encoded longs, specifying the %pcr register
 93          * encoding and the mask of PIC counters this even can
 94          * be scheduled on.  See perf_event_encode() et al.
 95          */
 96         unsigned long           events[MAX_HWEVENTS];
 97 
 98         /* The current counter index assigned to an event.  When the
 99          * event hasn't been programmed into the cpu yet, this will
100          * hold PIC_NO_INDEX.  The event->hw.idx value tells us where
101          * we ought to schedule the event.
102          */
103         int                     current_idx[MAX_HWEVENTS];
104 
105         /* Software copy of %pcr register(s) on this cpu.  */
106         u64                     pcr[MAX_HWEVENTS];
107 
108         /* Enabled/disable state.  */
109         int                     enabled;
110 
111         unsigned int            group_flag;
112 };
113 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { .enabled = 1, };
114 
115 /* An event map describes the characteristics of a performance
116  * counter event.  In particular it gives the encoding as well as
117  * a mask telling which counters the event can be measured on.
118  *
119  * The mask is unused on SPARC-T4 and later.
120  */
121 struct perf_event_map {
122         u16     encoding;
123         u8      pic_mask;
124 #define PIC_NONE        0x00
125 #define PIC_UPPER       0x01
126 #define PIC_LOWER       0x02
127 };
128 
129 /* Encode a perf_event_map entry into a long.  */
130 static unsigned long perf_event_encode(const struct perf_event_map *pmap)
131 {
132         return ((unsigned long) pmap->encoding << 16) | pmap->pic_mask;
133 }
134 
135 static u8 perf_event_get_msk(unsigned long val)
136 {
137         return val & 0xff;
138 }
139 
140 static u64 perf_event_get_enc(unsigned long val)
141 {
142         return val >> 16;
143 }
144 
145 #define C(x) PERF_COUNT_HW_CACHE_##x
146 
147 #define CACHE_OP_UNSUPPORTED    0xfffe
148 #define CACHE_OP_NONSENSE       0xffff
149 
150 typedef struct perf_event_map cache_map_t
151                                 [PERF_COUNT_HW_CACHE_MAX]
152                                 [PERF_COUNT_HW_CACHE_OP_MAX]
153                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
154 
155 struct sparc_pmu {
156         const struct perf_event_map     *(*event_map)(int);
157         const cache_map_t               *cache_map;
158         int                             max_events;
159         u32                             (*read_pmc)(int);
160         void                            (*write_pmc)(int, u64);
161         int                             upper_shift;
162         int                             lower_shift;
163         int                             event_mask;
164         int                             user_bit;
165         int                             priv_bit;
166         int                             hv_bit;
167         int                             irq_bit;
168         int                             upper_nop;
169         int                             lower_nop;
170         unsigned int                    flags;
171 #define SPARC_PMU_ALL_EXCLUDES_SAME     0x00000001
172 #define SPARC_PMU_HAS_CONFLICTS         0x00000002
173         int                             max_hw_events;
174         int                             num_pcrs;
175         int                             num_pic_regs;
176 };
177 
178 static u32 sparc_default_read_pmc(int idx)
179 {
180         u64 val;
181 
182         val = pcr_ops->read_pic(0);
183         if (idx == PIC_UPPER_INDEX)
184                 val >>= 32;
185 
186         return val & 0xffffffff;
187 }
188 
189 static void sparc_default_write_pmc(int idx, u64 val)
190 {
191         u64 shift, mask, pic;
192 
193         shift = 0;
194         if (idx == PIC_UPPER_INDEX)
195                 shift = 32;
196 
197         mask = ((u64) 0xffffffff) << shift;
198         val <<= shift;
199 
200         pic = pcr_ops->read_pic(0);
201         pic &= ~mask;
202         pic |= val;
203         pcr_ops->write_pic(0, pic);
204 }
205 
206 static const struct perf_event_map ultra3_perfmon_event_map[] = {
207         [PERF_COUNT_HW_CPU_CYCLES] = { 0x0000, PIC_UPPER | PIC_LOWER },
208         [PERF_COUNT_HW_INSTRUCTIONS] = { 0x0001, PIC_UPPER | PIC_LOWER },
209         [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x0009, PIC_LOWER },
210         [PERF_COUNT_HW_CACHE_MISSES] = { 0x0009, PIC_UPPER },
211 };
212 
213 static const struct perf_event_map *ultra3_event_map(int event_id)
214 {
215         return &ultra3_perfmon_event_map[event_id];
216 }
217 
218 static const cache_map_t ultra3_cache_map = {
219 [C(L1D)] = {
220         [C(OP_READ)] = {
221                 [C(RESULT_ACCESS)] = { 0x09, PIC_LOWER, },
222                 [C(RESULT_MISS)] = { 0x09, PIC_UPPER, },
223         },
224         [C(OP_WRITE)] = {
225                 [C(RESULT_ACCESS)] = { 0x0a, PIC_LOWER },
226                 [C(RESULT_MISS)] = { 0x0a, PIC_UPPER },
227         },
228         [C(OP_PREFETCH)] = {
229                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
230                 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
231         },
232 },
233 [C(L1I)] = {
234         [C(OP_READ)] = {
235                 [C(RESULT_ACCESS)] = { 0x09, PIC_LOWER, },
236                 [C(RESULT_MISS)] = { 0x09, PIC_UPPER, },
237         },
238         [ C(OP_WRITE) ] = {
239                 [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE },
240                 [ C(RESULT_MISS)   ] = { CACHE_OP_NONSENSE },
241         },
242         [ C(OP_PREFETCH) ] = {
243                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
244                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
245         },
246 },
247 [C(LL)] = {
248         [C(OP_READ)] = {
249                 [C(RESULT_ACCESS)] = { 0x0c, PIC_LOWER, },
250                 [C(RESULT_MISS)] = { 0x0c, PIC_UPPER, },
251         },
252         [C(OP_WRITE)] = {
253                 [C(RESULT_ACCESS)] = { 0x0c, PIC_LOWER },
254                 [C(RESULT_MISS)] = { 0x0c, PIC_UPPER },
255         },
256         [C(OP_PREFETCH)] = {
257                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
258                 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
259         },
260 },
261 [C(DTLB)] = {
262         [C(OP_READ)] = {
263                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
264                 [C(RESULT_MISS)] = { 0x12, PIC_UPPER, },
265         },
266         [ C(OP_WRITE) ] = {
267                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
268                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
269         },
270         [ C(OP_PREFETCH) ] = {
271                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
272                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
273         },
274 },
275 [C(ITLB)] = {
276         [C(OP_READ)] = {
277                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
278                 [C(RESULT_MISS)] = { 0x11, PIC_UPPER, },
279         },
280         [ C(OP_WRITE) ] = {
281                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
282                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
283         },
284         [ C(OP_PREFETCH) ] = {
285                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
286                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
287         },
288 },
289 [C(BPU)] = {
290         [C(OP_READ)] = {
291                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
292                 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
293         },
294         [ C(OP_WRITE) ] = {
295                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
296                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
297         },
298         [ C(OP_PREFETCH) ] = {
299                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
300                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
301         },
302 },
303 [C(NODE)] = {
304         [C(OP_READ)] = {
305                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
306                 [C(RESULT_MISS)  ] = { CACHE_OP_UNSUPPORTED },
307         },
308         [ C(OP_WRITE) ] = {
309                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
310                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
311         },
312         [ C(OP_PREFETCH) ] = {
313                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
314                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
315         },
316 },
317 };
318 
319 static const struct sparc_pmu ultra3_pmu = {
320         .event_map      = ultra3_event_map,
321         .cache_map      = &ultra3_cache_map,
322         .max_events     = ARRAY_SIZE(ultra3_perfmon_event_map),
323         .read_pmc       = sparc_default_read_pmc,
324         .write_pmc      = sparc_default_write_pmc,
325         .upper_shift    = 11,
326         .lower_shift    = 4,
327         .event_mask     = 0x3f,
328         .user_bit       = PCR_UTRACE,
329         .priv_bit       = PCR_STRACE,
330         .upper_nop      = 0x1c,
331         .lower_nop      = 0x14,
332         .flags          = (SPARC_PMU_ALL_EXCLUDES_SAME |
333                            SPARC_PMU_HAS_CONFLICTS),
334         .max_hw_events  = 2,
335         .num_pcrs       = 1,
336         .num_pic_regs   = 1,
337 };
338 
339 /* Niagara1 is very limited.  The upper PIC is hard-locked to count
340  * only instructions, so it is free running which creates all kinds of
341  * problems.  Some hardware designs make one wonder if the creator
342  * even looked at how this stuff gets used by software.
343  */
344 static const struct perf_event_map niagara1_perfmon_event_map[] = {
345         [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, PIC_UPPER },
346         [PERF_COUNT_HW_INSTRUCTIONS] = { 0x00, PIC_UPPER },
347         [PERF_COUNT_HW_CACHE_REFERENCES] = { 0, PIC_NONE },
348         [PERF_COUNT_HW_CACHE_MISSES] = { 0x03, PIC_LOWER },
349 };
350 
351 static const struct perf_event_map *niagara1_event_map(int event_id)
352 {
353         return &niagara1_perfmon_event_map[event_id];
354 }
355 
356 static const cache_map_t niagara1_cache_map = {
357 [C(L1D)] = {
358         [C(OP_READ)] = {
359                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
360                 [C(RESULT_MISS)] = { 0x03, PIC_LOWER, },
361         },
362         [C(OP_WRITE)] = {
363                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
364                 [C(RESULT_MISS)] = { 0x03, PIC_LOWER, },
365         },
366         [C(OP_PREFETCH)] = {
367                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
368                 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
369         },
370 },
371 [C(L1I)] = {
372         [C(OP_READ)] = {
373                 [C(RESULT_ACCESS)] = { 0x00, PIC_UPPER },
374                 [C(RESULT_MISS)] = { 0x02, PIC_LOWER, },
375         },
376         [ C(OP_WRITE) ] = {
377                 [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE },
378                 [ C(RESULT_MISS)   ] = { CACHE_OP_NONSENSE },
379         },
380         [ C(OP_PREFETCH) ] = {
381                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
382                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
383         },
384 },
385 [C(LL)] = {
386         [C(OP_READ)] = {
387                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
388                 [C(RESULT_MISS)] = { 0x07, PIC_LOWER, },
389         },
390         [C(OP_WRITE)] = {
391                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
392                 [C(RESULT_MISS)] = { 0x07, PIC_LOWER, },
393         },
394         [C(OP_PREFETCH)] = {
395                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
396                 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
397         },
398 },
399 [C(DTLB)] = {
400         [C(OP_READ)] = {
401                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
402                 [C(RESULT_MISS)] = { 0x05, PIC_LOWER, },
403         },
404         [ C(OP_WRITE) ] = {
405                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
406                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
407         },
408         [ C(OP_PREFETCH) ] = {
409                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
410                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
411         },
412 },
413 [C(ITLB)] = {
414         [C(OP_READ)] = {
415                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
416                 [C(RESULT_MISS)] = { 0x04, PIC_LOWER, },
417         },
418         [ C(OP_WRITE) ] = {
419                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
420                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
421         },
422         [ C(OP_PREFETCH) ] = {
423                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
424                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
425         },
426 },
427 [C(BPU)] = {
428         [C(OP_READ)] = {
429                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
430                 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
431         },
432         [ C(OP_WRITE) ] = {
433                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
434                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
435         },
436         [ C(OP_PREFETCH) ] = {
437                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
438                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
439         },
440 },
441 [C(NODE)] = {
442         [C(OP_READ)] = {
443                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
444                 [C(RESULT_MISS)  ] = { CACHE_OP_UNSUPPORTED },
445         },
446         [ C(OP_WRITE) ] = {
447                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
448                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
449         },
450         [ C(OP_PREFETCH) ] = {
451                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
452                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
453         },
454 },
455 };
456 
457 static const struct sparc_pmu niagara1_pmu = {
458         .event_map      = niagara1_event_map,
459         .cache_map      = &niagara1_cache_map,
460         .max_events     = ARRAY_SIZE(niagara1_perfmon_event_map),
461         .read_pmc       = sparc_default_read_pmc,
462         .write_pmc      = sparc_default_write_pmc,
463         .upper_shift    = 0,
464         .lower_shift    = 4,
465         .event_mask     = 0x7,
466         .user_bit       = PCR_UTRACE,
467         .priv_bit       = PCR_STRACE,
468         .upper_nop      = 0x0,
469         .lower_nop      = 0x0,
470         .flags          = (SPARC_PMU_ALL_EXCLUDES_SAME |
471                            SPARC_PMU_HAS_CONFLICTS),
472         .max_hw_events  = 2,
473         .num_pcrs       = 1,
474         .num_pic_regs   = 1,
475 };
476 
477 static const struct perf_event_map niagara2_perfmon_event_map[] = {
478         [PERF_COUNT_HW_CPU_CYCLES] = { 0x02ff, PIC_UPPER | PIC_LOWER },
479         [PERF_COUNT_HW_INSTRUCTIONS] = { 0x02ff, PIC_UPPER | PIC_LOWER },
480         [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x0208, PIC_UPPER | PIC_LOWER },
481         [PERF_COUNT_HW_CACHE_MISSES] = { 0x0302, PIC_UPPER | PIC_LOWER },
482         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x0201, PIC_UPPER | PIC_LOWER },
483         [PERF_COUNT_HW_BRANCH_MISSES] = { 0x0202, PIC_UPPER | PIC_LOWER },
484 };
485 
486 static const struct perf_event_map *niagara2_event_map(int event_id)
487 {
488         return &niagara2_perfmon_event_map[event_id];
489 }
490 
491 static const cache_map_t niagara2_cache_map = {
492 [C(L1D)] = {
493         [C(OP_READ)] = {
494                 [C(RESULT_ACCESS)] = { 0x0208, PIC_UPPER | PIC_LOWER, },
495                 [C(RESULT_MISS)] = { 0x0302, PIC_UPPER | PIC_LOWER, },
496         },
497         [C(OP_WRITE)] = {
498                 [C(RESULT_ACCESS)] = { 0x0210, PIC_UPPER | PIC_LOWER, },
499                 [C(RESULT_MISS)] = { 0x0302, PIC_UPPER | PIC_LOWER, },
500         },
501         [C(OP_PREFETCH)] = {
502                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
503                 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
504         },
505 },
506 [C(L1I)] = {
507         [C(OP_READ)] = {
508                 [C(RESULT_ACCESS)] = { 0x02ff, PIC_UPPER | PIC_LOWER, },
509                 [C(RESULT_MISS)] = { 0x0301, PIC_UPPER | PIC_LOWER, },
510         },
511         [ C(OP_WRITE) ] = {
512                 [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE },
513                 [ C(RESULT_MISS)   ] = { CACHE_OP_NONSENSE },
514         },
515         [ C(OP_PREFETCH) ] = {
516                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
517                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
518         },
519 },
520 [C(LL)] = {
521         [C(OP_READ)] = {
522                 [C(RESULT_ACCESS)] = { 0x0208, PIC_UPPER | PIC_LOWER, },
523                 [C(RESULT_MISS)] = { 0x0330, PIC_UPPER | PIC_LOWER, },
524         },
525         [C(OP_WRITE)] = {
526                 [C(RESULT_ACCESS)] = { 0x0210, PIC_UPPER | PIC_LOWER, },
527                 [C(RESULT_MISS)] = { 0x0320, PIC_UPPER | PIC_LOWER, },
528         },
529         [C(OP_PREFETCH)] = {
530                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
531                 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
532         },
533 },
534 [C(DTLB)] = {
535         [C(OP_READ)] = {
536                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
537                 [C(RESULT_MISS)] = { 0x0b08, PIC_UPPER | PIC_LOWER, },
538         },
539         [ C(OP_WRITE) ] = {
540                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
541                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
542         },
543         [ C(OP_PREFETCH) ] = {
544                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
545                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
546         },
547 },
548 [C(ITLB)] = {
549         [C(OP_READ)] = {
550                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
551                 [C(RESULT_MISS)] = { 0xb04, PIC_UPPER | PIC_LOWER, },
552         },
553         [ C(OP_WRITE) ] = {
554                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
555                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
556         },
557         [ C(OP_PREFETCH) ] = {
558                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
559                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
560         },
561 },
562 [C(BPU)] = {
563         [C(OP_READ)] = {
564                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
565                 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
566         },
567         [ C(OP_WRITE) ] = {
568                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
569                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
570         },
571         [ C(OP_PREFETCH) ] = {
572                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
573                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
574         },
575 },
576 [C(NODE)] = {
577         [C(OP_READ)] = {
578                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
579                 [C(RESULT_MISS)  ] = { CACHE_OP_UNSUPPORTED },
580         },
581         [ C(OP_WRITE) ] = {
582                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
583                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
584         },
585         [ C(OP_PREFETCH) ] = {
586                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
587                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
588         },
589 },
590 };
591 
592 static const struct sparc_pmu niagara2_pmu = {
593         .event_map      = niagara2_event_map,
594         .cache_map      = &niagara2_cache_map,
595         .max_events     = ARRAY_SIZE(niagara2_perfmon_event_map),
596         .read_pmc       = sparc_default_read_pmc,
597         .write_pmc      = sparc_default_write_pmc,
598         .upper_shift    = 19,
599         .lower_shift    = 6,
600         .event_mask     = 0xfff,
601         .user_bit       = PCR_UTRACE,
602         .priv_bit       = PCR_STRACE,
603         .hv_bit         = PCR_N2_HTRACE,
604         .irq_bit        = 0x30,
605         .upper_nop      = 0x220,
606         .lower_nop      = 0x220,
607         .flags          = (SPARC_PMU_ALL_EXCLUDES_SAME |
608                            SPARC_PMU_HAS_CONFLICTS),
609         .max_hw_events  = 2,
610         .num_pcrs       = 1,
611         .num_pic_regs   = 1,
612 };
613 
614 static const struct perf_event_map niagara4_perfmon_event_map[] = {
615         [PERF_COUNT_HW_CPU_CYCLES] = { (26 << 6) },
616         [PERF_COUNT_HW_INSTRUCTIONS] = { (3 << 6) | 0x3f },
617         [PERF_COUNT_HW_CACHE_REFERENCES] = { (3 << 6) | 0x04 },
618         [PERF_COUNT_HW_CACHE_MISSES] = { (16 << 6) | 0x07 },
619         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { (4 << 6) | 0x01 },
620         [PERF_COUNT_HW_BRANCH_MISSES] = { (25 << 6) | 0x0f },
621 };
622 
623 static const struct perf_event_map *niagara4_event_map(int event_id)
624 {
625         return &niagara4_perfmon_event_map[event_id];
626 }
627 
628 static const cache_map_t niagara4_cache_map = {
629 [C(L1D)] = {
630         [C(OP_READ)] = {
631                 [C(RESULT_ACCESS)] = { (3 << 6) | 0x04 },
632                 [C(RESULT_MISS)] = { (16 << 6) | 0x07 },
633         },
634         [C(OP_WRITE)] = {
635                 [C(RESULT_ACCESS)] = { (3 << 6) | 0x08 },
636                 [C(RESULT_MISS)] = { (16 << 6) | 0x07 },
637         },
638         [C(OP_PREFETCH)] = {
639                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
640                 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
641         },
642 },
643 [C(L1I)] = {
644         [C(OP_READ)] = {
645                 [C(RESULT_ACCESS)] = { (3 << 6) | 0x3f },
646                 [C(RESULT_MISS)] = { (11 << 6) | 0x03 },
647         },
648         [ C(OP_WRITE) ] = {
649                 [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE },
650                 [ C(RESULT_MISS)   ] = { CACHE_OP_NONSENSE },
651         },
652         [ C(OP_PREFETCH) ] = {
653                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
654                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
655         },
656 },
657 [C(LL)] = {
658         [C(OP_READ)] = {
659                 [C(RESULT_ACCESS)] = { (3 << 6) | 0x04 },
660                 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
661         },
662         [C(OP_WRITE)] = {
663                 [C(RESULT_ACCESS)] = { (3 << 6) | 0x08 },
664                 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
665         },
666         [C(OP_PREFETCH)] = {
667                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
668                 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
669         },
670 },
671 [C(DTLB)] = {
672         [C(OP_READ)] = {
673                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
674                 [C(RESULT_MISS)] = { (17 << 6) | 0x3f },
675         },
676         [ C(OP_WRITE) ] = {
677                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
678                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
679         },
680         [ C(OP_PREFETCH) ] = {
681                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
682                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
683         },
684 },
685 [C(ITLB)] = {
686         [C(OP_READ)] = {
687                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
688                 [C(RESULT_MISS)] = { (6 << 6) | 0x3f },
689         },
690         [ C(OP_WRITE) ] = {
691                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
692                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
693         },
694         [ C(OP_PREFETCH) ] = {
695                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
696                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
697         },
698 },
699 [C(BPU)] = {
700         [C(OP_READ)] = {
701                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
702                 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
703         },
704         [ C(OP_WRITE) ] = {
705                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
706                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
707         },
708         [ C(OP_PREFETCH) ] = {
709                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
710                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
711         },
712 },
713 [C(NODE)] = {
714         [C(OP_READ)] = {
715                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
716                 [C(RESULT_MISS)  ] = { CACHE_OP_UNSUPPORTED },
717         },
718         [ C(OP_WRITE) ] = {
719                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
720                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
721         },
722         [ C(OP_PREFETCH) ] = {
723                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
724                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
725         },
726 },
727 };
728 
729 static u32 sparc_vt_read_pmc(int idx)
730 {
731         u64 val = pcr_ops->read_pic(idx);
732 
733         return val & 0xffffffff;
734 }
735 
736 static void sparc_vt_write_pmc(int idx, u64 val)
737 {
738         u64 pcr;
739 
740         /* There seems to be an internal latch on the overflow event
741          * on SPARC-T4 that prevents it from triggering unless you
742          * update the PIC exactly as we do here.  The requirement
743          * seems to be that you have to turn off event counting in the
744          * PCR around the PIC update.
745          *
746          * For example, after the following sequence:
747          *
748          * 1) set PIC to -1
749          * 2) enable event counting and overflow reporting in PCR
750          * 3) overflow triggers, softint 15 handler invoked
751          * 4) clear OV bit in PCR
752          * 5) write PIC to -1
753          *
754          * a subsequent overflow event will not trigger.  This
755          * sequence works on SPARC-T3 and previous chips.
756          */
757         pcr = pcr_ops->read_pcr(idx);
758         pcr_ops->write_pcr(idx, PCR_N4_PICNPT);
759 
760         pcr_ops->write_pic(idx, val & 0xffffffff);
761 
762         pcr_ops->write_pcr(idx, pcr);
763 }
764 
765 static const struct sparc_pmu niagara4_pmu = {
766         .event_map      = niagara4_event_map,
767         .cache_map      = &niagara4_cache_map,
768         .max_events     = ARRAY_SIZE(niagara4_perfmon_event_map),
769         .read_pmc       = sparc_vt_read_pmc,
770         .write_pmc      = sparc_vt_write_pmc,
771         .upper_shift    = 5,
772         .lower_shift    = 5,
773         .event_mask     = 0x7ff,
774         .user_bit       = PCR_N4_UTRACE,
775         .priv_bit       = PCR_N4_STRACE,
776 
777         /* We explicitly don't support hypervisor tracing.  The T4
778          * generates the overflow event for precise events via a trap
779          * which will not be generated (ie. it's completely lost) if
780          * we happen to be in the hypervisor when the event triggers.
781          * Essentially, the overflow event reporting is completely
782          * unusable when you have hypervisor mode tracing enabled.
783          */
784         .hv_bit         = 0,
785 
786         .irq_bit        = PCR_N4_TOE,
787         .upper_nop      = 0,
788         .lower_nop      = 0,
789         .flags          = 0,
790         .max_hw_events  = 4,
791         .num_pcrs       = 4,
792         .num_pic_regs   = 4,
793 };
794 
795 static void sparc_m7_write_pmc(int idx, u64 val)
796 {
797         u64 pcr;
798 
799         pcr = pcr_ops->read_pcr(idx);
800         /* ensure ov and ntc are reset */
801         pcr &= ~(PCR_N4_OV | PCR_N4_NTC);
802 
803         pcr_ops->write_pic(idx, val & 0xffffffff);
804 
805         pcr_ops->write_pcr(idx, pcr);
806 }
807 
808 static const struct sparc_pmu sparc_m7_pmu = {
809         .event_map      = niagara4_event_map,
810         .cache_map      = &niagara4_cache_map,
811         .max_events     = ARRAY_SIZE(niagara4_perfmon_event_map),
812         .read_pmc       = sparc_vt_read_pmc,
813         .write_pmc      = sparc_m7_write_pmc,
814         .upper_shift    = 5,
815         .lower_shift    = 5,
816         .event_mask     = 0x7ff,
817         .user_bit       = PCR_N4_UTRACE,
818         .priv_bit       = PCR_N4_STRACE,
819 
820         /* We explicitly don't support hypervisor tracing. */
821         .hv_bit         = 0,
822 
823         .irq_bit        = PCR_N4_TOE,
824         .upper_nop      = 0,
825         .lower_nop      = 0,
826         .flags          = 0,
827         .max_hw_events  = 4,
828         .num_pcrs       = 4,
829         .num_pic_regs   = 4,
830 };
831 static const struct sparc_pmu *sparc_pmu __read_mostly;
832 
833 static u64 event_encoding(u64 event_id, int idx)
834 {
835         if (idx == PIC_UPPER_INDEX)
836                 event_id <<= sparc_pmu->upper_shift;
837         else
838                 event_id <<= sparc_pmu->lower_shift;
839         return event_id;
840 }
841 
842 static u64 mask_for_index(int idx)
843 {
844         return event_encoding(sparc_pmu->event_mask, idx);
845 }
846 
847 static u64 nop_for_index(int idx)
848 {
849         return event_encoding(idx == PIC_UPPER_INDEX ?
850                               sparc_pmu->upper_nop :
851                               sparc_pmu->lower_nop, idx);
852 }
853 
854 static inline void sparc_pmu_enable_event(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc, int idx)
855 {
856         u64 enc, val, mask = mask_for_index(idx);
857         int pcr_index = 0;
858 
859         if (sparc_pmu->num_pcrs > 1)
860                 pcr_index = idx;
861 
862         enc = perf_event_get_enc(cpuc->events[idx]);
863 
864         val = cpuc->pcr[pcr_index];
865         val &= ~mask;
866         val |= event_encoding(enc, idx);
867         cpuc->pcr[pcr_index] = val;
868 
869         pcr_ops->write_pcr(pcr_index, cpuc->pcr[pcr_index]);
870 }
871 
872 static inline void sparc_pmu_disable_event(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc, int idx)
873 {
874         u64 mask = mask_for_index(idx);
875         u64 nop = nop_for_index(idx);
876         int pcr_index = 0;
877         u64 val;
878 
879         if (sparc_pmu->num_pcrs > 1)
880                 pcr_index = idx;
881 
882         val = cpuc->pcr[pcr_index];
883         val &= ~mask;
884         val |= nop;
885         cpuc->pcr[pcr_index] = val;
886 
887         pcr_ops->write_pcr(pcr_index, cpuc->pcr[pcr_index]);
888 }
889 
890 static u64 sparc_perf_event_update(struct perf_event *event,
891                                    struct hw_perf_event *hwc, int idx)
892 {
893         int shift = 64 - 32;
894         u64 prev_raw_count, new_raw_count;
895         s64 delta;
896 
897 again:
898         prev_raw_count = local64_read(&hwc->prev_count);
899         new_raw_count = sparc_pmu->read_pmc(idx);
900 
901         if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
902                              new_raw_count) != prev_raw_count)
903                 goto again;
904 
905         delta = (new_raw_count << shift) - (prev_raw_count << shift);
906         delta >>= shift;
907 
908         local64_add(delta, &event->count);
909         local64_sub(delta, &hwc->period_left);
910 
911         return new_raw_count;
912 }
913 
914 static int sparc_perf_event_set_period(struct perf_event *event,
915                                        struct hw_perf_event *hwc, int idx)
916 {
917         s64 left = local64_read(&hwc->period_left);
918         s64 period = hwc->sample_period;
919         int ret = 0;
920 
921         if (unlikely(left <= -period)) {
922                 left = period;
923                 local64_set(&hwc->period_left, left);
924                 hwc->last_period = period;
925                 ret = 1;
926         }
927 
928         if (unlikely(left <= 0)) {
929                 left += period;
930                 local64_set(&hwc->period_left, left);
931                 hwc->last_period = period;
932                 ret = 1;
933         }
934         if (left > MAX_PERIOD)
935                 left = MAX_PERIOD;
936 
937         local64_set(&hwc->prev_count, (u64)-left);
938 
939         sparc_pmu->write_pmc(idx, (u64)(-left) & 0xffffffff);
940 
941         perf_event_update_userpage(event);
942 
943         return ret;
944 }
945 
946 static void read_in_all_counters(struct cpu_hw_events *cpuc)
947 {
948         int i;
949 
950         for (i = 0; i < cpuc->n_events; i++) {
951                 struct perf_event *cp = cpuc->event[i];
952 
953                 if (cpuc->current_idx[i] != PIC_NO_INDEX &&
954                     cpuc->current_idx[i] != cp->hw.idx) {
955                         sparc_perf_event_update(cp, &cp->hw,
956                                                 cpuc->current_idx[i]);
957                         cpuc->current_idx[i] = PIC_NO_INDEX;
958                 }
959         }
960 }
961 
962 /* On this PMU all PICs are programmed using a single PCR.  Calculate
963  * the combined control register value.
964  *
965  * For such chips we require that all of the events have the same
966  * configuration, so just fetch the settings from the first entry.
967  */
968 static void calculate_single_pcr(struct cpu_hw_events *cpuc)
969 {
970         int i;
971 
972         if (!cpuc->n_added)
973                 goto out;
974 
975         /* Assign to counters all unassigned events.  */
976         for (i = 0; i < cpuc->n_events; i++) {
977                 struct perf_event *cp = cpuc->event[i];
978                 struct hw_perf_event *hwc = &cp->hw;
979                 int idx = hwc->idx;
980                 u64 enc;
981 
982                 if (cpuc->current_idx[i] != PIC_NO_INDEX)
983                         continue;
984 
985                 sparc_perf_event_set_period(cp, hwc, idx);
986                 cpuc->current_idx[i] = idx;
987 
988                 enc = perf_event_get_enc(cpuc->events[i]);
989                 cpuc->pcr[0] &= ~mask_for_index(idx);
990                 if (hwc->state & PERF_HES_STOPPED)
991                         cpuc->pcr[0] |= nop_for_index(idx);
992                 else
993                         cpuc->pcr[0] |= event_encoding(enc, idx);
994         }
995 out:
996         cpuc->pcr[0] |= cpuc->event[0]->hw.config_base;
997 }
998 
999 static void sparc_pmu_start(struct perf_event *event, int flags);
1000 
1001 /* On this PMU each PIC has it's own PCR control register.  */
1002 static void calculate_multiple_pcrs(struct cpu_hw_events *cpuc)
1003 {
1004         int i;
1005 
1006         if (!cpuc->n_added)
1007                 goto out;
1008 
1009         for (i = 0; i < cpuc->n_events; i++) {
1010                 struct perf_event *cp = cpuc->event[i];
1011                 struct hw_perf_event *hwc = &cp->hw;
1012                 int idx = hwc->idx;
1013 
1014                 if (cpuc->current_idx[i] != PIC_NO_INDEX)
1015                         continue;
1016 
1017                 cpuc->current_idx[i] = idx;
1018 
1019                 sparc_pmu_start(cp, PERF_EF_RELOAD);
1020         }
1021 out:
1022         for (i = 0; i < cpuc->n_events; i++) {
1023                 struct perf_event *cp = cpuc->event[i];
1024                 int idx = cp->hw.idx;
1025 
1026                 cpuc->pcr[idx] |= cp->hw.config_base;
1027         }
1028 }
1029 
1030 /* If performance event entries have been added, move existing events
1031  * around (if necessary) and then assign new entries to counters.
1032  */
1033 static void update_pcrs_for_enable(struct cpu_hw_events *cpuc)
1034 {
1035         if (cpuc->n_added)
1036                 read_in_all_counters(cpuc);
1037 
1038         if (sparc_pmu->num_pcrs == 1) {
1039                 calculate_single_pcr(cpuc);
1040         } else {
1041                 calculate_multiple_pcrs(cpuc);
1042         }
1043 }
1044 
1045 static void sparc_pmu_enable(struct pmu *pmu)
1046 {
1047         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1048         int i;
1049 
1050         if (cpuc->enabled)
1051                 return;
1052 
1053         cpuc->enabled = 1;
1054         barrier();
1055 
1056         if (cpuc->n_events)
1057                 update_pcrs_for_enable(cpuc);
1058 
1059         for (i = 0; i < sparc_pmu->num_pcrs; i++)
1060                 pcr_ops->write_pcr(i, cpuc->pcr[i]);
1061 }
1062 
1063 static void sparc_pmu_disable(struct pmu *pmu)
1064 {
1065         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1066         int i;
1067 
1068         if (!cpuc->enabled)
1069                 return;
1070 
1071         cpuc->enabled = 0;
1072         cpuc->n_added = 0;
1073 
1074         for (i = 0; i < sparc_pmu->num_pcrs; i++) {
1075                 u64 val = cpuc->pcr[i];
1076 
1077                 val &= ~(sparc_pmu->user_bit | sparc_pmu->priv_bit |
1078                          sparc_pmu->hv_bit | sparc_pmu->irq_bit);
1079                 cpuc->pcr[i] = val;
1080                 pcr_ops->write_pcr(i, cpuc->pcr[i]);
1081         }
1082 }
1083 
1084 static int active_event_index(struct cpu_hw_events *cpuc,
1085                               struct perf_event *event)
1086 {
1087         int i;
1088 
1089         for (i = 0; i < cpuc->n_events; i++) {
1090                 if (cpuc->event[i] == event)
1091                         break;
1092         }
1093         BUG_ON(i == cpuc->n_events);
1094         return cpuc->current_idx[i];
1095 }
1096 
1097 static void sparc_pmu_start(struct perf_event *event, int flags)
1098 {
1099         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1100         int idx = active_event_index(cpuc, event);
1101 
1102         if (flags & PERF_EF_RELOAD) {
1103                 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1104                 sparc_perf_event_set_period(event, &event->hw, idx);
1105         }
1106 
1107         event->hw.state = 0;
1108 
1109         sparc_pmu_enable_event(cpuc, &event->hw, idx);
1110 }
1111 
1112 static void sparc_pmu_stop(struct perf_event *event, int flags)
1113 {
1114         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1115         int idx = active_event_index(cpuc, event);
1116 
1117         if (!(event->hw.state & PERF_HES_STOPPED)) {
1118                 sparc_pmu_disable_event(cpuc, &event->hw, idx);
1119                 event->hw.state |= PERF_HES_STOPPED;
1120         }
1121 
1122         if (!(event->hw.state & PERF_HES_UPTODATE) && (flags & PERF_EF_UPDATE)) {
1123                 sparc_perf_event_update(event, &event->hw, idx);
1124                 event->hw.state |= PERF_HES_UPTODATE;
1125         }
1126 }
1127 
1128 static void sparc_pmu_del(struct perf_event *event, int _flags)
1129 {
1130         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1131         unsigned long flags;
1132         int i;
1133 
1134         local_irq_save(flags);
1135 
1136         for (i = 0; i < cpuc->n_events; i++) {
1137                 if (event == cpuc->event[i]) {
1138                         /* Absorb the final count and turn off the
1139                          * event.
1140                          */
1141                         sparc_pmu_stop(event, PERF_EF_UPDATE);
1142 
1143                         /* Shift remaining entries down into
1144                          * the existing slot.
1145                          */
1146                         while (++i < cpuc->n_events) {
1147                                 cpuc->event[i - 1] = cpuc->event[i];
1148                                 cpuc->events[i - 1] = cpuc->events[i];
1149                                 cpuc->current_idx[i - 1] =
1150                                         cpuc->current_idx[i];
1151                         }
1152 
1153                         perf_event_update_userpage(event);
1154 
1155                         cpuc->n_events--;
1156                         break;
1157                 }
1158         }
1159 
1160         local_irq_restore(flags);
1161 }
1162 
1163 static void sparc_pmu_read(struct perf_event *event)
1164 {
1165         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1166         int idx = active_event_index(cpuc, event);
1167         struct hw_perf_event *hwc = &event->hw;
1168 
1169         sparc_perf_event_update(event, hwc, idx);
1170 }
1171 
1172 static atomic_t active_events = ATOMIC_INIT(0);
1173 static DEFINE_MUTEX(pmc_grab_mutex);
1174 
1175 static void perf_stop_nmi_watchdog(void *unused)
1176 {
1177         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1178         int i;
1179 
1180         stop_nmi_watchdog(NULL);
1181         for (i = 0; i < sparc_pmu->num_pcrs; i++)
1182                 cpuc->pcr[i] = pcr_ops->read_pcr(i);
1183 }
1184 
1185 static void perf_event_grab_pmc(void)
1186 {
1187         if (atomic_inc_not_zero(&active_events))
1188                 return;
1189 
1190         mutex_lock(&pmc_grab_mutex);
1191         if (atomic_read(&active_events) == 0) {
1192                 if (atomic_read(&nmi_active) > 0) {
1193                         on_each_cpu(perf_stop_nmi_watchdog, NULL, 1);
1194                         BUG_ON(atomic_read(&nmi_active) != 0);
1195                 }
1196                 atomic_inc(&active_events);
1197         }
1198         mutex_unlock(&pmc_grab_mutex);
1199 }
1200 
1201 static void perf_event_release_pmc(void)
1202 {
1203         if (atomic_dec_and_mutex_lock(&active_events, &pmc_grab_mutex)) {
1204                 if (atomic_read(&nmi_active) == 0)
1205                         on_each_cpu(start_nmi_watchdog, NULL, 1);
1206                 mutex_unlock(&pmc_grab_mutex);
1207         }
1208 }
1209 
1210 static const struct perf_event_map *sparc_map_cache_event(u64 config)
1211 {
1212         unsigned int cache_type, cache_op, cache_result;
1213         const struct perf_event_map *pmap;
1214 
1215         if (!sparc_pmu->cache_map)
1216                 return ERR_PTR(-ENOENT);
1217 
1218         cache_type = (config >>  0) & 0xff;
1219         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
1220                 return ERR_PTR(-EINVAL);
1221 
1222         cache_op = (config >>  8) & 0xff;
1223         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
1224                 return ERR_PTR(-EINVAL);
1225 
1226         cache_result = (config >> 16) & 0xff;
1227         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
1228                 return ERR_PTR(-EINVAL);
1229 
1230         pmap = &((*sparc_pmu->cache_map)[cache_type][cache_op][cache_result]);
1231 
1232         if (pmap->encoding == CACHE_OP_UNSUPPORTED)
1233                 return ERR_PTR(-ENOENT);
1234 
1235         if (pmap->encoding == CACHE_OP_NONSENSE)
1236                 return ERR_PTR(-EINVAL);
1237 
1238         return pmap;
1239 }
1240 
1241 static void hw_perf_event_destroy(struct perf_event *event)
1242 {
1243         perf_event_release_pmc();
1244 }
1245 
1246 /* Make sure all events can be scheduled into the hardware at
1247  * the same time.  This is simplified by the fact that we only
1248  * need to support 2 simultaneous HW events.
1249  *
1250  * As a side effect, the evts[]->hw.idx values will be assigned
1251  * on success.  These are pending indexes.  When the events are
1252  * actually programmed into the chip, these values will propagate
1253  * to the per-cpu cpuc->current_idx[] slots, see the code in
1254  * maybe_change_configuration() for details.
1255  */
1256 static int sparc_check_constraints(struct perf_event **evts,
1257                                    unsigned long *events, int n_ev)
1258 {
1259         u8 msk0 = 0, msk1 = 0;
1260         int idx0 = 0;
1261 
1262         /* This case is possible when we are invoked from
1263          * hw_perf_group_sched_in().
1264          */
1265         if (!n_ev)
1266                 return 0;
1267 
1268         if (n_ev > sparc_pmu->max_hw_events)
1269                 return -1;
1270 
1271         if (!(sparc_pmu->flags & SPARC_PMU_HAS_CONFLICTS)) {
1272                 int i;
1273 
1274                 for (i = 0; i < n_ev; i++)
1275                         evts[i]->hw.idx = i;
1276                 return 0;
1277         }
1278 
1279         msk0 = perf_event_get_msk(events[0]);
1280         if (n_ev == 1) {
1281                 if (msk0 & PIC_LOWER)
1282                         idx0 = 1;
1283                 goto success;
1284         }
1285         BUG_ON(n_ev != 2);
1286         msk1 = perf_event_get_msk(events[1]);
1287 
1288         /* If both events can go on any counter, OK.  */
1289         if (msk0 == (PIC_UPPER | PIC_LOWER) &&
1290             msk1 == (PIC_UPPER | PIC_LOWER))
1291                 goto success;
1292 
1293         /* If one event is limited to a specific counter,
1294          * and the other can go on both, OK.
1295          */
1296         if ((msk0 == PIC_UPPER || msk0 == PIC_LOWER) &&
1297             msk1 == (PIC_UPPER | PIC_LOWER)) {
1298                 if (msk0 & PIC_LOWER)
1299                         idx0 = 1;
1300                 goto success;
1301         }
1302 
1303         if ((msk1 == PIC_UPPER || msk1 == PIC_LOWER) &&
1304             msk0 == (PIC_UPPER | PIC_LOWER)) {
1305                 if (msk1 & PIC_UPPER)
1306                         idx0 = 1;
1307                 goto success;
1308         }
1309 
1310         /* If the events are fixed to different counters, OK.  */
1311         if ((msk0 == PIC_UPPER && msk1 == PIC_LOWER) ||
1312             (msk0 == PIC_LOWER && msk1 == PIC_UPPER)) {
1313                 if (msk0 & PIC_LOWER)
1314                         idx0 = 1;
1315                 goto success;
1316         }
1317 
1318         /* Otherwise, there is a conflict.  */
1319         return -1;
1320 
1321 success:
1322         evts[0]->hw.idx = idx0;
1323         if (n_ev == 2)
1324                 evts[1]->hw.idx = idx0 ^ 1;
1325         return 0;
1326 }
1327 
1328 static int check_excludes(struct perf_event **evts, int n_prev, int n_new)
1329 {
1330         int eu = 0, ek = 0, eh = 0;
1331         struct perf_event *event;
1332         int i, n, first;
1333 
1334         if (!(sparc_pmu->flags & SPARC_PMU_ALL_EXCLUDES_SAME))
1335                 return 0;
1336 
1337         n = n_prev + n_new;
1338         if (n <= 1)
1339                 return 0;
1340 
1341         first = 1;
1342         for (i = 0; i < n; i++) {
1343                 event = evts[i];
1344                 if (first) {
1345                         eu = event->attr.exclude_user;
1346                         ek = event->attr.exclude_kernel;
1347                         eh = event->attr.exclude_hv;
1348                         first = 0;
1349                 } else if (event->attr.exclude_user != eu ||
1350                            event->attr.exclude_kernel != ek ||
1351                            event->attr.exclude_hv != eh) {
1352                         return -EAGAIN;
1353                 }
1354         }
1355 
1356         return 0;
1357 }
1358 
1359 static int collect_events(struct perf_event *group, int max_count,
1360                           struct perf_event *evts[], unsigned long *events,
1361                           int *current_idx)
1362 {
1363         struct perf_event *event;
1364         int n = 0;
1365 
1366         if (!is_software_event(group)) {
1367                 if (n >= max_count)
1368                         return -1;
1369                 evts[n] = group;
1370                 events[n] = group->hw.event_base;
1371                 current_idx[n++] = PIC_NO_INDEX;
1372         }
1373         list_for_each_entry(event, &group->sibling_list, group_entry) {
1374                 if (!is_software_event(event) &&
1375                     event->state != PERF_EVENT_STATE_OFF) {
1376                         if (n >= max_count)
1377                                 return -1;
1378                         evts[n] = event;
1379                         events[n] = event->hw.event_base;
1380                         current_idx[n++] = PIC_NO_INDEX;
1381                 }
1382         }
1383         return n;
1384 }
1385 
1386 static int sparc_pmu_add(struct perf_event *event, int ef_flags)
1387 {
1388         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1389         int n0, ret = -EAGAIN;
1390         unsigned long flags;
1391 
1392         local_irq_save(flags);
1393 
1394         n0 = cpuc->n_events;
1395         if (n0 >= sparc_pmu->max_hw_events)
1396                 goto out;
1397 
1398         cpuc->event[n0] = event;
1399         cpuc->events[n0] = event->hw.event_base;
1400         cpuc->current_idx[n0] = PIC_NO_INDEX;
1401 
1402         event->hw.state = PERF_HES_UPTODATE;
1403         if (!(ef_flags & PERF_EF_START))
1404                 event->hw.state |= PERF_HES_STOPPED;
1405 
1406         /*
1407          * If group events scheduling transaction was started,
1408          * skip the schedulability test here, it will be performed
1409          * at commit time(->commit_txn) as a whole
1410          */
1411         if (cpuc->group_flag & PERF_EVENT_TXN)
1412                 goto nocheck;
1413 
1414         if (check_excludes(cpuc->event, n0, 1))
1415                 goto out;
1416         if (sparc_check_constraints(cpuc->event, cpuc->events, n0 + 1))
1417                 goto out;
1418 
1419 nocheck:
1420         cpuc->n_events++;
1421         cpuc->n_added++;
1422 
1423         ret = 0;
1424 out:
1425         local_irq_restore(flags);
1426         return ret;
1427 }
1428 
1429 static int sparc_pmu_event_init(struct perf_event *event)
1430 {
1431         struct perf_event_attr *attr = &event->attr;
1432         struct perf_event *evts[MAX_HWEVENTS];
1433         struct hw_perf_event *hwc = &event->hw;
1434         unsigned long events[MAX_HWEVENTS];
1435         int current_idx_dmy[MAX_HWEVENTS];
1436         const struct perf_event_map *pmap;
1437         int n;
1438 
1439         if (atomic_read(&nmi_active) < 0)
1440                 return -ENODEV;
1441 
1442         /* does not support taken branch sampling */
1443         if (has_branch_stack(event))
1444                 return -EOPNOTSUPP;
1445 
1446         switch (attr->type) {
1447         case PERF_TYPE_HARDWARE:
1448                 if (attr->config >= sparc_pmu->max_events)
1449                         return -EINVAL;
1450                 pmap = sparc_pmu->event_map(attr->config);
1451                 break;
1452 
1453         case PERF_TYPE_HW_CACHE:
1454                 pmap = sparc_map_cache_event(attr->config);
1455                 if (IS_ERR(pmap))
1456                         return PTR_ERR(pmap);
1457                 break;
1458 
1459         case PERF_TYPE_RAW:
1460                 pmap = NULL;
1461                 break;
1462 
1463         default:
1464                 return -ENOENT;
1465 
1466         }
1467 
1468         if (pmap) {
1469                 hwc->event_base = perf_event_encode(pmap);
1470         } else {
1471                 /*
1472                  * User gives us "(encoding << 16) | pic_mask" for
1473                  * PERF_TYPE_RAW events.
1474                  */
1475                 hwc->event_base = attr->config;
1476         }
1477 
1478         /* We save the enable bits in the config_base.  */
1479         hwc->config_base = sparc_pmu->irq_bit;
1480         if (!attr->exclude_user)
1481                 hwc->config_base |= sparc_pmu->user_bit;
1482         if (!attr->exclude_kernel)
1483                 hwc->config_base |= sparc_pmu->priv_bit;
1484         if (!attr->exclude_hv)
1485                 hwc->config_base |= sparc_pmu->hv_bit;
1486 
1487         n = 0;
1488         if (event->group_leader != event) {
1489                 n = collect_events(event->group_leader,
1490                                    sparc_pmu->max_hw_events - 1,
1491                                    evts, events, current_idx_dmy);
1492                 if (n < 0)
1493                         return -EINVAL;
1494         }
1495         events[n] = hwc->event_base;
1496         evts[n] = event;
1497 
1498         if (check_excludes(evts, n, 1))
1499                 return -EINVAL;
1500 
1501         if (sparc_check_constraints(evts, events, n + 1))
1502                 return -EINVAL;
1503 
1504         hwc->idx = PIC_NO_INDEX;
1505 
1506         /* Try to do all error checking before this point, as unwinding
1507          * state after grabbing the PMC is difficult.
1508          */
1509         perf_event_grab_pmc();
1510         event->destroy = hw_perf_event_destroy;
1511 
1512         if (!hwc->sample_period) {
1513                 hwc->sample_period = MAX_PERIOD;
1514                 hwc->last_period = hwc->sample_period;
1515                 local64_set(&hwc->period_left, hwc->sample_period);
1516         }
1517 
1518         return 0;
1519 }
1520 
1521 /*
1522  * Start group events scheduling transaction
1523  * Set the flag to make pmu::enable() not perform the
1524  * schedulability test, it will be performed at commit time
1525  */
1526 static void sparc_pmu_start_txn(struct pmu *pmu)
1527 {
1528         struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
1529 
1530         perf_pmu_disable(pmu);
1531         cpuhw->group_flag |= PERF_EVENT_TXN;
1532 }
1533 
1534 /*
1535  * Stop group events scheduling transaction
1536  * Clear the flag and pmu::enable() will perform the
1537  * schedulability test.
1538  */
1539 static void sparc_pmu_cancel_txn(struct pmu *pmu)
1540 {
1541         struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
1542 
1543         cpuhw->group_flag &= ~PERF_EVENT_TXN;
1544         perf_pmu_enable(pmu);
1545 }
1546 
1547 /*
1548  * Commit group events scheduling transaction
1549  * Perform the group schedulability test as a whole
1550  * Return 0 if success
1551  */
1552 static int sparc_pmu_commit_txn(struct pmu *pmu)
1553 {
1554         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1555         int n;
1556 
1557         if (!sparc_pmu)
1558                 return -EINVAL;
1559 
1560         cpuc = this_cpu_ptr(&cpu_hw_events);
1561         n = cpuc->n_events;
1562         if (check_excludes(cpuc->event, 0, n))
1563                 return -EINVAL;
1564         if (sparc_check_constraints(cpuc->event, cpuc->events, n))
1565                 return -EAGAIN;
1566 
1567         cpuc->group_flag &= ~PERF_EVENT_TXN;
1568         perf_pmu_enable(pmu);
1569         return 0;
1570 }
1571 
1572 static struct pmu pmu = {
1573         .pmu_enable     = sparc_pmu_enable,
1574         .pmu_disable    = sparc_pmu_disable,
1575         .event_init     = sparc_pmu_event_init,
1576         .add            = sparc_pmu_add,
1577         .del            = sparc_pmu_del,
1578         .start          = sparc_pmu_start,
1579         .stop           = sparc_pmu_stop,
1580         .read           = sparc_pmu_read,
1581         .start_txn      = sparc_pmu_start_txn,
1582         .cancel_txn     = sparc_pmu_cancel_txn,
1583         .commit_txn     = sparc_pmu_commit_txn,
1584 };
1585 
1586 void perf_event_print_debug(void)
1587 {
1588         unsigned long flags;
1589         int cpu, i;
1590 
1591         if (!sparc_pmu)
1592                 return;
1593 
1594         local_irq_save(flags);
1595 
1596         cpu = smp_processor_id();
1597 
1598         pr_info("\n");
1599         for (i = 0; i < sparc_pmu->num_pcrs; i++)
1600                 pr_info("CPU#%d: PCR%d[%016llx]\n",
1601                         cpu, i, pcr_ops->read_pcr(i));
1602         for (i = 0; i < sparc_pmu->num_pic_regs; i++)
1603                 pr_info("CPU#%d: PIC%d[%016llx]\n",
1604                         cpu, i, pcr_ops->read_pic(i));
1605 
1606         local_irq_restore(flags);
1607 }
1608 
1609 static int __kprobes perf_event_nmi_handler(struct notifier_block *self,
1610                                             unsigned long cmd, void *__args)
1611 {
1612         struct die_args *args = __args;
1613         struct perf_sample_data data;
1614         struct cpu_hw_events *cpuc;
1615         struct pt_regs *regs;
1616         int i;
1617 
1618         if (!atomic_read(&active_events))
1619                 return NOTIFY_DONE;
1620 
1621         switch (cmd) {
1622         case DIE_NMI:
1623                 break;
1624 
1625         default:
1626                 return NOTIFY_DONE;
1627         }
1628 
1629         regs = args->regs;
1630 
1631         cpuc = this_cpu_ptr(&cpu_hw_events);
1632 
1633         /* If the PMU has the TOE IRQ enable bits, we need to do a
1634          * dummy write to the %pcr to clear the overflow bits and thus
1635          * the interrupt.
1636          *
1637          * Do this before we peek at the counters to determine
1638          * overflow so we don't lose any events.
1639          */
1640         if (sparc_pmu->irq_bit &&
1641             sparc_pmu->num_pcrs == 1)
1642                 pcr_ops->write_pcr(0, cpuc->pcr[0]);
1643 
1644         for (i = 0; i < cpuc->n_events; i++) {
1645                 struct perf_event *event = cpuc->event[i];
1646                 int idx = cpuc->current_idx[i];
1647                 struct hw_perf_event *hwc;
1648                 u64 val;
1649 
1650                 if (sparc_pmu->irq_bit &&
1651                     sparc_pmu->num_pcrs > 1)
1652                         pcr_ops->write_pcr(idx, cpuc->pcr[idx]);
1653 
1654                 hwc = &event->hw;
1655                 val = sparc_perf_event_update(event, hwc, idx);
1656                 if (val & (1ULL << 31))
1657                         continue;
1658 
1659                 perf_sample_data_init(&data, 0, hwc->last_period);
1660                 if (!sparc_perf_event_set_period(event, hwc, idx))
1661                         continue;
1662 
1663                 if (perf_event_overflow(event, &data, regs))
1664                         sparc_pmu_stop(event, 0);
1665         }
1666 
1667         return NOTIFY_STOP;
1668 }
1669 
1670 static __read_mostly struct notifier_block perf_event_nmi_notifier = {
1671         .notifier_call          = perf_event_nmi_handler,
1672 };
1673 
1674 static bool __init supported_pmu(void)
1675 {
1676         if (!strcmp(sparc_pmu_type, "ultra3") ||
1677             !strcmp(sparc_pmu_type, "ultra3+") ||
1678             !strcmp(sparc_pmu_type, "ultra3i") ||
1679             !strcmp(sparc_pmu_type, "ultra4+")) {
1680                 sparc_pmu = &ultra3_pmu;
1681                 return true;
1682         }
1683         if (!strcmp(sparc_pmu_type, "niagara")) {
1684                 sparc_pmu = &niagara1_pmu;
1685                 return true;
1686         }
1687         if (!strcmp(sparc_pmu_type, "niagara2") ||
1688             !strcmp(sparc_pmu_type, "niagara3")) {
1689                 sparc_pmu = &niagara2_pmu;
1690                 return true;
1691         }
1692         if (!strcmp(sparc_pmu_type, "niagara4") ||
1693             !strcmp(sparc_pmu_type, "niagara5")) {
1694                 sparc_pmu = &niagara4_pmu;
1695                 return true;
1696         }
1697         if (!strcmp(sparc_pmu_type, "sparc-m7")) {
1698                 sparc_pmu = &sparc_m7_pmu;
1699                 return true;
1700         }
1701         return false;
1702 }
1703 
1704 static int __init init_hw_perf_events(void)
1705 {
1706         int err;
1707 
1708         pr_info("Performance events: ");
1709 
1710         err = pcr_arch_init();
1711         if (err || !supported_pmu()) {
1712                 pr_cont("No support for PMU type '%s'\n", sparc_pmu_type);
1713                 return 0;
1714         }
1715 
1716         pr_cont("Supported PMU type is '%s'\n", sparc_pmu_type);
1717 
1718         perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1719         register_die_notifier(&perf_event_nmi_notifier);
1720 
1721         return 0;
1722 }
1723 pure_initcall(init_hw_perf_events);
1724 
1725 void perf_callchain_kernel(struct perf_callchain_entry *entry,
1726                            struct pt_regs *regs)
1727 {
1728         unsigned long ksp, fp;
1729 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1730         int graph = 0;
1731 #endif
1732 
1733         stack_trace_flush();
1734 
1735         perf_callchain_store(entry, regs->tpc);
1736 
1737         ksp = regs->u_regs[UREG_I6];
1738         fp = ksp + STACK_BIAS;
1739         do {
1740                 struct sparc_stackf *sf;
1741                 struct pt_regs *regs;
1742                 unsigned long pc;
1743 
1744                 if (!kstack_valid(current_thread_info(), fp))
1745                         break;
1746 
1747                 sf = (struct sparc_stackf *) fp;
1748                 regs = (struct pt_regs *) (sf + 1);
1749 
1750                 if (kstack_is_trap_frame(current_thread_info(), regs)) {
1751                         if (user_mode(regs))
1752                                 break;
1753                         pc = regs->tpc;
1754                         fp = regs->u_regs[UREG_I6] + STACK_BIAS;
1755                 } else {
1756                         pc = sf->callers_pc;
1757                         fp = (unsigned long)sf->fp + STACK_BIAS;
1758                 }
1759                 perf_callchain_store(entry, pc);
1760 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1761                 if ((pc + 8UL) == (unsigned long) &return_to_handler) {
1762                         int index = current->curr_ret_stack;
1763                         if (current->ret_stack && index >= graph) {
1764                                 pc = current->ret_stack[index - graph].ret;
1765                                 perf_callchain_store(entry, pc);
1766                                 graph++;
1767                         }
1768                 }
1769 #endif
1770         } while (entry->nr < PERF_MAX_STACK_DEPTH);
1771 }
1772 
1773 static void perf_callchain_user_64(struct perf_callchain_entry *entry,
1774                                    struct pt_regs *regs)
1775 {
1776         unsigned long ufp;
1777 
1778         ufp = regs->u_regs[UREG_I6] + STACK_BIAS;
1779         do {
1780                 struct sparc_stackf __user *usf;
1781                 struct sparc_stackf sf;
1782                 unsigned long pc;
1783 
1784                 usf = (struct sparc_stackf __user *)ufp;
1785                 if (__copy_from_user_inatomic(&sf, usf, sizeof(sf)))
1786                         break;
1787 
1788                 pc = sf.callers_pc;
1789                 ufp = (unsigned long)sf.fp + STACK_BIAS;
1790                 perf_callchain_store(entry, pc);
1791         } while (entry->nr < PERF_MAX_STACK_DEPTH);
1792 }
1793 
1794 static void perf_callchain_user_32(struct perf_callchain_entry *entry,
1795                                    struct pt_regs *regs)
1796 {
1797         unsigned long ufp;
1798 
1799         ufp = regs->u_regs[UREG_I6] & 0xffffffffUL;
1800         do {
1801                 unsigned long pc;
1802 
1803                 if (thread32_stack_is_64bit(ufp)) {
1804                         struct sparc_stackf __user *usf;
1805                         struct sparc_stackf sf;
1806 
1807                         ufp += STACK_BIAS;
1808                         usf = (struct sparc_stackf __user *)ufp;
1809                         if (__copy_from_user_inatomic(&sf, usf, sizeof(sf)))
1810                                 break;
1811                         pc = sf.callers_pc & 0xffffffff;
1812                         ufp = ((unsigned long) sf.fp) & 0xffffffff;
1813                 } else {
1814                         struct sparc_stackf32 __user *usf;
1815                         struct sparc_stackf32 sf;
1816                         usf = (struct sparc_stackf32 __user *)ufp;
1817                         if (__copy_from_user_inatomic(&sf, usf, sizeof(sf)))
1818                                 break;
1819                         pc = sf.callers_pc;
1820                         ufp = (unsigned long)sf.fp;
1821                 }
1822                 perf_callchain_store(entry, pc);
1823         } while (entry->nr < PERF_MAX_STACK_DEPTH);
1824 }
1825 
1826 void
1827 perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
1828 {
1829         perf_callchain_store(entry, regs->tpc);
1830 
1831         if (!current->mm)
1832                 return;
1833 
1834         flushw_user();
1835         if (test_thread_flag(TIF_32BIT))
1836                 perf_callchain_user_32(entry, regs);
1837         else
1838                 perf_callchain_user_64(entry, regs);
1839 }
1840 

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