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TOMOYO Linux Cross Reference
Linux/arch/sparc/kernel/sbus.c

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  1 // SPDX-License-Identifier: GPL-2.0
  2 /*
  3  * sbus.c: UltraSparc SBUS controller support.
  4  *
  5  * Copyright (C) 1999 David S. Miller (davem@redhat.com)
  6  */
  7 
  8 #include <linux/kernel.h>
  9 #include <linux/types.h>
 10 #include <linux/mm.h>
 11 #include <linux/spinlock.h>
 12 #include <linux/slab.h>
 13 #include <linux/export.h>
 14 #include <linux/init.h>
 15 #include <linux/interrupt.h>
 16 #include <linux/of.h>
 17 #include <linux/of_device.h>
 18 
 19 #include <asm/page.h>
 20 #include <asm/io.h>
 21 #include <asm/upa.h>
 22 #include <asm/cache.h>
 23 #include <asm/dma.h>
 24 #include <asm/irq.h>
 25 #include <asm/prom.h>
 26 #include <asm/oplib.h>
 27 #include <asm/starfire.h>
 28 
 29 #include "iommu_common.h"
 30 
 31 #define MAP_BASE        ((u32)0xc0000000)
 32 
 33 /* Offsets from iommu_regs */
 34 #define SYSIO_IOMMUREG_BASE     0x2400UL
 35 #define IOMMU_CONTROL   (0x2400UL - 0x2400UL)   /* IOMMU control register */
 36 #define IOMMU_TSBBASE   (0x2408UL - 0x2400UL)   /* TSB base address register */
 37 #define IOMMU_FLUSH     (0x2410UL - 0x2400UL)   /* IOMMU flush register */
 38 #define IOMMU_VADIAG    (0x4400UL - 0x2400UL)   /* SBUS virtual address diagnostic */
 39 #define IOMMU_TAGCMP    (0x4408UL - 0x2400UL)   /* TLB tag compare diagnostics */
 40 #define IOMMU_LRUDIAG   (0x4500UL - 0x2400UL)   /* IOMMU LRU queue diagnostics */
 41 #define IOMMU_TAGDIAG   (0x4580UL - 0x2400UL)   /* TLB tag diagnostics */
 42 #define IOMMU_DRAMDIAG  (0x4600UL - 0x2400UL)   /* TLB data RAM diagnostics */
 43 
 44 #define IOMMU_DRAM_VALID        (1UL << 30UL)
 45 
 46 /* Offsets from strbuf_regs */
 47 #define SYSIO_STRBUFREG_BASE    0x2800UL
 48 #define STRBUF_CONTROL  (0x2800UL - 0x2800UL)   /* Control */
 49 #define STRBUF_PFLUSH   (0x2808UL - 0x2800UL)   /* Page flush/invalidate */
 50 #define STRBUF_FSYNC    (0x2810UL - 0x2800UL)   /* Flush synchronization */
 51 #define STRBUF_DRAMDIAG (0x5000UL - 0x2800UL)   /* data RAM diagnostic */
 52 #define STRBUF_ERRDIAG  (0x5400UL - 0x2800UL)   /* error status diagnostics */
 53 #define STRBUF_PTAGDIAG (0x5800UL - 0x2800UL)   /* Page tag diagnostics */
 54 #define STRBUF_LTAGDIAG (0x5900UL - 0x2800UL)   /* Line tag diagnostics */
 55 
 56 #define STRBUF_TAG_VALID        0x02UL
 57 
 58 /* Enable 64-bit DVMA mode for the given device. */
 59 void sbus_set_sbus64(struct device *dev, int bursts)
 60 {
 61         struct iommu *iommu = dev->archdata.iommu;
 62         struct platform_device *op = to_platform_device(dev);
 63         const struct linux_prom_registers *regs;
 64         unsigned long cfg_reg;
 65         int slot;
 66         u64 val;
 67 
 68         regs = of_get_property(op->dev.of_node, "reg", NULL);
 69         if (!regs) {
 70                 printk(KERN_ERR "sbus_set_sbus64: Cannot find regs for %s\n",
 71                        op->dev.of_node->full_name);
 72                 return;
 73         }
 74         slot = regs->which_io;
 75 
 76         cfg_reg = iommu->write_complete_reg;
 77         switch (slot) {
 78         case 0:
 79                 cfg_reg += 0x20UL;
 80                 break;
 81         case 1:
 82                 cfg_reg += 0x28UL;
 83                 break;
 84         case 2:
 85                 cfg_reg += 0x30UL;
 86                 break;
 87         case 3:
 88                 cfg_reg += 0x38UL;
 89                 break;
 90         case 13:
 91                 cfg_reg += 0x40UL;
 92                 break;
 93         case 14:
 94                 cfg_reg += 0x48UL;
 95                 break;
 96         case 15:
 97                 cfg_reg += 0x50UL;
 98                 break;
 99 
100         default:
101                 return;
102         }
103 
104         val = upa_readq(cfg_reg);
105         if (val & (1UL << 14UL)) {
106                 /* Extended transfer mode already enabled. */
107                 return;
108         }
109 
110         val |= (1UL << 14UL);
111 
112         if (bursts & DMA_BURST8)
113                 val |= (1UL << 1UL);
114         if (bursts & DMA_BURST16)
115                 val |= (1UL << 2UL);
116         if (bursts & DMA_BURST32)
117                 val |= (1UL << 3UL);
118         if (bursts & DMA_BURST64)
119                 val |= (1UL << 4UL);
120         upa_writeq(val, cfg_reg);
121 }
122 EXPORT_SYMBOL(sbus_set_sbus64);
123 
124 /* INO number to IMAP register offset for SYSIO external IRQ's.
125  * This should conform to both Sunfire/Wildfire server and Fusion
126  * desktop designs.
127  */
128 #define SYSIO_IMAP_SLOT0        0x2c00UL
129 #define SYSIO_IMAP_SLOT1        0x2c08UL
130 #define SYSIO_IMAP_SLOT2        0x2c10UL
131 #define SYSIO_IMAP_SLOT3        0x2c18UL
132 #define SYSIO_IMAP_SCSI         0x3000UL
133 #define SYSIO_IMAP_ETH          0x3008UL
134 #define SYSIO_IMAP_BPP          0x3010UL
135 #define SYSIO_IMAP_AUDIO        0x3018UL
136 #define SYSIO_IMAP_PFAIL        0x3020UL
137 #define SYSIO_IMAP_KMS          0x3028UL
138 #define SYSIO_IMAP_FLPY         0x3030UL
139 #define SYSIO_IMAP_SHW          0x3038UL
140 #define SYSIO_IMAP_KBD          0x3040UL
141 #define SYSIO_IMAP_MS           0x3048UL
142 #define SYSIO_IMAP_SER          0x3050UL
143 #define SYSIO_IMAP_TIM0         0x3060UL
144 #define SYSIO_IMAP_TIM1         0x3068UL
145 #define SYSIO_IMAP_UE           0x3070UL
146 #define SYSIO_IMAP_CE           0x3078UL
147 #define SYSIO_IMAP_SBERR        0x3080UL
148 #define SYSIO_IMAP_PMGMT        0x3088UL
149 #define SYSIO_IMAP_GFX          0x3090UL
150 #define SYSIO_IMAP_EUPA         0x3098UL
151 
152 #define bogon     ((unsigned long) -1)
153 static unsigned long sysio_irq_offsets[] = {
154         /* SBUS Slot 0 --> 3, level 1 --> 7 */
155         SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0,
156         SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0,
157         SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1,
158         SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1,
159         SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2,
160         SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2,
161         SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3,
162         SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3,
163 
164         /* Onboard devices (not relevant/used on SunFire). */
165         SYSIO_IMAP_SCSI,
166         SYSIO_IMAP_ETH,
167         SYSIO_IMAP_BPP,
168         bogon,
169         SYSIO_IMAP_AUDIO,
170         SYSIO_IMAP_PFAIL,
171         bogon,
172         bogon,
173         SYSIO_IMAP_KMS,
174         SYSIO_IMAP_FLPY,
175         SYSIO_IMAP_SHW,
176         SYSIO_IMAP_KBD,
177         SYSIO_IMAP_MS,
178         SYSIO_IMAP_SER,
179         bogon,
180         bogon,
181         SYSIO_IMAP_TIM0,
182         SYSIO_IMAP_TIM1,
183         bogon,
184         bogon,
185         SYSIO_IMAP_UE,
186         SYSIO_IMAP_CE,
187         SYSIO_IMAP_SBERR,
188         SYSIO_IMAP_PMGMT,
189 };
190 
191 #undef bogon
192 
193 #define NUM_SYSIO_OFFSETS ARRAY_SIZE(sysio_irq_offsets)
194 
195 /* Convert Interrupt Mapping register pointer to associated
196  * Interrupt Clear register pointer, SYSIO specific version.
197  */
198 #define SYSIO_ICLR_UNUSED0      0x3400UL
199 #define SYSIO_ICLR_SLOT0        0x3408UL
200 #define SYSIO_ICLR_SLOT1        0x3448UL
201 #define SYSIO_ICLR_SLOT2        0x3488UL
202 #define SYSIO_ICLR_SLOT3        0x34c8UL
203 static unsigned long sysio_imap_to_iclr(unsigned long imap)
204 {
205         unsigned long diff = SYSIO_ICLR_UNUSED0 - SYSIO_IMAP_SLOT0;
206         return imap + diff;
207 }
208 
209 static unsigned int sbus_build_irq(struct platform_device *op, unsigned int ino)
210 {
211         struct iommu *iommu = op->dev.archdata.iommu;
212         unsigned long reg_base = iommu->write_complete_reg - 0x2000UL;
213         unsigned long imap, iclr;
214         int sbus_level = 0;
215 
216         imap = sysio_irq_offsets[ino];
217         if (imap == ((unsigned long)-1)) {
218                 prom_printf("get_irq_translations: Bad SYSIO INO[%x]\n",
219                             ino);
220                 prom_halt();
221         }
222         imap += reg_base;
223 
224         /* SYSIO inconsistency.  For external SLOTS, we have to select
225          * the right ICLR register based upon the lower SBUS irq level
226          * bits.
227          */
228         if (ino >= 0x20) {
229                 iclr = sysio_imap_to_iclr(imap);
230         } else {
231                 int sbus_slot = (ino & 0x18)>>3;
232                 
233                 sbus_level = ino & 0x7;
234 
235                 switch(sbus_slot) {
236                 case 0:
237                         iclr = reg_base + SYSIO_ICLR_SLOT0;
238                         break;
239                 case 1:
240                         iclr = reg_base + SYSIO_ICLR_SLOT1;
241                         break;
242                 case 2:
243                         iclr = reg_base + SYSIO_ICLR_SLOT2;
244                         break;
245                 default:
246                 case 3:
247                         iclr = reg_base + SYSIO_ICLR_SLOT3;
248                         break;
249                 }
250 
251                 iclr += ((unsigned long)sbus_level - 1UL) * 8UL;
252         }
253         return build_irq(sbus_level, iclr, imap);
254 }
255 
256 /* Error interrupt handling. */
257 #define SYSIO_UE_AFSR   0x0030UL
258 #define SYSIO_UE_AFAR   0x0038UL
259 #define  SYSIO_UEAFSR_PPIO  0x8000000000000000UL /* Primary PIO cause         */
260 #define  SYSIO_UEAFSR_PDRD  0x4000000000000000UL /* Primary DVMA read cause   */
261 #define  SYSIO_UEAFSR_PDWR  0x2000000000000000UL /* Primary DVMA write cause  */
262 #define  SYSIO_UEAFSR_SPIO  0x1000000000000000UL /* Secondary PIO is cause    */
263 #define  SYSIO_UEAFSR_SDRD  0x0800000000000000UL /* Secondary DVMA read cause */
264 #define  SYSIO_UEAFSR_SDWR  0x0400000000000000UL /* Secondary DVMA write cause*/
265 #define  SYSIO_UEAFSR_RESV1 0x03ff000000000000UL /* Reserved                  */
266 #define  SYSIO_UEAFSR_DOFF  0x0000e00000000000UL /* Doubleword Offset         */
267 #define  SYSIO_UEAFSR_SIZE  0x00001c0000000000UL /* Bad transfer size 2^SIZE  */
268 #define  SYSIO_UEAFSR_MID   0x000003e000000000UL /* UPA MID causing the fault */
269 #define  SYSIO_UEAFSR_RESV2 0x0000001fffffffffUL /* Reserved                  */
270 static irqreturn_t sysio_ue_handler(int irq, void *dev_id)
271 {
272         struct platform_device *op = dev_id;
273         struct iommu *iommu = op->dev.archdata.iommu;
274         unsigned long reg_base = iommu->write_complete_reg - 0x2000UL;
275         unsigned long afsr_reg, afar_reg;
276         unsigned long afsr, afar, error_bits;
277         int reported, portid;
278 
279         afsr_reg = reg_base + SYSIO_UE_AFSR;
280         afar_reg = reg_base + SYSIO_UE_AFAR;
281 
282         /* Latch error status. */
283         afsr = upa_readq(afsr_reg);
284         afar = upa_readq(afar_reg);
285 
286         /* Clear primary/secondary error status bits. */
287         error_bits = afsr &
288                 (SYSIO_UEAFSR_PPIO | SYSIO_UEAFSR_PDRD | SYSIO_UEAFSR_PDWR |
289                  SYSIO_UEAFSR_SPIO | SYSIO_UEAFSR_SDRD | SYSIO_UEAFSR_SDWR);
290         upa_writeq(error_bits, afsr_reg);
291 
292         portid = of_getintprop_default(op->dev.of_node, "portid", -1);
293 
294         /* Log the error. */
295         printk("SYSIO[%x]: Uncorrectable ECC Error, primary error type[%s]\n",
296                portid,
297                (((error_bits & SYSIO_UEAFSR_PPIO) ?
298                  "PIO" :
299                  ((error_bits & SYSIO_UEAFSR_PDRD) ?
300                   "DVMA Read" :
301                   ((error_bits & SYSIO_UEAFSR_PDWR) ?
302                    "DVMA Write" : "???")))));
303         printk("SYSIO[%x]: DOFF[%lx] SIZE[%lx] MID[%lx]\n",
304                portid,
305                (afsr & SYSIO_UEAFSR_DOFF) >> 45UL,
306                (afsr & SYSIO_UEAFSR_SIZE) >> 42UL,
307                (afsr & SYSIO_UEAFSR_MID) >> 37UL);
308         printk("SYSIO[%x]: AFAR[%016lx]\n", portid, afar);
309         printk("SYSIO[%x]: Secondary UE errors [", portid);
310         reported = 0;
311         if (afsr & SYSIO_UEAFSR_SPIO) {
312                 reported++;
313                 printk("(PIO)");
314         }
315         if (afsr & SYSIO_UEAFSR_SDRD) {
316                 reported++;
317                 printk("(DVMA Read)");
318         }
319         if (afsr & SYSIO_UEAFSR_SDWR) {
320                 reported++;
321                 printk("(DVMA Write)");
322         }
323         if (!reported)
324                 printk("(none)");
325         printk("]\n");
326 
327         return IRQ_HANDLED;
328 }
329 
330 #define SYSIO_CE_AFSR   0x0040UL
331 #define SYSIO_CE_AFAR   0x0048UL
332 #define  SYSIO_CEAFSR_PPIO  0x8000000000000000UL /* Primary PIO cause         */
333 #define  SYSIO_CEAFSR_PDRD  0x4000000000000000UL /* Primary DVMA read cause   */
334 #define  SYSIO_CEAFSR_PDWR  0x2000000000000000UL /* Primary DVMA write cause  */
335 #define  SYSIO_CEAFSR_SPIO  0x1000000000000000UL /* Secondary PIO cause       */
336 #define  SYSIO_CEAFSR_SDRD  0x0800000000000000UL /* Secondary DVMA read cause */
337 #define  SYSIO_CEAFSR_SDWR  0x0400000000000000UL /* Secondary DVMA write cause*/
338 #define  SYSIO_CEAFSR_RESV1 0x0300000000000000UL /* Reserved                  */
339 #define  SYSIO_CEAFSR_ESYND 0x00ff000000000000UL /* Syndrome Bits             */
340 #define  SYSIO_CEAFSR_DOFF  0x0000e00000000000UL /* Double Offset             */
341 #define  SYSIO_CEAFSR_SIZE  0x00001c0000000000UL /* Bad transfer size 2^SIZE  */
342 #define  SYSIO_CEAFSR_MID   0x000003e000000000UL /* UPA MID causing the fault */
343 #define  SYSIO_CEAFSR_RESV2 0x0000001fffffffffUL /* Reserved                  */
344 static irqreturn_t sysio_ce_handler(int irq, void *dev_id)
345 {
346         struct platform_device *op = dev_id;
347         struct iommu *iommu = op->dev.archdata.iommu;
348         unsigned long reg_base = iommu->write_complete_reg - 0x2000UL;
349         unsigned long afsr_reg, afar_reg;
350         unsigned long afsr, afar, error_bits;
351         int reported, portid;
352 
353         afsr_reg = reg_base + SYSIO_CE_AFSR;
354         afar_reg = reg_base + SYSIO_CE_AFAR;
355 
356         /* Latch error status. */
357         afsr = upa_readq(afsr_reg);
358         afar = upa_readq(afar_reg);
359 
360         /* Clear primary/secondary error status bits. */
361         error_bits = afsr &
362                 (SYSIO_CEAFSR_PPIO | SYSIO_CEAFSR_PDRD | SYSIO_CEAFSR_PDWR |
363                  SYSIO_CEAFSR_SPIO | SYSIO_CEAFSR_SDRD | SYSIO_CEAFSR_SDWR);
364         upa_writeq(error_bits, afsr_reg);
365 
366         portid = of_getintprop_default(op->dev.of_node, "portid", -1);
367 
368         printk("SYSIO[%x]: Correctable ECC Error, primary error type[%s]\n",
369                portid,
370                (((error_bits & SYSIO_CEAFSR_PPIO) ?
371                  "PIO" :
372                  ((error_bits & SYSIO_CEAFSR_PDRD) ?
373                   "DVMA Read" :
374                   ((error_bits & SYSIO_CEAFSR_PDWR) ?
375                    "DVMA Write" : "???")))));
376 
377         /* XXX Use syndrome and afar to print out module string just like
378          * XXX UDB CE trap handler does... -DaveM
379          */
380         printk("SYSIO[%x]: DOFF[%lx] ECC Syndrome[%lx] Size[%lx] MID[%lx]\n",
381                portid,
382                (afsr & SYSIO_CEAFSR_DOFF) >> 45UL,
383                (afsr & SYSIO_CEAFSR_ESYND) >> 48UL,
384                (afsr & SYSIO_CEAFSR_SIZE) >> 42UL,
385                (afsr & SYSIO_CEAFSR_MID) >> 37UL);
386         printk("SYSIO[%x]: AFAR[%016lx]\n", portid, afar);
387 
388         printk("SYSIO[%x]: Secondary CE errors [", portid);
389         reported = 0;
390         if (afsr & SYSIO_CEAFSR_SPIO) {
391                 reported++;
392                 printk("(PIO)");
393         }
394         if (afsr & SYSIO_CEAFSR_SDRD) {
395                 reported++;
396                 printk("(DVMA Read)");
397         }
398         if (afsr & SYSIO_CEAFSR_SDWR) {
399                 reported++;
400                 printk("(DVMA Write)");
401         }
402         if (!reported)
403                 printk("(none)");
404         printk("]\n");
405 
406         return IRQ_HANDLED;
407 }
408 
409 #define SYSIO_SBUS_AFSR         0x2010UL
410 #define SYSIO_SBUS_AFAR         0x2018UL
411 #define  SYSIO_SBAFSR_PLE   0x8000000000000000UL /* Primary Late PIO Error    */
412 #define  SYSIO_SBAFSR_PTO   0x4000000000000000UL /* Primary SBUS Timeout      */
413 #define  SYSIO_SBAFSR_PBERR 0x2000000000000000UL /* Primary SBUS Error ACK    */
414 #define  SYSIO_SBAFSR_SLE   0x1000000000000000UL /* Secondary Late PIO Error  */
415 #define  SYSIO_SBAFSR_STO   0x0800000000000000UL /* Secondary SBUS Timeout    */
416 #define  SYSIO_SBAFSR_SBERR 0x0400000000000000UL /* Secondary SBUS Error ACK  */
417 #define  SYSIO_SBAFSR_RESV1 0x03ff000000000000UL /* Reserved                  */
418 #define  SYSIO_SBAFSR_RD    0x0000800000000000UL /* Primary was late PIO read */
419 #define  SYSIO_SBAFSR_RESV2 0x0000600000000000UL /* Reserved                  */
420 #define  SYSIO_SBAFSR_SIZE  0x00001c0000000000UL /* Size of transfer          */
421 #define  SYSIO_SBAFSR_MID   0x000003e000000000UL /* MID causing the error     */
422 #define  SYSIO_SBAFSR_RESV3 0x0000001fffffffffUL /* Reserved                  */
423 static irqreturn_t sysio_sbus_error_handler(int irq, void *dev_id)
424 {
425         struct platform_device *op = dev_id;
426         struct iommu *iommu = op->dev.archdata.iommu;
427         unsigned long afsr_reg, afar_reg, reg_base;
428         unsigned long afsr, afar, error_bits;
429         int reported, portid;
430 
431         reg_base = iommu->write_complete_reg - 0x2000UL;
432         afsr_reg = reg_base + SYSIO_SBUS_AFSR;
433         afar_reg = reg_base + SYSIO_SBUS_AFAR;
434 
435         afsr = upa_readq(afsr_reg);
436         afar = upa_readq(afar_reg);
437 
438         /* Clear primary/secondary error status bits. */
439         error_bits = afsr &
440                 (SYSIO_SBAFSR_PLE | SYSIO_SBAFSR_PTO | SYSIO_SBAFSR_PBERR |
441                  SYSIO_SBAFSR_SLE | SYSIO_SBAFSR_STO | SYSIO_SBAFSR_SBERR);
442         upa_writeq(error_bits, afsr_reg);
443 
444         portid = of_getintprop_default(op->dev.of_node, "portid", -1);
445 
446         /* Log the error. */
447         printk("SYSIO[%x]: SBUS Error, primary error type[%s] read(%d)\n",
448                portid,
449                (((error_bits & SYSIO_SBAFSR_PLE) ?
450                  "Late PIO Error" :
451                  ((error_bits & SYSIO_SBAFSR_PTO) ?
452                   "Time Out" :
453                   ((error_bits & SYSIO_SBAFSR_PBERR) ?
454                    "Error Ack" : "???")))),
455                (afsr & SYSIO_SBAFSR_RD) ? 1 : 0);
456         printk("SYSIO[%x]: size[%lx] MID[%lx]\n",
457                portid,
458                (afsr & SYSIO_SBAFSR_SIZE) >> 42UL,
459                (afsr & SYSIO_SBAFSR_MID) >> 37UL);
460         printk("SYSIO[%x]: AFAR[%016lx]\n", portid, afar);
461         printk("SYSIO[%x]: Secondary SBUS errors [", portid);
462         reported = 0;
463         if (afsr & SYSIO_SBAFSR_SLE) {
464                 reported++;
465                 printk("(Late PIO Error)");
466         }
467         if (afsr & SYSIO_SBAFSR_STO) {
468                 reported++;
469                 printk("(Time Out)");
470         }
471         if (afsr & SYSIO_SBAFSR_SBERR) {
472                 reported++;
473                 printk("(Error Ack)");
474         }
475         if (!reported)
476                 printk("(none)");
477         printk("]\n");
478 
479         /* XXX check iommu/strbuf for further error status XXX */
480 
481         return IRQ_HANDLED;
482 }
483 
484 #define ECC_CONTROL     0x0020UL
485 #define  SYSIO_ECNTRL_ECCEN     0x8000000000000000UL /* Enable ECC Checking   */
486 #define  SYSIO_ECNTRL_UEEN      0x4000000000000000UL /* Enable UE Interrupts  */
487 #define  SYSIO_ECNTRL_CEEN      0x2000000000000000UL /* Enable CE Interrupts  */
488 
489 #define SYSIO_UE_INO            0x34
490 #define SYSIO_CE_INO            0x35
491 #define SYSIO_SBUSERR_INO       0x36
492 
493 static void __init sysio_register_error_handlers(struct platform_device *op)
494 {
495         struct iommu *iommu = op->dev.archdata.iommu;
496         unsigned long reg_base = iommu->write_complete_reg - 0x2000UL;
497         unsigned int irq;
498         u64 control;
499         int portid;
500 
501         portid = of_getintprop_default(op->dev.of_node, "portid", -1);
502 
503         irq = sbus_build_irq(op, SYSIO_UE_INO);
504         if (request_irq(irq, sysio_ue_handler, 0,
505                         "SYSIO_UE", op) < 0) {
506                 prom_printf("SYSIO[%x]: Cannot register UE interrupt.\n",
507                             portid);
508                 prom_halt();
509         }
510 
511         irq = sbus_build_irq(op, SYSIO_CE_INO);
512         if (request_irq(irq, sysio_ce_handler, 0,
513                         "SYSIO_CE", op) < 0) {
514                 prom_printf("SYSIO[%x]: Cannot register CE interrupt.\n",
515                             portid);
516                 prom_halt();
517         }
518 
519         irq = sbus_build_irq(op, SYSIO_SBUSERR_INO);
520         if (request_irq(irq, sysio_sbus_error_handler, 0,
521                         "SYSIO_SBERR", op) < 0) {
522                 prom_printf("SYSIO[%x]: Cannot register SBUS Error interrupt.\n",
523                             portid);
524                 prom_halt();
525         }
526 
527         /* Now turn the error interrupts on and also enable ECC checking. */
528         upa_writeq((SYSIO_ECNTRL_ECCEN |
529                     SYSIO_ECNTRL_UEEN  |
530                     SYSIO_ECNTRL_CEEN),
531                    reg_base + ECC_CONTROL);
532 
533         control = upa_readq(iommu->write_complete_reg);
534         control |= 0x100UL; /* SBUS Error Interrupt Enable */
535         upa_writeq(control, iommu->write_complete_reg);
536 }
537 
538 /* Boot time initialization. */
539 static void __init sbus_iommu_init(struct platform_device *op)
540 {
541         const struct linux_prom64_registers *pr;
542         struct device_node *dp = op->dev.of_node;
543         struct iommu *iommu;
544         struct strbuf *strbuf;
545         unsigned long regs, reg_base;
546         int i, portid;
547         u64 control;
548 
549         pr = of_get_property(dp, "reg", NULL);
550         if (!pr) {
551                 prom_printf("sbus_iommu_init: Cannot map SYSIO "
552                             "control registers.\n");
553                 prom_halt();
554         }
555         regs = pr->phys_addr;
556 
557         iommu = kzalloc(sizeof(*iommu), GFP_ATOMIC);
558         strbuf = kzalloc(sizeof(*strbuf), GFP_ATOMIC);
559         if (!iommu || !strbuf)
560                 goto fatal_memory_error;
561 
562         op->dev.archdata.iommu = iommu;
563         op->dev.archdata.stc = strbuf;
564         op->dev.archdata.numa_node = -1;
565 
566         reg_base = regs + SYSIO_IOMMUREG_BASE;
567         iommu->iommu_control = reg_base + IOMMU_CONTROL;
568         iommu->iommu_tsbbase = reg_base + IOMMU_TSBBASE;
569         iommu->iommu_flush = reg_base + IOMMU_FLUSH;
570         iommu->iommu_tags = iommu->iommu_control +
571                 (IOMMU_TAGDIAG - IOMMU_CONTROL);
572 
573         reg_base = regs + SYSIO_STRBUFREG_BASE;
574         strbuf->strbuf_control = reg_base + STRBUF_CONTROL;
575         strbuf->strbuf_pflush = reg_base + STRBUF_PFLUSH;
576         strbuf->strbuf_fsync = reg_base + STRBUF_FSYNC;
577 
578         strbuf->strbuf_enabled = 1;
579 
580         strbuf->strbuf_flushflag = (volatile unsigned long *)
581                 ((((unsigned long)&strbuf->__flushflag_buf[0])
582                   + 63UL)
583                  & ~63UL);
584         strbuf->strbuf_flushflag_pa = (unsigned long)
585                 __pa(strbuf->strbuf_flushflag);
586 
587         /* The SYSIO SBUS control register is used for dummy reads
588          * in order to ensure write completion.
589          */
590         iommu->write_complete_reg = regs + 0x2000UL;
591 
592         portid = of_getintprop_default(op->dev.of_node, "portid", -1);
593         printk(KERN_INFO "SYSIO: UPA portID %x, at %016lx\n",
594                portid, regs);
595 
596         /* Setup for TSB_SIZE=7, TBW_SIZE=0, MMU_DE=1, MMU_EN=1 */
597         if (iommu_table_init(iommu, IO_TSB_SIZE, MAP_BASE, 0xffffffff, -1))
598                 goto fatal_memory_error;
599 
600         control = upa_readq(iommu->iommu_control);
601         control = ((7UL << 16UL)        |
602                    (0UL << 2UL)         |
603                    (1UL << 1UL)         |
604                    (1UL << 0UL));
605         upa_writeq(control, iommu->iommu_control);
606 
607         /* Clean out any cruft in the IOMMU using
608          * diagnostic accesses.
609          */
610         for (i = 0; i < 16; i++) {
611                 unsigned long dram, tag;
612 
613                 dram = iommu->iommu_control + (IOMMU_DRAMDIAG - IOMMU_CONTROL);
614                 tag = iommu->iommu_control + (IOMMU_TAGDIAG - IOMMU_CONTROL);
615 
616                 dram += (unsigned long)i * 8UL;
617                 tag += (unsigned long)i * 8UL;
618                 upa_writeq(0, dram);
619                 upa_writeq(0, tag);
620         }
621         upa_readq(iommu->write_complete_reg);
622 
623         /* Give the TSB to SYSIO. */
624         upa_writeq(__pa(iommu->page_table), iommu->iommu_tsbbase);
625 
626         /* Setup streaming buffer, DE=1 SB_EN=1 */
627         control = (1UL << 1UL) | (1UL << 0UL);
628         upa_writeq(control, strbuf->strbuf_control);
629 
630         /* Clear out the tags using diagnostics. */
631         for (i = 0; i < 16; i++) {
632                 unsigned long ptag, ltag;
633 
634                 ptag = strbuf->strbuf_control +
635                         (STRBUF_PTAGDIAG - STRBUF_CONTROL);
636                 ltag = strbuf->strbuf_control +
637                         (STRBUF_LTAGDIAG - STRBUF_CONTROL);
638                 ptag += (unsigned long)i * 8UL;
639                 ltag += (unsigned long)i * 8UL;
640 
641                 upa_writeq(0UL, ptag);
642                 upa_writeq(0UL, ltag);
643         }
644 
645         /* Enable DVMA arbitration for all devices/slots. */
646         control = upa_readq(iommu->write_complete_reg);
647         control |= 0x3fUL;
648         upa_writeq(control, iommu->write_complete_reg);
649 
650         /* Now some Xfire specific grot... */
651         if (this_is_starfire)
652                 starfire_hookup(portid);
653 
654         sysio_register_error_handlers(op);
655         return;
656 
657 fatal_memory_error:
658         kfree(iommu);
659         kfree(strbuf);
660         prom_printf("sbus_iommu_init: Fatal memory allocation error.\n");
661 }
662 
663 static int __init sbus_init(void)
664 {
665         struct device_node *dp;
666 
667         for_each_node_by_name(dp, "sbus") {
668                 struct platform_device *op = of_find_device_by_node(dp);
669 
670                 sbus_iommu_init(op);
671                 of_propagate_archdata(op);
672         }
673 
674         return 0;
675 }
676 
677 subsys_initcall(sbus_init);
678 

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