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Linux/arch/sparc/kernel/sun4m_smp.c

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  1 /*
  2  *  sun4m SMP support.
  3  *
  4  * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
  5  */
  6 
  7 #include <linux/clockchips.h>
  8 #include <linux/interrupt.h>
  9 #include <linux/profile.h>
 10 #include <linux/delay.h>
 11 #include <linux/sched.h>
 12 #include <linux/cpu.h>
 13 
 14 #include <asm/cacheflush.h>
 15 #include <asm/switch_to.h>
 16 #include <asm/tlbflush.h>
 17 #include <asm/timer.h>
 18 #include <asm/oplib.h>
 19 
 20 #include "irq.h"
 21 #include "kernel.h"
 22 
 23 #define IRQ_IPI_SINGLE          12
 24 #define IRQ_IPI_MASK            13
 25 #define IRQ_IPI_RESCHED         14
 26 #define IRQ_CROSS_CALL          15
 27 
 28 static inline unsigned long
 29 swap_ulong(volatile unsigned long *ptr, unsigned long val)
 30 {
 31         __asm__ __volatile__("swap [%1], %0\n\t" :
 32                              "=&r" (val), "=&r" (ptr) :
 33                              "" (val), "1" (ptr));
 34         return val;
 35 }
 36 
 37 void __cpuinit smp4m_callin(void)
 38 {
 39         int cpuid = hard_smp_processor_id();
 40 
 41         local_ops->cache_all();
 42         local_ops->tlb_all();
 43 
 44         notify_cpu_starting(cpuid);
 45 
 46         register_percpu_ce(cpuid);
 47 
 48         calibrate_delay();
 49         smp_store_cpu_info(cpuid);
 50 
 51         local_ops->cache_all();
 52         local_ops->tlb_all();
 53 
 54         /*
 55          * Unblock the master CPU _only_ when the scheduler state
 56          * of all secondary CPUs will be up-to-date, so after
 57          * the SMP initialization the master will be just allowed
 58          * to call the scheduler code.
 59          */
 60         /* Allow master to continue. */
 61         swap_ulong(&cpu_callin_map[cpuid], 1);
 62 
 63         /* XXX: What's up with all the flushes? */
 64         local_ops->cache_all();
 65         local_ops->tlb_all();
 66 
 67         /* Fix idle thread fields. */
 68         __asm__ __volatile__("ld [%0], %%g6\n\t"
 69                              : : "r" (&current_set[cpuid])
 70                              : "memory" /* paranoid */);
 71 
 72         /* Attach to the address space of init_task. */
 73         atomic_inc(&init_mm.mm_count);
 74         current->active_mm = &init_mm;
 75 
 76         while (!cpumask_test_cpu(cpuid, &smp_commenced_mask))
 77                 mb();
 78 
 79         local_irq_enable();
 80 
 81         set_cpu_online(cpuid, true);
 82 }
 83 
 84 /*
 85  *      Cycle through the processors asking the PROM to start each one.
 86  */
 87 void __init smp4m_boot_cpus(void)
 88 {
 89         sun4m_unmask_profile_irq();
 90         local_ops->cache_all();
 91 }
 92 
 93 int __cpuinit smp4m_boot_one_cpu(int i, struct task_struct *idle)
 94 {
 95         unsigned long *entry = &sun4m_cpu_startup;
 96         int timeout;
 97         int cpu_node;
 98 
 99         cpu_find_by_mid(i, &cpu_node);
100         current_set[i] = task_thread_info(idle);
101 
102         /* See trampoline.S for details... */
103         entry += ((i - 1) * 3);
104 
105         /*
106          * Initialize the contexts table
107          * Since the call to prom_startcpu() trashes the structure,
108          * we need to re-initialize it for each cpu
109          */
110         smp_penguin_ctable.which_io = 0;
111         smp_penguin_ctable.phys_addr = (unsigned int) srmmu_ctx_table_phys;
112         smp_penguin_ctable.reg_size = 0;
113 
114         /* whirrr, whirrr, whirrrrrrrrr... */
115         printk(KERN_INFO "Starting CPU %d at %p\n", i, entry);
116         local_ops->cache_all();
117         prom_startcpu(cpu_node, &smp_penguin_ctable, 0, (char *)entry);
118 
119         /* wheee... it's going... */
120         for (timeout = 0; timeout < 10000; timeout++) {
121                 if (cpu_callin_map[i])
122                         break;
123                 udelay(200);
124         }
125 
126         if (!(cpu_callin_map[i])) {
127                 printk(KERN_ERR "Processor %d is stuck.\n", i);
128                 return -ENODEV;
129         }
130 
131         local_ops->cache_all();
132         return 0;
133 }
134 
135 void __init smp4m_smp_done(void)
136 {
137         int i, first;
138         int *prev;
139 
140         /* setup cpu list for irq rotation */
141         first = 0;
142         prev = &first;
143         for_each_online_cpu(i) {
144                 *prev = i;
145                 prev = &cpu_data(i).next;
146         }
147         *prev = first;
148         local_ops->cache_all();
149 
150         /* Ok, they are spinning and ready to go. */
151 }
152 
153 static void sun4m_send_ipi(int cpu, int level)
154 {
155         sbus_writel(SUN4M_SOFT_INT(level), &sun4m_irq_percpu[cpu]->set);
156 }
157 
158 static void sun4m_ipi_resched(int cpu)
159 {
160         sun4m_send_ipi(cpu, IRQ_IPI_RESCHED);
161 }
162 
163 static void sun4m_ipi_single(int cpu)
164 {
165         sun4m_send_ipi(cpu, IRQ_IPI_SINGLE);
166 }
167 
168 static void sun4m_ipi_mask_one(int cpu)
169 {
170         sun4m_send_ipi(cpu, IRQ_IPI_MASK);
171 }
172 
173 static struct smp_funcall {
174         smpfunc_t func;
175         unsigned long arg1;
176         unsigned long arg2;
177         unsigned long arg3;
178         unsigned long arg4;
179         unsigned long arg5;
180         unsigned long processors_in[SUN4M_NCPUS];  /* Set when ipi entered. */
181         unsigned long processors_out[SUN4M_NCPUS]; /* Set when ipi exited. */
182 } ccall_info;
183 
184 static DEFINE_SPINLOCK(cross_call_lock);
185 
186 /* Cross calls must be serialized, at least currently. */
187 static void sun4m_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1,
188                              unsigned long arg2, unsigned long arg3,
189                              unsigned long arg4)
190 {
191                 register int ncpus = SUN4M_NCPUS;
192                 unsigned long flags;
193 
194                 spin_lock_irqsave(&cross_call_lock, flags);
195 
196                 /* Init function glue. */
197                 ccall_info.func = func;
198                 ccall_info.arg1 = arg1;
199                 ccall_info.arg2 = arg2;
200                 ccall_info.arg3 = arg3;
201                 ccall_info.arg4 = arg4;
202                 ccall_info.arg5 = 0;
203 
204                 /* Init receive/complete mapping, plus fire the IPI's off. */
205                 {
206                         register int i;
207 
208                         cpumask_clear_cpu(smp_processor_id(), &mask);
209                         cpumask_and(&mask, cpu_online_mask, &mask);
210                         for (i = 0; i < ncpus; i++) {
211                                 if (cpumask_test_cpu(i, &mask)) {
212                                         ccall_info.processors_in[i] = 0;
213                                         ccall_info.processors_out[i] = 0;
214                                         sun4m_send_ipi(i, IRQ_CROSS_CALL);
215                                 } else {
216                                         ccall_info.processors_in[i] = 1;
217                                         ccall_info.processors_out[i] = 1;
218                                 }
219                         }
220                 }
221 
222                 {
223                         register int i;
224 
225                         i = 0;
226                         do {
227                                 if (!cpumask_test_cpu(i, &mask))
228                                         continue;
229                                 while (!ccall_info.processors_in[i])
230                                         barrier();
231                         } while (++i < ncpus);
232 
233                         i = 0;
234                         do {
235                                 if (!cpumask_test_cpu(i, &mask))
236                                         continue;
237                                 while (!ccall_info.processors_out[i])
238                                         barrier();
239                         } while (++i < ncpus);
240                 }
241                 spin_unlock_irqrestore(&cross_call_lock, flags);
242 }
243 
244 /* Running cross calls. */
245 void smp4m_cross_call_irq(void)
246 {
247         int i = smp_processor_id();
248 
249         ccall_info.processors_in[i] = 1;
250         ccall_info.func(ccall_info.arg1, ccall_info.arg2, ccall_info.arg3,
251                         ccall_info.arg4, ccall_info.arg5);
252         ccall_info.processors_out[i] = 1;
253 }
254 
255 void smp4m_percpu_timer_interrupt(struct pt_regs *regs)
256 {
257         struct pt_regs *old_regs;
258         struct clock_event_device *ce;
259         int cpu = smp_processor_id();
260 
261         old_regs = set_irq_regs(regs);
262 
263         ce = &per_cpu(sparc32_clockevent, cpu);
264 
265         if (ce->mode & CLOCK_EVT_MODE_PERIODIC)
266                 sun4m_clear_profile_irq(cpu);
267         else
268                 sparc_config.load_profile_irq(cpu, 0); /* Is this needless? */
269 
270         irq_enter();
271         ce->event_handler(ce);
272         irq_exit();
273 
274         set_irq_regs(old_regs);
275 }
276 
277 static const struct sparc32_ipi_ops sun4m_ipi_ops = {
278         .cross_call = sun4m_cross_call,
279         .resched    = sun4m_ipi_resched,
280         .single     = sun4m_ipi_single,
281         .mask_one   = sun4m_ipi_mask_one,
282 };
283 
284 void __init sun4m_init_smp(void)
285 {
286         sparc32_ipi_ops = &sun4m_ipi_ops;
287 }
288 

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