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TOMOYO Linux Cross Reference
Linux/arch/sparc/kernel/traps_64.c

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  1 /* arch/sparc64/kernel/traps.c
  2  *
  3  * Copyright (C) 1995,1997,2008,2009,2012 David S. Miller (davem@davemloft.net)
  4  * Copyright (C) 1997,1999,2000 Jakub Jelinek (jakub@redhat.com)
  5  */
  6 
  7 /*
  8  * I like traps on v9, :))))
  9  */
 10 
 11 #include <linux/extable.h>
 12 #include <linux/sched/mm.h>
 13 #include <linux/sched/debug.h>
 14 #include <linux/linkage.h>
 15 #include <linux/kernel.h>
 16 #include <linux/signal.h>
 17 #include <linux/smp.h>
 18 #include <linux/mm.h>
 19 #include <linux/init.h>
 20 #include <linux/kdebug.h>
 21 #include <linux/ftrace.h>
 22 #include <linux/reboot.h>
 23 #include <linux/gfp.h>
 24 #include <linux/context_tracking.h>
 25 
 26 #include <asm/smp.h>
 27 #include <asm/delay.h>
 28 #include <asm/ptrace.h>
 29 #include <asm/oplib.h>
 30 #include <asm/page.h>
 31 #include <asm/pgtable.h>
 32 #include <asm/unistd.h>
 33 #include <linux/uaccess.h>
 34 #include <asm/fpumacro.h>
 35 #include <asm/lsu.h>
 36 #include <asm/dcu.h>
 37 #include <asm/estate.h>
 38 #include <asm/chafsr.h>
 39 #include <asm/sfafsr.h>
 40 #include <asm/psrcompat.h>
 41 #include <asm/processor.h>
 42 #include <asm/timer.h>
 43 #include <asm/head.h>
 44 #include <asm/prom.h>
 45 #include <asm/memctrl.h>
 46 #include <asm/cacheflush.h>
 47 #include <asm/setup.h>
 48 
 49 #include "entry.h"
 50 #include "kernel.h"
 51 #include "kstack.h"
 52 
 53 /* When an irrecoverable trap occurs at tl > 0, the trap entry
 54  * code logs the trap state registers at every level in the trap
 55  * stack.  It is found at (pt_regs + sizeof(pt_regs)) and the layout
 56  * is as follows:
 57  */
 58 struct tl1_traplog {
 59         struct {
 60                 unsigned long tstate;
 61                 unsigned long tpc;
 62                 unsigned long tnpc;
 63                 unsigned long tt;
 64         } trapstack[4];
 65         unsigned long tl;
 66 };
 67 
 68 static void dump_tl1_traplog(struct tl1_traplog *p)
 69 {
 70         int i, limit;
 71 
 72         printk(KERN_EMERG "TRAPLOG: Error at trap level 0x%lx, "
 73                "dumping track stack.\n", p->tl);
 74 
 75         limit = (tlb_type == hypervisor) ? 2 : 4;
 76         for (i = 0; i < limit; i++) {
 77                 printk(KERN_EMERG
 78                        "TRAPLOG: Trap level %d TSTATE[%016lx] TPC[%016lx] "
 79                        "TNPC[%016lx] TT[%lx]\n",
 80                        i + 1,
 81                        p->trapstack[i].tstate, p->trapstack[i].tpc,
 82                        p->trapstack[i].tnpc, p->trapstack[i].tt);
 83                 printk("TRAPLOG: TPC<%pS>\n", (void *) p->trapstack[i].tpc);
 84         }
 85 }
 86 
 87 void bad_trap(struct pt_regs *regs, long lvl)
 88 {
 89         char buffer[36];
 90 
 91         if (notify_die(DIE_TRAP, "bad trap", regs,
 92                        0, lvl, SIGTRAP) == NOTIFY_STOP)
 93                 return;
 94 
 95         if (lvl < 0x100) {
 96                 sprintf(buffer, "Bad hw trap %lx at tl0\n", lvl);
 97                 die_if_kernel(buffer, regs);
 98         }
 99 
100         lvl -= 0x100;
101         if (regs->tstate & TSTATE_PRIV) {
102                 sprintf(buffer, "Kernel bad sw trap %lx", lvl);
103                 die_if_kernel(buffer, regs);
104         }
105         if (test_thread_flag(TIF_32BIT)) {
106                 regs->tpc &= 0xffffffff;
107                 regs->tnpc &= 0xffffffff;
108         }
109         force_sig_fault(SIGILL, ILL_ILLTRP,
110                         (void __user *)regs->tpc, lvl, current);
111 }
112 
113 void bad_trap_tl1(struct pt_regs *regs, long lvl)
114 {
115         char buffer[36];
116         
117         if (notify_die(DIE_TRAP_TL1, "bad trap tl1", regs,
118                        0, lvl, SIGTRAP) == NOTIFY_STOP)
119                 return;
120 
121         dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
122 
123         sprintf (buffer, "Bad trap %lx at tl>0", lvl);
124         die_if_kernel (buffer, regs);
125 }
126 
127 #ifdef CONFIG_DEBUG_BUGVERBOSE
128 void do_BUG(const char *file, int line)
129 {
130         bust_spinlocks(1);
131         printk("kernel BUG at %s:%d!\n", file, line);
132 }
133 EXPORT_SYMBOL(do_BUG);
134 #endif
135 
136 static DEFINE_SPINLOCK(dimm_handler_lock);
137 static dimm_printer_t dimm_handler;
138 
139 static int sprintf_dimm(int synd_code, unsigned long paddr, char *buf, int buflen)
140 {
141         unsigned long flags;
142         int ret = -ENODEV;
143 
144         spin_lock_irqsave(&dimm_handler_lock, flags);
145         if (dimm_handler) {
146                 ret = dimm_handler(synd_code, paddr, buf, buflen);
147         } else if (tlb_type == spitfire) {
148                 if (prom_getunumber(synd_code, paddr, buf, buflen) == -1)
149                         ret = -EINVAL;
150                 else
151                         ret = 0;
152         } else
153                 ret = -ENODEV;
154         spin_unlock_irqrestore(&dimm_handler_lock, flags);
155 
156         return ret;
157 }
158 
159 int register_dimm_printer(dimm_printer_t func)
160 {
161         unsigned long flags;
162         int ret = 0;
163 
164         spin_lock_irqsave(&dimm_handler_lock, flags);
165         if (!dimm_handler)
166                 dimm_handler = func;
167         else
168                 ret = -EEXIST;
169         spin_unlock_irqrestore(&dimm_handler_lock, flags);
170 
171         return ret;
172 }
173 EXPORT_SYMBOL_GPL(register_dimm_printer);
174 
175 void unregister_dimm_printer(dimm_printer_t func)
176 {
177         unsigned long flags;
178 
179         spin_lock_irqsave(&dimm_handler_lock, flags);
180         if (dimm_handler == func)
181                 dimm_handler = NULL;
182         spin_unlock_irqrestore(&dimm_handler_lock, flags);
183 }
184 EXPORT_SYMBOL_GPL(unregister_dimm_printer);
185 
186 void spitfire_insn_access_exception(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)
187 {
188         enum ctx_state prev_state = exception_enter();
189 
190         if (notify_die(DIE_TRAP, "instruction access exception", regs,
191                        0, 0x8, SIGTRAP) == NOTIFY_STOP)
192                 goto out;
193 
194         if (regs->tstate & TSTATE_PRIV) {
195                 printk("spitfire_insn_access_exception: SFSR[%016lx] "
196                        "SFAR[%016lx], going.\n", sfsr, sfar);
197                 die_if_kernel("Iax", regs);
198         }
199         if (test_thread_flag(TIF_32BIT)) {
200                 regs->tpc &= 0xffffffff;
201                 regs->tnpc &= 0xffffffff;
202         }
203         force_sig_fault(SIGSEGV, SEGV_MAPERR,
204                         (void __user *)regs->tpc, 0, current);
205 out:
206         exception_exit(prev_state);
207 }
208 
209 void spitfire_insn_access_exception_tl1(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)
210 {
211         if (notify_die(DIE_TRAP_TL1, "instruction access exception tl1", regs,
212                        0, 0x8, SIGTRAP) == NOTIFY_STOP)
213                 return;
214 
215         dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
216         spitfire_insn_access_exception(regs, sfsr, sfar);
217 }
218 
219 void sun4v_insn_access_exception(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
220 {
221         unsigned short type = (type_ctx >> 16);
222         unsigned short ctx  = (type_ctx & 0xffff);
223 
224         if (notify_die(DIE_TRAP, "instruction access exception", regs,
225                        0, 0x8, SIGTRAP) == NOTIFY_STOP)
226                 return;
227 
228         if (regs->tstate & TSTATE_PRIV) {
229                 printk("sun4v_insn_access_exception: ADDR[%016lx] "
230                        "CTX[%04x] TYPE[%04x], going.\n",
231                        addr, ctx, type);
232                 die_if_kernel("Iax", regs);
233         }
234 
235         if (test_thread_flag(TIF_32BIT)) {
236                 regs->tpc &= 0xffffffff;
237                 regs->tnpc &= 0xffffffff;
238         }
239         force_sig_fault(SIGSEGV, SEGV_MAPERR, (void __user *) addr, 0, current);
240 }
241 
242 void sun4v_insn_access_exception_tl1(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
243 {
244         if (notify_die(DIE_TRAP_TL1, "instruction access exception tl1", regs,
245                        0, 0x8, SIGTRAP) == NOTIFY_STOP)
246                 return;
247 
248         dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
249         sun4v_insn_access_exception(regs, addr, type_ctx);
250 }
251 
252 bool is_no_fault_exception(struct pt_regs *regs)
253 {
254         unsigned char asi;
255         u32 insn;
256 
257         if (get_user(insn, (u32 __user *)regs->tpc) == -EFAULT)
258                 return false;
259 
260         /*
261          * Must do a little instruction decoding here in order to
262          * decide on a course of action. The bits of interest are:
263          *  insn[31:30] = op, where 3 indicates the load/store group
264          *  insn[24:19] = op3, which identifies individual opcodes
265          *  insn[13] indicates an immediate offset
266          *  op3[4]=1 identifies alternate space instructions
267          *  op3[5:4]=3 identifies floating point instructions
268          *  op3[2]=1 identifies stores
269          * See "Opcode Maps" in the appendix of any Sparc V9
270          * architecture spec for full details.
271          */
272         if ((insn & 0xc0800000) == 0xc0800000) {    /* op=3, op3[4]=1   */
273                 if (insn & 0x2000)                  /* immediate offset */
274                         asi = (regs->tstate >> 24); /* saved %asi       */
275                 else
276                         asi = (insn >> 5);          /* immediate asi    */
277                 if ((asi & 0xf2) == ASI_PNF) {
278                         if (insn & 0x1000000) {     /* op3[5:4]=3       */
279                                 handle_ldf_stq(insn, regs);
280                                 return true;
281                         } else if (insn & 0x200000) { /* op3[2], stores */
282                                 return false;
283                         }
284                         handle_ld_nf(insn, regs);
285                         return true;
286                 }
287         }
288         return false;
289 }
290 
291 void spitfire_data_access_exception(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)
292 {
293         enum ctx_state prev_state = exception_enter();
294 
295         if (notify_die(DIE_TRAP, "data access exception", regs,
296                        0, 0x30, SIGTRAP) == NOTIFY_STOP)
297                 goto out;
298 
299         if (regs->tstate & TSTATE_PRIV) {
300                 /* Test if this comes from uaccess places. */
301                 const struct exception_table_entry *entry;
302 
303                 entry = search_exception_tables(regs->tpc);
304                 if (entry) {
305                         /* Ouch, somebody is trying VM hole tricks on us... */
306 #ifdef DEBUG_EXCEPTIONS
307                         printk("Exception: PC<%016lx> faddr<UNKNOWN>\n", regs->tpc);
308                         printk("EX_TABLE: insn<%016lx> fixup<%016lx>\n",
309                                regs->tpc, entry->fixup);
310 #endif
311                         regs->tpc = entry->fixup;
312                         regs->tnpc = regs->tpc + 4;
313                         goto out;
314                 }
315                 /* Shit... */
316                 printk("spitfire_data_access_exception: SFSR[%016lx] "
317                        "SFAR[%016lx], going.\n", sfsr, sfar);
318                 die_if_kernel("Dax", regs);
319         }
320 
321         if (is_no_fault_exception(regs))
322                 return;
323 
324         force_sig_fault(SIGSEGV, SEGV_MAPERR, (void __user *)sfar, 0, current);
325 out:
326         exception_exit(prev_state);
327 }
328 
329 void spitfire_data_access_exception_tl1(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)
330 {
331         if (notify_die(DIE_TRAP_TL1, "data access exception tl1", regs,
332                        0, 0x30, SIGTRAP) == NOTIFY_STOP)
333                 return;
334 
335         dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
336         spitfire_data_access_exception(regs, sfsr, sfar);
337 }
338 
339 void sun4v_data_access_exception(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
340 {
341         unsigned short type = (type_ctx >> 16);
342         unsigned short ctx  = (type_ctx & 0xffff);
343 
344         if (notify_die(DIE_TRAP, "data access exception", regs,
345                        0, 0x8, SIGTRAP) == NOTIFY_STOP)
346                 return;
347 
348         if (regs->tstate & TSTATE_PRIV) {
349                 /* Test if this comes from uaccess places. */
350                 const struct exception_table_entry *entry;
351 
352                 entry = search_exception_tables(regs->tpc);
353                 if (entry) {
354                         /* Ouch, somebody is trying VM hole tricks on us... */
355 #ifdef DEBUG_EXCEPTIONS
356                         printk("Exception: PC<%016lx> faddr<UNKNOWN>\n", regs->tpc);
357                         printk("EX_TABLE: insn<%016lx> fixup<%016lx>\n",
358                                regs->tpc, entry->fixup);
359 #endif
360                         regs->tpc = entry->fixup;
361                         regs->tnpc = regs->tpc + 4;
362                         return;
363                 }
364                 printk("sun4v_data_access_exception: ADDR[%016lx] "
365                        "CTX[%04x] TYPE[%04x], going.\n",
366                        addr, ctx, type);
367                 die_if_kernel("Dax", regs);
368         }
369 
370         if (test_thread_flag(TIF_32BIT)) {
371                 regs->tpc &= 0xffffffff;
372                 regs->tnpc &= 0xffffffff;
373         }
374         if (is_no_fault_exception(regs))
375                 return;
376 
377         /* MCD (Memory Corruption Detection) disabled trap (TT=0x19) in HV
378          * is vectored thorugh data access exception trap with fault type
379          * set to HV_FAULT_TYPE_MCD_DIS. Check for MCD disabled trap.
380          * Accessing an address with invalid ASI for the address, for
381          * example setting an ADI tag on an address with ASI_MCD_PRIMARY
382          * when TTE.mcd is not set for the VA, is also vectored into
383          * kerbel by HV as data access exception with fault type set to
384          * HV_FAULT_TYPE_INV_ASI.
385          */
386         switch (type) {
387         case HV_FAULT_TYPE_INV_ASI:
388                 force_sig_fault(SIGILL, ILL_ILLADR, (void __user *)addr, 0,
389                                 current);
390                 break;
391         case HV_FAULT_TYPE_MCD_DIS:
392                 force_sig_fault(SIGSEGV, SEGV_ACCADI, (void __user *)addr, 0,
393                                 current);
394                 break;
395         default:
396                 force_sig_fault(SIGSEGV, SEGV_MAPERR, (void __user *)addr, 0,
397                                 current);
398                 break;
399         }
400 }
401 
402 void sun4v_data_access_exception_tl1(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
403 {
404         if (notify_die(DIE_TRAP_TL1, "data access exception tl1", regs,
405                        0, 0x8, SIGTRAP) == NOTIFY_STOP)
406                 return;
407 
408         dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
409         sun4v_data_access_exception(regs, addr, type_ctx);
410 }
411 
412 #ifdef CONFIG_PCI
413 #include "pci_impl.h"
414 #endif
415 
416 /* When access exceptions happen, we must do this. */
417 static void spitfire_clean_and_reenable_l1_caches(void)
418 {
419         unsigned long va;
420 
421         if (tlb_type != spitfire)
422                 BUG();
423 
424         /* Clean 'em. */
425         for (va =  0; va < (PAGE_SIZE << 1); va += 32) {
426                 spitfire_put_icache_tag(va, 0x0);
427                 spitfire_put_dcache_tag(va, 0x0);
428         }
429 
430         /* Re-enable in LSU. */
431         __asm__ __volatile__("flush %%g6\n\t"
432                              "membar #Sync\n\t"
433                              "stxa %0, [%%g0] %1\n\t"
434                              "membar #Sync"
435                              : /* no outputs */
436                              : "r" (LSU_CONTROL_IC | LSU_CONTROL_DC |
437                                     LSU_CONTROL_IM | LSU_CONTROL_DM),
438                              "i" (ASI_LSU_CONTROL)
439                              : "memory");
440 }
441 
442 static void spitfire_enable_estate_errors(void)
443 {
444         __asm__ __volatile__("stxa      %0, [%%g0] %1\n\t"
445                              "membar    #Sync"
446                              : /* no outputs */
447                              : "r" (ESTATE_ERR_ALL),
448                                "i" (ASI_ESTATE_ERROR_EN));
449 }
450 
451 static char ecc_syndrome_table[] = {
452         0x4c, 0x40, 0x41, 0x48, 0x42, 0x48, 0x48, 0x49,
453         0x43, 0x48, 0x48, 0x49, 0x48, 0x49, 0x49, 0x4a,
454         0x44, 0x48, 0x48, 0x20, 0x48, 0x39, 0x4b, 0x48,
455         0x48, 0x25, 0x31, 0x48, 0x28, 0x48, 0x48, 0x2c,
456         0x45, 0x48, 0x48, 0x21, 0x48, 0x3d, 0x04, 0x48,
457         0x48, 0x4b, 0x35, 0x48, 0x2d, 0x48, 0x48, 0x29,
458         0x48, 0x00, 0x01, 0x48, 0x0a, 0x48, 0x48, 0x4b,
459         0x0f, 0x48, 0x48, 0x4b, 0x48, 0x49, 0x49, 0x48,
460         0x46, 0x48, 0x48, 0x2a, 0x48, 0x3b, 0x27, 0x48,
461         0x48, 0x4b, 0x33, 0x48, 0x22, 0x48, 0x48, 0x2e,
462         0x48, 0x19, 0x1d, 0x48, 0x1b, 0x4a, 0x48, 0x4b,
463         0x1f, 0x48, 0x4a, 0x4b, 0x48, 0x4b, 0x4b, 0x48,
464         0x48, 0x4b, 0x24, 0x48, 0x07, 0x48, 0x48, 0x36,
465         0x4b, 0x48, 0x48, 0x3e, 0x48, 0x30, 0x38, 0x48,
466         0x49, 0x48, 0x48, 0x4b, 0x48, 0x4b, 0x16, 0x48,
467         0x48, 0x12, 0x4b, 0x48, 0x49, 0x48, 0x48, 0x4b,
468         0x47, 0x48, 0x48, 0x2f, 0x48, 0x3f, 0x4b, 0x48,
469         0x48, 0x06, 0x37, 0x48, 0x23, 0x48, 0x48, 0x2b,
470         0x48, 0x05, 0x4b, 0x48, 0x4b, 0x48, 0x48, 0x32,
471         0x26, 0x48, 0x48, 0x3a, 0x48, 0x34, 0x3c, 0x48,
472         0x48, 0x11, 0x15, 0x48, 0x13, 0x4a, 0x48, 0x4b,
473         0x17, 0x48, 0x4a, 0x4b, 0x48, 0x4b, 0x4b, 0x48,
474         0x49, 0x48, 0x48, 0x4b, 0x48, 0x4b, 0x1e, 0x48,
475         0x48, 0x1a, 0x4b, 0x48, 0x49, 0x48, 0x48, 0x4b,
476         0x48, 0x08, 0x0d, 0x48, 0x02, 0x48, 0x48, 0x49,
477         0x03, 0x48, 0x48, 0x49, 0x48, 0x4b, 0x4b, 0x48,
478         0x49, 0x48, 0x48, 0x49, 0x48, 0x4b, 0x10, 0x48,
479         0x48, 0x14, 0x4b, 0x48, 0x4b, 0x48, 0x48, 0x4b,
480         0x49, 0x48, 0x48, 0x49, 0x48, 0x4b, 0x18, 0x48,
481         0x48, 0x1c, 0x4b, 0x48, 0x4b, 0x48, 0x48, 0x4b,
482         0x4a, 0x0c, 0x09, 0x48, 0x0e, 0x48, 0x48, 0x4b,
483         0x0b, 0x48, 0x48, 0x4b, 0x48, 0x4b, 0x4b, 0x4a
484 };
485 
486 static char *syndrome_unknown = "<Unknown>";
487 
488 static void spitfire_log_udb_syndrome(unsigned long afar, unsigned long udbh, unsigned long udbl, unsigned long bit)
489 {
490         unsigned short scode;
491         char memmod_str[64], *p;
492 
493         if (udbl & bit) {
494                 scode = ecc_syndrome_table[udbl & 0xff];
495                 if (sprintf_dimm(scode, afar, memmod_str, sizeof(memmod_str)) < 0)
496                         p = syndrome_unknown;
497                 else
498                         p = memmod_str;
499                 printk(KERN_WARNING "CPU[%d]: UDBL Syndrome[%x] "
500                        "Memory Module \"%s\"\n",
501                        smp_processor_id(), scode, p);
502         }
503 
504         if (udbh & bit) {
505                 scode = ecc_syndrome_table[udbh & 0xff];
506                 if (sprintf_dimm(scode, afar, memmod_str, sizeof(memmod_str)) < 0)
507                         p = syndrome_unknown;
508                 else
509                         p = memmod_str;
510                 printk(KERN_WARNING "CPU[%d]: UDBH Syndrome[%x] "
511                        "Memory Module \"%s\"\n",
512                        smp_processor_id(), scode, p);
513         }
514 
515 }
516 
517 static void spitfire_cee_log(unsigned long afsr, unsigned long afar, unsigned long udbh, unsigned long udbl, int tl1, struct pt_regs *regs)
518 {
519 
520         printk(KERN_WARNING "CPU[%d]: Correctable ECC Error "
521                "AFSR[%lx] AFAR[%016lx] UDBL[%lx] UDBH[%lx] TL>1[%d]\n",
522                smp_processor_id(), afsr, afar, udbl, udbh, tl1);
523 
524         spitfire_log_udb_syndrome(afar, udbh, udbl, UDBE_CE);
525 
526         /* We always log it, even if someone is listening for this
527          * trap.
528          */
529         notify_die(DIE_TRAP, "Correctable ECC Error", regs,
530                    0, TRAP_TYPE_CEE, SIGTRAP);
531 
532         /* The Correctable ECC Error trap does not disable I/D caches.  So
533          * we only have to restore the ESTATE Error Enable register.
534          */
535         spitfire_enable_estate_errors();
536 }
537 
538 static void spitfire_ue_log(unsigned long afsr, unsigned long afar, unsigned long udbh, unsigned long udbl, unsigned long tt, int tl1, struct pt_regs *regs)
539 {
540         printk(KERN_WARNING "CPU[%d]: Uncorrectable Error AFSR[%lx] "
541                "AFAR[%lx] UDBL[%lx] UDBH[%ld] TT[%lx] TL>1[%d]\n",
542                smp_processor_id(), afsr, afar, udbl, udbh, tt, tl1);
543 
544         /* XXX add more human friendly logging of the error status
545          * XXX as is implemented for cheetah
546          */
547 
548         spitfire_log_udb_syndrome(afar, udbh, udbl, UDBE_UE);
549 
550         /* We always log it, even if someone is listening for this
551          * trap.
552          */
553         notify_die(DIE_TRAP, "Uncorrectable Error", regs,
554                    0, tt, SIGTRAP);
555 
556         if (regs->tstate & TSTATE_PRIV) {
557                 if (tl1)
558                         dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
559                 die_if_kernel("UE", regs);
560         }
561 
562         /* XXX need more intelligent processing here, such as is implemented
563          * XXX for cheetah errors, in fact if the E-cache still holds the
564          * XXX line with bad parity this will loop
565          */
566 
567         spitfire_clean_and_reenable_l1_caches();
568         spitfire_enable_estate_errors();
569 
570         if (test_thread_flag(TIF_32BIT)) {
571                 regs->tpc &= 0xffffffff;
572                 regs->tnpc &= 0xffffffff;
573         }
574         force_sig_fault(SIGBUS, BUS_OBJERR, (void *)0, 0, current);
575 }
576 
577 void spitfire_access_error(struct pt_regs *regs, unsigned long status_encoded, unsigned long afar)
578 {
579         unsigned long afsr, tt, udbh, udbl;
580         int tl1;
581 
582         afsr = (status_encoded & SFSTAT_AFSR_MASK) >> SFSTAT_AFSR_SHIFT;
583         tt = (status_encoded & SFSTAT_TRAP_TYPE) >> SFSTAT_TRAP_TYPE_SHIFT;
584         tl1 = (status_encoded & SFSTAT_TL_GT_ONE) ? 1 : 0;
585         udbl = (status_encoded & SFSTAT_UDBL_MASK) >> SFSTAT_UDBL_SHIFT;
586         udbh = (status_encoded & SFSTAT_UDBH_MASK) >> SFSTAT_UDBH_SHIFT;
587 
588 #ifdef CONFIG_PCI
589         if (tt == TRAP_TYPE_DAE &&
590             pci_poke_in_progress && pci_poke_cpu == smp_processor_id()) {
591                 spitfire_clean_and_reenable_l1_caches();
592                 spitfire_enable_estate_errors();
593 
594                 pci_poke_faulted = 1;
595                 regs->tnpc = regs->tpc + 4;
596                 return;
597         }
598 #endif
599 
600         if (afsr & SFAFSR_UE)
601                 spitfire_ue_log(afsr, afar, udbh, udbl, tt, tl1, regs);
602 
603         if (tt == TRAP_TYPE_CEE) {
604                 /* Handle the case where we took a CEE trap, but ACK'd
605                  * only the UE state in the UDB error registers.
606                  */
607                 if (afsr & SFAFSR_UE) {
608                         if (udbh & UDBE_CE) {
609                                 __asm__ __volatile__(
610                                         "stxa   %0, [%1] %2\n\t"
611                                         "membar #Sync"
612                                         : /* no outputs */
613                                         : "r" (udbh & UDBE_CE),
614                                           "r" (0x0), "i" (ASI_UDB_ERROR_W));
615                         }
616                         if (udbl & UDBE_CE) {
617                                 __asm__ __volatile__(
618                                         "stxa   %0, [%1] %2\n\t"
619                                         "membar #Sync"
620                                         : /* no outputs */
621                                         : "r" (udbl & UDBE_CE),
622                                           "r" (0x18), "i" (ASI_UDB_ERROR_W));
623                         }
624                 }
625 
626                 spitfire_cee_log(afsr, afar, udbh, udbl, tl1, regs);
627         }
628 }
629 
630 int cheetah_pcache_forced_on;
631 
632 void cheetah_enable_pcache(void)
633 {
634         unsigned long dcr;
635 
636         printk("CHEETAH: Enabling P-Cache on cpu %d.\n",
637                smp_processor_id());
638 
639         __asm__ __volatile__("ldxa [%%g0] %1, %0"
640                              : "=r" (dcr)
641                              : "i" (ASI_DCU_CONTROL_REG));
642         dcr |= (DCU_PE | DCU_HPE | DCU_SPE | DCU_SL);
643         __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
644                              "membar #Sync"
645                              : /* no outputs */
646                              : "r" (dcr), "i" (ASI_DCU_CONTROL_REG));
647 }
648 
649 /* Cheetah error trap handling. */
650 static unsigned long ecache_flush_physbase;
651 static unsigned long ecache_flush_linesize;
652 static unsigned long ecache_flush_size;
653 
654 /* This table is ordered in priority of errors and matches the
655  * AFAR overwrite policy as well.
656  */
657 
658 struct afsr_error_table {
659         unsigned long mask;
660         const char *name;
661 };
662 
663 static const char CHAFSR_PERR_msg[] =
664         "System interface protocol error";
665 static const char CHAFSR_IERR_msg[] =
666         "Internal processor error";
667 static const char CHAFSR_ISAP_msg[] =
668         "System request parity error on incoming address";
669 static const char CHAFSR_UCU_msg[] =
670         "Uncorrectable E-cache ECC error for ifetch/data";
671 static const char CHAFSR_UCC_msg[] =
672         "SW Correctable E-cache ECC error for ifetch/data";
673 static const char CHAFSR_UE_msg[] =
674         "Uncorrectable system bus data ECC error for read";
675 static const char CHAFSR_EDU_msg[] =
676         "Uncorrectable E-cache ECC error for stmerge/blkld";
677 static const char CHAFSR_EMU_msg[] =
678         "Uncorrectable system bus MTAG error";
679 static const char CHAFSR_WDU_msg[] =
680         "Uncorrectable E-cache ECC error for writeback";
681 static const char CHAFSR_CPU_msg[] =
682         "Uncorrectable ECC error for copyout";
683 static const char CHAFSR_CE_msg[] =
684         "HW corrected system bus data ECC error for read";
685 static const char CHAFSR_EDC_msg[] =
686         "HW corrected E-cache ECC error for stmerge/blkld";
687 static const char CHAFSR_EMC_msg[] =
688         "HW corrected system bus MTAG ECC error";
689 static const char CHAFSR_WDC_msg[] =
690         "HW corrected E-cache ECC error for writeback";
691 static const char CHAFSR_CPC_msg[] =
692         "HW corrected ECC error for copyout";
693 static const char CHAFSR_TO_msg[] =
694         "Unmapped error from system bus";
695 static const char CHAFSR_BERR_msg[] =
696         "Bus error response from system bus";
697 static const char CHAFSR_IVC_msg[] =
698         "HW corrected system bus data ECC error for ivec read";
699 static const char CHAFSR_IVU_msg[] =
700         "Uncorrectable system bus data ECC error for ivec read";
701 static struct afsr_error_table __cheetah_error_table[] = {
702         {       CHAFSR_PERR,    CHAFSR_PERR_msg         },
703         {       CHAFSR_IERR,    CHAFSR_IERR_msg         },
704         {       CHAFSR_ISAP,    CHAFSR_ISAP_msg         },
705         {       CHAFSR_UCU,     CHAFSR_UCU_msg          },
706         {       CHAFSR_UCC,     CHAFSR_UCC_msg          },
707         {       CHAFSR_UE,      CHAFSR_UE_msg           },
708         {       CHAFSR_EDU,     CHAFSR_EDU_msg          },
709         {       CHAFSR_EMU,     CHAFSR_EMU_msg          },
710         {       CHAFSR_WDU,     CHAFSR_WDU_msg          },
711         {       CHAFSR_CPU,     CHAFSR_CPU_msg          },
712         {       CHAFSR_CE,      CHAFSR_CE_msg           },
713         {       CHAFSR_EDC,     CHAFSR_EDC_msg          },
714         {       CHAFSR_EMC,     CHAFSR_EMC_msg          },
715         {       CHAFSR_WDC,     CHAFSR_WDC_msg          },
716         {       CHAFSR_CPC,     CHAFSR_CPC_msg          },
717         {       CHAFSR_TO,      CHAFSR_TO_msg           },
718         {       CHAFSR_BERR,    CHAFSR_BERR_msg         },
719         /* These two do not update the AFAR. */
720         {       CHAFSR_IVC,     CHAFSR_IVC_msg          },
721         {       CHAFSR_IVU,     CHAFSR_IVU_msg          },
722         {       0,              NULL                    },
723 };
724 static const char CHPAFSR_DTO_msg[] =
725         "System bus unmapped error for prefetch/storequeue-read";
726 static const char CHPAFSR_DBERR_msg[] =
727         "System bus error for prefetch/storequeue-read";
728 static const char CHPAFSR_THCE_msg[] =
729         "Hardware corrected E-cache Tag ECC error";
730 static const char CHPAFSR_TSCE_msg[] =
731         "SW handled correctable E-cache Tag ECC error";
732 static const char CHPAFSR_TUE_msg[] =
733         "Uncorrectable E-cache Tag ECC error";
734 static const char CHPAFSR_DUE_msg[] =
735         "System bus uncorrectable data ECC error due to prefetch/store-fill";
736 static struct afsr_error_table __cheetah_plus_error_table[] = {
737         {       CHAFSR_PERR,    CHAFSR_PERR_msg         },
738         {       CHAFSR_IERR,    CHAFSR_IERR_msg         },
739         {       CHAFSR_ISAP,    CHAFSR_ISAP_msg         },
740         {       CHAFSR_UCU,     CHAFSR_UCU_msg          },
741         {       CHAFSR_UCC,     CHAFSR_UCC_msg          },
742         {       CHAFSR_UE,      CHAFSR_UE_msg           },
743         {       CHAFSR_EDU,     CHAFSR_EDU_msg          },
744         {       CHAFSR_EMU,     CHAFSR_EMU_msg          },
745         {       CHAFSR_WDU,     CHAFSR_WDU_msg          },
746         {       CHAFSR_CPU,     CHAFSR_CPU_msg          },
747         {       CHAFSR_CE,      CHAFSR_CE_msg           },
748         {       CHAFSR_EDC,     CHAFSR_EDC_msg          },
749         {       CHAFSR_EMC,     CHAFSR_EMC_msg          },
750         {       CHAFSR_WDC,     CHAFSR_WDC_msg          },
751         {       CHAFSR_CPC,     CHAFSR_CPC_msg          },
752         {       CHAFSR_TO,      CHAFSR_TO_msg           },
753         {       CHAFSR_BERR,    CHAFSR_BERR_msg         },
754         {       CHPAFSR_DTO,    CHPAFSR_DTO_msg         },
755         {       CHPAFSR_DBERR,  CHPAFSR_DBERR_msg       },
756         {       CHPAFSR_THCE,   CHPAFSR_THCE_msg        },
757         {       CHPAFSR_TSCE,   CHPAFSR_TSCE_msg        },
758         {       CHPAFSR_TUE,    CHPAFSR_TUE_msg         },
759         {       CHPAFSR_DUE,    CHPAFSR_DUE_msg         },
760         /* These two do not update the AFAR. */
761         {       CHAFSR_IVC,     CHAFSR_IVC_msg          },
762         {       CHAFSR_IVU,     CHAFSR_IVU_msg          },
763         {       0,              NULL                    },
764 };
765 static const char JPAFSR_JETO_msg[] =
766         "System interface protocol error, hw timeout caused";
767 static const char JPAFSR_SCE_msg[] =
768         "Parity error on system snoop results";
769 static const char JPAFSR_JEIC_msg[] =
770         "System interface protocol error, illegal command detected";
771 static const char JPAFSR_JEIT_msg[] =
772         "System interface protocol error, illegal ADTYPE detected";
773 static const char JPAFSR_OM_msg[] =
774         "Out of range memory error has occurred";
775 static const char JPAFSR_ETP_msg[] =
776         "Parity error on L2 cache tag SRAM";
777 static const char JPAFSR_UMS_msg[] =
778         "Error due to unsupported store";
779 static const char JPAFSR_RUE_msg[] =
780         "Uncorrectable ECC error from remote cache/memory";
781 static const char JPAFSR_RCE_msg[] =
782         "Correctable ECC error from remote cache/memory";
783 static const char JPAFSR_BP_msg[] =
784         "JBUS parity error on returned read data";
785 static const char JPAFSR_WBP_msg[] =
786         "JBUS parity error on data for writeback or block store";
787 static const char JPAFSR_FRC_msg[] =
788         "Foreign read to DRAM incurring correctable ECC error";
789 static const char JPAFSR_FRU_msg[] =
790         "Foreign read to DRAM incurring uncorrectable ECC error";
791 static struct afsr_error_table __jalapeno_error_table[] = {
792         {       JPAFSR_JETO,    JPAFSR_JETO_msg         },
793         {       JPAFSR_SCE,     JPAFSR_SCE_msg          },
794         {       JPAFSR_JEIC,    JPAFSR_JEIC_msg         },
795         {       JPAFSR_JEIT,    JPAFSR_JEIT_msg         },
796         {       CHAFSR_PERR,    CHAFSR_PERR_msg         },
797         {       CHAFSR_IERR,    CHAFSR_IERR_msg         },
798         {       CHAFSR_ISAP,    CHAFSR_ISAP_msg         },
799         {       CHAFSR_UCU,     CHAFSR_UCU_msg          },
800         {       CHAFSR_UCC,     CHAFSR_UCC_msg          },
801         {       CHAFSR_UE,      CHAFSR_UE_msg           },
802         {       CHAFSR_EDU,     CHAFSR_EDU_msg          },
803         {       JPAFSR_OM,      JPAFSR_OM_msg           },
804         {       CHAFSR_WDU,     CHAFSR_WDU_msg          },
805         {       CHAFSR_CPU,     CHAFSR_CPU_msg          },
806         {       CHAFSR_CE,      CHAFSR_CE_msg           },
807         {       CHAFSR_EDC,     CHAFSR_EDC_msg          },
808         {       JPAFSR_ETP,     JPAFSR_ETP_msg          },
809         {       CHAFSR_WDC,     CHAFSR_WDC_msg          },
810         {       CHAFSR_CPC,     CHAFSR_CPC_msg          },
811         {       CHAFSR_TO,      CHAFSR_TO_msg           },
812         {       CHAFSR_BERR,    CHAFSR_BERR_msg         },
813         {       JPAFSR_UMS,     JPAFSR_UMS_msg          },
814         {       JPAFSR_RUE,     JPAFSR_RUE_msg          },
815         {       JPAFSR_RCE,     JPAFSR_RCE_msg          },
816         {       JPAFSR_BP,      JPAFSR_BP_msg           },
817         {       JPAFSR_WBP,     JPAFSR_WBP_msg          },
818         {       JPAFSR_FRC,     JPAFSR_FRC_msg          },
819         {       JPAFSR_FRU,     JPAFSR_FRU_msg          },
820         /* These two do not update the AFAR. */
821         {       CHAFSR_IVU,     CHAFSR_IVU_msg          },
822         {       0,              NULL                    },
823 };
824 static struct afsr_error_table *cheetah_error_table;
825 static unsigned long cheetah_afsr_errors;
826 
827 struct cheetah_err_info *cheetah_error_log;
828 
829 static inline struct cheetah_err_info *cheetah_get_error_log(unsigned long afsr)
830 {
831         struct cheetah_err_info *p;
832         int cpu = smp_processor_id();
833 
834         if (!cheetah_error_log)
835                 return NULL;
836 
837         p = cheetah_error_log + (cpu * 2);
838         if ((afsr & CHAFSR_TL1) != 0UL)
839                 p++;
840 
841         return p;
842 }
843 
844 extern unsigned int tl0_icpe[], tl1_icpe[];
845 extern unsigned int tl0_dcpe[], tl1_dcpe[];
846 extern unsigned int tl0_fecc[], tl1_fecc[];
847 extern unsigned int tl0_cee[], tl1_cee[];
848 extern unsigned int tl0_iae[], tl1_iae[];
849 extern unsigned int tl0_dae[], tl1_dae[];
850 extern unsigned int cheetah_plus_icpe_trap_vector[], cheetah_plus_icpe_trap_vector_tl1[];
851 extern unsigned int cheetah_plus_dcpe_trap_vector[], cheetah_plus_dcpe_trap_vector_tl1[];
852 extern unsigned int cheetah_fecc_trap_vector[], cheetah_fecc_trap_vector_tl1[];
853 extern unsigned int cheetah_cee_trap_vector[], cheetah_cee_trap_vector_tl1[];
854 extern unsigned int cheetah_deferred_trap_vector[], cheetah_deferred_trap_vector_tl1[];
855 
856 void __init cheetah_ecache_flush_init(void)
857 {
858         unsigned long largest_size, smallest_linesize, order, ver;
859         int i, sz;
860 
861         /* Scan all cpu device tree nodes, note two values:
862          * 1) largest E-cache size
863          * 2) smallest E-cache line size
864          */
865         largest_size = 0UL;
866         smallest_linesize = ~0UL;
867 
868         for (i = 0; i < NR_CPUS; i++) {
869                 unsigned long val;
870 
871                 val = cpu_data(i).ecache_size;
872                 if (!val)
873                         continue;
874 
875                 if (val > largest_size)
876                         largest_size = val;
877 
878                 val = cpu_data(i).ecache_line_size;
879                 if (val < smallest_linesize)
880                         smallest_linesize = val;
881 
882         }
883 
884         if (largest_size == 0UL || smallest_linesize == ~0UL) {
885                 prom_printf("cheetah_ecache_flush_init: Cannot probe cpu E-cache "
886                             "parameters.\n");
887                 prom_halt();
888         }
889 
890         ecache_flush_size = (2 * largest_size);
891         ecache_flush_linesize = smallest_linesize;
892 
893         ecache_flush_physbase = find_ecache_flush_span(ecache_flush_size);
894 
895         if (ecache_flush_physbase == ~0UL) {
896                 prom_printf("cheetah_ecache_flush_init: Cannot find %ld byte "
897                             "contiguous physical memory.\n",
898                             ecache_flush_size);
899                 prom_halt();
900         }
901 
902         /* Now allocate error trap reporting scoreboard. */
903         sz = NR_CPUS * (2 * sizeof(struct cheetah_err_info));
904         for (order = 0; order < MAX_ORDER; order++) {
905                 if ((PAGE_SIZE << order) >= sz)
906                         break;
907         }
908         cheetah_error_log = (struct cheetah_err_info *)
909                 __get_free_pages(GFP_KERNEL, order);
910         if (!cheetah_error_log) {
911                 prom_printf("cheetah_ecache_flush_init: Failed to allocate "
912                             "error logging scoreboard (%d bytes).\n", sz);
913                 prom_halt();
914         }
915         memset(cheetah_error_log, 0, PAGE_SIZE << order);
916 
917         /* Mark all AFSRs as invalid so that the trap handler will
918          * log new new information there.
919          */
920         for (i = 0; i < 2 * NR_CPUS; i++)
921                 cheetah_error_log[i].afsr = CHAFSR_INVALID;
922 
923         __asm__ ("rdpr %%ver, %0" : "=r" (ver));
924         if ((ver >> 32) == __JALAPENO_ID ||
925             (ver >> 32) == __SERRANO_ID) {
926                 cheetah_error_table = &__jalapeno_error_table[0];
927                 cheetah_afsr_errors = JPAFSR_ERRORS;
928         } else if ((ver >> 32) == 0x003e0015) {
929                 cheetah_error_table = &__cheetah_plus_error_table[0];
930                 cheetah_afsr_errors = CHPAFSR_ERRORS;
931         } else {
932                 cheetah_error_table = &__cheetah_error_table[0];
933                 cheetah_afsr_errors = CHAFSR_ERRORS;
934         }
935 
936         /* Now patch trap tables. */
937         memcpy(tl0_fecc, cheetah_fecc_trap_vector, (8 * 4));
938         memcpy(tl1_fecc, cheetah_fecc_trap_vector_tl1, (8 * 4));
939         memcpy(tl0_cee, cheetah_cee_trap_vector, (8 * 4));
940         memcpy(tl1_cee, cheetah_cee_trap_vector_tl1, (8 * 4));
941         memcpy(tl0_iae, cheetah_deferred_trap_vector, (8 * 4));
942         memcpy(tl1_iae, cheetah_deferred_trap_vector_tl1, (8 * 4));
943         memcpy(tl0_dae, cheetah_deferred_trap_vector, (8 * 4));
944         memcpy(tl1_dae, cheetah_deferred_trap_vector_tl1, (8 * 4));
945         if (tlb_type == cheetah_plus) {
946                 memcpy(tl0_dcpe, cheetah_plus_dcpe_trap_vector, (8 * 4));
947                 memcpy(tl1_dcpe, cheetah_plus_dcpe_trap_vector_tl1, (8 * 4));
948                 memcpy(tl0_icpe, cheetah_plus_icpe_trap_vector, (8 * 4));
949                 memcpy(tl1_icpe, cheetah_plus_icpe_trap_vector_tl1, (8 * 4));
950         }
951         flushi(PAGE_OFFSET);
952 }
953 
954 static void cheetah_flush_ecache(void)
955 {
956         unsigned long flush_base = ecache_flush_physbase;
957         unsigned long flush_linesize = ecache_flush_linesize;
958         unsigned long flush_size = ecache_flush_size;
959 
960         __asm__ __volatile__("1: subcc  %0, %4, %0\n\t"
961                              "   bne,pt %%xcc, 1b\n\t"
962                              "    ldxa  [%2 + %0] %3, %%g0\n\t"
963                              : "=&r" (flush_size)
964                              : "" (flush_size), "r" (flush_base),
965                                "i" (ASI_PHYS_USE_EC), "r" (flush_linesize));
966 }
967 
968 static void cheetah_flush_ecache_line(unsigned long physaddr)
969 {
970         unsigned long alias;
971 
972         physaddr &= ~(8UL - 1UL);
973         physaddr = (ecache_flush_physbase +
974                     (physaddr & ((ecache_flush_size>>1UL) - 1UL)));
975         alias = physaddr + (ecache_flush_size >> 1UL);
976         __asm__ __volatile__("ldxa [%0] %2, %%g0\n\t"
977                              "ldxa [%1] %2, %%g0\n\t"
978                              "membar #Sync"
979                              : /* no outputs */
980                              : "r" (physaddr), "r" (alias),
981                                "i" (ASI_PHYS_USE_EC));
982 }
983 
984 /* Unfortunately, the diagnostic access to the I-cache tags we need to
985  * use to clear the thing interferes with I-cache coherency transactions.
986  *
987  * So we must only flush the I-cache when it is disabled.
988  */
989 static void __cheetah_flush_icache(void)
990 {
991         unsigned int icache_size, icache_line_size;
992         unsigned long addr;
993 
994         icache_size = local_cpu_data().icache_size;
995         icache_line_size = local_cpu_data().icache_line_size;
996 
997         /* Clear the valid bits in all the tags. */
998         for (addr = 0; addr < icache_size; addr += icache_line_size) {
999                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1000                                      "membar #Sync"
1001                                      : /* no outputs */
1002                                      : "r" (addr | (2 << 3)),
1003                                        "i" (ASI_IC_TAG));
1004         }
1005 }
1006 
1007 static void cheetah_flush_icache(void)
1008 {
1009         unsigned long dcu_save;
1010 
1011         /* Save current DCU, disable I-cache. */
1012         __asm__ __volatile__("ldxa [%%g0] %1, %0\n\t"
1013                              "or %0, %2, %%g1\n\t"
1014                              "stxa %%g1, [%%g0] %1\n\t"
1015                              "membar #Sync"
1016                              : "=r" (dcu_save)
1017                              : "i" (ASI_DCU_CONTROL_REG), "i" (DCU_IC)
1018                              : "g1");
1019 
1020         __cheetah_flush_icache();
1021 
1022         /* Restore DCU register */
1023         __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
1024                              "membar #Sync"
1025                              : /* no outputs */
1026                              : "r" (dcu_save), "i" (ASI_DCU_CONTROL_REG));
1027 }
1028 
1029 static void cheetah_flush_dcache(void)
1030 {
1031         unsigned int dcache_size, dcache_line_size;
1032         unsigned long addr;
1033 
1034         dcache_size = local_cpu_data().dcache_size;
1035         dcache_line_size = local_cpu_data().dcache_line_size;
1036 
1037         for (addr = 0; addr < dcache_size; addr += dcache_line_size) {
1038                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1039                                      "membar #Sync"
1040                                      : /* no outputs */
1041                                      : "r" (addr), "i" (ASI_DCACHE_TAG));
1042         }
1043 }
1044 
1045 /* In order to make the even parity correct we must do two things.
1046  * First, we clear DC_data_parity and set DC_utag to an appropriate value.
1047  * Next, we clear out all 32-bytes of data for that line.  Data of
1048  * all-zero + tag parity value of zero == correct parity.
1049  */
1050 static void cheetah_plus_zap_dcache_parity(void)
1051 {
1052         unsigned int dcache_size, dcache_line_size;
1053         unsigned long addr;
1054 
1055         dcache_size = local_cpu_data().dcache_size;
1056         dcache_line_size = local_cpu_data().dcache_line_size;
1057 
1058         for (addr = 0; addr < dcache_size; addr += dcache_line_size) {
1059                 unsigned long tag = (addr >> 14);
1060                 unsigned long line;
1061 
1062                 __asm__ __volatile__("membar    #Sync\n\t"
1063                                      "stxa      %0, [%1] %2\n\t"
1064                                      "membar    #Sync"
1065                                      : /* no outputs */
1066                                      : "r" (tag), "r" (addr),
1067                                        "i" (ASI_DCACHE_UTAG));
1068                 for (line = addr; line < addr + dcache_line_size; line += 8)
1069                         __asm__ __volatile__("membar    #Sync\n\t"
1070                                              "stxa      %%g0, [%0] %1\n\t"
1071                                              "membar    #Sync"
1072                                              : /* no outputs */
1073                                              : "r" (line),
1074                                                "i" (ASI_DCACHE_DATA));
1075         }
1076 }
1077 
1078 /* Conversion tables used to frob Cheetah AFSR syndrome values into
1079  * something palatable to the memory controller driver get_unumber
1080  * routine.
1081  */
1082 #define MT0     137
1083 #define MT1     138
1084 #define MT2     139
1085 #define NONE    254
1086 #define MTC0    140
1087 #define MTC1    141
1088 #define MTC2    142
1089 #define MTC3    143
1090 #define C0      128
1091 #define C1      129
1092 #define C2      130
1093 #define C3      131
1094 #define C4      132
1095 #define C5      133
1096 #define C6      134
1097 #define C7      135
1098 #define C8      136
1099 #define M2      144
1100 #define M3      145
1101 #define M4      146
1102 #define M       147
1103 static unsigned char cheetah_ecc_syntab[] = {
1104 /*00*/NONE, C0, C1, M2, C2, M2, M3, 47, C3, M2, M2, 53, M2, 41, 29, M,
1105 /*01*/C4, M, M, 50, M2, 38, 25, M2, M2, 33, 24, M2, 11, M, M2, 16,
1106 /*02*/C5, M, M, 46, M2, 37, 19, M2, M, 31, 32, M, 7, M2, M2, 10,
1107 /*03*/M2, 40, 13, M2, 59, M, M2, 66, M, M2, M2, 0, M2, 67, 71, M,
1108 /*04*/C6, M, M, 43, M, 36, 18, M, M2, 49, 15, M, 63, M2, M2, 6,
1109 /*05*/M2, 44, 28, M2, M, M2, M2, 52, 68, M2, M2, 62, M2, M3, M3, M4,
1110 /*06*/M2, 26, 106, M2, 64, M, M2, 2, 120, M, M2, M3, M, M3, M3, M4,
1111 /*07*/116, M2, M2, M3, M2, M3, M, M4, M2, 58, 54, M2, M, M4, M4, M3,
1112 /*08*/C7, M2, M, 42, M, 35, 17, M2, M, 45, 14, M2, 21, M2, M2, 5,
1113 /*09*/M, 27, M, M, 99, M, M, 3, 114, M2, M2, 20, M2, M3, M3, M,
1114 /*0a*/M2, 23, 113, M2, 112, M2, M, 51, 95, M, M2, M3, M2, M3, M3, M2,
1115 /*0b*/103, M, M2, M3, M2, M3, M3, M4, M2, 48, M, M, 73, M2, M, M3,
1116 /*0c*/M2, 22, 110, M2, 109, M2, M, 9, 108, M2, M, M3, M2, M3, M3, M,
1117 /*0d*/102, M2, M, M, M2, M3, M3, M, M2, M3, M3, M2, M, M4, M, M3,
1118 /*0e*/98, M, M2, M3, M2, M, M3, M4, M2, M3, M3, M4, M3, M, M, M,
1119 /*0f*/M2, M3, M3, M, M3, M, M, M, 56, M4, M, M3, M4, M, M, M,
1120 /*10*/C8, M, M2, 39, M, 34, 105, M2, M, 30, 104, M, 101, M, M, 4,
1121 /*11*/M, M, 100, M, 83, M, M2, 12, 87, M, M, 57, M2, M, M3, M,
1122 /*12*/M2, 97, 82, M2, 78, M2, M2, 1, 96, M, M, M, M, M, M3, M2,
1123 /*13*/94, M, M2, M3, M2, M, M3, M, M2, M, 79, M, 69, M, M4, M,
1124 /*14*/M2, 93, 92, M, 91, M, M2, 8, 90, M2, M2, M, M, M, M, M4,
1125 /*15*/89, M, M, M3, M2, M3, M3, M, M, M, M3, M2, M3, M2, M, M3,
1126 /*16*/86, M, M2, M3, M2, M, M3, M, M2, M, M3, M, M3, M, M, M3,
1127 /*17*/M, M, M3, M2, M3, M2, M4, M, 60, M, M2, M3, M4, M, M, M2,
1128 /*18*/M2, 88, 85, M2, 84, M, M2, 55, 81, M2, M2, M3, M2, M3, M3, M4,
1129 /*19*/77, M, M, M, M2, M3, M, M, M2, M3, M3, M4, M3, M2, M, M,
1130 /*1a*/74, M, M2, M3, M, M, M3, M, M, M, M3, M, M3, M, M4, M3,
1131 /*1b*/M2, 70, 107, M4, 65, M2, M2, M, 127, M, M, M, M2, M3, M3, M,
1132 /*1c*/80, M2, M2, 72, M, 119, 118, M, M2, 126, 76, M, 125, M, M4, M3,
1133 /*1d*/M2, 115, 124, M, 75, M, M, M3, 61, M, M4, M, M4, M, M, M,
1134 /*1e*/M, 123, 122, M4, 121, M4, M, M3, 117, M2, M2, M3, M4, M3, M, M,
1135 /*1f*/111, M, M, M, M4, M3, M3, M, M, M, M3, M, M3, M2, M, M
1136 };
1137 static unsigned char cheetah_mtag_syntab[] = {
1138        NONE, MTC0,
1139        MTC1, NONE,
1140        MTC2, NONE,
1141        NONE, MT0,
1142        MTC3, NONE,
1143        NONE, MT1,
1144        NONE, MT2,
1145        NONE, NONE
1146 };
1147 
1148 /* Return the highest priority error conditon mentioned. */
1149 static inline unsigned long cheetah_get_hipri(unsigned long afsr)
1150 {
1151         unsigned long tmp = 0;
1152         int i;
1153 
1154         for (i = 0; cheetah_error_table[i].mask; i++) {
1155                 if ((tmp = (afsr & cheetah_error_table[i].mask)) != 0UL)
1156                         return tmp;
1157         }
1158         return tmp;
1159 }
1160 
1161 static const char *cheetah_get_string(unsigned long bit)
1162 {
1163         int i;
1164 
1165         for (i = 0; cheetah_error_table[i].mask; i++) {
1166                 if ((bit & cheetah_error_table[i].mask) != 0UL)
1167                         return cheetah_error_table[i].name;
1168         }
1169         return "???";
1170 }
1171 
1172 static void cheetah_log_errors(struct pt_regs *regs, struct cheetah_err_info *info,
1173                                unsigned long afsr, unsigned long afar, int recoverable)
1174 {
1175         unsigned long hipri;
1176         char unum[256];
1177 
1178         printk("%s" "ERROR(%d): Cheetah error trap taken afsr[%016lx] afar[%016lx] TL1(%d)\n",
1179                (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1180                afsr, afar,
1181                (afsr & CHAFSR_TL1) ? 1 : 0);
1182         printk("%s" "ERROR(%d): TPC[%lx] TNPC[%lx] O7[%lx] TSTATE[%lx]\n",
1183                (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1184                regs->tpc, regs->tnpc, regs->u_regs[UREG_I7], regs->tstate);
1185         printk("%s" "ERROR(%d): ",
1186                (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id());
1187         printk("TPC<%pS>\n", (void *) regs->tpc);
1188         printk("%s" "ERROR(%d): M_SYND(%lx),  E_SYND(%lx)%s%s\n",
1189                (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1190                (afsr & CHAFSR_M_SYNDROME) >> CHAFSR_M_SYNDROME_SHIFT,
1191                (afsr & CHAFSR_E_SYNDROME) >> CHAFSR_E_SYNDROME_SHIFT,
1192                (afsr & CHAFSR_ME) ? ", Multiple Errors" : "",
1193                (afsr & CHAFSR_PRIV) ? ", Privileged" : "");
1194         hipri = cheetah_get_hipri(afsr);
1195         printk("%s" "ERROR(%d): Highest priority error (%016lx) \"%s\"\n",
1196                (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1197                hipri, cheetah_get_string(hipri));
1198 
1199         /* Try to get unumber if relevant. */
1200 #define ESYND_ERRORS    (CHAFSR_IVC | CHAFSR_IVU | \
1201                          CHAFSR_CPC | CHAFSR_CPU | \
1202                          CHAFSR_UE  | CHAFSR_CE  | \
1203                          CHAFSR_EDC | CHAFSR_EDU  | \
1204                          CHAFSR_UCC | CHAFSR_UCU  | \
1205                          CHAFSR_WDU | CHAFSR_WDC)
1206 #define MSYND_ERRORS    (CHAFSR_EMC | CHAFSR_EMU)
1207         if (afsr & ESYND_ERRORS) {
1208                 int syndrome;
1209                 int ret;
1210 
1211                 syndrome = (afsr & CHAFSR_E_SYNDROME) >> CHAFSR_E_SYNDROME_SHIFT;
1212                 syndrome = cheetah_ecc_syntab[syndrome];
1213                 ret = sprintf_dimm(syndrome, afar, unum, sizeof(unum));
1214                 if (ret != -1)
1215                         printk("%s" "ERROR(%d): AFAR E-syndrome [%s]\n",
1216                                (recoverable ? KERN_WARNING : KERN_CRIT),
1217                                smp_processor_id(), unum);
1218         } else if (afsr & MSYND_ERRORS) {
1219                 int syndrome;
1220                 int ret;
1221 
1222                 syndrome = (afsr & CHAFSR_M_SYNDROME) >> CHAFSR_M_SYNDROME_SHIFT;
1223                 syndrome = cheetah_mtag_syntab[syndrome];
1224                 ret = sprintf_dimm(syndrome, afar, unum, sizeof(unum));
1225                 if (ret != -1)
1226                         printk("%s" "ERROR(%d): AFAR M-syndrome [%s]\n",
1227                                (recoverable ? KERN_WARNING : KERN_CRIT),
1228                                smp_processor_id(), unum);
1229         }
1230 
1231         /* Now dump the cache snapshots. */
1232         printk("%s" "ERROR(%d): D-cache idx[%x] tag[%016llx] utag[%016llx] stag[%016llx]\n",
1233                (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1234                (int) info->dcache_index,
1235                info->dcache_tag,
1236                info->dcache_utag,
1237                info->dcache_stag);
1238         printk("%s" "ERROR(%d): D-cache data0[%016llx] data1[%016llx] data2[%016llx] data3[%016llx]\n",
1239                (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1240                info->dcache_data[0],
1241                info->dcache_data[1],
1242                info->dcache_data[2],
1243                info->dcache_data[3]);
1244         printk("%s" "ERROR(%d): I-cache idx[%x] tag[%016llx] utag[%016llx] stag[%016llx] "
1245                "u[%016llx] l[%016llx]\n",
1246                (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1247                (int) info->icache_index,
1248                info->icache_tag,
1249                info->icache_utag,
1250                info->icache_stag,
1251                info->icache_upper,
1252                info->icache_lower);
1253         printk("%s" "ERROR(%d): I-cache INSN0[%016llx] INSN1[%016llx] INSN2[%016llx] INSN3[%016llx]\n",
1254                (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1255                info->icache_data[0],
1256                info->icache_data[1],
1257                info->icache_data[2],
1258                info->icache_data[3]);
1259         printk("%s" "ERROR(%d): I-cache INSN4[%016llx] INSN5[%016llx] INSN6[%016llx] INSN7[%016llx]\n",
1260                (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1261                info->icache_data[4],
1262                info->icache_data[5],
1263                info->icache_data[6],
1264                info->icache_data[7]);
1265         printk("%s" "ERROR(%d): E-cache idx[%x] tag[%016llx]\n",
1266                (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1267                (int) info->ecache_index, info->ecache_tag);
1268         printk("%s" "ERROR(%d): E-cache data0[%016llx] data1[%016llx] data2[%016llx] data3[%016llx]\n",
1269                (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1270                info->ecache_data[0],
1271                info->ecache_data[1],
1272                info->ecache_data[2],
1273                info->ecache_data[3]);
1274 
1275         afsr = (afsr & ~hipri) & cheetah_afsr_errors;
1276         while (afsr != 0UL) {
1277                 unsigned long bit = cheetah_get_hipri(afsr);
1278 
1279                 printk("%s" "ERROR: Multiple-error (%016lx) \"%s\"\n",
1280                        (recoverable ? KERN_WARNING : KERN_CRIT),
1281                        bit, cheetah_get_string(bit));
1282 
1283                 afsr &= ~bit;
1284         }
1285 
1286         if (!recoverable)
1287                 printk(KERN_CRIT "ERROR: This condition is not recoverable.\n");
1288 }
1289 
1290 static int cheetah_recheck_errors(struct cheetah_err_info *logp)
1291 {
1292         unsigned long afsr, afar;
1293         int ret = 0;
1294 
1295         __asm__ __volatile__("ldxa [%%g0] %1, %0\n\t"
1296                              : "=r" (afsr)
1297                              : "i" (ASI_AFSR));
1298         if ((afsr & cheetah_afsr_errors) != 0) {
1299                 if (logp != NULL) {
1300                         __asm__ __volatile__("ldxa [%%g0] %1, %0\n\t"
1301                                              : "=r" (afar)
1302                                              : "i" (ASI_AFAR));
1303                         logp->afsr = afsr;
1304                         logp->afar = afar;
1305                 }
1306                 ret = 1;
1307         }
1308         __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
1309                              "membar #Sync\n\t"
1310                              : : "r" (afsr), "i" (ASI_AFSR));
1311 
1312         return ret;
1313 }
1314 
1315 void cheetah_fecc_handler(struct pt_regs *regs, unsigned long afsr, unsigned long afar)
1316 {
1317         struct cheetah_err_info local_snapshot, *p;
1318         int recoverable;
1319 
1320         /* Flush E-cache */
1321         cheetah_flush_ecache();
1322 
1323         p = cheetah_get_error_log(afsr);
1324         if (!p) {
1325                 prom_printf("ERROR: Early Fast-ECC error afsr[%016lx] afar[%016lx]\n",
1326                             afsr, afar);
1327                 prom_printf("ERROR: CPU(%d) TPC[%016lx] TNPC[%016lx] TSTATE[%016lx]\n",
1328                             smp_processor_id(), regs->tpc, regs->tnpc, regs->tstate);
1329                 prom_halt();
1330         }
1331 
1332         /* Grab snapshot of logged error. */
1333         memcpy(&local_snapshot, p, sizeof(local_snapshot));
1334 
1335         /* If the current trap snapshot does not match what the
1336          * trap handler passed along into our args, big trouble.
1337          * In such a case, mark the local copy as invalid.
1338          *
1339          * Else, it matches and we mark the afsr in the non-local
1340          * copy as invalid so we may log new error traps there.
1341          */
1342         if (p->afsr != afsr || p->afar != afar)
1343                 local_snapshot.afsr = CHAFSR_INVALID;
1344         else
1345                 p->afsr = CHAFSR_INVALID;
1346 
1347         cheetah_flush_icache();
1348         cheetah_flush_dcache();
1349 
1350         /* Re-enable I-cache/D-cache */
1351         __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1352                              "or %%g1, %1, %%g1\n\t"
1353                              "stxa %%g1, [%%g0] %0\n\t"
1354                              "membar #Sync"
1355                              : /* no outputs */
1356                              : "i" (ASI_DCU_CONTROL_REG),
1357                                "i" (DCU_DC | DCU_IC)
1358                              : "g1");
1359 
1360         /* Re-enable error reporting */
1361         __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1362                              "or %%g1, %1, %%g1\n\t"
1363                              "stxa %%g1, [%%g0] %0\n\t"
1364                              "membar #Sync"
1365                              : /* no outputs */
1366                              : "i" (ASI_ESTATE_ERROR_EN),
1367                                "i" (ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN)
1368                              : "g1");
1369 
1370         /* Decide if we can continue after handling this trap and
1371          * logging the error.
1372          */
1373         recoverable = 1;
1374         if (afsr & (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP))
1375                 recoverable = 0;
1376 
1377         /* Re-check AFSR/AFAR.  What we are looking for here is whether a new
1378          * error was logged while we had error reporting traps disabled.
1379          */
1380         if (cheetah_recheck_errors(&local_snapshot)) {
1381                 unsigned long new_afsr = local_snapshot.afsr;
1382 
1383                 /* If we got a new asynchronous error, die... */
1384                 if (new_afsr & (CHAFSR_EMU | CHAFSR_EDU |
1385                                 CHAFSR_WDU | CHAFSR_CPU |
1386                                 CHAFSR_IVU | CHAFSR_UE |
1387                                 CHAFSR_BERR | CHAFSR_TO))
1388                         recoverable = 0;
1389         }
1390 
1391         /* Log errors. */
1392         cheetah_log_errors(regs, &local_snapshot, afsr, afar, recoverable);
1393 
1394         if (!recoverable)
1395                 panic("Irrecoverable Fast-ECC error trap.\n");
1396 
1397         /* Flush E-cache to kick the error trap handlers out. */
1398         cheetah_flush_ecache();
1399 }
1400 
1401 /* Try to fix a correctable error by pushing the line out from
1402  * the E-cache.  Recheck error reporting registers to see if the
1403  * problem is intermittent.
1404  */
1405 static int cheetah_fix_ce(unsigned long physaddr)
1406 {
1407         unsigned long orig_estate;
1408         unsigned long alias1, alias2;
1409         int ret;
1410 
1411         /* Make sure correctable error traps are disabled. */
1412         __asm__ __volatile__("ldxa      [%%g0] %2, %0\n\t"
1413                              "andn      %0, %1, %%g1\n\t"
1414                              "stxa      %%g1, [%%g0] %2\n\t"
1415                              "membar    #Sync"
1416                              : "=&r" (orig_estate)
1417                              : "i" (ESTATE_ERROR_CEEN),
1418                                "i" (ASI_ESTATE_ERROR_EN)
1419                              : "g1");
1420 
1421         /* We calculate alias addresses that will force the
1422          * cache line in question out of the E-cache.  Then
1423          * we bring it back in with an atomic instruction so
1424          * that we get it in some modified/exclusive state,
1425          * then we displace it again to try and get proper ECC
1426          * pushed back into the system.
1427          */
1428         physaddr &= ~(8UL - 1UL);
1429         alias1 = (ecache_flush_physbase +
1430                   (physaddr & ((ecache_flush_size >> 1) - 1)));
1431         alias2 = alias1 + (ecache_flush_size >> 1);
1432         __asm__ __volatile__("ldxa      [%0] %3, %%g0\n\t"
1433                              "ldxa      [%1] %3, %%g0\n\t"
1434                              "casxa     [%2] %3, %%g0, %%g0\n\t"
1435                              "ldxa      [%0] %3, %%g0\n\t"
1436                              "ldxa      [%1] %3, %%g0\n\t"
1437                              "membar    #Sync"
1438                              : /* no outputs */
1439                              : "r" (alias1), "r" (alias2),
1440                                "r" (physaddr), "i" (ASI_PHYS_USE_EC));
1441 
1442         /* Did that trigger another error? */
1443         if (cheetah_recheck_errors(NULL)) {
1444                 /* Try one more time. */
1445                 __asm__ __volatile__("ldxa [%0] %1, %%g0\n\t"
1446                                      "membar #Sync"
1447                                      : : "r" (physaddr), "i" (ASI_PHYS_USE_EC));
1448                 if (cheetah_recheck_errors(NULL))
1449                         ret = 2;
1450                 else
1451                         ret = 1;
1452         } else {
1453                 /* No new error, intermittent problem. */
1454                 ret = 0;
1455         }
1456 
1457         /* Restore error enables. */
1458         __asm__ __volatile__("stxa      %0, [%%g0] %1\n\t"
1459                              "membar    #Sync"
1460                              : : "r" (orig_estate), "i" (ASI_ESTATE_ERROR_EN));
1461 
1462         return ret;
1463 }
1464 
1465 /* Return non-zero if PADDR is a valid physical memory address. */
1466 static int cheetah_check_main_memory(unsigned long paddr)
1467 {
1468         unsigned long vaddr = PAGE_OFFSET + paddr;
1469 
1470         if (vaddr > (unsigned long) high_memory)
1471                 return 0;
1472 
1473         return kern_addr_valid(vaddr);
1474 }
1475 
1476 void cheetah_cee_handler(struct pt_regs *regs, unsigned long afsr, unsigned long afar)
1477 {
1478         struct cheetah_err_info local_snapshot, *p;
1479         int recoverable, is_memory;
1480 
1481         p = cheetah_get_error_log(afsr);
1482         if (!p) {
1483                 prom_printf("ERROR: Early CEE error afsr[%016lx] afar[%016lx]\n",
1484                             afsr, afar);
1485                 prom_printf("ERROR: CPU(%d) TPC[%016lx] TNPC[%016lx] TSTATE[%016lx]\n",
1486                             smp_processor_id(), regs->tpc, regs->tnpc, regs->tstate);
1487                 prom_halt();
1488         }
1489 
1490         /* Grab snapshot of logged error. */
1491         memcpy(&local_snapshot, p, sizeof(local_snapshot));
1492 
1493         /* If the current trap snapshot does not match what the
1494          * trap handler passed along into our args, big trouble.
1495          * In such a case, mark the local copy as invalid.
1496          *
1497          * Else, it matches and we mark the afsr in the non-local
1498          * copy as invalid so we may log new error traps there.
1499          */
1500         if (p->afsr != afsr || p->afar != afar)
1501                 local_snapshot.afsr = CHAFSR_INVALID;
1502         else
1503                 p->afsr = CHAFSR_INVALID;
1504 
1505         is_memory = cheetah_check_main_memory(afar);
1506 
1507         if (is_memory && (afsr & CHAFSR_CE) != 0UL) {
1508                 /* XXX Might want to log the results of this operation
1509                  * XXX somewhere... -DaveM
1510                  */
1511                 cheetah_fix_ce(afar);
1512         }
1513 
1514         {
1515                 int flush_all, flush_line;
1516 
1517                 flush_all = flush_line = 0;
1518                 if ((afsr & CHAFSR_EDC) != 0UL) {
1519                         if ((afsr & cheetah_afsr_errors) == CHAFSR_EDC)
1520                                 flush_line = 1;
1521                         else
1522                                 flush_all = 1;
1523                 } else if ((afsr & CHAFSR_CPC) != 0UL) {
1524                         if ((afsr & cheetah_afsr_errors) == CHAFSR_CPC)
1525                                 flush_line = 1;
1526                         else
1527                                 flush_all = 1;
1528                 }
1529 
1530                 /* Trap handler only disabled I-cache, flush it. */
1531                 cheetah_flush_icache();
1532 
1533                 /* Re-enable I-cache */
1534                 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1535                                      "or %%g1, %1, %%g1\n\t"
1536                                      "stxa %%g1, [%%g0] %0\n\t"
1537                                      "membar #Sync"
1538                                      : /* no outputs */
1539                                      : "i" (ASI_DCU_CONTROL_REG),
1540                                      "i" (DCU_IC)
1541                                      : "g1");
1542 
1543                 if (flush_all)
1544                         cheetah_flush_ecache();
1545                 else if (flush_line)
1546                         cheetah_flush_ecache_line(afar);
1547         }
1548 
1549         /* Re-enable error reporting */
1550         __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1551                              "or %%g1, %1, %%g1\n\t"
1552                              "stxa %%g1, [%%g0] %0\n\t"
1553                              "membar #Sync"
1554                              : /* no outputs */
1555                              : "i" (ASI_ESTATE_ERROR_EN),
1556                                "i" (ESTATE_ERROR_CEEN)
1557                              : "g1");
1558 
1559         /* Decide if we can continue after handling this trap and
1560          * logging the error.
1561          */
1562         recoverable = 1;
1563         if (afsr & (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP))
1564                 recoverable = 0;
1565 
1566         /* Re-check AFSR/AFAR */
1567         (void) cheetah_recheck_errors(&local_snapshot);
1568 
1569         /* Log errors. */
1570         cheetah_log_errors(regs, &local_snapshot, afsr, afar, recoverable);
1571 
1572         if (!recoverable)
1573                 panic("Irrecoverable Correctable-ECC error trap.\n");
1574 }
1575 
1576 void cheetah_deferred_handler(struct pt_regs *regs, unsigned long afsr, unsigned long afar)
1577 {
1578         struct cheetah_err_info local_snapshot, *p;
1579         int recoverable, is_memory;
1580 
1581 #ifdef CONFIG_PCI
1582         /* Check for the special PCI poke sequence. */
1583         if (pci_poke_in_progress && pci_poke_cpu == smp_processor_id()) {
1584                 cheetah_flush_icache();
1585                 cheetah_flush_dcache();
1586 
1587                 /* Re-enable I-cache/D-cache */
1588                 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1589                                      "or %%g1, %1, %%g1\n\t"
1590                                      "stxa %%g1, [%%g0] %0\n\t"
1591                                      "membar #Sync"
1592                                      : /* no outputs */
1593                                      : "i" (ASI_DCU_CONTROL_REG),
1594                                        "i" (DCU_DC | DCU_IC)
1595                                      : "g1");
1596 
1597                 /* Re-enable error reporting */
1598                 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1599                                      "or %%g1, %1, %%g1\n\t"
1600                                      "stxa %%g1, [%%g0] %0\n\t"
1601                                      "membar #Sync"
1602                                      : /* no outputs */
1603                                      : "i" (ASI_ESTATE_ERROR_EN),
1604                                        "i" (ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN)
1605                                      : "g1");
1606 
1607                 (void) cheetah_recheck_errors(NULL);
1608 
1609                 pci_poke_faulted = 1;
1610                 regs->tpc += 4;
1611                 regs->tnpc = regs->tpc + 4;
1612                 return;
1613         }
1614 #endif
1615 
1616         p = cheetah_get_error_log(afsr);
1617         if (!p) {
1618                 prom_printf("ERROR: Early deferred error afsr[%016lx] afar[%016lx]\n",
1619                             afsr, afar);
1620                 prom_printf("ERROR: CPU(%d) TPC[%016lx] TNPC[%016lx] TSTATE[%016lx]\n",
1621                             smp_processor_id(), regs->tpc, regs->tnpc, regs->tstate);
1622                 prom_halt();
1623         }
1624 
1625         /* Grab snapshot of logged error. */
1626         memcpy(&local_snapshot, p, sizeof(local_snapshot));
1627 
1628         /* If the current trap snapshot does not match what the
1629          * trap handler passed along into our args, big trouble.
1630          * In such a case, mark the local copy as invalid.
1631          *
1632          * Else, it matches and we mark the afsr in the non-local
1633          * copy as invalid so we may log new error traps there.
1634          */
1635         if (p->afsr != afsr || p->afar != afar)
1636                 local_snapshot.afsr = CHAFSR_INVALID;
1637         else
1638                 p->afsr = CHAFSR_INVALID;
1639 
1640         is_memory = cheetah_check_main_memory(afar);
1641 
1642         {
1643                 int flush_all, flush_line;
1644 
1645                 flush_all = flush_line = 0;
1646                 if ((afsr & CHAFSR_EDU) != 0UL) {
1647                         if ((afsr & cheetah_afsr_errors) == CHAFSR_EDU)
1648                                 flush_line = 1;
1649                         else
1650                                 flush_all = 1;
1651                 } else if ((afsr & CHAFSR_BERR) != 0UL) {
1652                         if ((afsr & cheetah_afsr_errors) == CHAFSR_BERR)
1653                                 flush_line = 1;
1654                         else
1655                                 flush_all = 1;
1656                 }
1657 
1658                 cheetah_flush_icache();
1659                 cheetah_flush_dcache();
1660 
1661                 /* Re-enable I/D caches */
1662                 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1663                                      "or %%g1, %1, %%g1\n\t"
1664                                      "stxa %%g1, [%%g0] %0\n\t"
1665                                      "membar #Sync"
1666                                      : /* no outputs */
1667                                      : "i" (ASI_DCU_CONTROL_REG),
1668                                      "i" (DCU_IC | DCU_DC)
1669                                      : "g1");
1670 
1671                 if (flush_all)
1672                         cheetah_flush_ecache();
1673                 else if (flush_line)
1674                         cheetah_flush_ecache_line(afar);
1675         }
1676 
1677         /* Re-enable error reporting */
1678         __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1679                              "or %%g1, %1, %%g1\n\t"
1680                              "stxa %%g1, [%%g0] %0\n\t"
1681                              "membar #Sync"
1682                              : /* no outputs */
1683                              : "i" (ASI_ESTATE_ERROR_EN),
1684                              "i" (ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN)
1685                              : "g1");
1686 
1687         /* Decide if we can continue after handling this trap and
1688          * logging the error.
1689          */
1690         recoverable = 1;
1691         if (afsr & (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP))
1692                 recoverable = 0;
1693 
1694         /* Re-check AFSR/AFAR.  What we are looking for here is whether a new
1695          * error was logged while we had error reporting traps disabled.
1696          */
1697         if (cheetah_recheck_errors(&local_snapshot)) {
1698                 unsigned long new_afsr = local_snapshot.afsr;
1699 
1700                 /* If we got a new asynchronous error, die... */
1701                 if (new_afsr & (CHAFSR_EMU | CHAFSR_EDU |
1702                                 CHAFSR_WDU | CHAFSR_CPU |
1703                                 CHAFSR_IVU | CHAFSR_UE |
1704                                 CHAFSR_BERR | CHAFSR_TO))
1705                         recoverable = 0;
1706         }
1707 
1708         /* Log errors. */
1709         cheetah_log_errors(regs, &local_snapshot, afsr, afar, recoverable);
1710 
1711         /* "Recoverable" here means we try to yank the page from ever
1712          * being newly used again.  This depends upon a few things:
1713          * 1) Must be main memory, and AFAR must be valid.
1714          * 2) If we trapped from user, OK.
1715          * 3) Else, if we trapped from kernel we must find exception
1716          *    table entry (ie. we have to have been accessing user
1717          *    space).
1718          *
1719          * If AFAR is not in main memory, or we trapped from kernel
1720          * and cannot find an exception table entry, it is unacceptable
1721          * to try and continue.
1722          */
1723         if (recoverable && is_memory) {
1724                 if ((regs->tstate & TSTATE_PRIV) == 0UL) {
1725                         /* OK, usermode access. */
1726                         recoverable = 1;
1727                 } else {
1728                         const struct exception_table_entry *entry;
1729 
1730                         entry = search_exception_tables(regs->tpc);
1731                         if (entry) {
1732                                 /* OK, kernel access to userspace. */
1733                                 recoverable = 1;
1734 
1735                         } else {
1736                                 /* BAD, privileged state is corrupted. */
1737                                 recoverable = 0;
1738                         }
1739 
1740                         if (recoverable) {
1741                                 if (pfn_valid(afar >> PAGE_SHIFT))
1742                                         get_page(pfn_to_page(afar >> PAGE_SHIFT));
1743                                 else
1744                                         recoverable = 0;
1745 
1746                                 /* Only perform fixup if we still have a
1747                                  * recoverable condition.
1748                                  */
1749                                 if (recoverable) {
1750                                         regs->tpc = entry->fixup;
1751                                         regs->tnpc = regs->tpc + 4;
1752                                 }
1753                         }
1754                 }
1755         } else {
1756                 recoverable = 0;
1757         }
1758 
1759         if (!recoverable)
1760                 panic("Irrecoverable deferred error trap.\n");
1761 }
1762 
1763 /* Handle a D/I cache parity error trap.  TYPE is encoded as:
1764  *
1765  * Bit0:        0=dcache,1=icache
1766  * Bit1:        0=recoverable,1=unrecoverable
1767  *
1768  * The hardware has disabled both the I-cache and D-cache in
1769  * the %dcr register.  
1770  */
1771 void cheetah_plus_parity_error(int type, struct pt_regs *regs)
1772 {
1773         if (type & 0x1)
1774                 __cheetah_flush_icache();
1775         else
1776                 cheetah_plus_zap_dcache_parity();
1777         cheetah_flush_dcache();
1778 
1779         /* Re-enable I-cache/D-cache */
1780         __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1781                              "or %%g1, %1, %%g1\n\t"
1782                              "stxa %%g1, [%%g0] %0\n\t"
1783                              "membar #Sync"
1784                              : /* no outputs */
1785                              : "i" (ASI_DCU_CONTROL_REG),
1786                                "i" (DCU_DC | DCU_IC)
1787                              : "g1");
1788 
1789         if (type & 0x2) {
1790                 printk(KERN_EMERG "CPU[%d]: Cheetah+ %c-cache parity error at TPC[%016lx]\n",
1791                        smp_processor_id(),
1792                        (type & 0x1) ? 'I' : 'D',
1793                        regs->tpc);
1794                 printk(KERN_EMERG "TPC<%pS>\n", (void *) regs->tpc);
1795                 panic("Irrecoverable Cheetah+ parity error.");
1796         }
1797 
1798         printk(KERN_WARNING "CPU[%d]: Cheetah+ %c-cache parity error at TPC[%016lx]\n",
1799                smp_processor_id(),
1800                (type & 0x1) ? 'I' : 'D',
1801                regs->tpc);
1802         printk(KERN_WARNING "TPC<%pS>\n", (void *) regs->tpc);
1803 }
1804 
1805 struct sun4v_error_entry {
1806         /* Unique error handle */
1807 /*0x00*/u64             err_handle;
1808 
1809         /* %stick value at the time of the error */
1810 /*0x08*/u64             err_stick;
1811 
1812 /*0x10*/u8              reserved_1[3];
1813 
1814         /* Error type */
1815 /*0x13*/u8              err_type;
1816 #define SUN4V_ERR_TYPE_UNDEFINED        0
1817 #define SUN4V_ERR_TYPE_UNCORRECTED_RES  1
1818 #define SUN4V_ERR_TYPE_PRECISE_NONRES   2
1819 #define SUN4V_ERR_TYPE_DEFERRED_NONRES  3
1820 #define SUN4V_ERR_TYPE_SHUTDOWN_RQST    4
1821 #define SUN4V_ERR_TYPE_DUMP_CORE        5
1822 #define SUN4V_ERR_TYPE_SP_STATE_CHANGE  6
1823 #define SUN4V_ERR_TYPE_NUM              7
1824 
1825         /* Error attributes */
1826 /*0x14*/u32             err_attrs;
1827 #define SUN4V_ERR_ATTRS_PROCESSOR       0x00000001
1828 #define SUN4V_ERR_ATTRS_MEMORY          0x00000002
1829 #define SUN4V_ERR_ATTRS_PIO             0x00000004
1830 #define SUN4V_ERR_ATTRS_INT_REGISTERS   0x00000008
1831 #define SUN4V_ERR_ATTRS_FPU_REGISTERS   0x00000010
1832 #define SUN4V_ERR_ATTRS_SHUTDOWN_RQST   0x00000020
1833 #define SUN4V_ERR_ATTRS_ASR             0x00000040
1834 #define SUN4V_ERR_ATTRS_ASI             0x00000080
1835 #define SUN4V_ERR_ATTRS_PRIV_REG        0x00000100
1836 #define SUN4V_ERR_ATTRS_SPSTATE_MSK     0x00000600
1837 #define SUN4V_ERR_ATTRS_MCD             0x00000800
1838 #define SUN4V_ERR_ATTRS_SPSTATE_SHFT    9
1839 #define SUN4V_ERR_ATTRS_MODE_MSK        0x03000000
1840 #define SUN4V_ERR_ATTRS_MODE_SHFT       24
1841 #define SUN4V_ERR_ATTRS_RES_QUEUE_FULL  0x80000000
1842 
1843 #define SUN4V_ERR_SPSTATE_FAULTED       0
1844 #define SUN4V_ERR_SPSTATE_AVAILABLE     1
1845 #define SUN4V_ERR_SPSTATE_NOT_PRESENT   2
1846 
1847 #define SUN4V_ERR_MODE_USER             1
1848 #define SUN4V_ERR_MODE_PRIV             2
1849 
1850         /* Real address of the memory region or PIO transaction */
1851 /*0x18*/u64             err_raddr;
1852 
1853         /* Size of the operation triggering the error, in bytes */
1854 /*0x20*/u32             err_size;
1855 
1856         /* ID of the CPU */
1857 /*0x24*/u16             err_cpu;
1858 
1859         /* Grace periof for shutdown, in seconds */
1860 /*0x26*/u16             err_secs;
1861 
1862         /* Value of the %asi register */
1863 /*0x28*/u8              err_asi;
1864 
1865 /*0x29*/u8              reserved_2;
1866 
1867         /* Value of the ASR register number */
1868 /*0x2a*/u16             err_asr;
1869 #define SUN4V_ERR_ASR_VALID             0x8000
1870 
1871 /*0x2c*/u32             reserved_3;
1872 /*0x30*/u64             reserved_4;
1873 /*0x38*/u64             reserved_5;
1874 };
1875 
1876 static atomic_t sun4v_resum_oflow_cnt = ATOMIC_INIT(0);
1877 static atomic_t sun4v_nonresum_oflow_cnt = ATOMIC_INIT(0);
1878 
1879 static const char *sun4v_err_type_to_str(u8 type)
1880 {
1881         static const char *types[SUN4V_ERR_TYPE_NUM] = {
1882                 "undefined",
1883                 "uncorrected resumable",
1884                 "precise nonresumable",
1885                 "deferred nonresumable",
1886                 "shutdown request",
1887                 "dump core",
1888                 "SP state change",
1889         };
1890 
1891         if (type < SUN4V_ERR_TYPE_NUM)
1892                 return types[type];
1893 
1894         return "unknown";
1895 }
1896 
1897 static void sun4v_emit_err_attr_strings(u32 attrs)
1898 {
1899         static const char *attr_names[] = {
1900                 "processor",
1901                 "memory",
1902                 "PIO",
1903                 "int-registers",
1904                 "fpu-registers",
1905                 "shutdown-request",
1906                 "ASR",
1907                 "ASI",
1908                 "priv-reg",
1909         };
1910         static const char *sp_states[] = {
1911                 "sp-faulted",
1912                 "sp-available",
1913                 "sp-not-present",
1914                 "sp-state-reserved",
1915         };
1916         static const char *modes[] = {
1917                 "mode-reserved0",
1918                 "user",
1919                 "priv",
1920                 "mode-reserved1",
1921         };
1922         u32 sp_state, mode;
1923         int i;
1924 
1925         for (i = 0; i < ARRAY_SIZE(attr_names); i++) {
1926                 if (attrs & (1U << i)) {
1927                         const char *s = attr_names[i];
1928 
1929                         pr_cont("%s ", s);
1930                 }
1931         }
1932 
1933         sp_state = ((attrs & SUN4V_ERR_ATTRS_SPSTATE_MSK) >>
1934                     SUN4V_ERR_ATTRS_SPSTATE_SHFT);
1935         pr_cont("%s ", sp_states[sp_state]);
1936 
1937         mode = ((attrs & SUN4V_ERR_ATTRS_MODE_MSK) >>
1938                 SUN4V_ERR_ATTRS_MODE_SHFT);
1939         pr_cont("%s ", modes[mode]);
1940 
1941         if (attrs & SUN4V_ERR_ATTRS_RES_QUEUE_FULL)
1942                 pr_cont("res-queue-full ");
1943 }
1944 
1945 /* When the report contains a real-address of "-1" it means that the
1946  * hardware did not provide the address.  So we compute the effective
1947  * address of the load or store instruction at regs->tpc and report
1948  * that.  Usually when this happens it's a PIO and in such a case we
1949  * are using physical addresses with bypass ASIs anyways, so what we
1950  * report here is exactly what we want.
1951  */
1952 static void sun4v_report_real_raddr(const char *pfx, struct pt_regs *regs)
1953 {
1954         unsigned int insn;
1955         u64 addr;
1956 
1957         if (!(regs->tstate & TSTATE_PRIV))
1958                 return;
1959 
1960         insn = *(unsigned int *) regs->tpc;
1961 
1962         addr = compute_effective_address(regs, insn, 0);
1963 
1964         printk("%s: insn effective address [0x%016llx]\n",
1965                pfx, addr);
1966 }
1967 
1968 static void sun4v_log_error(struct pt_regs *regs, struct sun4v_error_entry *ent,
1969                             int cpu, const char *pfx, atomic_t *ocnt)
1970 {
1971         u64 *raw_ptr = (u64 *) ent;
1972         u32 attrs;
1973         int cnt;
1974 
1975         printk("%s: Reporting on cpu %d\n", pfx, cpu);
1976         printk("%s: TPC [0x%016lx] <%pS>\n",
1977                pfx, regs->tpc, (void *) regs->tpc);
1978 
1979         printk("%s: RAW [%016llx:%016llx:%016llx:%016llx\n",
1980                pfx, raw_ptr[0], raw_ptr[1], raw_ptr[2], raw_ptr[3]);
1981         printk("%s:      %016llx:%016llx:%016llx:%016llx]\n",
1982                pfx, raw_ptr[4], raw_ptr[5], raw_ptr[6], raw_ptr[7]);
1983 
1984         printk("%s: handle [0x%016llx] stick [0x%016llx]\n",
1985                pfx, ent->err_handle, ent->err_stick);
1986 
1987         printk("%s: type [%s]\n", pfx, sun4v_err_type_to_str(ent->err_type));
1988 
1989         attrs = ent->err_attrs;
1990         printk("%s: attrs [0x%08x] < ", pfx, attrs);
1991         sun4v_emit_err_attr_strings(attrs);
1992         pr_cont(">\n");
1993 
1994         /* Various fields in the error report are only valid if
1995          * certain attribute bits are set.
1996          */
1997         if (attrs & (SUN4V_ERR_ATTRS_MEMORY |
1998                      SUN4V_ERR_ATTRS_PIO |
1999                      SUN4V_ERR_ATTRS_ASI)) {
2000                 printk("%s: raddr [0x%016llx]\n", pfx, ent->err_raddr);
2001 
2002                 if (ent->err_raddr == ~(u64)0)
2003                         sun4v_report_real_raddr(pfx, regs);
2004         }
2005 
2006         if (attrs & (SUN4V_ERR_ATTRS_MEMORY | SUN4V_ERR_ATTRS_ASI))
2007                 printk("%s: size [0x%x]\n", pfx, ent->err_size);
2008 
2009         if (attrs & (SUN4V_ERR_ATTRS_PROCESSOR |
2010                      SUN4V_ERR_ATTRS_INT_REGISTERS |
2011                      SUN4V_ERR_ATTRS_FPU_REGISTERS |
2012                      SUN4V_ERR_ATTRS_PRIV_REG))
2013                 printk("%s: cpu[%u]\n", pfx, ent->err_cpu);
2014 
2015         if (attrs & SUN4V_ERR_ATTRS_ASI)
2016                 printk("%s: asi [0x%02x]\n", pfx, ent->err_asi);
2017 
2018         if ((attrs & (SUN4V_ERR_ATTRS_INT_REGISTERS |
2019                       SUN4V_ERR_ATTRS_FPU_REGISTERS |
2020                       SUN4V_ERR_ATTRS_PRIV_REG)) &&
2021             (ent->err_asr & SUN4V_ERR_ASR_VALID) != 0)
2022                 printk("%s: reg [0x%04x]\n",
2023                        pfx, ent->err_asr & ~SUN4V_ERR_ASR_VALID);
2024 
2025         show_regs(regs);
2026 
2027         if ((cnt = atomic_read(ocnt)) != 0) {
2028                 atomic_set(ocnt, 0);
2029                 wmb();
2030                 printk("%s: Queue overflowed %d times.\n",
2031                        pfx, cnt);
2032         }
2033 }
2034 
2035 /* Handle memory corruption detected error which is vectored in
2036  * through resumable error trap.
2037  */
2038 void do_mcd_err(struct pt_regs *regs, struct sun4v_error_entry ent)
2039 {
2040         if (notify_die(DIE_TRAP, "MCD error", regs, 0, 0x34,
2041                        SIGSEGV) == NOTIFY_STOP)
2042                 return;
2043 
2044         if (regs->tstate & TSTATE_PRIV) {
2045                 /* MCD exception could happen because the task was
2046                  * running a system call with MCD enabled and passed a
2047                  * non-versioned pointer or pointer with bad version
2048                  * tag to the system call. In such cases, hypervisor
2049                  * places the address of offending instruction in the
2050                  * resumable error report. This is a deferred error,
2051                  * so the read/write that caused the trap was potentially
2052                  * retired long time back and we may have no choice
2053                  * but to send SIGSEGV to the process.
2054                  */
2055                 const struct exception_table_entry *entry;
2056 
2057                 entry = search_exception_tables(regs->tpc);
2058                 if (entry) {
2059                         /* Looks like a bad syscall parameter */
2060 #ifdef DEBUG_EXCEPTIONS
2061                         pr_emerg("Exception: PC<%016lx> faddr<UNKNOWN>\n",
2062                                  regs->tpc);
2063                         pr_emerg("EX_TABLE: insn<%016lx> fixup<%016lx>\n",
2064                                  ent.err_raddr, entry->fixup);
2065 #endif
2066                         regs->tpc = entry->fixup;
2067                         regs->tnpc = regs->tpc + 4;
2068                         return;
2069                 }
2070         }
2071 
2072         /* Send SIGSEGV to the userspace process with the right signal
2073          * code
2074          */
2075         force_sig_fault(SIGSEGV, SEGV_ADIDERR, (void __user *)ent.err_raddr,
2076                         0, current);
2077 }
2078 
2079 /* We run with %pil set to PIL_NORMAL_MAX and PSTATE_IE enabled in %pstate.
2080  * Log the event and clear the first word of the entry.
2081  */
2082 void sun4v_resum_error(struct pt_regs *regs, unsigned long offset)
2083 {
2084         enum ctx_state prev_state = exception_enter();
2085         struct sun4v_error_entry *ent, local_copy;
2086         struct trap_per_cpu *tb;
2087         unsigned long paddr;
2088         int cpu;
2089 
2090         cpu = get_cpu();
2091 
2092         tb = &trap_block[cpu];
2093         paddr = tb->resum_kernel_buf_pa + offset;
2094         ent = __va(paddr);
2095 
2096         memcpy(&local_copy, ent, sizeof(struct sun4v_error_entry));
2097 
2098         /* We have a local copy now, so release the entry.  */
2099         ent->err_handle = 0;
2100         wmb();
2101 
2102         put_cpu();
2103 
2104         if (local_copy.err_type == SUN4V_ERR_TYPE_SHUTDOWN_RQST) {
2105                 /* We should really take the seconds field of
2106                  * the error report and use it for the shutdown
2107                  * invocation, but for now do the same thing we
2108                  * do for a DS shutdown request.
2109                  */
2110                 pr_info("Shutdown request, %u seconds...\n",
2111                         local_copy.err_secs);
2112                 orderly_poweroff(true);
2113                 goto out;
2114         }
2115 
2116         /* If this is a memory corruption detected error vectored in
2117          * by HV through resumable error trap, call the handler
2118          */
2119         if (local_copy.err_attrs & SUN4V_ERR_ATTRS_MCD) {
2120                 do_mcd_err(regs, local_copy);
2121                 return;
2122         }
2123 
2124         sun4v_log_error(regs, &local_copy, cpu,
2125                         KERN_ERR "RESUMABLE ERROR",
2126                         &sun4v_resum_oflow_cnt);
2127 out:
2128         exception_exit(prev_state);
2129 }
2130 
2131 /* If we try to printk() we'll probably make matters worse, by trying
2132  * to retake locks this cpu already holds or causing more errors. So
2133  * just bump a counter, and we'll report these counter bumps above.
2134  */
2135 void sun4v_resum_overflow(struct pt_regs *regs)
2136 {
2137         atomic_inc(&sun4v_resum_oflow_cnt);
2138 }
2139 
2140 /* Given a set of registers, get the virtual addressi that was being accessed
2141  * by the faulting instructions at tpc.
2142  */
2143 static unsigned long sun4v_get_vaddr(struct pt_regs *regs)
2144 {
2145         unsigned int insn;
2146 
2147         if (!copy_from_user(&insn, (void __user *)regs->tpc, 4)) {
2148                 return compute_effective_address(regs, insn,
2149                                                  (insn >> 25) & 0x1f);
2150         }
2151         return 0;
2152 }
2153 
2154 /* Attempt to handle non-resumable errors generated from userspace.
2155  * Returns true if the signal was handled, false otherwise.
2156  */
2157 bool sun4v_nonresum_error_user_handled(struct pt_regs *regs,
2158                                   struct sun4v_error_entry *ent) {
2159 
2160         unsigned int attrs = ent->err_attrs;
2161 
2162         if (attrs & SUN4V_ERR_ATTRS_MEMORY) {
2163                 unsigned long addr = ent->err_raddr;
2164 
2165                 if (addr == ~(u64)0) {
2166                         /* This seems highly unlikely to ever occur */
2167                         pr_emerg("SUN4V NON-RECOVERABLE ERROR: Memory error detected in unknown location!\n");
2168                 } else {
2169                         unsigned long page_cnt = DIV_ROUND_UP(ent->err_size,
2170                                                               PAGE_SIZE);
2171 
2172                         /* Break the unfortunate news. */
2173                         pr_emerg("SUN4V NON-RECOVERABLE ERROR: Memory failed at %016lX\n",
2174                                  addr);
2175                         pr_emerg("SUN4V NON-RECOVERABLE ERROR:   Claiming %lu ages.\n",
2176                                  page_cnt);
2177 
2178                         while (page_cnt-- > 0) {
2179                                 if (pfn_valid(addr >> PAGE_SHIFT))
2180                                         get_page(pfn_to_page(addr >> PAGE_SHIFT));
2181                                 addr += PAGE_SIZE;
2182                         }
2183                 }
2184                 force_sig(SIGKILL, current);
2185 
2186                 return true;
2187         }
2188         if (attrs & SUN4V_ERR_ATTRS_PIO) {
2189                 force_sig_fault(SIGBUS, BUS_ADRERR,
2190                                 (void __user *)sun4v_get_vaddr(regs), 0, current);
2191                 return true;
2192         }
2193 
2194         /* Default to doing nothing */
2195         return false;
2196 }
2197 
2198 /* We run with %pil set to PIL_NORMAL_MAX and PSTATE_IE enabled in %pstate.
2199  * Log the event, clear the first word of the entry, and die.
2200  */
2201 void sun4v_nonresum_error(struct pt_regs *regs, unsigned long offset)
2202 {
2203         struct sun4v_error_entry *ent, local_copy;
2204         struct trap_per_cpu *tb;
2205         unsigned long paddr;
2206         int cpu;
2207 
2208         cpu = get_cpu();
2209 
2210         tb = &trap_block[cpu];
2211         paddr = tb->nonresum_kernel_buf_pa + offset;
2212         ent = __va(paddr);
2213 
2214         memcpy(&local_copy, ent, sizeof(struct sun4v_error_entry));
2215 
2216         /* We have a local copy now, so release the entry.  */
2217         ent->err_handle = 0;
2218         wmb();
2219 
2220         put_cpu();
2221 
2222         if (!(regs->tstate & TSTATE_PRIV) &&
2223             sun4v_nonresum_error_user_handled(regs, &local_copy)) {
2224                 /* DON'T PANIC: This userspace error was handled. */
2225                 return;
2226         }
2227 
2228 #ifdef CONFIG_PCI
2229         /* Check for the special PCI poke sequence. */
2230         if (pci_poke_in_progress && pci_poke_cpu == cpu) {
2231                 pci_poke_faulted = 1;
2232                 regs->tpc += 4;
2233                 regs->tnpc = regs->tpc + 4;
2234                 return;
2235         }
2236 #endif
2237 
2238         sun4v_log_error(regs, &local_copy, cpu,
2239                         KERN_EMERG "NON-RESUMABLE ERROR",
2240                         &sun4v_nonresum_oflow_cnt);
2241 
2242         panic("Non-resumable error.");
2243 }
2244 
2245 /* If we try to printk() we'll probably make matters worse, by trying
2246  * to retake locks this cpu already holds or causing more errors. So
2247  * just bump a counter, and we'll report these counter bumps above.
2248  */
2249 void sun4v_nonresum_overflow(struct pt_regs *regs)
2250 {
2251         /* XXX Actually even this can make not that much sense.  Perhaps
2252          * XXX we should just pull the plug and panic directly from here?
2253          */
2254         atomic_inc(&sun4v_nonresum_oflow_cnt);
2255 }
2256 
2257 static void sun4v_tlb_error(struct pt_regs *regs)
2258 {
2259         die_if_kernel("TLB/TSB error", regs);
2260 }
2261 
2262 unsigned long sun4v_err_itlb_vaddr;
2263 unsigned long sun4v_err_itlb_ctx;
2264 unsigned long sun4v_err_itlb_pte;
2265 unsigned long sun4v_err_itlb_error;
2266 
2267 void sun4v_itlb_error_report(struct pt_regs *regs, int tl)
2268 {
2269         dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2270 
2271         printk(KERN_EMERG "SUN4V-ITLB: Error at TPC[%lx], tl %d\n",
2272                regs->tpc, tl);
2273         printk(KERN_EMERG "SUN4V-ITLB: TPC<%pS>\n", (void *) regs->tpc);
2274         printk(KERN_EMERG "SUN4V-ITLB: O7[%lx]\n", regs->u_regs[UREG_I7]);
2275         printk(KERN_EMERG "SUN4V-ITLB: O7<%pS>\n",
2276                (void *) regs->u_regs[UREG_I7]);
2277         printk(KERN_EMERG "SUN4V-ITLB: vaddr[%lx] ctx[%lx] "
2278                "pte[%lx] error[%lx]\n",
2279                sun4v_err_itlb_vaddr, sun4v_err_itlb_ctx,
2280                sun4v_err_itlb_pte, sun4v_err_itlb_error);
2281 
2282         sun4v_tlb_error(regs);
2283 }
2284 
2285 unsigned long sun4v_err_dtlb_vaddr;
2286 unsigned long sun4v_err_dtlb_ctx;
2287 unsigned long sun4v_err_dtlb_pte;
2288 unsigned long sun4v_err_dtlb_error;
2289 
2290 void sun4v_dtlb_error_report(struct pt_regs *regs, int tl)
2291 {
2292         dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2293 
2294         printk(KERN_EMERG "SUN4V-DTLB: Error at TPC[%lx], tl %d\n",
2295                regs->tpc, tl);
2296         printk(KERN_EMERG "SUN4V-DTLB: TPC<%pS>\n", (void *) regs->tpc);
2297         printk(KERN_EMERG "SUN4V-DTLB: O7[%lx]\n", regs->u_regs[UREG_I7]);
2298         printk(KERN_EMERG "SUN4V-DTLB: O7<%pS>\n",
2299                (void *) regs->u_regs[UREG_I7]);
2300         printk(KERN_EMERG "SUN4V-DTLB: vaddr[%lx] ctx[%lx] "
2301                "pte[%lx] error[%lx]\n",
2302                sun4v_err_dtlb_vaddr, sun4v_err_dtlb_ctx,
2303                sun4v_err_dtlb_pte, sun4v_err_dtlb_error);
2304 
2305         sun4v_tlb_error(regs);
2306 }
2307 
2308 void hypervisor_tlbop_error(unsigned long err, unsigned long op)
2309 {
2310         printk(KERN_CRIT "SUN4V: TLB hv call error %lu for op %lu\n",
2311                err, op);
2312 }
2313 
2314 void hypervisor_tlbop_error_xcall(unsigned long err, unsigned long op)
2315 {
2316         printk(KERN_CRIT "SUN4V: XCALL TLB hv call error %lu for op %lu\n",
2317                err, op);
2318 }
2319 
2320 static void do_fpe_common(struct pt_regs *regs)
2321 {
2322         if (regs->tstate & TSTATE_PRIV) {
2323                 regs->tpc = regs->tnpc;
2324                 regs->tnpc += 4;
2325         } else {
2326                 unsigned long fsr = current_thread_info()->xfsr[0];
2327                 int code;
2328 
2329                 if (test_thread_flag(TIF_32BIT)) {
2330                         regs->tpc &= 0xffffffff;
2331                         regs->tnpc &= 0xffffffff;
2332                 }
2333                 code = FPE_FLTUNK;
2334                 if ((fsr & 0x1c000) == (1 << 14)) {
2335                         if (fsr & 0x10)
2336                                 code = FPE_FLTINV;
2337                         else if (fsr & 0x08)
2338                                 code = FPE_FLTOVF;
2339                         else if (fsr & 0x04)
2340                                 code = FPE_FLTUND;
2341                         else if (fsr & 0x02)
2342                                 code = FPE_FLTDIV;
2343                         else if (fsr & 0x01)
2344                                 code = FPE_FLTRES;
2345                 }
2346                 force_sig_fault(SIGFPE, code,
2347                                 (void __user *)regs->tpc, 0, current);
2348         }
2349 }
2350 
2351 void do_fpieee(struct pt_regs *regs)
2352 {
2353         enum ctx_state prev_state = exception_enter();
2354 
2355         if (notify_die(DIE_TRAP, "fpu exception ieee", regs,
2356                        0, 0x24, SIGFPE) == NOTIFY_STOP)
2357                 goto out;
2358 
2359         do_fpe_common(regs);
2360 out:
2361         exception_exit(prev_state);
2362 }
2363 
2364 void do_fpother(struct pt_regs *regs)
2365 {
2366         enum ctx_state prev_state = exception_enter();
2367         struct fpustate *f = FPUSTATE;
2368         int ret = 0;
2369 
2370         if (notify_die(DIE_TRAP, "fpu exception other", regs,
2371                        0, 0x25, SIGFPE) == NOTIFY_STOP)
2372                 goto out;
2373 
2374         switch ((current_thread_info()->xfsr[0] & 0x1c000)) {
2375         case (2 << 14): /* unfinished_FPop */
2376         case (3 << 14): /* unimplemented_FPop */
2377                 ret = do_mathemu(regs, f, false);
2378                 break;
2379         }
2380         if (ret)
2381                 goto out;
2382         do_fpe_common(regs);
2383 out:
2384         exception_exit(prev_state);
2385 }
2386 
2387 void do_tof(struct pt_regs *regs)
2388 {
2389         enum ctx_state prev_state = exception_enter();
2390 
2391         if (notify_die(DIE_TRAP, "tagged arithmetic overflow", regs,
2392                        0, 0x26, SIGEMT) == NOTIFY_STOP)
2393                 goto out;
2394 
2395         if (regs->tstate & TSTATE_PRIV)
2396                 die_if_kernel("Penguin overflow trap from kernel mode", regs);
2397         if (test_thread_flag(TIF_32BIT)) {
2398                 regs->tpc &= 0xffffffff;
2399                 regs->tnpc &= 0xffffffff;
2400         }
2401         force_sig_fault(SIGEMT, EMT_TAGOVF,
2402                         (void __user *)regs->tpc, 0, current);
2403 out:
2404         exception_exit(prev_state);
2405 }
2406 
2407 void do_div0(struct pt_regs *regs)
2408 {
2409         enum ctx_state prev_state = exception_enter();
2410 
2411         if (notify_die(DIE_TRAP, "integer division by zero", regs,
2412                        0, 0x28, SIGFPE) == NOTIFY_STOP)
2413                 goto out;
2414 
2415         if (regs->tstate & TSTATE_PRIV)
2416                 die_if_kernel("TL0: Kernel divide by zero.", regs);
2417         if (test_thread_flag(TIF_32BIT)) {
2418                 regs->tpc &= 0xffffffff;
2419                 regs->tnpc &= 0xffffffff;
2420         }
2421         force_sig_fault(SIGFPE, FPE_INTDIV,
2422                         (void __user *)regs->tpc, 0, current);
2423 out:
2424         exception_exit(prev_state);
2425 }
2426 
2427 static void instruction_dump(unsigned int *pc)
2428 {
2429         int i;
2430 
2431         if ((((unsigned long) pc) & 3))
2432                 return;
2433 
2434         printk("Instruction DUMP:");
2435         for (i = -3; i < 6; i++)
2436                 printk("%c%08x%c",i?' ':'<',pc[i],i?' ':'>');
2437         printk("\n");
2438 }
2439 
2440 static void user_instruction_dump(unsigned int __user *pc)
2441 {
2442         int i;
2443         unsigned int buf[9];
2444         
2445         if ((((unsigned long) pc) & 3))
2446                 return;
2447                 
2448         if (copy_from_user(buf, pc - 3, sizeof(buf)))
2449                 return;
2450 
2451         printk("Instruction DUMP:");
2452         for (i = 0; i < 9; i++)
2453                 printk("%c%08x%c",i==3?' ':'<',buf[i],i==3?' ':'>');
2454         printk("\n");
2455 }
2456 
2457 void show_stack(struct task_struct *tsk, unsigned long *_ksp)
2458 {
2459         unsigned long fp, ksp;
2460         struct thread_info *tp;
2461         int count = 0;
2462 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
2463         int graph = 0;
2464 #endif
2465 
2466         ksp = (unsigned long) _ksp;
2467         if (!tsk)
2468                 tsk = current;
2469         tp = task_thread_info(tsk);
2470         if (ksp == 0UL) {
2471                 if (tsk == current)
2472                         asm("mov %%fp, %0" : "=r" (ksp));
2473                 else
2474                         ksp = tp->ksp;
2475         }
2476         if (tp == current_thread_info())
2477                 flushw_all();
2478 
2479         fp = ksp + STACK_BIAS;
2480 
2481         printk("Call Trace:\n");
2482         do {
2483                 struct sparc_stackf *sf;
2484                 struct pt_regs *regs;
2485                 unsigned long pc;
2486 
2487                 if (!kstack_valid(tp, fp))
2488                         break;
2489                 sf = (struct sparc_stackf *) fp;
2490                 regs = (struct pt_regs *) (sf + 1);
2491 
2492                 if (kstack_is_trap_frame(tp, regs)) {
2493                         if (!(regs->tstate & TSTATE_PRIV))
2494                                 break;
2495                         pc = regs->tpc;
2496                         fp = regs->u_regs[UREG_I6] + STACK_BIAS;
2497                 } else {
2498                         pc = sf->callers_pc;
2499                         fp = (unsigned long)sf->fp + STACK_BIAS;
2500                 }
2501 
2502                 printk(" [%016lx] %pS\n", pc, (void *) pc);
2503 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
2504                 if ((pc + 8UL) == (unsigned long) &return_to_handler) {
2505                         int index = tsk->curr_ret_stack;
2506                         if (tsk->ret_stack && index >= graph) {
2507                                 pc = tsk->ret_stack[index - graph].ret;
2508                                 printk(" [%016lx] %pS\n", pc, (void *) pc);
2509                                 graph++;
2510                         }
2511                 }
2512 #endif
2513         } while (++count < 16);
2514 }
2515 
2516 static inline struct reg_window *kernel_stack_up(struct reg_window *rw)
2517 {
2518         unsigned long fp = rw->ins[6];
2519 
2520         if (!fp)
2521                 return NULL;
2522 
2523         return (struct reg_window *) (fp + STACK_BIAS);
2524 }
2525 
2526 void __noreturn die_if_kernel(char *str, struct pt_regs *regs)
2527 {
2528         static int die_counter;
2529         int count = 0;
2530         
2531         /* Amuse the user. */
2532         printk(
2533 "              \\|/ ____ \\|/\n"
2534 "              \"@'/ .. \\`@\"\n"
2535 "              /_| \\__/ |_\\\n"
2536 "                 \\__U_/\n");
2537 
2538         printk("%s(%d): %s [#%d]\n", current->comm, task_pid_nr(current), str, ++die_counter);
2539         notify_die(DIE_OOPS, str, regs, 0, 255, SIGSEGV);
2540         __asm__ __volatile__("flushw");
2541         show_regs(regs);
2542         add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
2543         if (regs->tstate & TSTATE_PRIV) {
2544                 struct thread_info *tp = current_thread_info();
2545                 struct reg_window *rw = (struct reg_window *)
2546                         (regs->u_regs[UREG_FP] + STACK_BIAS);
2547 
2548                 /* Stop the back trace when we hit userland or we
2549                  * find some badly aligned kernel stack.
2550                  */
2551                 while (rw &&
2552                        count++ < 30 &&
2553                        kstack_valid(tp, (unsigned long) rw)) {
2554                         printk("Caller[%016lx]: %pS\n", rw->ins[7],
2555                                (void *) rw->ins[7]);
2556 
2557                         rw = kernel_stack_up(rw);
2558                 }
2559                 instruction_dump ((unsigned int *) regs->tpc);
2560         } else {
2561                 if (test_thread_flag(TIF_32BIT)) {
2562                         regs->tpc &= 0xffffffff;
2563                         regs->tnpc &= 0xffffffff;
2564                 }
2565                 user_instruction_dump ((unsigned int __user *) regs->tpc);
2566         }
2567         if (panic_on_oops)
2568                 panic("Fatal exception");
2569         if (regs->tstate & TSTATE_PRIV)
2570                 do_exit(SIGKILL);
2571         do_exit(SIGSEGV);
2572 }
2573 EXPORT_SYMBOL(die_if_kernel);
2574 
2575 #define VIS_OPCODE_MASK ((0x3 << 30) | (0x3f << 19))
2576 #define VIS_OPCODE_VAL  ((0x2 << 30) | (0x36 << 19))
2577 
2578 void do_illegal_instruction(struct pt_regs *regs)
2579 {
2580         enum ctx_state prev_state = exception_enter();
2581         unsigned long pc = regs->tpc;
2582         unsigned long tstate = regs->tstate;
2583         u32 insn;
2584 
2585         if (notify_die(DIE_TRAP, "illegal instruction", regs,
2586                        0, 0x10, SIGILL) == NOTIFY_STOP)
2587                 goto out;
2588 
2589         if (tstate & TSTATE_PRIV)
2590                 die_if_kernel("Kernel illegal instruction", regs);
2591         if (test_thread_flag(TIF_32BIT))
2592                 pc = (u32)pc;
2593         if (get_user(insn, (u32 __user *) pc) != -EFAULT) {
2594                 if ((insn & 0xc1ffc000) == 0x81700000) /* POPC */ {
2595                         if (handle_popc(insn, regs))
2596                                 goto out;
2597                 } else if ((insn & 0xc1580000) == 0xc1100000) /* LDQ/STQ */ {
2598                         if (handle_ldf_stq(insn, regs))
2599                                 goto out;
2600                 } else if (tlb_type == hypervisor) {
2601                         if ((insn & VIS_OPCODE_MASK) == VIS_OPCODE_VAL) {
2602                                 if (!vis_emul(regs, insn))
2603                                         goto out;
2604                         } else {
2605                                 struct fpustate *f = FPUSTATE;
2606 
2607                                 /* On UltraSPARC T2 and later, FPU insns which
2608                                  * are not implemented in HW signal an illegal
2609                                  * instruction trap and do not set the FP Trap
2610                                  * Trap in the %fsr to unimplemented_FPop.
2611                                  */
2612                                 if (do_mathemu(regs, f, true))
2613                                         goto out;
2614                         }
2615                 }
2616         }
2617         force_sig_fault(SIGILL, ILL_ILLOPC, (void __user *)pc, 0, current);
2618 out:
2619         exception_exit(prev_state);
2620 }
2621 
2622 void mem_address_unaligned(struct pt_regs *regs, unsigned long sfar, unsigned long sfsr)
2623 {
2624         enum ctx_state prev_state = exception_enter();
2625 
2626         if (notify_die(DIE_TRAP, "memory address unaligned", regs,
2627                        0, 0x34, SIGSEGV) == NOTIFY_STOP)
2628                 goto out;
2629 
2630         if (regs->tstate & TSTATE_PRIV) {
2631                 kernel_unaligned_trap(regs, *((unsigned int *)regs->tpc));
2632                 goto out;
2633         }
2634         if (is_no_fault_exception(regs))
2635                 return;
2636 
2637         force_sig_fault(SIGBUS, BUS_ADRALN, (void __user *)sfar, 0, current);
2638 out:
2639         exception_exit(prev_state);
2640 }
2641 
2642 void sun4v_do_mna(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
2643 {
2644         if (notify_die(DIE_TRAP, "memory address unaligned", regs,
2645                        0, 0x34, SIGSEGV) == NOTIFY_STOP)
2646                 return;
2647 
2648         if (regs->tstate & TSTATE_PRIV) {
2649                 kernel_unaligned_trap(regs, *((unsigned int *)regs->tpc));
2650                 return;
2651         }
2652         if (is_no_fault_exception(regs))
2653                 return;
2654 
2655         force_sig_fault(SIGBUS, BUS_ADRALN, (void __user *) addr, 0, current);
2656 }
2657 
2658 /* sun4v_mem_corrupt_detect_precise() - Handle precise exception on an ADI
2659  * tag mismatch.
2660  *
2661  * ADI version tag mismatch on a load from memory always results in a
2662  * precise exception. Tag mismatch on a store to memory will result in
2663  * precise exception if MCDPER or PMCDPER is set to 1.
2664  */
2665 void sun4v_mem_corrupt_detect_precise(struct pt_regs *regs, unsigned long addr,
2666                                       unsigned long context)
2667 {
2668         if (notify_die(DIE_TRAP, "memory corruption precise exception", regs,
2669                        0, 0x8, SIGSEGV) == NOTIFY_STOP)
2670                 return;
2671 
2672         if (regs->tstate & TSTATE_PRIV) {
2673                 /* MCD exception could happen because the task was running
2674                  * a system call with MCD enabled and passed a non-versioned
2675                  * pointer or pointer with bad version tag to  the system
2676                  * call.
2677                  */
2678                 const struct exception_table_entry *entry;
2679 
2680                 entry = search_exception_tables(regs->tpc);
2681                 if (entry) {
2682                         /* Looks like a bad syscall parameter */
2683 #ifdef DEBUG_EXCEPTIONS
2684                         pr_emerg("Exception: PC<%016lx> faddr<UNKNOWN>\n",
2685                                  regs->tpc);
2686                         pr_emerg("EX_TABLE: insn<%016lx> fixup<%016lx>\n",
2687                                  regs->tpc, entry->fixup);
2688 #endif
2689                         regs->tpc = entry->fixup;
2690                         regs->tnpc = regs->tpc + 4;
2691                         return;
2692                 }
2693                 pr_emerg("%s: ADDR[%016lx] CTX[%lx], going.\n",
2694                          __func__, addr, context);
2695                 die_if_kernel("MCD precise", regs);
2696         }
2697 
2698         if (test_thread_flag(TIF_32BIT)) {
2699                 regs->tpc &= 0xffffffff;
2700                 regs->tnpc &= 0xffffffff;
2701         }
2702         force_sig_fault(SIGSEGV, SEGV_ADIPERR, (void __user *)addr, 0, current);
2703 }
2704 
2705 void do_privop(struct pt_regs *regs)
2706 {
2707         enum ctx_state prev_state = exception_enter();
2708 
2709         if (notify_die(DIE_TRAP, "privileged operation", regs,
2710                        0, 0x11, SIGILL) == NOTIFY_STOP)
2711                 goto out;
2712 
2713         if (test_thread_flag(TIF_32BIT)) {
2714                 regs->tpc &= 0xffffffff;
2715                 regs->tnpc &= 0xffffffff;
2716         }
2717         force_sig_fault(SIGILL, ILL_PRVOPC,
2718                         (void __user *)regs->tpc, 0, current);
2719 out:
2720         exception_exit(prev_state);
2721 }
2722 
2723 void do_privact(struct pt_regs *regs)
2724 {
2725         do_privop(regs);
2726 }
2727 
2728 /* Trap level 1 stuff or other traps we should never see... */
2729 void do_cee(struct pt_regs *regs)
2730 {
2731         exception_enter();
2732         die_if_kernel("TL0: Cache Error Exception", regs);
2733 }
2734 
2735 void do_div0_tl1(struct pt_regs *regs)
2736 {
2737         exception_enter();
2738         dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2739         die_if_kernel("TL1: DIV0 Exception", regs);
2740 }
2741 
2742 void do_fpieee_tl1(struct pt_regs *regs)
2743 {
2744         exception_enter();
2745         dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2746         die_if_kernel("TL1: FPU IEEE Exception", regs);
2747 }
2748 
2749 void do_fpother_tl1(struct pt_regs *regs)
2750 {
2751         exception_enter();
2752         dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2753         die_if_kernel("TL1: FPU Other Exception", regs);
2754 }
2755 
2756 void do_ill_tl1(struct pt_regs *regs)
2757 {
2758         exception_enter();
2759         dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2760         die_if_kernel("TL1: Illegal Instruction Exception", regs);
2761 }
2762 
2763 void do_irq_tl1(struct pt_regs *regs)
2764 {
2765         exception_enter();
2766         dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2767         die_if_kernel("TL1: IRQ Exception", regs);
2768 }
2769 
2770 void do_lddfmna_tl1(struct pt_regs *regs)
2771 {
2772         exception_enter();
2773         dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2774         die_if_kernel("TL1: LDDF Exception", regs);
2775 }
2776 
2777 void do_stdfmna_tl1(struct pt_regs *regs)
2778 {
2779         exception_enter();
2780         dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2781         die_if_kernel("TL1: STDF Exception", regs);
2782 }
2783 
2784 void do_paw(struct pt_regs *regs)
2785 {
2786         exception_enter();
2787         die_if_kernel("TL0: Phys Watchpoint Exception", regs);
2788 }
2789 
2790 void do_paw_tl1(struct pt_regs *regs)
2791 {
2792         exception_enter();
2793         dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2794         die_if_kernel("TL1: Phys Watchpoint Exception", regs);
2795 }
2796 
2797 void do_vaw(struct pt_regs *regs)
2798 {
2799         exception_enter();
2800         die_if_kernel("TL0: Virt Watchpoint Exception", regs);
2801 }
2802 
2803 void do_vaw_tl1(struct pt_regs *regs)
2804 {
2805         exception_enter();
2806         dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2807         die_if_kernel("TL1: Virt Watchpoint Exception", regs);
2808 }
2809 
2810 void do_tof_tl1(struct pt_regs *regs)
2811 {
2812         exception_enter();
2813         dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2814         die_if_kernel("TL1: Tag Overflow Exception", regs);
2815 }
2816 
2817 void do_getpsr(struct pt_regs *regs)
2818 {
2819         regs->u_regs[UREG_I0] = tstate_to_psr(regs->tstate);
2820         regs->tpc   = regs->tnpc;
2821         regs->tnpc += 4;
2822         if (test_thread_flag(TIF_32BIT)) {
2823                 regs->tpc &= 0xffffffff;
2824                 regs->tnpc &= 0xffffffff;
2825         }
2826 }
2827 
2828 u64 cpu_mondo_counter[NR_CPUS] = {0};
2829 struct trap_per_cpu trap_block[NR_CPUS];
2830 EXPORT_SYMBOL(trap_block);
2831 
2832 /* This can get invoked before sched_init() so play it super safe
2833  * and use hard_smp_processor_id().
2834  */
2835 void notrace init_cur_cpu_trap(struct thread_info *t)
2836 {
2837         int cpu = hard_smp_processor_id();
2838         struct trap_per_cpu *p = &trap_block[cpu];
2839 
2840         p->thread = t;
2841         p->pgd_paddr = 0;
2842 }
2843 
2844 extern void thread_info_offsets_are_bolixed_dave(void);
2845 extern void trap_per_cpu_offsets_are_bolixed_dave(void);
2846 extern void tsb_config_offsets_are_bolixed_dave(void);
2847 
2848 /* Only invoked on boot processor. */
2849 void __init trap_init(void)
2850 {
2851         /* Compile time sanity check. */
2852         BUILD_BUG_ON(TI_TASK != offsetof(struct thread_info, task) ||
2853                      TI_FLAGS != offsetof(struct thread_info, flags) ||
2854                      TI_CPU != offsetof(struct thread_info, cpu) ||
2855                      TI_FPSAVED != offsetof(struct thread_info, fpsaved) ||
2856                      TI_KSP != offsetof(struct thread_info, ksp) ||
2857                      TI_FAULT_ADDR != offsetof(struct thread_info,
2858                                                fault_address) ||
2859                      TI_KREGS != offsetof(struct thread_info, kregs) ||
2860                      TI_UTRAPS != offsetof(struct thread_info, utraps) ||
2861                      TI_REG_WINDOW != offsetof(struct thread_info,
2862                                                reg_window) ||
2863                      TI_RWIN_SPTRS != offsetof(struct thread_info,
2864                                                rwbuf_stkptrs) ||
2865                      TI_GSR != offsetof(struct thread_info, gsr) ||
2866                      TI_XFSR != offsetof(struct thread_info, xfsr) ||
2867                      TI_PRE_COUNT != offsetof(struct thread_info,
2868                                               preempt_count) ||
2869                      TI_NEW_CHILD != offsetof(struct thread_info, new_child) ||
2870                      TI_CURRENT_DS != offsetof(struct thread_info,
2871                                                 current_ds) ||
2872                      TI_KUNA_REGS != offsetof(struct thread_info,
2873                                               kern_una_regs) ||
2874                      TI_KUNA_INSN != offsetof(struct thread_info,
2875                                               kern_una_insn) ||
2876                      TI_FPREGS != offsetof(struct thread_info, fpregs) ||
2877                      (TI_FPREGS & (64 - 1)));
2878 
2879         BUILD_BUG_ON(TRAP_PER_CPU_THREAD != offsetof(struct trap_per_cpu,
2880                                                      thread) ||
2881                      (TRAP_PER_CPU_PGD_PADDR !=
2882                       offsetof(struct trap_per_cpu, pgd_paddr)) ||
2883                      (TRAP_PER_CPU_CPU_MONDO_PA !=
2884                       offsetof(struct trap_per_cpu, cpu_mondo_pa)) ||
2885                      (TRAP_PER_CPU_DEV_MONDO_PA !=
2886                       offsetof(struct trap_per_cpu, dev_mondo_pa)) ||
2887                      (TRAP_PER_CPU_RESUM_MONDO_PA !=
2888                       offsetof(struct trap_per_cpu, resum_mondo_pa)) ||
2889                      (TRAP_PER_CPU_RESUM_KBUF_PA !=
2890                       offsetof(struct trap_per_cpu, resum_kernel_buf_pa)) ||
2891                      (TRAP_PER_CPU_NONRESUM_MONDO_PA !=
2892                       offsetof(struct trap_per_cpu, nonresum_mondo_pa)) ||
2893                      (TRAP_PER_CPU_NONRESUM_KBUF_PA !=
2894                       offsetof(struct trap_per_cpu, nonresum_kernel_buf_pa)) ||
2895                      (TRAP_PER_CPU_FAULT_INFO !=
2896                       offsetof(struct trap_per_cpu, fault_info)) ||
2897                      (TRAP_PER_CPU_CPU_MONDO_BLOCK_PA !=
2898                       offsetof(struct trap_per_cpu, cpu_mondo_block_pa)) ||
2899                      (TRAP_PER_CPU_CPU_LIST_PA !=
2900                       offsetof(struct trap_per_cpu, cpu_list_pa)) ||
2901                      (TRAP_PER_CPU_TSB_HUGE !=
2902                       offsetof(struct trap_per_cpu, tsb_huge)) ||
2903                      (TRAP_PER_CPU_TSB_HUGE_TEMP !=
2904                       offsetof(struct trap_per_cpu, tsb_huge_temp)) ||
2905                      (TRAP_PER_CPU_IRQ_WORKLIST_PA !=
2906                       offsetof(struct trap_per_cpu, irq_worklist_pa)) ||
2907                      (TRAP_PER_CPU_CPU_MONDO_QMASK !=
2908                       offsetof(struct trap_per_cpu, cpu_mondo_qmask)) ||
2909                      (TRAP_PER_CPU_DEV_MONDO_QMASK !=
2910                       offsetof(struct trap_per_cpu, dev_mondo_qmask)) ||
2911                      (TRAP_PER_CPU_RESUM_QMASK !=
2912                       offsetof(struct trap_per_cpu, resum_qmask)) ||
2913                      (TRAP_PER_CPU_NONRESUM_QMASK !=
2914                       offsetof(struct trap_per_cpu, nonresum_qmask)) ||
2915                      (TRAP_PER_CPU_PER_CPU_BASE !=
2916                       offsetof(struct trap_per_cpu, __per_cpu_base)));
2917 
2918         BUILD_BUG_ON((TSB_CONFIG_TSB !=
2919                       offsetof(struct tsb_config, tsb)) ||
2920                      (TSB_CONFIG_RSS_LIMIT !=
2921                       offsetof(struct tsb_config, tsb_rss_limit)) ||
2922                      (TSB_CONFIG_NENTRIES !=
2923                       offsetof(struct tsb_config, tsb_nentries)) ||
2924                      (TSB_CONFIG_REG_VAL !=
2925                       offsetof(struct tsb_config, tsb_reg_val)) ||
2926                      (TSB_CONFIG_MAP_VADDR !=
2927                       offsetof(struct tsb_config, tsb_map_vaddr)) ||
2928                      (TSB_CONFIG_MAP_PTE !=
2929                       offsetof(struct tsb_config, tsb_map_pte)));
2930 
2931         /* Attach to the address space of init_task.  On SMP we
2932          * do this in smp.c:smp_callin for other cpus.
2933          */
2934         mmgrab(&init_mm);
2935         current->active_mm = &init_mm;
2936 }
2937 

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