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TOMOYO Linux Cross Reference
Linux/arch/sparc/kernel/traps_64.c

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Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 /* arch/sparc64/kernel/traps.c
  2  *
  3  * Copyright (C) 1995,1997,2008,2009,2012 David S. Miller (davem@davemloft.net)
  4  * Copyright (C) 1997,1999,2000 Jakub Jelinek (jakub@redhat.com)
  5  */
  6 
  7 /*
  8  * I like traps on v9, :))))
  9  */
 10 
 11 #include <linux/extable.h>
 12 #include <linux/sched/mm.h>
 13 #include <linux/sched/debug.h>
 14 #include <linux/linkage.h>
 15 #include <linux/kernel.h>
 16 #include <linux/signal.h>
 17 #include <linux/smp.h>
 18 #include <linux/mm.h>
 19 #include <linux/init.h>
 20 #include <linux/kdebug.h>
 21 #include <linux/ftrace.h>
 22 #include <linux/reboot.h>
 23 #include <linux/gfp.h>
 24 #include <linux/context_tracking.h>
 25 
 26 #include <asm/smp.h>
 27 #include <asm/delay.h>
 28 #include <asm/ptrace.h>
 29 #include <asm/oplib.h>
 30 #include <asm/page.h>
 31 #include <asm/pgtable.h>
 32 #include <asm/unistd.h>
 33 #include <linux/uaccess.h>
 34 #include <asm/fpumacro.h>
 35 #include <asm/lsu.h>
 36 #include <asm/dcu.h>
 37 #include <asm/estate.h>
 38 #include <asm/chafsr.h>
 39 #include <asm/sfafsr.h>
 40 #include <asm/psrcompat.h>
 41 #include <asm/processor.h>
 42 #include <asm/timer.h>
 43 #include <asm/head.h>
 44 #include <asm/prom.h>
 45 #include <asm/memctrl.h>
 46 #include <asm/cacheflush.h>
 47 #include <asm/setup.h>
 48 
 49 #include "entry.h"
 50 #include "kernel.h"
 51 #include "kstack.h"
 52 
 53 /* When an irrecoverable trap occurs at tl > 0, the trap entry
 54  * code logs the trap state registers at every level in the trap
 55  * stack.  It is found at (pt_regs + sizeof(pt_regs)) and the layout
 56  * is as follows:
 57  */
 58 struct tl1_traplog {
 59         struct {
 60                 unsigned long tstate;
 61                 unsigned long tpc;
 62                 unsigned long tnpc;
 63                 unsigned long tt;
 64         } trapstack[4];
 65         unsigned long tl;
 66 };
 67 
 68 static void dump_tl1_traplog(struct tl1_traplog *p)
 69 {
 70         int i, limit;
 71 
 72         printk(KERN_EMERG "TRAPLOG: Error at trap level 0x%lx, "
 73                "dumping track stack.\n", p->tl);
 74 
 75         limit = (tlb_type == hypervisor) ? 2 : 4;
 76         for (i = 0; i < limit; i++) {
 77                 printk(KERN_EMERG
 78                        "TRAPLOG: Trap level %d TSTATE[%016lx] TPC[%016lx] "
 79                        "TNPC[%016lx] TT[%lx]\n",
 80                        i + 1,
 81                        p->trapstack[i].tstate, p->trapstack[i].tpc,
 82                        p->trapstack[i].tnpc, p->trapstack[i].tt);
 83                 printk("TRAPLOG: TPC<%pS>\n", (void *) p->trapstack[i].tpc);
 84         }
 85 }
 86 
 87 void bad_trap(struct pt_regs *regs, long lvl)
 88 {
 89         char buffer[36];
 90         siginfo_t info;
 91 
 92         if (notify_die(DIE_TRAP, "bad trap", regs,
 93                        0, lvl, SIGTRAP) == NOTIFY_STOP)
 94                 return;
 95 
 96         if (lvl < 0x100) {
 97                 sprintf(buffer, "Bad hw trap %lx at tl0\n", lvl);
 98                 die_if_kernel(buffer, regs);
 99         }
100 
101         lvl -= 0x100;
102         if (regs->tstate & TSTATE_PRIV) {
103                 sprintf(buffer, "Kernel bad sw trap %lx", lvl);
104                 die_if_kernel(buffer, regs);
105         }
106         if (test_thread_flag(TIF_32BIT)) {
107                 regs->tpc &= 0xffffffff;
108                 regs->tnpc &= 0xffffffff;
109         }
110         info.si_signo = SIGILL;
111         info.si_errno = 0;
112         info.si_code = ILL_ILLTRP;
113         info.si_addr = (void __user *)regs->tpc;
114         info.si_trapno = lvl;
115         force_sig_info(SIGILL, &info, current);
116 }
117 
118 void bad_trap_tl1(struct pt_regs *regs, long lvl)
119 {
120         char buffer[36];
121         
122         if (notify_die(DIE_TRAP_TL1, "bad trap tl1", regs,
123                        0, lvl, SIGTRAP) == NOTIFY_STOP)
124                 return;
125 
126         dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
127 
128         sprintf (buffer, "Bad trap %lx at tl>0", lvl);
129         die_if_kernel (buffer, regs);
130 }
131 
132 #ifdef CONFIG_DEBUG_BUGVERBOSE
133 void do_BUG(const char *file, int line)
134 {
135         bust_spinlocks(1);
136         printk("kernel BUG at %s:%d!\n", file, line);
137 }
138 EXPORT_SYMBOL(do_BUG);
139 #endif
140 
141 static DEFINE_SPINLOCK(dimm_handler_lock);
142 static dimm_printer_t dimm_handler;
143 
144 static int sprintf_dimm(int synd_code, unsigned long paddr, char *buf, int buflen)
145 {
146         unsigned long flags;
147         int ret = -ENODEV;
148 
149         spin_lock_irqsave(&dimm_handler_lock, flags);
150         if (dimm_handler) {
151                 ret = dimm_handler(synd_code, paddr, buf, buflen);
152         } else if (tlb_type == spitfire) {
153                 if (prom_getunumber(synd_code, paddr, buf, buflen) == -1)
154                         ret = -EINVAL;
155                 else
156                         ret = 0;
157         } else
158                 ret = -ENODEV;
159         spin_unlock_irqrestore(&dimm_handler_lock, flags);
160 
161         return ret;
162 }
163 
164 int register_dimm_printer(dimm_printer_t func)
165 {
166         unsigned long flags;
167         int ret = 0;
168 
169         spin_lock_irqsave(&dimm_handler_lock, flags);
170         if (!dimm_handler)
171                 dimm_handler = func;
172         else
173                 ret = -EEXIST;
174         spin_unlock_irqrestore(&dimm_handler_lock, flags);
175 
176         return ret;
177 }
178 EXPORT_SYMBOL_GPL(register_dimm_printer);
179 
180 void unregister_dimm_printer(dimm_printer_t func)
181 {
182         unsigned long flags;
183 
184         spin_lock_irqsave(&dimm_handler_lock, flags);
185         if (dimm_handler == func)
186                 dimm_handler = NULL;
187         spin_unlock_irqrestore(&dimm_handler_lock, flags);
188 }
189 EXPORT_SYMBOL_GPL(unregister_dimm_printer);
190 
191 void spitfire_insn_access_exception(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)
192 {
193         enum ctx_state prev_state = exception_enter();
194         siginfo_t info;
195 
196         if (notify_die(DIE_TRAP, "instruction access exception", regs,
197                        0, 0x8, SIGTRAP) == NOTIFY_STOP)
198                 goto out;
199 
200         if (regs->tstate & TSTATE_PRIV) {
201                 printk("spitfire_insn_access_exception: SFSR[%016lx] "
202                        "SFAR[%016lx], going.\n", sfsr, sfar);
203                 die_if_kernel("Iax", regs);
204         }
205         if (test_thread_flag(TIF_32BIT)) {
206                 regs->tpc &= 0xffffffff;
207                 regs->tnpc &= 0xffffffff;
208         }
209         info.si_signo = SIGSEGV;
210         info.si_errno = 0;
211         info.si_code = SEGV_MAPERR;
212         info.si_addr = (void __user *)regs->tpc;
213         info.si_trapno = 0;
214         force_sig_info(SIGSEGV, &info, current);
215 out:
216         exception_exit(prev_state);
217 }
218 
219 void spitfire_insn_access_exception_tl1(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)
220 {
221         if (notify_die(DIE_TRAP_TL1, "instruction access exception tl1", regs,
222                        0, 0x8, SIGTRAP) == NOTIFY_STOP)
223                 return;
224 
225         dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
226         spitfire_insn_access_exception(regs, sfsr, sfar);
227 }
228 
229 void sun4v_insn_access_exception(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
230 {
231         unsigned short type = (type_ctx >> 16);
232         unsigned short ctx  = (type_ctx & 0xffff);
233         siginfo_t info;
234 
235         if (notify_die(DIE_TRAP, "instruction access exception", regs,
236                        0, 0x8, SIGTRAP) == NOTIFY_STOP)
237                 return;
238 
239         if (regs->tstate & TSTATE_PRIV) {
240                 printk("sun4v_insn_access_exception: ADDR[%016lx] "
241                        "CTX[%04x] TYPE[%04x], going.\n",
242                        addr, ctx, type);
243                 die_if_kernel("Iax", regs);
244         }
245 
246         if (test_thread_flag(TIF_32BIT)) {
247                 regs->tpc &= 0xffffffff;
248                 regs->tnpc &= 0xffffffff;
249         }
250         info.si_signo = SIGSEGV;
251         info.si_errno = 0;
252         info.si_code = SEGV_MAPERR;
253         info.si_addr = (void __user *) addr;
254         info.si_trapno = 0;
255         force_sig_info(SIGSEGV, &info, current);
256 }
257 
258 void sun4v_insn_access_exception_tl1(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
259 {
260         if (notify_die(DIE_TRAP_TL1, "instruction access exception tl1", regs,
261                        0, 0x8, SIGTRAP) == NOTIFY_STOP)
262                 return;
263 
264         dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
265         sun4v_insn_access_exception(regs, addr, type_ctx);
266 }
267 
268 bool is_no_fault_exception(struct pt_regs *regs)
269 {
270         unsigned char asi;
271         u32 insn;
272 
273         if (get_user(insn, (u32 __user *)regs->tpc) == -EFAULT)
274                 return false;
275 
276         /*
277          * Must do a little instruction decoding here in order to
278          * decide on a course of action. The bits of interest are:
279          *  insn[31:30] = op, where 3 indicates the load/store group
280          *  insn[24:19] = op3, which identifies individual opcodes
281          *  insn[13] indicates an immediate offset
282          *  op3[4]=1 identifies alternate space instructions
283          *  op3[5:4]=3 identifies floating point instructions
284          *  op3[2]=1 identifies stores
285          * See "Opcode Maps" in the appendix of any Sparc V9
286          * architecture spec for full details.
287          */
288         if ((insn & 0xc0800000) == 0xc0800000) {    /* op=3, op3[4]=1   */
289                 if (insn & 0x2000)                  /* immediate offset */
290                         asi = (regs->tstate >> 24); /* saved %asi       */
291                 else
292                         asi = (insn >> 5);          /* immediate asi    */
293                 if ((asi & 0xf2) == ASI_PNF) {
294                         if (insn & 0x1000000) {     /* op3[5:4]=3       */
295                                 handle_ldf_stq(insn, regs);
296                                 return true;
297                         } else if (insn & 0x200000) { /* op3[2], stores */
298                                 return false;
299                         }
300                         handle_ld_nf(insn, regs);
301                         return true;
302                 }
303         }
304         return false;
305 }
306 
307 void spitfire_data_access_exception(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)
308 {
309         enum ctx_state prev_state = exception_enter();
310         siginfo_t info;
311 
312         if (notify_die(DIE_TRAP, "data access exception", regs,
313                        0, 0x30, SIGTRAP) == NOTIFY_STOP)
314                 goto out;
315 
316         if (regs->tstate & TSTATE_PRIV) {
317                 /* Test if this comes from uaccess places. */
318                 const struct exception_table_entry *entry;
319 
320                 entry = search_exception_tables(regs->tpc);
321                 if (entry) {
322                         /* Ouch, somebody is trying VM hole tricks on us... */
323 #ifdef DEBUG_EXCEPTIONS
324                         printk("Exception: PC<%016lx> faddr<UNKNOWN>\n", regs->tpc);
325                         printk("EX_TABLE: insn<%016lx> fixup<%016lx>\n",
326                                regs->tpc, entry->fixup);
327 #endif
328                         regs->tpc = entry->fixup;
329                         regs->tnpc = regs->tpc + 4;
330                         goto out;
331                 }
332                 /* Shit... */
333                 printk("spitfire_data_access_exception: SFSR[%016lx] "
334                        "SFAR[%016lx], going.\n", sfsr, sfar);
335                 die_if_kernel("Dax", regs);
336         }
337 
338         if (is_no_fault_exception(regs))
339                 return;
340 
341         info.si_signo = SIGSEGV;
342         info.si_errno = 0;
343         info.si_code = SEGV_MAPERR;
344         info.si_addr = (void __user *)sfar;
345         info.si_trapno = 0;
346         force_sig_info(SIGSEGV, &info, current);
347 out:
348         exception_exit(prev_state);
349 }
350 
351 void spitfire_data_access_exception_tl1(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)
352 {
353         if (notify_die(DIE_TRAP_TL1, "data access exception tl1", regs,
354                        0, 0x30, SIGTRAP) == NOTIFY_STOP)
355                 return;
356 
357         dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
358         spitfire_data_access_exception(regs, sfsr, sfar);
359 }
360 
361 void sun4v_data_access_exception(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
362 {
363         unsigned short type = (type_ctx >> 16);
364         unsigned short ctx  = (type_ctx & 0xffff);
365 
366         if (notify_die(DIE_TRAP, "data access exception", regs,
367                        0, 0x8, SIGTRAP) == NOTIFY_STOP)
368                 return;
369 
370         if (regs->tstate & TSTATE_PRIV) {
371                 /* Test if this comes from uaccess places. */
372                 const struct exception_table_entry *entry;
373 
374                 entry = search_exception_tables(regs->tpc);
375                 if (entry) {
376                         /* Ouch, somebody is trying VM hole tricks on us... */
377 #ifdef DEBUG_EXCEPTIONS
378                         printk("Exception: PC<%016lx> faddr<UNKNOWN>\n", regs->tpc);
379                         printk("EX_TABLE: insn<%016lx> fixup<%016lx>\n",
380                                regs->tpc, entry->fixup);
381 #endif
382                         regs->tpc = entry->fixup;
383                         regs->tnpc = regs->tpc + 4;
384                         return;
385                 }
386                 printk("sun4v_data_access_exception: ADDR[%016lx] "
387                        "CTX[%04x] TYPE[%04x], going.\n",
388                        addr, ctx, type);
389                 die_if_kernel("Dax", regs);
390         }
391 
392         if (test_thread_flag(TIF_32BIT)) {
393                 regs->tpc &= 0xffffffff;
394                 regs->tnpc &= 0xffffffff;
395         }
396         if (is_no_fault_exception(regs))
397                 return;
398 
399         /* MCD (Memory Corruption Detection) disabled trap (TT=0x19) in HV
400          * is vectored thorugh data access exception trap with fault type
401          * set to HV_FAULT_TYPE_MCD_DIS. Check for MCD disabled trap.
402          * Accessing an address with invalid ASI for the address, for
403          * example setting an ADI tag on an address with ASI_MCD_PRIMARY
404          * when TTE.mcd is not set for the VA, is also vectored into
405          * kerbel by HV as data access exception with fault type set to
406          * HV_FAULT_TYPE_INV_ASI.
407          */
408         switch (type) {
409         case HV_FAULT_TYPE_INV_ASI:
410                 force_sig_fault(SIGILL, ILL_ILLADR, (void __user *)addr, 0,
411                                 current);
412                 break;
413         case HV_FAULT_TYPE_MCD_DIS:
414                 force_sig_fault(SIGSEGV, SEGV_ACCADI, (void __user *)addr, 0,
415                                 current);
416                 break;
417         default:
418                 force_sig_fault(SIGSEGV, SEGV_MAPERR, (void __user *)addr, 0,
419                                 current);
420                 break;
421         }
422 }
423 
424 void sun4v_data_access_exception_tl1(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
425 {
426         if (notify_die(DIE_TRAP_TL1, "data access exception tl1", regs,
427                        0, 0x8, SIGTRAP) == NOTIFY_STOP)
428                 return;
429 
430         dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
431         sun4v_data_access_exception(regs, addr, type_ctx);
432 }
433 
434 #ifdef CONFIG_PCI
435 #include "pci_impl.h"
436 #endif
437 
438 /* When access exceptions happen, we must do this. */
439 static void spitfire_clean_and_reenable_l1_caches(void)
440 {
441         unsigned long va;
442 
443         if (tlb_type != spitfire)
444                 BUG();
445 
446         /* Clean 'em. */
447         for (va =  0; va < (PAGE_SIZE << 1); va += 32) {
448                 spitfire_put_icache_tag(va, 0x0);
449                 spitfire_put_dcache_tag(va, 0x0);
450         }
451 
452         /* Re-enable in LSU. */
453         __asm__ __volatile__("flush %%g6\n\t"
454                              "membar #Sync\n\t"
455                              "stxa %0, [%%g0] %1\n\t"
456                              "membar #Sync"
457                              : /* no outputs */
458                              : "r" (LSU_CONTROL_IC | LSU_CONTROL_DC |
459                                     LSU_CONTROL_IM | LSU_CONTROL_DM),
460                              "i" (ASI_LSU_CONTROL)
461                              : "memory");
462 }
463 
464 static void spitfire_enable_estate_errors(void)
465 {
466         __asm__ __volatile__("stxa      %0, [%%g0] %1\n\t"
467                              "membar    #Sync"
468                              : /* no outputs */
469                              : "r" (ESTATE_ERR_ALL),
470                                "i" (ASI_ESTATE_ERROR_EN));
471 }
472 
473 static char ecc_syndrome_table[] = {
474         0x4c, 0x40, 0x41, 0x48, 0x42, 0x48, 0x48, 0x49,
475         0x43, 0x48, 0x48, 0x49, 0x48, 0x49, 0x49, 0x4a,
476         0x44, 0x48, 0x48, 0x20, 0x48, 0x39, 0x4b, 0x48,
477         0x48, 0x25, 0x31, 0x48, 0x28, 0x48, 0x48, 0x2c,
478         0x45, 0x48, 0x48, 0x21, 0x48, 0x3d, 0x04, 0x48,
479         0x48, 0x4b, 0x35, 0x48, 0x2d, 0x48, 0x48, 0x29,
480         0x48, 0x00, 0x01, 0x48, 0x0a, 0x48, 0x48, 0x4b,
481         0x0f, 0x48, 0x48, 0x4b, 0x48, 0x49, 0x49, 0x48,
482         0x46, 0x48, 0x48, 0x2a, 0x48, 0x3b, 0x27, 0x48,
483         0x48, 0x4b, 0x33, 0x48, 0x22, 0x48, 0x48, 0x2e,
484         0x48, 0x19, 0x1d, 0x48, 0x1b, 0x4a, 0x48, 0x4b,
485         0x1f, 0x48, 0x4a, 0x4b, 0x48, 0x4b, 0x4b, 0x48,
486         0x48, 0x4b, 0x24, 0x48, 0x07, 0x48, 0x48, 0x36,
487         0x4b, 0x48, 0x48, 0x3e, 0x48, 0x30, 0x38, 0x48,
488         0x49, 0x48, 0x48, 0x4b, 0x48, 0x4b, 0x16, 0x48,
489         0x48, 0x12, 0x4b, 0x48, 0x49, 0x48, 0x48, 0x4b,
490         0x47, 0x48, 0x48, 0x2f, 0x48, 0x3f, 0x4b, 0x48,
491         0x48, 0x06, 0x37, 0x48, 0x23, 0x48, 0x48, 0x2b,
492         0x48, 0x05, 0x4b, 0x48, 0x4b, 0x48, 0x48, 0x32,
493         0x26, 0x48, 0x48, 0x3a, 0x48, 0x34, 0x3c, 0x48,
494         0x48, 0x11, 0x15, 0x48, 0x13, 0x4a, 0x48, 0x4b,
495         0x17, 0x48, 0x4a, 0x4b, 0x48, 0x4b, 0x4b, 0x48,
496         0x49, 0x48, 0x48, 0x4b, 0x48, 0x4b, 0x1e, 0x48,
497         0x48, 0x1a, 0x4b, 0x48, 0x49, 0x48, 0x48, 0x4b,
498         0x48, 0x08, 0x0d, 0x48, 0x02, 0x48, 0x48, 0x49,
499         0x03, 0x48, 0x48, 0x49, 0x48, 0x4b, 0x4b, 0x48,
500         0x49, 0x48, 0x48, 0x49, 0x48, 0x4b, 0x10, 0x48,
501         0x48, 0x14, 0x4b, 0x48, 0x4b, 0x48, 0x48, 0x4b,
502         0x49, 0x48, 0x48, 0x49, 0x48, 0x4b, 0x18, 0x48,
503         0x48, 0x1c, 0x4b, 0x48, 0x4b, 0x48, 0x48, 0x4b,
504         0x4a, 0x0c, 0x09, 0x48, 0x0e, 0x48, 0x48, 0x4b,
505         0x0b, 0x48, 0x48, 0x4b, 0x48, 0x4b, 0x4b, 0x4a
506 };
507 
508 static char *syndrome_unknown = "<Unknown>";
509 
510 static void spitfire_log_udb_syndrome(unsigned long afar, unsigned long udbh, unsigned long udbl, unsigned long bit)
511 {
512         unsigned short scode;
513         char memmod_str[64], *p;
514 
515         if (udbl & bit) {
516                 scode = ecc_syndrome_table[udbl & 0xff];
517                 if (sprintf_dimm(scode, afar, memmod_str, sizeof(memmod_str)) < 0)
518                         p = syndrome_unknown;
519                 else
520                         p = memmod_str;
521                 printk(KERN_WARNING "CPU[%d]: UDBL Syndrome[%x] "
522                        "Memory Module \"%s\"\n",
523                        smp_processor_id(), scode, p);
524         }
525 
526         if (udbh & bit) {
527                 scode = ecc_syndrome_table[udbh & 0xff];
528                 if (sprintf_dimm(scode, afar, memmod_str, sizeof(memmod_str)) < 0)
529                         p = syndrome_unknown;
530                 else
531                         p = memmod_str;
532                 printk(KERN_WARNING "CPU[%d]: UDBH Syndrome[%x] "
533                        "Memory Module \"%s\"\n",
534                        smp_processor_id(), scode, p);
535         }
536 
537 }
538 
539 static void spitfire_cee_log(unsigned long afsr, unsigned long afar, unsigned long udbh, unsigned long udbl, int tl1, struct pt_regs *regs)
540 {
541 
542         printk(KERN_WARNING "CPU[%d]: Correctable ECC Error "
543                "AFSR[%lx] AFAR[%016lx] UDBL[%lx] UDBH[%lx] TL>1[%d]\n",
544                smp_processor_id(), afsr, afar, udbl, udbh, tl1);
545 
546         spitfire_log_udb_syndrome(afar, udbh, udbl, UDBE_CE);
547 
548         /* We always log it, even if someone is listening for this
549          * trap.
550          */
551         notify_die(DIE_TRAP, "Correctable ECC Error", regs,
552                    0, TRAP_TYPE_CEE, SIGTRAP);
553 
554         /* The Correctable ECC Error trap does not disable I/D caches.  So
555          * we only have to restore the ESTATE Error Enable register.
556          */
557         spitfire_enable_estate_errors();
558 }
559 
560 static void spitfire_ue_log(unsigned long afsr, unsigned long afar, unsigned long udbh, unsigned long udbl, unsigned long tt, int tl1, struct pt_regs *regs)
561 {
562         siginfo_t info;
563 
564         printk(KERN_WARNING "CPU[%d]: Uncorrectable Error AFSR[%lx] "
565                "AFAR[%lx] UDBL[%lx] UDBH[%ld] TT[%lx] TL>1[%d]\n",
566                smp_processor_id(), afsr, afar, udbl, udbh, tt, tl1);
567 
568         /* XXX add more human friendly logging of the error status
569          * XXX as is implemented for cheetah
570          */
571 
572         spitfire_log_udb_syndrome(afar, udbh, udbl, UDBE_UE);
573 
574         /* We always log it, even if someone is listening for this
575          * trap.
576          */
577         notify_die(DIE_TRAP, "Uncorrectable Error", regs,
578                    0, tt, SIGTRAP);
579 
580         if (regs->tstate & TSTATE_PRIV) {
581                 if (tl1)
582                         dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
583                 die_if_kernel("UE", regs);
584         }
585 
586         /* XXX need more intelligent processing here, such as is implemented
587          * XXX for cheetah errors, in fact if the E-cache still holds the
588          * XXX line with bad parity this will loop
589          */
590 
591         spitfire_clean_and_reenable_l1_caches();
592         spitfire_enable_estate_errors();
593 
594         if (test_thread_flag(TIF_32BIT)) {
595                 regs->tpc &= 0xffffffff;
596                 regs->tnpc &= 0xffffffff;
597         }
598         info.si_signo = SIGBUS;
599         info.si_errno = 0;
600         info.si_code = BUS_OBJERR;
601         info.si_addr = (void *)0;
602         info.si_trapno = 0;
603         force_sig_info(SIGBUS, &info, current);
604 }
605 
606 void spitfire_access_error(struct pt_regs *regs, unsigned long status_encoded, unsigned long afar)
607 {
608         unsigned long afsr, tt, udbh, udbl;
609         int tl1;
610 
611         afsr = (status_encoded & SFSTAT_AFSR_MASK) >> SFSTAT_AFSR_SHIFT;
612         tt = (status_encoded & SFSTAT_TRAP_TYPE) >> SFSTAT_TRAP_TYPE_SHIFT;
613         tl1 = (status_encoded & SFSTAT_TL_GT_ONE) ? 1 : 0;
614         udbl = (status_encoded & SFSTAT_UDBL_MASK) >> SFSTAT_UDBL_SHIFT;
615         udbh = (status_encoded & SFSTAT_UDBH_MASK) >> SFSTAT_UDBH_SHIFT;
616 
617 #ifdef CONFIG_PCI
618         if (tt == TRAP_TYPE_DAE &&
619             pci_poke_in_progress && pci_poke_cpu == smp_processor_id()) {
620                 spitfire_clean_and_reenable_l1_caches();
621                 spitfire_enable_estate_errors();
622 
623                 pci_poke_faulted = 1;
624                 regs->tnpc = regs->tpc + 4;
625                 return;
626         }
627 #endif
628 
629         if (afsr & SFAFSR_UE)
630                 spitfire_ue_log(afsr, afar, udbh, udbl, tt, tl1, regs);
631 
632         if (tt == TRAP_TYPE_CEE) {
633                 /* Handle the case where we took a CEE trap, but ACK'd
634                  * only the UE state in the UDB error registers.
635                  */
636                 if (afsr & SFAFSR_UE) {
637                         if (udbh & UDBE_CE) {
638                                 __asm__ __volatile__(
639                                         "stxa   %0, [%1] %2\n\t"
640                                         "membar #Sync"
641                                         : /* no outputs */
642                                         : "r" (udbh & UDBE_CE),
643                                           "r" (0x0), "i" (ASI_UDB_ERROR_W));
644                         }
645                         if (udbl & UDBE_CE) {
646                                 __asm__ __volatile__(
647                                         "stxa   %0, [%1] %2\n\t"
648                                         "membar #Sync"
649                                         : /* no outputs */
650                                         : "r" (udbl & UDBE_CE),
651                                           "r" (0x18), "i" (ASI_UDB_ERROR_W));
652                         }
653                 }
654 
655                 spitfire_cee_log(afsr, afar, udbh, udbl, tl1, regs);
656         }
657 }
658 
659 int cheetah_pcache_forced_on;
660 
661 void cheetah_enable_pcache(void)
662 {
663         unsigned long dcr;
664 
665         printk("CHEETAH: Enabling P-Cache on cpu %d.\n",
666                smp_processor_id());
667 
668         __asm__ __volatile__("ldxa [%%g0] %1, %0"
669                              : "=r" (dcr)
670                              : "i" (ASI_DCU_CONTROL_REG));
671         dcr |= (DCU_PE | DCU_HPE | DCU_SPE | DCU_SL);
672         __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
673                              "membar #Sync"
674                              : /* no outputs */
675                              : "r" (dcr), "i" (ASI_DCU_CONTROL_REG));
676 }
677 
678 /* Cheetah error trap handling. */
679 static unsigned long ecache_flush_physbase;
680 static unsigned long ecache_flush_linesize;
681 static unsigned long ecache_flush_size;
682 
683 /* This table is ordered in priority of errors and matches the
684  * AFAR overwrite policy as well.
685  */
686 
687 struct afsr_error_table {
688         unsigned long mask;
689         const char *name;
690 };
691 
692 static const char CHAFSR_PERR_msg[] =
693         "System interface protocol error";
694 static const char CHAFSR_IERR_msg[] =
695         "Internal processor error";
696 static const char CHAFSR_ISAP_msg[] =
697         "System request parity error on incoming address";
698 static const char CHAFSR_UCU_msg[] =
699         "Uncorrectable E-cache ECC error for ifetch/data";
700 static const char CHAFSR_UCC_msg[] =
701         "SW Correctable E-cache ECC error for ifetch/data";
702 static const char CHAFSR_UE_msg[] =
703         "Uncorrectable system bus data ECC error for read";
704 static const char CHAFSR_EDU_msg[] =
705         "Uncorrectable E-cache ECC error for stmerge/blkld";
706 static const char CHAFSR_EMU_msg[] =
707         "Uncorrectable system bus MTAG error";
708 static const char CHAFSR_WDU_msg[] =
709         "Uncorrectable E-cache ECC error for writeback";
710 static const char CHAFSR_CPU_msg[] =
711         "Uncorrectable ECC error for copyout";
712 static const char CHAFSR_CE_msg[] =
713         "HW corrected system bus data ECC error for read";
714 static const char CHAFSR_EDC_msg[] =
715         "HW corrected E-cache ECC error for stmerge/blkld";
716 static const char CHAFSR_EMC_msg[] =
717         "HW corrected system bus MTAG ECC error";
718 static const char CHAFSR_WDC_msg[] =
719         "HW corrected E-cache ECC error for writeback";
720 static const char CHAFSR_CPC_msg[] =
721         "HW corrected ECC error for copyout";
722 static const char CHAFSR_TO_msg[] =
723         "Unmapped error from system bus";
724 static const char CHAFSR_BERR_msg[] =
725         "Bus error response from system bus";
726 static const char CHAFSR_IVC_msg[] =
727         "HW corrected system bus data ECC error for ivec read";
728 static const char CHAFSR_IVU_msg[] =
729         "Uncorrectable system bus data ECC error for ivec read";
730 static struct afsr_error_table __cheetah_error_table[] = {
731         {       CHAFSR_PERR,    CHAFSR_PERR_msg         },
732         {       CHAFSR_IERR,    CHAFSR_IERR_msg         },
733         {       CHAFSR_ISAP,    CHAFSR_ISAP_msg         },
734         {       CHAFSR_UCU,     CHAFSR_UCU_msg          },
735         {       CHAFSR_UCC,     CHAFSR_UCC_msg          },
736         {       CHAFSR_UE,      CHAFSR_UE_msg           },
737         {       CHAFSR_EDU,     CHAFSR_EDU_msg          },
738         {       CHAFSR_EMU,     CHAFSR_EMU_msg          },
739         {       CHAFSR_WDU,     CHAFSR_WDU_msg          },
740         {       CHAFSR_CPU,     CHAFSR_CPU_msg          },
741         {       CHAFSR_CE,      CHAFSR_CE_msg           },
742         {       CHAFSR_EDC,     CHAFSR_EDC_msg          },
743         {       CHAFSR_EMC,     CHAFSR_EMC_msg          },
744         {       CHAFSR_WDC,     CHAFSR_WDC_msg          },
745         {       CHAFSR_CPC,     CHAFSR_CPC_msg          },
746         {       CHAFSR_TO,      CHAFSR_TO_msg           },
747         {       CHAFSR_BERR,    CHAFSR_BERR_msg         },
748         /* These two do not update the AFAR. */
749         {       CHAFSR_IVC,     CHAFSR_IVC_msg          },
750         {       CHAFSR_IVU,     CHAFSR_IVU_msg          },
751         {       0,              NULL                    },
752 };
753 static const char CHPAFSR_DTO_msg[] =
754         "System bus unmapped error for prefetch/storequeue-read";
755 static const char CHPAFSR_DBERR_msg[] =
756         "System bus error for prefetch/storequeue-read";
757 static const char CHPAFSR_THCE_msg[] =
758         "Hardware corrected E-cache Tag ECC error";
759 static const char CHPAFSR_TSCE_msg[] =
760         "SW handled correctable E-cache Tag ECC error";
761 static const char CHPAFSR_TUE_msg[] =
762         "Uncorrectable E-cache Tag ECC error";
763 static const char CHPAFSR_DUE_msg[] =
764         "System bus uncorrectable data ECC error due to prefetch/store-fill";
765 static struct afsr_error_table __cheetah_plus_error_table[] = {
766         {       CHAFSR_PERR,    CHAFSR_PERR_msg         },
767         {       CHAFSR_IERR,    CHAFSR_IERR_msg         },
768         {       CHAFSR_ISAP,    CHAFSR_ISAP_msg         },
769         {       CHAFSR_UCU,     CHAFSR_UCU_msg          },
770         {       CHAFSR_UCC,     CHAFSR_UCC_msg          },
771         {       CHAFSR_UE,      CHAFSR_UE_msg           },
772         {       CHAFSR_EDU,     CHAFSR_EDU_msg          },
773         {       CHAFSR_EMU,     CHAFSR_EMU_msg          },
774         {       CHAFSR_WDU,     CHAFSR_WDU_msg          },
775         {       CHAFSR_CPU,     CHAFSR_CPU_msg          },
776         {       CHAFSR_CE,      CHAFSR_CE_msg           },
777         {       CHAFSR_EDC,     CHAFSR_EDC_msg          },
778         {       CHAFSR_EMC,     CHAFSR_EMC_msg          },
779         {       CHAFSR_WDC,     CHAFSR_WDC_msg          },
780         {       CHAFSR_CPC,     CHAFSR_CPC_msg          },
781         {       CHAFSR_TO,      CHAFSR_TO_msg           },
782         {       CHAFSR_BERR,    CHAFSR_BERR_msg         },
783         {       CHPAFSR_DTO,    CHPAFSR_DTO_msg         },
784         {       CHPAFSR_DBERR,  CHPAFSR_DBERR_msg       },
785         {       CHPAFSR_THCE,   CHPAFSR_THCE_msg        },
786         {       CHPAFSR_TSCE,   CHPAFSR_TSCE_msg        },
787         {       CHPAFSR_TUE,    CHPAFSR_TUE_msg         },
788         {       CHPAFSR_DUE,    CHPAFSR_DUE_msg         },
789         /* These two do not update the AFAR. */
790         {       CHAFSR_IVC,     CHAFSR_IVC_msg          },
791         {       CHAFSR_IVU,     CHAFSR_IVU_msg          },
792         {       0,              NULL                    },
793 };
794 static const char JPAFSR_JETO_msg[] =
795         "System interface protocol error, hw timeout caused";
796 static const char JPAFSR_SCE_msg[] =
797         "Parity error on system snoop results";
798 static const char JPAFSR_JEIC_msg[] =
799         "System interface protocol error, illegal command detected";
800 static const char JPAFSR_JEIT_msg[] =
801         "System interface protocol error, illegal ADTYPE detected";
802 static const char JPAFSR_OM_msg[] =
803         "Out of range memory error has occurred";
804 static const char JPAFSR_ETP_msg[] =
805         "Parity error on L2 cache tag SRAM";
806 static const char JPAFSR_UMS_msg[] =
807         "Error due to unsupported store";
808 static const char JPAFSR_RUE_msg[] =
809         "Uncorrectable ECC error from remote cache/memory";
810 static const char JPAFSR_RCE_msg[] =
811         "Correctable ECC error from remote cache/memory";
812 static const char JPAFSR_BP_msg[] =
813         "JBUS parity error on returned read data";
814 static const char JPAFSR_WBP_msg[] =
815         "JBUS parity error on data for writeback or block store";
816 static const char JPAFSR_FRC_msg[] =
817         "Foreign read to DRAM incurring correctable ECC error";
818 static const char JPAFSR_FRU_msg[] =
819         "Foreign read to DRAM incurring uncorrectable ECC error";
820 static struct afsr_error_table __jalapeno_error_table[] = {
821         {       JPAFSR_JETO,    JPAFSR_JETO_msg         },
822         {       JPAFSR_SCE,     JPAFSR_SCE_msg          },
823         {       JPAFSR_JEIC,    JPAFSR_JEIC_msg         },
824         {       JPAFSR_JEIT,    JPAFSR_JEIT_msg         },
825         {       CHAFSR_PERR,    CHAFSR_PERR_msg         },
826         {       CHAFSR_IERR,    CHAFSR_IERR_msg         },
827         {       CHAFSR_ISAP,    CHAFSR_ISAP_msg         },
828         {       CHAFSR_UCU,     CHAFSR_UCU_msg          },
829         {       CHAFSR_UCC,     CHAFSR_UCC_msg          },
830         {       CHAFSR_UE,      CHAFSR_UE_msg           },
831         {       CHAFSR_EDU,     CHAFSR_EDU_msg          },
832         {       JPAFSR_OM,      JPAFSR_OM_msg           },
833         {       CHAFSR_WDU,     CHAFSR_WDU_msg          },
834         {       CHAFSR_CPU,     CHAFSR_CPU_msg          },
835         {       CHAFSR_CE,      CHAFSR_CE_msg           },
836         {       CHAFSR_EDC,     CHAFSR_EDC_msg          },
837         {       JPAFSR_ETP,     JPAFSR_ETP_msg          },
838         {       CHAFSR_WDC,     CHAFSR_WDC_msg          },
839         {       CHAFSR_CPC,     CHAFSR_CPC_msg          },
840         {       CHAFSR_TO,      CHAFSR_TO_msg           },
841         {       CHAFSR_BERR,    CHAFSR_BERR_msg         },
842         {       JPAFSR_UMS,     JPAFSR_UMS_msg          },
843         {       JPAFSR_RUE,     JPAFSR_RUE_msg          },
844         {       JPAFSR_RCE,     JPAFSR_RCE_msg          },
845         {       JPAFSR_BP,      JPAFSR_BP_msg           },
846         {       JPAFSR_WBP,     JPAFSR_WBP_msg          },
847         {       JPAFSR_FRC,     JPAFSR_FRC_msg          },
848         {       JPAFSR_FRU,     JPAFSR_FRU_msg          },
849         /* These two do not update the AFAR. */
850         {       CHAFSR_IVU,     CHAFSR_IVU_msg          },
851         {       0,              NULL                    },
852 };
853 static struct afsr_error_table *cheetah_error_table;
854 static unsigned long cheetah_afsr_errors;
855 
856 struct cheetah_err_info *cheetah_error_log;
857 
858 static inline struct cheetah_err_info *cheetah_get_error_log(unsigned long afsr)
859 {
860         struct cheetah_err_info *p;
861         int cpu = smp_processor_id();
862 
863         if (!cheetah_error_log)
864                 return NULL;
865 
866         p = cheetah_error_log + (cpu * 2);
867         if ((afsr & CHAFSR_TL1) != 0UL)
868                 p++;
869 
870         return p;
871 }
872 
873 extern unsigned int tl0_icpe[], tl1_icpe[];
874 extern unsigned int tl0_dcpe[], tl1_dcpe[];
875 extern unsigned int tl0_fecc[], tl1_fecc[];
876 extern unsigned int tl0_cee[], tl1_cee[];
877 extern unsigned int tl0_iae[], tl1_iae[];
878 extern unsigned int tl0_dae[], tl1_dae[];
879 extern unsigned int cheetah_plus_icpe_trap_vector[], cheetah_plus_icpe_trap_vector_tl1[];
880 extern unsigned int cheetah_plus_dcpe_trap_vector[], cheetah_plus_dcpe_trap_vector_tl1[];
881 extern unsigned int cheetah_fecc_trap_vector[], cheetah_fecc_trap_vector_tl1[];
882 extern unsigned int cheetah_cee_trap_vector[], cheetah_cee_trap_vector_tl1[];
883 extern unsigned int cheetah_deferred_trap_vector[], cheetah_deferred_trap_vector_tl1[];
884 
885 void __init cheetah_ecache_flush_init(void)
886 {
887         unsigned long largest_size, smallest_linesize, order, ver;
888         int i, sz;
889 
890         /* Scan all cpu device tree nodes, note two values:
891          * 1) largest E-cache size
892          * 2) smallest E-cache line size
893          */
894         largest_size = 0UL;
895         smallest_linesize = ~0UL;
896 
897         for (i = 0; i < NR_CPUS; i++) {
898                 unsigned long val;
899 
900                 val = cpu_data(i).ecache_size;
901                 if (!val)
902                         continue;
903 
904                 if (val > largest_size)
905                         largest_size = val;
906 
907                 val = cpu_data(i).ecache_line_size;
908                 if (val < smallest_linesize)
909                         smallest_linesize = val;
910 
911         }
912 
913         if (largest_size == 0UL || smallest_linesize == ~0UL) {
914                 prom_printf("cheetah_ecache_flush_init: Cannot probe cpu E-cache "
915                             "parameters.\n");
916                 prom_halt();
917         }
918 
919         ecache_flush_size = (2 * largest_size);
920         ecache_flush_linesize = smallest_linesize;
921 
922         ecache_flush_physbase = find_ecache_flush_span(ecache_flush_size);
923 
924         if (ecache_flush_physbase == ~0UL) {
925                 prom_printf("cheetah_ecache_flush_init: Cannot find %ld byte "
926                             "contiguous physical memory.\n",
927                             ecache_flush_size);
928                 prom_halt();
929         }
930 
931         /* Now allocate error trap reporting scoreboard. */
932         sz = NR_CPUS * (2 * sizeof(struct cheetah_err_info));
933         for (order = 0; order < MAX_ORDER; order++) {
934                 if ((PAGE_SIZE << order) >= sz)
935                         break;
936         }
937         cheetah_error_log = (struct cheetah_err_info *)
938                 __get_free_pages(GFP_KERNEL, order);
939         if (!cheetah_error_log) {
940                 prom_printf("cheetah_ecache_flush_init: Failed to allocate "
941                             "error logging scoreboard (%d bytes).\n", sz);
942                 prom_halt();
943         }
944         memset(cheetah_error_log, 0, PAGE_SIZE << order);
945 
946         /* Mark all AFSRs as invalid so that the trap handler will
947          * log new new information there.
948          */
949         for (i = 0; i < 2 * NR_CPUS; i++)
950                 cheetah_error_log[i].afsr = CHAFSR_INVALID;
951 
952         __asm__ ("rdpr %%ver, %0" : "=r" (ver));
953         if ((ver >> 32) == __JALAPENO_ID ||
954             (ver >> 32) == __SERRANO_ID) {
955                 cheetah_error_table = &__jalapeno_error_table[0];
956                 cheetah_afsr_errors = JPAFSR_ERRORS;
957         } else if ((ver >> 32) == 0x003e0015) {
958                 cheetah_error_table = &__cheetah_plus_error_table[0];
959                 cheetah_afsr_errors = CHPAFSR_ERRORS;
960         } else {
961                 cheetah_error_table = &__cheetah_error_table[0];
962                 cheetah_afsr_errors = CHAFSR_ERRORS;
963         }
964 
965         /* Now patch trap tables. */
966         memcpy(tl0_fecc, cheetah_fecc_trap_vector, (8 * 4));
967         memcpy(tl1_fecc, cheetah_fecc_trap_vector_tl1, (8 * 4));
968         memcpy(tl0_cee, cheetah_cee_trap_vector, (8 * 4));
969         memcpy(tl1_cee, cheetah_cee_trap_vector_tl1, (8 * 4));
970         memcpy(tl0_iae, cheetah_deferred_trap_vector, (8 * 4));
971         memcpy(tl1_iae, cheetah_deferred_trap_vector_tl1, (8 * 4));
972         memcpy(tl0_dae, cheetah_deferred_trap_vector, (8 * 4));
973         memcpy(tl1_dae, cheetah_deferred_trap_vector_tl1, (8 * 4));
974         if (tlb_type == cheetah_plus) {
975                 memcpy(tl0_dcpe, cheetah_plus_dcpe_trap_vector, (8 * 4));
976                 memcpy(tl1_dcpe, cheetah_plus_dcpe_trap_vector_tl1, (8 * 4));
977                 memcpy(tl0_icpe, cheetah_plus_icpe_trap_vector, (8 * 4));
978                 memcpy(tl1_icpe, cheetah_plus_icpe_trap_vector_tl1, (8 * 4));
979         }
980         flushi(PAGE_OFFSET);
981 }
982 
983 static void cheetah_flush_ecache(void)
984 {
985         unsigned long flush_base = ecache_flush_physbase;
986         unsigned long flush_linesize = ecache_flush_linesize;
987         unsigned long flush_size = ecache_flush_size;
988 
989         __asm__ __volatile__("1: subcc  %0, %4, %0\n\t"
990                              "   bne,pt %%xcc, 1b\n\t"
991                              "    ldxa  [%2 + %0] %3, %%g0\n\t"
992                              : "=&r" (flush_size)
993                              : "" (flush_size), "r" (flush_base),
994                                "i" (ASI_PHYS_USE_EC), "r" (flush_linesize));
995 }
996 
997 static void cheetah_flush_ecache_line(unsigned long physaddr)
998 {
999         unsigned long alias;
1000 
1001         physaddr &= ~(8UL - 1UL);
1002         physaddr = (ecache_flush_physbase +
1003                     (physaddr & ((ecache_flush_size>>1UL) - 1UL)));
1004         alias = physaddr + (ecache_flush_size >> 1UL);
1005         __asm__ __volatile__("ldxa [%0] %2, %%g0\n\t"
1006                              "ldxa [%1] %2, %%g0\n\t"
1007                              "membar #Sync"
1008                              : /* no outputs */
1009                              : "r" (physaddr), "r" (alias),
1010                                "i" (ASI_PHYS_USE_EC));
1011 }
1012 
1013 /* Unfortunately, the diagnostic access to the I-cache tags we need to
1014  * use to clear the thing interferes with I-cache coherency transactions.
1015  *
1016  * So we must only flush the I-cache when it is disabled.
1017  */
1018 static void __cheetah_flush_icache(void)
1019 {
1020         unsigned int icache_size, icache_line_size;
1021         unsigned long addr;
1022 
1023         icache_size = local_cpu_data().icache_size;
1024         icache_line_size = local_cpu_data().icache_line_size;
1025 
1026         /* Clear the valid bits in all the tags. */
1027         for (addr = 0; addr < icache_size; addr += icache_line_size) {
1028                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1029                                      "membar #Sync"
1030                                      : /* no outputs */
1031                                      : "r" (addr | (2 << 3)),
1032                                        "i" (ASI_IC_TAG));
1033         }
1034 }
1035 
1036 static void cheetah_flush_icache(void)
1037 {
1038         unsigned long dcu_save;
1039 
1040         /* Save current DCU, disable I-cache. */
1041         __asm__ __volatile__("ldxa [%%g0] %1, %0\n\t"
1042                              "or %0, %2, %%g1\n\t"
1043                              "stxa %%g1, [%%g0] %1\n\t"
1044                              "membar #Sync"
1045                              : "=r" (dcu_save)
1046                              : "i" (ASI_DCU_CONTROL_REG), "i" (DCU_IC)
1047                              : "g1");
1048 
1049         __cheetah_flush_icache();
1050 
1051         /* Restore DCU register */
1052         __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
1053                              "membar #Sync"
1054                              : /* no outputs */
1055                              : "r" (dcu_save), "i" (ASI_DCU_CONTROL_REG));
1056 }
1057 
1058 static void cheetah_flush_dcache(void)
1059 {
1060         unsigned int dcache_size, dcache_line_size;
1061         unsigned long addr;
1062 
1063         dcache_size = local_cpu_data().dcache_size;
1064         dcache_line_size = local_cpu_data().dcache_line_size;
1065 
1066         for (addr = 0; addr < dcache_size; addr += dcache_line_size) {
1067                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1068                                      "membar #Sync"
1069                                      : /* no outputs */
1070                                      : "r" (addr), "i" (ASI_DCACHE_TAG));
1071         }
1072 }
1073 
1074 /* In order to make the even parity correct we must do two things.
1075  * First, we clear DC_data_parity and set DC_utag to an appropriate value.
1076  * Next, we clear out all 32-bytes of data for that line.  Data of
1077  * all-zero + tag parity value of zero == correct parity.
1078  */
1079 static void cheetah_plus_zap_dcache_parity(void)
1080 {
1081         unsigned int dcache_size, dcache_line_size;
1082         unsigned long addr;
1083 
1084         dcache_size = local_cpu_data().dcache_size;
1085         dcache_line_size = local_cpu_data().dcache_line_size;
1086 
1087         for (addr = 0; addr < dcache_size; addr += dcache_line_size) {
1088                 unsigned long tag = (addr >> 14);
1089                 unsigned long line;
1090 
1091                 __asm__ __volatile__("membar    #Sync\n\t"
1092                                      "stxa      %0, [%1] %2\n\t"
1093                                      "membar    #Sync"
1094                                      : /* no outputs */
1095                                      : "r" (tag), "r" (addr),
1096                                        "i" (ASI_DCACHE_UTAG));
1097                 for (line = addr; line < addr + dcache_line_size; line += 8)
1098                         __asm__ __volatile__("membar    #Sync\n\t"
1099                                              "stxa      %%g0, [%0] %1\n\t"
1100                                              "membar    #Sync"
1101                                              : /* no outputs */
1102                                              : "r" (line),
1103                                                "i" (ASI_DCACHE_DATA));
1104         }
1105 }
1106 
1107 /* Conversion tables used to frob Cheetah AFSR syndrome values into
1108  * something palatable to the memory controller driver get_unumber
1109  * routine.
1110  */
1111 #define MT0     137
1112 #define MT1     138
1113 #define MT2     139
1114 #define NONE    254
1115 #define MTC0    140
1116 #define MTC1    141
1117 #define MTC2    142
1118 #define MTC3    143
1119 #define C0      128
1120 #define C1      129
1121 #define C2      130
1122 #define C3      131
1123 #define C4      132
1124 #define C5      133
1125 #define C6      134
1126 #define C7      135
1127 #define C8      136
1128 #define M2      144
1129 #define M3      145
1130 #define M4      146
1131 #define M       147
1132 static unsigned char cheetah_ecc_syntab[] = {
1133 /*00*/NONE, C0, C1, M2, C2, M2, M3, 47, C3, M2, M2, 53, M2, 41, 29, M,
1134 /*01*/C4, M, M, 50, M2, 38, 25, M2, M2, 33, 24, M2, 11, M, M2, 16,
1135 /*02*/C5, M, M, 46, M2, 37, 19, M2, M, 31, 32, M, 7, M2, M2, 10,
1136 /*03*/M2, 40, 13, M2, 59, M, M2, 66, M, M2, M2, 0, M2, 67, 71, M,
1137 /*04*/C6, M, M, 43, M, 36, 18, M, M2, 49, 15, M, 63, M2, M2, 6,
1138 /*05*/M2, 44, 28, M2, M, M2, M2, 52, 68, M2, M2, 62, M2, M3, M3, M4,
1139 /*06*/M2, 26, 106, M2, 64, M, M2, 2, 120, M, M2, M3, M, M3, M3, M4,
1140 /*07*/116, M2, M2, M3, M2, M3, M, M4, M2, 58, 54, M2, M, M4, M4, M3,
1141 /*08*/C7, M2, M, 42, M, 35, 17, M2, M, 45, 14, M2, 21, M2, M2, 5,
1142 /*09*/M, 27, M, M, 99, M, M, 3, 114, M2, M2, 20, M2, M3, M3, M,
1143 /*0a*/M2, 23, 113, M2, 112, M2, M, 51, 95, M, M2, M3, M2, M3, M3, M2,
1144 /*0b*/103, M, M2, M3, M2, M3, M3, M4, M2, 48, M, M, 73, M2, M, M3,
1145 /*0c*/M2, 22, 110, M2, 109, M2, M, 9, 108, M2, M, M3, M2, M3, M3, M,
1146 /*0d*/102, M2, M, M, M2, M3, M3, M, M2, M3, M3, M2, M, M4, M, M3,
1147 /*0e*/98, M, M2, M3, M2, M, M3, M4, M2, M3, M3, M4, M3, M, M, M,
1148 /*0f*/M2, M3, M3, M, M3, M, M, M, 56, M4, M, M3, M4, M, M, M,
1149 /*10*/C8, M, M2, 39, M, 34, 105, M2, M, 30, 104, M, 101, M, M, 4,
1150 /*11*/M, M, 100, M, 83, M, M2, 12, 87, M, M, 57, M2, M, M3, M,
1151 /*12*/M2, 97, 82, M2, 78, M2, M2, 1, 96, M, M, M, M, M, M3, M2,
1152 /*13*/94, M, M2, M3, M2, M, M3, M, M2, M, 79, M, 69, M, M4, M,
1153 /*14*/M2, 93, 92, M, 91, M, M2, 8, 90, M2, M2, M, M, M, M, M4,
1154 /*15*/89, M, M, M3, M2, M3, M3, M, M, M, M3, M2, M3, M2, M, M3,
1155 /*16*/86, M, M2, M3, M2, M, M3, M, M2, M, M3, M, M3, M, M, M3,
1156 /*17*/M, M, M3, M2, M3, M2, M4, M, 60, M, M2, M3, M4, M, M, M2,
1157 /*18*/M2, 88, 85, M2, 84, M, M2, 55, 81, M2, M2, M3, M2, M3, M3, M4,
1158 /*19*/77, M, M, M, M2, M3, M, M, M2, M3, M3, M4, M3, M2, M, M,
1159 /*1a*/74, M, M2, M3, M, M, M3, M, M, M, M3, M, M3, M, M4, M3,
1160 /*1b*/M2, 70, 107, M4, 65, M2, M2, M, 127, M, M, M, M2, M3, M3, M,
1161 /*1c*/80, M2, M2, 72, M, 119, 118, M, M2, 126, 76, M, 125, M, M4, M3,
1162 /*1d*/M2, 115, 124, M, 75, M, M, M3, 61, M, M4, M, M4, M, M, M,
1163 /*1e*/M, 123, 122, M4, 121, M4, M, M3, 117, M2, M2, M3, M4, M3, M, M,
1164 /*1f*/111, M, M, M, M4, M3, M3, M, M, M, M3, M, M3, M2, M, M
1165 };
1166 static unsigned char cheetah_mtag_syntab[] = {
1167        NONE, MTC0,
1168        MTC1, NONE,
1169        MTC2, NONE,
1170        NONE, MT0,
1171        MTC3, NONE,
1172        NONE, MT1,
1173        NONE, MT2,
1174        NONE, NONE
1175 };
1176 
1177 /* Return the highest priority error conditon mentioned. */
1178 static inline unsigned long cheetah_get_hipri(unsigned long afsr)
1179 {
1180         unsigned long tmp = 0;
1181         int i;
1182 
1183         for (i = 0; cheetah_error_table[i].mask; i++) {
1184                 if ((tmp = (afsr & cheetah_error_table[i].mask)) != 0UL)
1185                         return tmp;
1186         }
1187         return tmp;
1188 }
1189 
1190 static const char *cheetah_get_string(unsigned long bit)
1191 {
1192         int i;
1193 
1194         for (i = 0; cheetah_error_table[i].mask; i++) {
1195                 if ((bit & cheetah_error_table[i].mask) != 0UL)
1196                         return cheetah_error_table[i].name;
1197         }
1198         return "???";
1199 }
1200 
1201 static void cheetah_log_errors(struct pt_regs *regs, struct cheetah_err_info *info,
1202                                unsigned long afsr, unsigned long afar, int recoverable)
1203 {
1204         unsigned long hipri;
1205         char unum[256];
1206 
1207         printk("%s" "ERROR(%d): Cheetah error trap taken afsr[%016lx] afar[%016lx] TL1(%d)\n",
1208                (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1209                afsr, afar,
1210                (afsr & CHAFSR_TL1) ? 1 : 0);
1211         printk("%s" "ERROR(%d): TPC[%lx] TNPC[%lx] O7[%lx] TSTATE[%lx]\n",
1212                (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1213                regs->tpc, regs->tnpc, regs->u_regs[UREG_I7], regs->tstate);
1214         printk("%s" "ERROR(%d): ",
1215                (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id());
1216         printk("TPC<%pS>\n", (void *) regs->tpc);
1217         printk("%s" "ERROR(%d): M_SYND(%lx),  E_SYND(%lx)%s%s\n",
1218                (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1219                (afsr & CHAFSR_M_SYNDROME) >> CHAFSR_M_SYNDROME_SHIFT,
1220                (afsr & CHAFSR_E_SYNDROME) >> CHAFSR_E_SYNDROME_SHIFT,
1221                (afsr & CHAFSR_ME) ? ", Multiple Errors" : "",
1222                (afsr & CHAFSR_PRIV) ? ", Privileged" : "");
1223         hipri = cheetah_get_hipri(afsr);
1224         printk("%s" "ERROR(%d): Highest priority error (%016lx) \"%s\"\n",
1225                (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1226                hipri, cheetah_get_string(hipri));
1227 
1228         /* Try to get unumber if relevant. */
1229 #define ESYND_ERRORS    (CHAFSR_IVC | CHAFSR_IVU | \
1230                          CHAFSR_CPC | CHAFSR_CPU | \
1231                          CHAFSR_UE  | CHAFSR_CE  | \
1232                          CHAFSR_EDC | CHAFSR_EDU  | \
1233                          CHAFSR_UCC | CHAFSR_UCU  | \
1234                          CHAFSR_WDU | CHAFSR_WDC)
1235 #define MSYND_ERRORS    (CHAFSR_EMC | CHAFSR_EMU)
1236         if (afsr & ESYND_ERRORS) {
1237                 int syndrome;
1238                 int ret;
1239 
1240                 syndrome = (afsr & CHAFSR_E_SYNDROME) >> CHAFSR_E_SYNDROME_SHIFT;
1241                 syndrome = cheetah_ecc_syntab[syndrome];
1242                 ret = sprintf_dimm(syndrome, afar, unum, sizeof(unum));
1243                 if (ret != -1)
1244                         printk("%s" "ERROR(%d): AFAR E-syndrome [%s]\n",
1245                                (recoverable ? KERN_WARNING : KERN_CRIT),
1246                                smp_processor_id(), unum);
1247         } else if (afsr & MSYND_ERRORS) {
1248                 int syndrome;
1249                 int ret;
1250 
1251                 syndrome = (afsr & CHAFSR_M_SYNDROME) >> CHAFSR_M_SYNDROME_SHIFT;
1252                 syndrome = cheetah_mtag_syntab[syndrome];
1253                 ret = sprintf_dimm(syndrome, afar, unum, sizeof(unum));
1254                 if (ret != -1)
1255                         printk("%s" "ERROR(%d): AFAR M-syndrome [%s]\n",
1256                                (recoverable ? KERN_WARNING : KERN_CRIT),
1257                                smp_processor_id(), unum);
1258         }
1259 
1260         /* Now dump the cache snapshots. */
1261         printk("%s" "ERROR(%d): D-cache idx[%x] tag[%016llx] utag[%016llx] stag[%016llx]\n",
1262                (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1263                (int) info->dcache_index,
1264                info->dcache_tag,
1265                info->dcache_utag,
1266                info->dcache_stag);
1267         printk("%s" "ERROR(%d): D-cache data0[%016llx] data1[%016llx] data2[%016llx] data3[%016llx]\n",
1268                (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1269                info->dcache_data[0],
1270                info->dcache_data[1],
1271                info->dcache_data[2],
1272                info->dcache_data[3]);
1273         printk("%s" "ERROR(%d): I-cache idx[%x] tag[%016llx] utag[%016llx] stag[%016llx] "
1274                "u[%016llx] l[%016llx]\n",
1275                (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1276                (int) info->icache_index,
1277                info->icache_tag,
1278                info->icache_utag,
1279                info->icache_stag,
1280                info->icache_upper,
1281                info->icache_lower);
1282         printk("%s" "ERROR(%d): I-cache INSN0[%016llx] INSN1[%016llx] INSN2[%016llx] INSN3[%016llx]\n",
1283                (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1284                info->icache_data[0],
1285                info->icache_data[1],
1286                info->icache_data[2],
1287                info->icache_data[3]);
1288         printk("%s" "ERROR(%d): I-cache INSN4[%016llx] INSN5[%016llx] INSN6[%016llx] INSN7[%016llx]\n",
1289                (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1290                info->icache_data[4],
1291                info->icache_data[5],
1292                info->icache_data[6],
1293                info->icache_data[7]);
1294         printk("%s" "ERROR(%d): E-cache idx[%x] tag[%016llx]\n",
1295                (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1296                (int) info->ecache_index, info->ecache_tag);
1297         printk("%s" "ERROR(%d): E-cache data0[%016llx] data1[%016llx] data2[%016llx] data3[%016llx]\n",
1298                (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1299                info->ecache_data[0],
1300                info->ecache_data[1],
1301                info->ecache_data[2],
1302                info->ecache_data[3]);
1303 
1304         afsr = (afsr & ~hipri) & cheetah_afsr_errors;
1305         while (afsr != 0UL) {
1306                 unsigned long bit = cheetah_get_hipri(afsr);
1307 
1308                 printk("%s" "ERROR: Multiple-error (%016lx) \"%s\"\n",
1309                        (recoverable ? KERN_WARNING : KERN_CRIT),
1310                        bit, cheetah_get_string(bit));
1311 
1312                 afsr &= ~bit;
1313         }
1314 
1315         if (!recoverable)
1316                 printk(KERN_CRIT "ERROR: This condition is not recoverable.\n");
1317 }
1318 
1319 static int cheetah_recheck_errors(struct cheetah_err_info *logp)
1320 {
1321         unsigned long afsr, afar;
1322         int ret = 0;
1323 
1324         __asm__ __volatile__("ldxa [%%g0] %1, %0\n\t"
1325                              : "=r" (afsr)
1326                              : "i" (ASI_AFSR));
1327         if ((afsr & cheetah_afsr_errors) != 0) {
1328                 if (logp != NULL) {
1329                         __asm__ __volatile__("ldxa [%%g0] %1, %0\n\t"
1330                                              : "=r" (afar)
1331                                              : "i" (ASI_AFAR));
1332                         logp->afsr = afsr;
1333                         logp->afar = afar;
1334                 }
1335                 ret = 1;
1336         }
1337         __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
1338                              "membar #Sync\n\t"
1339                              : : "r" (afsr), "i" (ASI_AFSR));
1340 
1341         return ret;
1342 }
1343 
1344 void cheetah_fecc_handler(struct pt_regs *regs, unsigned long afsr, unsigned long afar)
1345 {
1346         struct cheetah_err_info local_snapshot, *p;
1347         int recoverable;
1348 
1349         /* Flush E-cache */
1350         cheetah_flush_ecache();
1351 
1352         p = cheetah_get_error_log(afsr);
1353         if (!p) {
1354                 prom_printf("ERROR: Early Fast-ECC error afsr[%016lx] afar[%016lx]\n",
1355                             afsr, afar);
1356                 prom_printf("ERROR: CPU(%d) TPC[%016lx] TNPC[%016lx] TSTATE[%016lx]\n",
1357                             smp_processor_id(), regs->tpc, regs->tnpc, regs->tstate);
1358                 prom_halt();
1359         }
1360 
1361         /* Grab snapshot of logged error. */
1362         memcpy(&local_snapshot, p, sizeof(local_snapshot));
1363 
1364         /* If the current trap snapshot does not match what the
1365          * trap handler passed along into our args, big trouble.
1366          * In such a case, mark the local copy as invalid.
1367          *
1368          * Else, it matches and we mark the afsr in the non-local
1369          * copy as invalid so we may log new error traps there.
1370          */
1371         if (p->afsr != afsr || p->afar != afar)
1372                 local_snapshot.afsr = CHAFSR_INVALID;
1373         else
1374                 p->afsr = CHAFSR_INVALID;
1375 
1376         cheetah_flush_icache();
1377         cheetah_flush_dcache();
1378 
1379         /* Re-enable I-cache/D-cache */
1380         __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1381                              "or %%g1, %1, %%g1\n\t"
1382                              "stxa %%g1, [%%g0] %0\n\t"
1383                              "membar #Sync"
1384                              : /* no outputs */
1385                              : "i" (ASI_DCU_CONTROL_REG),
1386                                "i" (DCU_DC | DCU_IC)
1387                              : "g1");
1388 
1389         /* Re-enable error reporting */
1390         __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1391                              "or %%g1, %1, %%g1\n\t"
1392                              "stxa %%g1, [%%g0] %0\n\t"
1393                              "membar #Sync"
1394                              : /* no outputs */
1395                              : "i" (ASI_ESTATE_ERROR_EN),
1396                                "i" (ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN)
1397                              : "g1");
1398 
1399         /* Decide if we can continue after handling this trap and
1400          * logging the error.
1401          */
1402         recoverable = 1;
1403         if (afsr & (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP))
1404                 recoverable = 0;
1405 
1406         /* Re-check AFSR/AFAR.  What we are looking for here is whether a new
1407          * error was logged while we had error reporting traps disabled.
1408          */
1409         if (cheetah_recheck_errors(&local_snapshot)) {
1410                 unsigned long new_afsr = local_snapshot.afsr;
1411 
1412                 /* If we got a new asynchronous error, die... */
1413                 if (new_afsr & (CHAFSR_EMU | CHAFSR_EDU |
1414                                 CHAFSR_WDU | CHAFSR_CPU |
1415                                 CHAFSR_IVU | CHAFSR_UE |
1416                                 CHAFSR_BERR | CHAFSR_TO))
1417                         recoverable = 0;
1418         }
1419 
1420         /* Log errors. */
1421         cheetah_log_errors(regs, &local_snapshot, afsr, afar, recoverable);
1422 
1423         if (!recoverable)
1424                 panic("Irrecoverable Fast-ECC error trap.\n");
1425 
1426         /* Flush E-cache to kick the error trap handlers out. */
1427         cheetah_flush_ecache();
1428 }
1429 
1430 /* Try to fix a correctable error by pushing the line out from
1431  * the E-cache.  Recheck error reporting registers to see if the
1432  * problem is intermittent.
1433  */
1434 static int cheetah_fix_ce(unsigned long physaddr)
1435 {
1436         unsigned long orig_estate;
1437         unsigned long alias1, alias2;
1438         int ret;
1439 
1440         /* Make sure correctable error traps are disabled. */
1441         __asm__ __volatile__("ldxa      [%%g0] %2, %0\n\t"
1442                              "andn      %0, %1, %%g1\n\t"
1443                              "stxa      %%g1, [%%g0] %2\n\t"
1444                              "membar    #Sync"
1445                              : "=&r" (orig_estate)
1446                              : "i" (ESTATE_ERROR_CEEN),
1447                                "i" (ASI_ESTATE_ERROR_EN)
1448                              : "g1");
1449 
1450         /* We calculate alias addresses that will force the
1451          * cache line in question out of the E-cache.  Then
1452          * we bring it back in with an atomic instruction so
1453          * that we get it in some modified/exclusive state,
1454          * then we displace it again to try and get proper ECC
1455          * pushed back into the system.
1456          */
1457         physaddr &= ~(8UL - 1UL);
1458         alias1 = (ecache_flush_physbase +
1459                   (physaddr & ((ecache_flush_size >> 1) - 1)));
1460         alias2 = alias1 + (ecache_flush_size >> 1);
1461         __asm__ __volatile__("ldxa      [%0] %3, %%g0\n\t"
1462                              "ldxa      [%1] %3, %%g0\n\t"
1463                              "casxa     [%2] %3, %%g0, %%g0\n\t"
1464                              "ldxa      [%0] %3, %%g0\n\t"
1465                              "ldxa      [%1] %3, %%g0\n\t"
1466                              "membar    #Sync"
1467                              : /* no outputs */
1468                              : "r" (alias1), "r" (alias2),
1469                                "r" (physaddr), "i" (ASI_PHYS_USE_EC));
1470 
1471         /* Did that trigger another error? */
1472         if (cheetah_recheck_errors(NULL)) {
1473                 /* Try one more time. */
1474                 __asm__ __volatile__("ldxa [%0] %1, %%g0\n\t"
1475                                      "membar #Sync"
1476                                      : : "r" (physaddr), "i" (ASI_PHYS_USE_EC));
1477                 if (cheetah_recheck_errors(NULL))
1478                         ret = 2;
1479                 else
1480                         ret = 1;
1481         } else {
1482                 /* No new error, intermittent problem. */
1483                 ret = 0;
1484         }
1485 
1486         /* Restore error enables. */
1487         __asm__ __volatile__("stxa      %0, [%%g0] %1\n\t"
1488                              "membar    #Sync"
1489                              : : "r" (orig_estate), "i" (ASI_ESTATE_ERROR_EN));
1490 
1491         return ret;
1492 }
1493 
1494 /* Return non-zero if PADDR is a valid physical memory address. */
1495 static int cheetah_check_main_memory(unsigned long paddr)
1496 {
1497         unsigned long vaddr = PAGE_OFFSET + paddr;
1498 
1499         if (vaddr > (unsigned long) high_memory)
1500                 return 0;
1501 
1502         return kern_addr_valid(vaddr);
1503 }
1504 
1505 void cheetah_cee_handler(struct pt_regs *regs, unsigned long afsr, unsigned long afar)
1506 {
1507         struct cheetah_err_info local_snapshot, *p;
1508         int recoverable, is_memory;
1509 
1510         p = cheetah_get_error_log(afsr);
1511         if (!p) {
1512                 prom_printf("ERROR: Early CEE error afsr[%016lx] afar[%016lx]\n",
1513                             afsr, afar);
1514                 prom_printf("ERROR: CPU(%d) TPC[%016lx] TNPC[%016lx] TSTATE[%016lx]\n",
1515                             smp_processor_id(), regs->tpc, regs->tnpc, regs->tstate);
1516                 prom_halt();
1517         }
1518 
1519         /* Grab snapshot of logged error. */
1520         memcpy(&local_snapshot, p, sizeof(local_snapshot));
1521 
1522         /* If the current trap snapshot does not match what the
1523          * trap handler passed along into our args, big trouble.
1524          * In such a case, mark the local copy as invalid.
1525          *
1526          * Else, it matches and we mark the afsr in the non-local
1527          * copy as invalid so we may log new error traps there.
1528          */
1529         if (p->afsr != afsr || p->afar != afar)
1530                 local_snapshot.afsr = CHAFSR_INVALID;
1531         else
1532                 p->afsr = CHAFSR_INVALID;
1533 
1534         is_memory = cheetah_check_main_memory(afar);
1535 
1536         if (is_memory && (afsr & CHAFSR_CE) != 0UL) {
1537                 /* XXX Might want to log the results of this operation
1538                  * XXX somewhere... -DaveM
1539                  */
1540                 cheetah_fix_ce(afar);
1541         }
1542 
1543         {
1544                 int flush_all, flush_line;
1545 
1546                 flush_all = flush_line = 0;
1547                 if ((afsr & CHAFSR_EDC) != 0UL) {
1548                         if ((afsr & cheetah_afsr_errors) == CHAFSR_EDC)
1549                                 flush_line = 1;
1550                         else
1551                                 flush_all = 1;
1552                 } else if ((afsr & CHAFSR_CPC) != 0UL) {
1553                         if ((afsr & cheetah_afsr_errors) == CHAFSR_CPC)
1554                                 flush_line = 1;
1555                         else
1556                                 flush_all = 1;
1557                 }
1558 
1559                 /* Trap handler only disabled I-cache, flush it. */
1560                 cheetah_flush_icache();
1561 
1562                 /* Re-enable I-cache */
1563                 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1564                                      "or %%g1, %1, %%g1\n\t"
1565                                      "stxa %%g1, [%%g0] %0\n\t"
1566                                      "membar #Sync"
1567                                      : /* no outputs */
1568                                      : "i" (ASI_DCU_CONTROL_REG),
1569                                      "i" (DCU_IC)
1570                                      : "g1");
1571 
1572                 if (flush_all)
1573                         cheetah_flush_ecache();
1574                 else if (flush_line)
1575                         cheetah_flush_ecache_line(afar);
1576         }
1577 
1578         /* Re-enable error reporting */
1579         __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1580                              "or %%g1, %1, %%g1\n\t"
1581                              "stxa %%g1, [%%g0] %0\n\t"
1582                              "membar #Sync"
1583                              : /* no outputs */
1584                              : "i" (ASI_ESTATE_ERROR_EN),
1585                                "i" (ESTATE_ERROR_CEEN)
1586                              : "g1");
1587 
1588         /* Decide if we can continue after handling this trap and
1589          * logging the error.
1590          */
1591         recoverable = 1;
1592         if (afsr & (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP))
1593                 recoverable = 0;
1594 
1595         /* Re-check AFSR/AFAR */
1596         (void) cheetah_recheck_errors(&local_snapshot);
1597 
1598         /* Log errors. */
1599         cheetah_log_errors(regs, &local_snapshot, afsr, afar, recoverable);
1600 
1601         if (!recoverable)
1602                 panic("Irrecoverable Correctable-ECC error trap.\n");
1603 }
1604 
1605 void cheetah_deferred_handler(struct pt_regs *regs, unsigned long afsr, unsigned long afar)
1606 {
1607         struct cheetah_err_info local_snapshot, *p;
1608         int recoverable, is_memory;
1609 
1610 #ifdef CONFIG_PCI
1611         /* Check for the special PCI poke sequence. */
1612         if (pci_poke_in_progress && pci_poke_cpu == smp_processor_id()) {
1613                 cheetah_flush_icache();
1614                 cheetah_flush_dcache();
1615 
1616                 /* Re-enable I-cache/D-cache */
1617                 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1618                                      "or %%g1, %1, %%g1\n\t"
1619                                      "stxa %%g1, [%%g0] %0\n\t"
1620                                      "membar #Sync"
1621                                      : /* no outputs */
1622                                      : "i" (ASI_DCU_CONTROL_REG),
1623                                        "i" (DCU_DC | DCU_IC)
1624                                      : "g1");
1625 
1626                 /* Re-enable error reporting */
1627                 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1628                                      "or %%g1, %1, %%g1\n\t"
1629                                      "stxa %%g1, [%%g0] %0\n\t"
1630                                      "membar #Sync"
1631                                      : /* no outputs */
1632                                      : "i" (ASI_ESTATE_ERROR_EN),
1633                                        "i" (ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN)
1634                                      : "g1");
1635 
1636                 (void) cheetah_recheck_errors(NULL);
1637 
1638                 pci_poke_faulted = 1;
1639                 regs->tpc += 4;
1640                 regs->tnpc = regs->tpc + 4;
1641                 return;
1642         }
1643 #endif
1644 
1645         p = cheetah_get_error_log(afsr);
1646         if (!p) {
1647                 prom_printf("ERROR: Early deferred error afsr[%016lx] afar[%016lx]\n",
1648                             afsr, afar);
1649                 prom_printf("ERROR: CPU(%d) TPC[%016lx] TNPC[%016lx] TSTATE[%016lx]\n",
1650                             smp_processor_id(), regs->tpc, regs->tnpc, regs->tstate);
1651                 prom_halt();
1652         }
1653 
1654         /* Grab snapshot of logged error. */
1655         memcpy(&local_snapshot, p, sizeof(local_snapshot));
1656 
1657         /* If the current trap snapshot does not match what the
1658          * trap handler passed along into our args, big trouble.
1659          * In such a case, mark the local copy as invalid.
1660          *
1661          * Else, it matches and we mark the afsr in the non-local
1662          * copy as invalid so we may log new error traps there.
1663          */
1664         if (p->afsr != afsr || p->afar != afar)
1665                 local_snapshot.afsr = CHAFSR_INVALID;
1666         else
1667                 p->afsr = CHAFSR_INVALID;
1668 
1669         is_memory = cheetah_check_main_memory(afar);
1670 
1671         {
1672                 int flush_all, flush_line;
1673 
1674                 flush_all = flush_line = 0;
1675                 if ((afsr & CHAFSR_EDU) != 0UL) {
1676                         if ((afsr & cheetah_afsr_errors) == CHAFSR_EDU)
1677                                 flush_line = 1;
1678                         else
1679                                 flush_all = 1;
1680                 } else if ((afsr & CHAFSR_BERR) != 0UL) {
1681                         if ((afsr & cheetah_afsr_errors) == CHAFSR_BERR)
1682                                 flush_line = 1;
1683                         else
1684                                 flush_all = 1;
1685                 }
1686 
1687                 cheetah_flush_icache();
1688                 cheetah_flush_dcache();
1689 
1690                 /* Re-enable I/D caches */
1691                 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1692                                      "or %%g1, %1, %%g1\n\t"
1693                                      "stxa %%g1, [%%g0] %0\n\t"
1694                                      "membar #Sync"
1695                                      : /* no outputs */
1696                                      : "i" (ASI_DCU_CONTROL_REG),
1697                                      "i" (DCU_IC | DCU_DC)
1698                                      : "g1");
1699 
1700                 if (flush_all)
1701                         cheetah_flush_ecache();
1702                 else if (flush_line)
1703                         cheetah_flush_ecache_line(afar);
1704         }
1705 
1706         /* Re-enable error reporting */
1707         __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1708                              "or %%g1, %1, %%g1\n\t"
1709                              "stxa %%g1, [%%g0] %0\n\t"
1710                              "membar #Sync"
1711                              : /* no outputs */
1712                              : "i" (ASI_ESTATE_ERROR_EN),
1713                              "i" (ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN)
1714                              : "g1");
1715 
1716         /* Decide if we can continue after handling this trap and
1717          * logging the error.
1718          */
1719         recoverable = 1;
1720         if (afsr & (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP))
1721                 recoverable = 0;
1722 
1723         /* Re-check AFSR/AFAR.  What we are looking for here is whether a new
1724          * error was logged while we had error reporting traps disabled.
1725          */
1726         if (cheetah_recheck_errors(&local_snapshot)) {
1727                 unsigned long new_afsr = local_snapshot.afsr;
1728 
1729                 /* If we got a new asynchronous error, die... */
1730                 if (new_afsr & (CHAFSR_EMU | CHAFSR_EDU |
1731                                 CHAFSR_WDU | CHAFSR_CPU |
1732                                 CHAFSR_IVU | CHAFSR_UE |
1733                                 CHAFSR_BERR | CHAFSR_TO))
1734                         recoverable = 0;
1735         }
1736 
1737         /* Log errors. */
1738         cheetah_log_errors(regs, &local_snapshot, afsr, afar, recoverable);
1739 
1740         /* "Recoverable" here means we try to yank the page from ever
1741          * being newly used again.  This depends upon a few things:
1742          * 1) Must be main memory, and AFAR must be valid.
1743          * 2) If we trapped from user, OK.
1744          * 3) Else, if we trapped from kernel we must find exception
1745          *    table entry (ie. we have to have been accessing user
1746          *    space).
1747          *
1748          * If AFAR is not in main memory, or we trapped from kernel
1749          * and cannot find an exception table entry, it is unacceptable
1750          * to try and continue.
1751          */
1752         if (recoverable && is_memory) {
1753                 if ((regs->tstate & TSTATE_PRIV) == 0UL) {
1754                         /* OK, usermode access. */
1755                         recoverable = 1;
1756                 } else {
1757                         const struct exception_table_entry *entry;
1758 
1759                         entry = search_exception_tables(regs->tpc);
1760                         if (entry) {
1761                                 /* OK, kernel access to userspace. */
1762                                 recoverable = 1;
1763 
1764                         } else {
1765                                 /* BAD, privileged state is corrupted. */
1766                                 recoverable = 0;
1767                         }
1768 
1769                         if (recoverable) {
1770                                 if (pfn_valid(afar >> PAGE_SHIFT))
1771                                         get_page(pfn_to_page(afar >> PAGE_SHIFT));
1772                                 else
1773                                         recoverable = 0;
1774 
1775                                 /* Only perform fixup if we still have a
1776                                  * recoverable condition.
1777                                  */
1778                                 if (recoverable) {
1779                                         regs->tpc = entry->fixup;
1780                                         regs->tnpc = regs->tpc + 4;
1781                                 }
1782                         }
1783                 }
1784         } else {
1785                 recoverable = 0;
1786         }
1787 
1788         if (!recoverable)
1789                 panic("Irrecoverable deferred error trap.\n");
1790 }
1791 
1792 /* Handle a D/I cache parity error trap.  TYPE is encoded as:
1793  *
1794  * Bit0:        0=dcache,1=icache
1795  * Bit1:        0=recoverable,1=unrecoverable
1796  *
1797  * The hardware has disabled both the I-cache and D-cache in
1798  * the %dcr register.  
1799  */
1800 void cheetah_plus_parity_error(int type, struct pt_regs *regs)
1801 {
1802         if (type & 0x1)
1803                 __cheetah_flush_icache();
1804         else
1805                 cheetah_plus_zap_dcache_parity();
1806         cheetah_flush_dcache();
1807 
1808         /* Re-enable I-cache/D-cache */
1809         __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1810                              "or %%g1, %1, %%g1\n\t"
1811                              "stxa %%g1, [%%g0] %0\n\t"
1812                              "membar #Sync"
1813                              : /* no outputs */
1814                              : "i" (ASI_DCU_CONTROL_REG),
1815                                "i" (DCU_DC | DCU_IC)
1816                              : "g1");
1817 
1818         if (type & 0x2) {
1819                 printk(KERN_EMERG "CPU[%d]: Cheetah+ %c-cache parity error at TPC[%016lx]\n",
1820                        smp_processor_id(),
1821                        (type & 0x1) ? 'I' : 'D',
1822                        regs->tpc);
1823                 printk(KERN_EMERG "TPC<%pS>\n", (void *) regs->tpc);
1824                 panic("Irrecoverable Cheetah+ parity error.");
1825         }
1826 
1827         printk(KERN_WARNING "CPU[%d]: Cheetah+ %c-cache parity error at TPC[%016lx]\n",
1828                smp_processor_id(),
1829                (type & 0x1) ? 'I' : 'D',
1830                regs->tpc);
1831         printk(KERN_WARNING "TPC<%pS>\n", (void *) regs->tpc);
1832 }
1833 
1834 struct sun4v_error_entry {
1835         /* Unique error handle */
1836 /*0x00*/u64             err_handle;
1837 
1838         /* %stick value at the time of the error */
1839 /*0x08*/u64             err_stick;
1840 
1841 /*0x10*/u8              reserved_1[3];
1842 
1843         /* Error type */
1844 /*0x13*/u8              err_type;
1845 #define SUN4V_ERR_TYPE_UNDEFINED        0
1846 #define SUN4V_ERR_TYPE_UNCORRECTED_RES  1
1847 #define SUN4V_ERR_TYPE_PRECISE_NONRES   2
1848 #define SUN4V_ERR_TYPE_DEFERRED_NONRES  3
1849 #define SUN4V_ERR_TYPE_SHUTDOWN_RQST    4
1850 #define SUN4V_ERR_TYPE_DUMP_CORE        5
1851 #define SUN4V_ERR_TYPE_SP_STATE_CHANGE  6
1852 #define SUN4V_ERR_TYPE_NUM              7
1853 
1854         /* Error attributes */
1855 /*0x14*/u32             err_attrs;
1856 #define SUN4V_ERR_ATTRS_PROCESSOR       0x00000001
1857 #define SUN4V_ERR_ATTRS_MEMORY          0x00000002
1858 #define SUN4V_ERR_ATTRS_PIO             0x00000004
1859 #define SUN4V_ERR_ATTRS_INT_REGISTERS   0x00000008
1860 #define SUN4V_ERR_ATTRS_FPU_REGISTERS   0x00000010
1861 #define SUN4V_ERR_ATTRS_SHUTDOWN_RQST   0x00000020
1862 #define SUN4V_ERR_ATTRS_ASR             0x00000040
1863 #define SUN4V_ERR_ATTRS_ASI             0x00000080
1864 #define SUN4V_ERR_ATTRS_PRIV_REG        0x00000100
1865 #define SUN4V_ERR_ATTRS_SPSTATE_MSK     0x00000600
1866 #define SUN4V_ERR_ATTRS_MCD             0x00000800
1867 #define SUN4V_ERR_ATTRS_SPSTATE_SHFT    9
1868 #define SUN4V_ERR_ATTRS_MODE_MSK        0x03000000
1869 #define SUN4V_ERR_ATTRS_MODE_SHFT       24
1870 #define SUN4V_ERR_ATTRS_RES_QUEUE_FULL  0x80000000
1871 
1872 #define SUN4V_ERR_SPSTATE_FAULTED       0
1873 #define SUN4V_ERR_SPSTATE_AVAILABLE     1
1874 #define SUN4V_ERR_SPSTATE_NOT_PRESENT   2
1875 
1876 #define SUN4V_ERR_MODE_USER             1
1877 #define SUN4V_ERR_MODE_PRIV             2
1878 
1879         /* Real address of the memory region or PIO transaction */
1880 /*0x18*/u64             err_raddr;
1881 
1882         /* Size of the operation triggering the error, in bytes */
1883 /*0x20*/u32             err_size;
1884 
1885         /* ID of the CPU */
1886 /*0x24*/u16             err_cpu;
1887 
1888         /* Grace periof for shutdown, in seconds */
1889 /*0x26*/u16             err_secs;
1890 
1891         /* Value of the %asi register */
1892 /*0x28*/u8              err_asi;
1893 
1894 /*0x29*/u8              reserved_2;
1895 
1896         /* Value of the ASR register number */
1897 /*0x2a*/u16             err_asr;
1898 #define SUN4V_ERR_ASR_VALID             0x8000
1899 
1900 /*0x2c*/u32             reserved_3;
1901 /*0x30*/u64             reserved_4;
1902 /*0x38*/u64             reserved_5;
1903 };
1904 
1905 static atomic_t sun4v_resum_oflow_cnt = ATOMIC_INIT(0);
1906 static atomic_t sun4v_nonresum_oflow_cnt = ATOMIC_INIT(0);
1907 
1908 static const char *sun4v_err_type_to_str(u8 type)
1909 {
1910         static const char *types[SUN4V_ERR_TYPE_NUM] = {
1911                 "undefined",
1912                 "uncorrected resumable",
1913                 "precise nonresumable",
1914                 "deferred nonresumable",
1915                 "shutdown request",
1916                 "dump core",
1917                 "SP state change",
1918         };
1919 
1920         if (type < SUN4V_ERR_TYPE_NUM)
1921                 return types[type];
1922 
1923         return "unknown";
1924 }
1925 
1926 static void sun4v_emit_err_attr_strings(u32 attrs)
1927 {
1928         static const char *attr_names[] = {
1929                 "processor",
1930                 "memory",
1931                 "PIO",
1932                 "int-registers",
1933                 "fpu-registers",
1934                 "shutdown-request",
1935                 "ASR",
1936                 "ASI",
1937                 "priv-reg",
1938         };
1939         static const char *sp_states[] = {
1940                 "sp-faulted",
1941                 "sp-available",
1942                 "sp-not-present",
1943                 "sp-state-reserved",
1944         };
1945         static const char *modes[] = {
1946                 "mode-reserved0",
1947                 "user",
1948                 "priv",
1949                 "mode-reserved1",
1950         };
1951         u32 sp_state, mode;
1952         int i;
1953 
1954         for (i = 0; i < ARRAY_SIZE(attr_names); i++) {
1955                 if (attrs & (1U << i)) {
1956                         const char *s = attr_names[i];
1957 
1958                         pr_cont("%s ", s);
1959                 }
1960         }
1961 
1962         sp_state = ((attrs & SUN4V_ERR_ATTRS_SPSTATE_MSK) >>
1963                     SUN4V_ERR_ATTRS_SPSTATE_SHFT);
1964         pr_cont("%s ", sp_states[sp_state]);
1965 
1966         mode = ((attrs & SUN4V_ERR_ATTRS_MODE_MSK) >>
1967                 SUN4V_ERR_ATTRS_MODE_SHFT);
1968         pr_cont("%s ", modes[mode]);
1969 
1970         if (attrs & SUN4V_ERR_ATTRS_RES_QUEUE_FULL)
1971                 pr_cont("res-queue-full ");
1972 }
1973 
1974 /* When the report contains a real-address of "-1" it means that the
1975  * hardware did not provide the address.  So we compute the effective
1976  * address of the load or store instruction at regs->tpc and report
1977  * that.  Usually when this happens it's a PIO and in such a case we
1978  * are using physical addresses with bypass ASIs anyways, so what we
1979  * report here is exactly what we want.
1980  */
1981 static void sun4v_report_real_raddr(const char *pfx, struct pt_regs *regs)
1982 {
1983         unsigned int insn;
1984         u64 addr;
1985 
1986         if (!(regs->tstate & TSTATE_PRIV))
1987                 return;
1988 
1989         insn = *(unsigned int *) regs->tpc;
1990 
1991         addr = compute_effective_address(regs, insn, 0);
1992 
1993         printk("%s: insn effective address [0x%016llx]\n",
1994                pfx, addr);
1995 }
1996 
1997 static void sun4v_log_error(struct pt_regs *regs, struct sun4v_error_entry *ent,
1998                             int cpu, const char *pfx, atomic_t *ocnt)
1999 {
2000         u64 *raw_ptr = (u64 *) ent;
2001         u32 attrs;
2002         int cnt;
2003 
2004         printk("%s: Reporting on cpu %d\n", pfx, cpu);
2005         printk("%s: TPC [0x%016lx] <%pS>\n",
2006                pfx, regs->tpc, (void *) regs->tpc);
2007 
2008         printk("%s: RAW [%016llx:%016llx:%016llx:%016llx\n",
2009                pfx, raw_ptr[0], raw_ptr[1], raw_ptr[2], raw_ptr[3]);
2010         printk("%s:      %016llx:%016llx:%016llx:%016llx]\n",
2011                pfx, raw_ptr[4], raw_ptr[5], raw_ptr[6], raw_ptr[7]);
2012 
2013         printk("%s: handle [0x%016llx] stick [0x%016llx]\n",
2014                pfx, ent->err_handle, ent->err_stick);
2015 
2016         printk("%s: type [%s]\n", pfx, sun4v_err_type_to_str(ent->err_type));
2017 
2018         attrs = ent->err_attrs;
2019         printk("%s: attrs [0x%08x] < ", pfx, attrs);
2020         sun4v_emit_err_attr_strings(attrs);
2021         pr_cont(">\n");
2022 
2023         /* Various fields in the error report are only valid if
2024          * certain attribute bits are set.
2025          */
2026         if (attrs & (SUN4V_ERR_ATTRS_MEMORY |
2027                      SUN4V_ERR_ATTRS_PIO |
2028                      SUN4V_ERR_ATTRS_ASI)) {
2029                 printk("%s: raddr [0x%016llx]\n", pfx, ent->err_raddr);
2030 
2031                 if (ent->err_raddr == ~(u64)0)
2032                         sun4v_report_real_raddr(pfx, regs);
2033         }
2034 
2035         if (attrs & (SUN4V_ERR_ATTRS_MEMORY | SUN4V_ERR_ATTRS_ASI))
2036                 printk("%s: size [0x%x]\n", pfx, ent->err_size);
2037 
2038         if (attrs & (SUN4V_ERR_ATTRS_PROCESSOR |
2039                      SUN4V_ERR_ATTRS_INT_REGISTERS |
2040                      SUN4V_ERR_ATTRS_FPU_REGISTERS |
2041                      SUN4V_ERR_ATTRS_PRIV_REG))
2042                 printk("%s: cpu[%u]\n", pfx, ent->err_cpu);
2043 
2044         if (attrs & SUN4V_ERR_ATTRS_ASI)
2045                 printk("%s: asi [0x%02x]\n", pfx, ent->err_asi);
2046 
2047         if ((attrs & (SUN4V_ERR_ATTRS_INT_REGISTERS |
2048                       SUN4V_ERR_ATTRS_FPU_REGISTERS |
2049                       SUN4V_ERR_ATTRS_PRIV_REG)) &&
2050             (ent->err_asr & SUN4V_ERR_ASR_VALID) != 0)
2051                 printk("%s: reg [0x%04x]\n",
2052                        pfx, ent->err_asr & ~SUN4V_ERR_ASR_VALID);
2053 
2054         show_regs(regs);
2055 
2056         if ((cnt = atomic_read(ocnt)) != 0) {
2057                 atomic_set(ocnt, 0);
2058                 wmb();
2059                 printk("%s: Queue overflowed %d times.\n",
2060                        pfx, cnt);
2061         }
2062 }
2063 
2064 /* Handle memory corruption detected error which is vectored in
2065  * through resumable error trap.
2066  */
2067 void do_mcd_err(struct pt_regs *regs, struct sun4v_error_entry ent)
2068 {
2069         if (notify_die(DIE_TRAP, "MCD error", regs, 0, 0x34,
2070                        SIGSEGV) == NOTIFY_STOP)
2071                 return;
2072 
2073         if (regs->tstate & TSTATE_PRIV) {
2074                 /* MCD exception could happen because the task was
2075                  * running a system call with MCD enabled and passed a
2076                  * non-versioned pointer or pointer with bad version
2077                  * tag to the system call. In such cases, hypervisor
2078                  * places the address of offending instruction in the
2079                  * resumable error report. This is a deferred error,
2080                  * so the read/write that caused the trap was potentially
2081                  * retired long time back and we may have no choice
2082                  * but to send SIGSEGV to the process.
2083                  */
2084                 const struct exception_table_entry *entry;
2085 
2086                 entry = search_exception_tables(regs->tpc);
2087                 if (entry) {
2088                         /* Looks like a bad syscall parameter */
2089 #ifdef DEBUG_EXCEPTIONS
2090                         pr_emerg("Exception: PC<%016lx> faddr<UNKNOWN>\n",
2091                                  regs->tpc);
2092                         pr_emerg("EX_TABLE: insn<%016lx> fixup<%016lx>\n",
2093                                  ent.err_raddr, entry->fixup);
2094 #endif
2095                         regs->tpc = entry->fixup;
2096                         regs->tnpc = regs->tpc + 4;
2097                         return;
2098                 }
2099         }
2100 
2101         /* Send SIGSEGV to the userspace process with the right signal
2102          * code
2103          */
2104         force_sig_fault(SIGSEGV, SEGV_ADIDERR, (void __user *)ent.err_raddr,
2105                         0, current);
2106 }
2107 
2108 /* We run with %pil set to PIL_NORMAL_MAX and PSTATE_IE enabled in %pstate.
2109  * Log the event and clear the first word of the entry.
2110  */
2111 void sun4v_resum_error(struct pt_regs *regs, unsigned long offset)
2112 {
2113         enum ctx_state prev_state = exception_enter();
2114         struct sun4v_error_entry *ent, local_copy;
2115         struct trap_per_cpu *tb;
2116         unsigned long paddr;
2117         int cpu;
2118 
2119         cpu = get_cpu();
2120 
2121         tb = &trap_block[cpu];
2122         paddr = tb->resum_kernel_buf_pa + offset;
2123         ent = __va(paddr);
2124 
2125         memcpy(&local_copy, ent, sizeof(struct sun4v_error_entry));
2126 
2127         /* We have a local copy now, so release the entry.  */
2128         ent->err_handle = 0;
2129         wmb();
2130 
2131         put_cpu();
2132 
2133         if (local_copy.err_type == SUN4V_ERR_TYPE_SHUTDOWN_RQST) {
2134                 /* We should really take the seconds field of
2135                  * the error report and use it for the shutdown
2136                  * invocation, but for now do the same thing we
2137                  * do for a DS shutdown request.
2138                  */
2139                 pr_info("Shutdown request, %u seconds...\n",
2140                         local_copy.err_secs);
2141                 orderly_poweroff(true);
2142                 goto out;
2143         }
2144 
2145         /* If this is a memory corruption detected error vectored in
2146          * by HV through resumable error trap, call the handler
2147          */
2148         if (local_copy.err_attrs & SUN4V_ERR_ATTRS_MCD) {
2149                 do_mcd_err(regs, local_copy);
2150                 return;
2151         }
2152 
2153         sun4v_log_error(regs, &local_copy, cpu,
2154                         KERN_ERR "RESUMABLE ERROR",
2155                         &sun4v_resum_oflow_cnt);
2156 out:
2157         exception_exit(prev_state);
2158 }
2159 
2160 /* If we try to printk() we'll probably make matters worse, by trying
2161  * to retake locks this cpu already holds or causing more errors. So
2162  * just bump a counter, and we'll report these counter bumps above.
2163  */
2164 void sun4v_resum_overflow(struct pt_regs *regs)
2165 {
2166         atomic_inc(&sun4v_resum_oflow_cnt);
2167 }
2168 
2169 /* Given a set of registers, get the virtual addressi that was being accessed
2170  * by the faulting instructions at tpc.
2171  */
2172 static unsigned long sun4v_get_vaddr(struct pt_regs *regs)
2173 {
2174         unsigned int insn;
2175 
2176         if (!copy_from_user(&insn, (void __user *)regs->tpc, 4)) {
2177                 return compute_effective_address(regs, insn,
2178                                                  (insn >> 25) & 0x1f);
2179         }
2180         return 0;
2181 }
2182 
2183 /* Attempt to handle non-resumable errors generated from userspace.
2184  * Returns true if the signal was handled, false otherwise.
2185  */
2186 bool sun4v_nonresum_error_user_handled(struct pt_regs *regs,
2187                                   struct sun4v_error_entry *ent) {
2188 
2189         unsigned int attrs = ent->err_attrs;
2190 
2191         if (attrs & SUN4V_ERR_ATTRS_MEMORY) {
2192                 unsigned long addr = ent->err_raddr;
2193                 siginfo_t info;
2194 
2195                 if (addr == ~(u64)0) {
2196                         /* This seems highly unlikely to ever occur */
2197                         pr_emerg("SUN4V NON-RECOVERABLE ERROR: Memory error detected in unknown location!\n");
2198                 } else {
2199                         unsigned long page_cnt = DIV_ROUND_UP(ent->err_size,
2200                                                               PAGE_SIZE);
2201 
2202                         /* Break the unfortunate news. */
2203                         pr_emerg("SUN4V NON-RECOVERABLE ERROR: Memory failed at %016lX\n",
2204                                  addr);
2205                         pr_emerg("SUN4V NON-RECOVERABLE ERROR:   Claiming %lu ages.\n",
2206                                  page_cnt);
2207 
2208                         while (page_cnt-- > 0) {
2209                                 if (pfn_valid(addr >> PAGE_SHIFT))
2210                                         get_page(pfn_to_page(addr >> PAGE_SHIFT));
2211                                 addr += PAGE_SIZE;
2212                         }
2213                 }
2214                 info.si_signo = SIGKILL;
2215                 info.si_errno = 0;
2216                 info.si_trapno = 0;
2217                 force_sig_info(info.si_signo, &info, current);
2218 
2219                 return true;
2220         }
2221         if (attrs & SUN4V_ERR_ATTRS_PIO) {
2222                 siginfo_t info;
2223 
2224                 info.si_signo = SIGBUS;
2225                 info.si_code = BUS_ADRERR;
2226                 info.si_addr = (void __user *)sun4v_get_vaddr(regs);
2227                 force_sig_info(info.si_signo, &info, current);
2228 
2229                 return true;
2230         }
2231 
2232         /* Default to doing nothing */
2233         return false;
2234 }
2235 
2236 /* We run with %pil set to PIL_NORMAL_MAX and PSTATE_IE enabled in %pstate.
2237  * Log the event, clear the first word of the entry, and die.
2238  */
2239 void sun4v_nonresum_error(struct pt_regs *regs, unsigned long offset)
2240 {
2241         struct sun4v_error_entry *ent, local_copy;
2242         struct trap_per_cpu *tb;
2243         unsigned long paddr;
2244         int cpu;
2245 
2246         cpu = get_cpu();
2247 
2248         tb = &trap_block[cpu];
2249         paddr = tb->nonresum_kernel_buf_pa + offset;
2250         ent = __va(paddr);
2251 
2252         memcpy(&local_copy, ent, sizeof(struct sun4v_error_entry));
2253 
2254         /* We have a local copy now, so release the entry.  */
2255         ent->err_handle = 0;
2256         wmb();
2257 
2258         put_cpu();
2259 
2260         if (!(regs->tstate & TSTATE_PRIV) &&
2261             sun4v_nonresum_error_user_handled(regs, &local_copy)) {
2262                 /* DON'T PANIC: This userspace error was handled. */
2263                 return;
2264         }
2265 
2266 #ifdef CONFIG_PCI
2267         /* Check for the special PCI poke sequence. */
2268         if (pci_poke_in_progress && pci_poke_cpu == cpu) {
2269                 pci_poke_faulted = 1;
2270                 regs->tpc += 4;
2271                 regs->tnpc = regs->tpc + 4;
2272                 return;
2273         }
2274 #endif
2275 
2276         sun4v_log_error(regs, &local_copy, cpu,
2277                         KERN_EMERG "NON-RESUMABLE ERROR",
2278                         &sun4v_nonresum_oflow_cnt);
2279 
2280         panic("Non-resumable error.");
2281 }
2282 
2283 /* If we try to printk() we'll probably make matters worse, by trying
2284  * to retake locks this cpu already holds or causing more errors. So
2285  * just bump a counter, and we'll report these counter bumps above.
2286  */
2287 void sun4v_nonresum_overflow(struct pt_regs *regs)
2288 {
2289         /* XXX Actually even this can make not that much sense.  Perhaps
2290          * XXX we should just pull the plug and panic directly from here?
2291          */
2292         atomic_inc(&sun4v_nonresum_oflow_cnt);
2293 }
2294 
2295 static void sun4v_tlb_error(struct pt_regs *regs)
2296 {
2297         die_if_kernel("TLB/TSB error", regs);
2298 }
2299 
2300 unsigned long sun4v_err_itlb_vaddr;
2301 unsigned long sun4v_err_itlb_ctx;
2302 unsigned long sun4v_err_itlb_pte;
2303 unsigned long sun4v_err_itlb_error;
2304 
2305 void sun4v_itlb_error_report(struct pt_regs *regs, int tl)
2306 {
2307         dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2308 
2309         printk(KERN_EMERG "SUN4V-ITLB: Error at TPC[%lx], tl %d\n",
2310                regs->tpc, tl);
2311         printk(KERN_EMERG "SUN4V-ITLB: TPC<%pS>\n", (void *) regs->tpc);
2312         printk(KERN_EMERG "SUN4V-ITLB: O7[%lx]\n", regs->u_regs[UREG_I7]);
2313         printk(KERN_EMERG "SUN4V-ITLB: O7<%pS>\n",
2314                (void *) regs->u_regs[UREG_I7]);
2315         printk(KERN_EMERG "SUN4V-ITLB: vaddr[%lx] ctx[%lx] "
2316                "pte[%lx] error[%lx]\n",
2317                sun4v_err_itlb_vaddr, sun4v_err_itlb_ctx,
2318                sun4v_err_itlb_pte, sun4v_err_itlb_error);
2319 
2320         sun4v_tlb_error(regs);
2321 }
2322 
2323 unsigned long sun4v_err_dtlb_vaddr;
2324 unsigned long sun4v_err_dtlb_ctx;
2325 unsigned long sun4v_err_dtlb_pte;
2326 unsigned long sun4v_err_dtlb_error;
2327 
2328 void sun4v_dtlb_error_report(struct pt_regs *regs, int tl)
2329 {
2330         dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2331 
2332         printk(KERN_EMERG "SUN4V-DTLB: Error at TPC[%lx], tl %d\n",
2333                regs->tpc, tl);
2334         printk(KERN_EMERG "SUN4V-DTLB: TPC<%pS>\n", (void *) regs->tpc);
2335         printk(KERN_EMERG "SUN4V-DTLB: O7[%lx]\n", regs->u_regs[UREG_I7]);
2336         printk(KERN_EMERG "SUN4V-DTLB: O7<%pS>\n",
2337                (void *) regs->u_regs[UREG_I7]);
2338         printk(KERN_EMERG "SUN4V-DTLB: vaddr[%lx] ctx[%lx] "
2339                "pte[%lx] error[%lx]\n",
2340                sun4v_err_dtlb_vaddr, sun4v_err_dtlb_ctx,
2341                sun4v_err_dtlb_pte, sun4v_err_dtlb_error);
2342 
2343         sun4v_tlb_error(regs);
2344 }
2345 
2346 void hypervisor_tlbop_error(unsigned long err, unsigned long op)
2347 {
2348         printk(KERN_CRIT "SUN4V: TLB hv call error %lu for op %lu\n",
2349                err, op);
2350 }
2351 
2352 void hypervisor_tlbop_error_xcall(unsigned long err, unsigned long op)
2353 {
2354         printk(KERN_CRIT "SUN4V: XCALL TLB hv call error %lu for op %lu\n",
2355                err, op);
2356 }
2357 
2358 static void do_fpe_common(struct pt_regs *regs)
2359 {
2360         if (regs->tstate & TSTATE_PRIV) {
2361                 regs->tpc = regs->tnpc;
2362                 regs->tnpc += 4;
2363         } else {
2364                 unsigned long fsr = current_thread_info()->xfsr[0];
2365                 siginfo_t info;
2366 
2367                 if (test_thread_flag(TIF_32BIT)) {
2368                         regs->tpc &= 0xffffffff;
2369                         regs->tnpc &= 0xffffffff;
2370                 }
2371                 info.si_signo = SIGFPE;
2372                 info.si_errno = 0;
2373                 info.si_addr = (void __user *)regs->tpc;
2374                 info.si_trapno = 0;
2375                 info.si_code = FPE_FIXME;
2376                 if ((fsr & 0x1c000) == (1 << 14)) {
2377                         if (fsr & 0x10)
2378                                 info.si_code = FPE_FLTINV;
2379                         else if (fsr & 0x08)
2380                                 info.si_code = FPE_FLTOVF;
2381                         else if (fsr & 0x04)
2382                                 info.si_code = FPE_FLTUND;
2383                         else if (fsr & 0x02)
2384                                 info.si_code = FPE_FLTDIV;
2385                         else if (fsr & 0x01)
2386                                 info.si_code = FPE_FLTRES;
2387                 }
2388                 force_sig_info(SIGFPE, &info, current);
2389         }
2390 }
2391 
2392 void do_fpieee(struct pt_regs *regs)
2393 {
2394         enum ctx_state prev_state = exception_enter();
2395 
2396         if (notify_die(DIE_TRAP, "fpu exception ieee", regs,
2397                        0, 0x24, SIGFPE) == NOTIFY_STOP)
2398                 goto out;
2399 
2400         do_fpe_common(regs);
2401 out:
2402         exception_exit(prev_state);
2403 }
2404 
2405 void do_fpother(struct pt_regs *regs)
2406 {
2407         enum ctx_state prev_state = exception_enter();
2408         struct fpustate *f = FPUSTATE;
2409         int ret = 0;
2410 
2411         if (notify_die(DIE_TRAP, "fpu exception other", regs,
2412                        0, 0x25, SIGFPE) == NOTIFY_STOP)
2413                 goto out;
2414 
2415         switch ((current_thread_info()->xfsr[0] & 0x1c000)) {
2416         case (2 << 14): /* unfinished_FPop */
2417         case (3 << 14): /* unimplemented_FPop */
2418                 ret = do_mathemu(regs, f, false);
2419                 break;
2420         }
2421         if (ret)
2422                 goto out;
2423         do_fpe_common(regs);
2424 out:
2425         exception_exit(prev_state);
2426 }
2427 
2428 void do_tof(struct pt_regs *regs)
2429 {
2430         enum ctx_state prev_state = exception_enter();
2431         siginfo_t info;
2432 
2433         if (notify_die(DIE_TRAP, "tagged arithmetic overflow", regs,
2434                        0, 0x26, SIGEMT) == NOTIFY_STOP)
2435                 goto out;
2436 
2437         if (regs->tstate & TSTATE_PRIV)
2438                 die_if_kernel("Penguin overflow trap from kernel mode", regs);
2439         if (test_thread_flag(TIF_32BIT)) {
2440                 regs->tpc &= 0xffffffff;
2441                 regs->tnpc &= 0xffffffff;
2442         }
2443         info.si_signo = SIGEMT;
2444         info.si_errno = 0;
2445         info.si_code = EMT_TAGOVF;
2446         info.si_addr = (void __user *)regs->tpc;
2447         info.si_trapno = 0;
2448         force_sig_info(SIGEMT, &info, current);
2449 out:
2450         exception_exit(prev_state);
2451 }
2452 
2453 void do_div0(struct pt_regs *regs)
2454 {
2455         enum ctx_state prev_state = exception_enter();
2456         siginfo_t info;
2457 
2458         if (notify_die(DIE_TRAP, "integer division by zero", regs,
2459                        0, 0x28, SIGFPE) == NOTIFY_STOP)
2460                 goto out;
2461 
2462         if (regs->tstate & TSTATE_PRIV)
2463                 die_if_kernel("TL0: Kernel divide by zero.", regs);
2464         if (test_thread_flag(TIF_32BIT)) {
2465                 regs->tpc &= 0xffffffff;
2466                 regs->tnpc &= 0xffffffff;
2467         }
2468         info.si_signo = SIGFPE;
2469         info.si_errno = 0;
2470         info.si_code = FPE_INTDIV;
2471         info.si_addr = (void __user *)regs->tpc;
2472         info.si_trapno = 0;
2473         force_sig_info(SIGFPE, &info, current);
2474 out:
2475         exception_exit(prev_state);
2476 }
2477 
2478 static void instruction_dump(unsigned int *pc)
2479 {
2480         int i;
2481 
2482         if ((((unsigned long) pc) & 3))
2483                 return;
2484 
2485         printk("Instruction DUMP:");
2486         for (i = -3; i < 6; i++)
2487                 printk("%c%08x%c",i?' ':'<',pc[i],i?' ':'>');
2488         printk("\n");
2489 }
2490 
2491 static void user_instruction_dump(unsigned int __user *pc)
2492 {
2493         int i;
2494         unsigned int buf[9];
2495         
2496         if ((((unsigned long) pc) & 3))
2497                 return;
2498                 
2499         if (copy_from_user(buf, pc - 3, sizeof(buf)))
2500                 return;
2501 
2502         printk("Instruction DUMP:");
2503         for (i = 0; i < 9; i++)
2504                 printk("%c%08x%c",i==3?' ':'<',buf[i],i==3?' ':'>');
2505         printk("\n");
2506 }
2507 
2508 void show_stack(struct task_struct *tsk, unsigned long *_ksp)
2509 {
2510         unsigned long fp, ksp;
2511         struct thread_info *tp;
2512         int count = 0;
2513 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
2514         int graph = 0;
2515 #endif
2516 
2517         ksp = (unsigned long) _ksp;
2518         if (!tsk)
2519                 tsk = current;
2520         tp = task_thread_info(tsk);
2521         if (ksp == 0UL) {
2522                 if (tsk == current)
2523                         asm("mov %%fp, %0" : "=r" (ksp));
2524                 else
2525                         ksp = tp->ksp;
2526         }
2527         if (tp == current_thread_info())
2528                 flushw_all();
2529 
2530         fp = ksp + STACK_BIAS;
2531 
2532         printk("Call Trace:\n");
2533         do {
2534                 struct sparc_stackf *sf;
2535                 struct pt_regs *regs;
2536                 unsigned long pc;
2537 
2538                 if (!kstack_valid(tp, fp))
2539                         break;
2540                 sf = (struct sparc_stackf *) fp;
2541                 regs = (struct pt_regs *) (sf + 1);
2542 
2543                 if (kstack_is_trap_frame(tp, regs)) {
2544                         if (!(regs->tstate & TSTATE_PRIV))
2545                                 break;
2546                         pc = regs->tpc;
2547                         fp = regs->u_regs[UREG_I6] + STACK_BIAS;
2548                 } else {
2549                         pc = sf->callers_pc;
2550                         fp = (unsigned long)sf->fp + STACK_BIAS;
2551                 }
2552 
2553                 printk(" [%016lx] %pS\n", pc, (void *) pc);
2554 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
2555                 if ((pc + 8UL) == (unsigned long) &return_to_handler) {
2556                         int index = tsk->curr_ret_stack;
2557                         if (tsk->ret_stack && index >= graph) {
2558                                 pc = tsk->ret_stack[index - graph].ret;
2559                                 printk(" [%016lx] %pS\n", pc, (void *) pc);
2560                                 graph++;
2561                         }
2562                 }
2563 #endif
2564         } while (++count < 16);
2565 }
2566 
2567 static inline struct reg_window *kernel_stack_up(struct reg_window *rw)
2568 {
2569         unsigned long fp = rw->ins[6];
2570 
2571         if (!fp)
2572                 return NULL;
2573 
2574         return (struct reg_window *) (fp + STACK_BIAS);
2575 }
2576 
2577 void __noreturn die_if_kernel(char *str, struct pt_regs *regs)
2578 {
2579         static int die_counter;
2580         int count = 0;
2581         
2582         /* Amuse the user. */
2583         printk(
2584 "              \\|/ ____ \\|/\n"
2585 "              \"@'/ .. \\`@\"\n"
2586 "              /_| \\__/ |_\\\n"
2587 "                 \\__U_/\n");
2588 
2589         printk("%s(%d): %s [#%d]\n", current->comm, task_pid_nr(current), str, ++die_counter);
2590         notify_die(DIE_OOPS, str, regs, 0, 255, SIGSEGV);
2591         __asm__ __volatile__("flushw");
2592         show_regs(regs);
2593         add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
2594         if (regs->tstate & TSTATE_PRIV) {
2595                 struct thread_info *tp = current_thread_info();
2596                 struct reg_window *rw = (struct reg_window *)
2597                         (regs->u_regs[UREG_FP] + STACK_BIAS);
2598 
2599                 /* Stop the back trace when we hit userland or we
2600                  * find some badly aligned kernel stack.
2601                  */
2602                 while (rw &&
2603                        count++ < 30 &&
2604                        kstack_valid(tp, (unsigned long) rw)) {
2605                         printk("Caller[%016lx]: %pS\n", rw->ins[7],
2606                                (void *) rw->ins[7]);
2607 
2608                         rw = kernel_stack_up(rw);
2609                 }
2610                 instruction_dump ((unsigned int *) regs->tpc);
2611         } else {
2612                 if (test_thread_flag(TIF_32BIT)) {
2613                         regs->tpc &= 0xffffffff;
2614                         regs->tnpc &= 0xffffffff;
2615                 }
2616                 user_instruction_dump ((unsigned int __user *) regs->tpc);
2617         }
2618         if (panic_on_oops)
2619                 panic("Fatal exception");
2620         if (regs->tstate & TSTATE_PRIV)
2621                 do_exit(SIGKILL);
2622         do_exit(SIGSEGV);
2623 }
2624 EXPORT_SYMBOL(die_if_kernel);
2625 
2626 #define VIS_OPCODE_MASK ((0x3 << 30) | (0x3f << 19))
2627 #define VIS_OPCODE_VAL  ((0x2 << 30) | (0x36 << 19))
2628 
2629 void do_illegal_instruction(struct pt_regs *regs)
2630 {
2631         enum ctx_state prev_state = exception_enter();
2632         unsigned long pc = regs->tpc;
2633         unsigned long tstate = regs->tstate;
2634         u32 insn;
2635         siginfo_t info;
2636 
2637         if (notify_die(DIE_TRAP, "illegal instruction", regs,
2638                        0, 0x10, SIGILL) == NOTIFY_STOP)
2639                 goto out;
2640 
2641         if (tstate & TSTATE_PRIV)
2642                 die_if_kernel("Kernel illegal instruction", regs);
2643         if (test_thread_flag(TIF_32BIT))
2644                 pc = (u32)pc;
2645         if (get_user(insn, (u32 __user *) pc) != -EFAULT) {
2646                 if ((insn & 0xc1ffc000) == 0x81700000) /* POPC */ {
2647                         if (handle_popc(insn, regs))
2648                                 goto out;
2649                 } else if ((insn & 0xc1580000) == 0xc1100000) /* LDQ/STQ */ {
2650                         if (handle_ldf_stq(insn, regs))
2651                                 goto out;
2652                 } else if (tlb_type == hypervisor) {
2653                         if ((insn & VIS_OPCODE_MASK) == VIS_OPCODE_VAL) {
2654                                 if (!vis_emul(regs, insn))
2655                                         goto out;
2656                         } else {
2657                                 struct fpustate *f = FPUSTATE;
2658 
2659                                 /* On UltraSPARC T2 and later, FPU insns which
2660                                  * are not implemented in HW signal an illegal
2661                                  * instruction trap and do not set the FP Trap
2662                                  * Trap in the %fsr to unimplemented_FPop.
2663                                  */
2664                                 if (do_mathemu(regs, f, true))
2665                                         goto out;
2666                         }
2667                 }
2668         }
2669         info.si_signo = SIGILL;
2670         info.si_errno = 0;
2671         info.si_code = ILL_ILLOPC;
2672         info.si_addr = (void __user *)pc;
2673         info.si_trapno = 0;
2674         force_sig_info(SIGILL, &info, current);
2675 out:
2676         exception_exit(prev_state);
2677 }
2678 
2679 void mem_address_unaligned(struct pt_regs *regs, unsigned long sfar, unsigned long sfsr)
2680 {
2681         enum ctx_state prev_state = exception_enter();
2682         siginfo_t info;
2683 
2684         if (notify_die(DIE_TRAP, "memory address unaligned", regs,
2685                        0, 0x34, SIGSEGV) == NOTIFY_STOP)
2686                 goto out;
2687 
2688         if (regs->tstate & TSTATE_PRIV) {
2689                 kernel_unaligned_trap(regs, *((unsigned int *)regs->tpc));
2690                 goto out;
2691         }
2692         if (is_no_fault_exception(regs))
2693                 return;
2694 
2695         info.si_signo = SIGBUS;
2696         info.si_errno = 0;
2697         info.si_code = BUS_ADRALN;
2698         info.si_addr = (void __user *)sfar;
2699         info.si_trapno = 0;
2700         force_sig_info(SIGBUS, &info, current);
2701 out:
2702         exception_exit(prev_state);
2703 }
2704 
2705 void sun4v_do_mna(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
2706 {
2707         siginfo_t info;
2708 
2709         if (notify_die(DIE_TRAP, "memory address unaligned", regs,
2710                        0, 0x34, SIGSEGV) == NOTIFY_STOP)
2711                 return;
2712 
2713         if (regs->tstate & TSTATE_PRIV) {
2714                 kernel_unaligned_trap(regs, *((unsigned int *)regs->tpc));
2715                 return;
2716         }
2717         if (is_no_fault_exception(regs))
2718                 return;
2719 
2720         info.si_signo = SIGBUS;
2721         info.si_errno = 0;
2722         info.si_code = BUS_ADRALN;
2723         info.si_addr = (void __user *) addr;
2724         info.si_trapno = 0;
2725         force_sig_info(SIGBUS, &info, current);
2726 }
2727 
2728 /* sun4v_mem_corrupt_detect_precise() - Handle precise exception on an ADI
2729  * tag mismatch.
2730  *
2731  * ADI version tag mismatch on a load from memory always results in a
2732  * precise exception. Tag mismatch on a store to memory will result in
2733  * precise exception if MCDPER or PMCDPER is set to 1.
2734  */
2735 void sun4v_mem_corrupt_detect_precise(struct pt_regs *regs, unsigned long addr,
2736                                       unsigned long context)
2737 {
2738         if (notify_die(DIE_TRAP, "memory corruption precise exception", regs,
2739                        0, 0x8, SIGSEGV) == NOTIFY_STOP)
2740                 return;
2741 
2742         if (regs->tstate & TSTATE_PRIV) {
2743                 /* MCD exception could happen because the task was running
2744                  * a system call with MCD enabled and passed a non-versioned
2745                  * pointer or pointer with bad version tag to  the system
2746                  * call.
2747                  */
2748                 const struct exception_table_entry *entry;
2749 
2750                 entry = search_exception_tables(regs->tpc);
2751                 if (entry) {
2752                         /* Looks like a bad syscall parameter */
2753 #ifdef DEBUG_EXCEPTIONS
2754                         pr_emerg("Exception: PC<%016lx> faddr<UNKNOWN>\n",
2755                                  regs->tpc);
2756                         pr_emerg("EX_TABLE: insn<%016lx> fixup<%016lx>\n",
2757                                  regs->tpc, entry->fixup);
2758 #endif
2759                         regs->tpc = entry->fixup;
2760                         regs->tnpc = regs->tpc + 4;
2761                         return;
2762                 }
2763                 pr_emerg("%s: ADDR[%016lx] CTX[%lx], going.\n",
2764                          __func__, addr, context);
2765                 die_if_kernel("MCD precise", regs);
2766         }
2767 
2768         if (test_thread_flag(TIF_32BIT)) {
2769                 regs->tpc &= 0xffffffff;
2770                 regs->tnpc &= 0xffffffff;
2771         }
2772         force_sig_fault(SIGSEGV, SEGV_ADIPERR, (void __user *)addr, 0, current);
2773 }
2774 
2775 void do_privop(struct pt_regs *regs)
2776 {
2777         enum ctx_state prev_state = exception_enter();
2778         siginfo_t info;
2779 
2780         if (notify_die(DIE_TRAP, "privileged operation", regs,
2781                        0, 0x11, SIGILL) == NOTIFY_STOP)
2782                 goto out;
2783 
2784         if (test_thread_flag(TIF_32BIT)) {
2785                 regs->tpc &= 0xffffffff;
2786                 regs->tnpc &= 0xffffffff;
2787         }
2788         info.si_signo = SIGILL;
2789         info.si_errno = 0;
2790         info.si_code = ILL_PRVOPC;
2791         info.si_addr = (void __user *)regs->tpc;
2792         info.si_trapno = 0;
2793         force_sig_info(SIGILL, &info, current);
2794 out:
2795         exception_exit(prev_state);
2796 }
2797 
2798 void do_privact(struct pt_regs *regs)
2799 {
2800         do_privop(regs);
2801 }
2802 
2803 /* Trap level 1 stuff or other traps we should never see... */
2804 void do_cee(struct pt_regs *regs)
2805 {
2806         exception_enter();
2807         die_if_kernel("TL0: Cache Error Exception", regs);
2808 }
2809 
2810 void do_div0_tl1(struct pt_regs *regs)
2811 {
2812         exception_enter();
2813         dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2814         die_if_kernel("TL1: DIV0 Exception", regs);
2815 }
2816 
2817 void do_fpieee_tl1(struct pt_regs *regs)
2818 {
2819         exception_enter();
2820         dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2821         die_if_kernel("TL1: FPU IEEE Exception", regs);
2822 }
2823 
2824 void do_fpother_tl1(struct pt_regs *regs)
2825 {
2826         exception_enter();
2827         dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2828         die_if_kernel("TL1: FPU Other Exception", regs);
2829 }
2830 
2831 void do_ill_tl1(struct pt_regs *regs)
2832 {
2833         exception_enter();
2834         dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2835         die_if_kernel("TL1: Illegal Instruction Exception", regs);
2836 }
2837 
2838 void do_irq_tl1(struct pt_regs *regs)
2839 {
2840         exception_enter();
2841         dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2842         die_if_kernel("TL1: IRQ Exception", regs);
2843 }
2844 
2845 void do_lddfmna_tl1(struct pt_regs *regs)
2846 {
2847         exception_enter();
2848         dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2849         die_if_kernel("TL1: LDDF Exception", regs);
2850 }
2851 
2852 void do_stdfmna_tl1(struct pt_regs *regs)
2853 {
2854         exception_enter();
2855         dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2856         die_if_kernel("TL1: STDF Exception", regs);
2857 }
2858 
2859 void do_paw(struct pt_regs *regs)
2860 {
2861         exception_enter();
2862         die_if_kernel("TL0: Phys Watchpoint Exception", regs);
2863 }
2864 
2865 void do_paw_tl1(struct pt_regs *regs)
2866 {
2867         exception_enter();
2868         dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2869         die_if_kernel("TL1: Phys Watchpoint Exception", regs);
2870 }
2871 
2872 void do_vaw(struct pt_regs *regs)
2873 {
2874         exception_enter();
2875         die_if_kernel("TL0: Virt Watchpoint Exception", regs);
2876 }
2877 
2878 void do_vaw_tl1(struct pt_regs *regs)
2879 {
2880         exception_enter();
2881         dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2882         die_if_kernel("TL1: Virt Watchpoint Exception", regs);
2883 }
2884 
2885 void do_tof_tl1(struct pt_regs *regs)
2886 {
2887         exception_enter();
2888         dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2889         die_if_kernel("TL1: Tag Overflow Exception", regs);
2890 }
2891 
2892 void do_getpsr(struct pt_regs *regs)
2893 {
2894         regs->u_regs[UREG_I0] = tstate_to_psr(regs->tstate);
2895         regs->tpc   = regs->tnpc;
2896         regs->tnpc += 4;
2897         if (test_thread_flag(TIF_32BIT)) {
2898                 regs->tpc &= 0xffffffff;
2899                 regs->tnpc &= 0xffffffff;
2900         }
2901 }
2902 
2903 u64 cpu_mondo_counter[NR_CPUS] = {0};
2904 struct trap_per_cpu trap_block[NR_CPUS];
2905 EXPORT_SYMBOL(trap_block);
2906 
2907 /* This can get invoked before sched_init() so play it super safe
2908  * and use hard_smp_processor_id().
2909  */
2910 void notrace init_cur_cpu_trap(struct thread_info *t)
2911 {
2912         int cpu = hard_smp_processor_id();
2913         struct trap_per_cpu *p = &trap_block[cpu];
2914 
2915         p->thread = t;
2916         p->pgd_paddr = 0;
2917 }
2918 
2919 extern void thread_info_offsets_are_bolixed_dave(void);
2920 extern void trap_per_cpu_offsets_are_bolixed_dave(void);
2921 extern void tsb_config_offsets_are_bolixed_dave(void);
2922 
2923 /* Only invoked on boot processor. */
2924 void __init trap_init(void)
2925 {
2926         /* Compile time sanity check. */
2927         BUILD_BUG_ON(TI_TASK != offsetof(struct thread_info, task) ||
2928                      TI_FLAGS != offsetof(struct thread_info, flags) ||
2929                      TI_CPU != offsetof(struct thread_info, cpu) ||
2930                      TI_FPSAVED != offsetof(struct thread_info, fpsaved) ||
2931                      TI_KSP != offsetof(struct thread_info, ksp) ||
2932                      TI_FAULT_ADDR != offsetof(struct thread_info,
2933                                                fault_address) ||
2934                      TI_KREGS != offsetof(struct thread_info, kregs) ||
2935                      TI_UTRAPS != offsetof(struct thread_info, utraps) ||
2936                      TI_REG_WINDOW != offsetof(struct thread_info,
2937                                                reg_window) ||
2938                      TI_RWIN_SPTRS != offsetof(struct thread_info,
2939                                                rwbuf_stkptrs) ||
2940                      TI_GSR != offsetof(struct thread_info, gsr) ||
2941                      TI_XFSR != offsetof(struct thread_info, xfsr) ||
2942                      TI_PRE_COUNT != offsetof(struct thread_info,
2943                                               preempt_count) ||
2944                      TI_NEW_CHILD != offsetof(struct thread_info, new_child) ||
2945                      TI_CURRENT_DS != offsetof(struct thread_info,
2946                                                 current_ds) ||
2947                      TI_KUNA_REGS != offsetof(struct thread_info,
2948                                               kern_una_regs) ||
2949                      TI_KUNA_INSN != offsetof(struct thread_info,
2950                                               kern_una_insn) ||
2951                      TI_FPREGS != offsetof(struct thread_info, fpregs) ||
2952                      (TI_FPREGS & (64 - 1)));
2953 
2954         BUILD_BUG_ON(TRAP_PER_CPU_THREAD != offsetof(struct trap_per_cpu,
2955                                                      thread) ||
2956                      (TRAP_PER_CPU_PGD_PADDR !=
2957                       offsetof(struct trap_per_cpu, pgd_paddr)) ||
2958                      (TRAP_PER_CPU_CPU_MONDO_PA !=
2959                       offsetof(struct trap_per_cpu, cpu_mondo_pa)) ||
2960                      (TRAP_PER_CPU_DEV_MONDO_PA !=
2961                       offsetof(struct trap_per_cpu, dev_mondo_pa)) ||
2962                      (TRAP_PER_CPU_RESUM_MONDO_PA !=
2963                       offsetof(struct trap_per_cpu, resum_mondo_pa)) ||
2964                      (TRAP_PER_CPU_RESUM_KBUF_PA !=
2965                       offsetof(struct trap_per_cpu, resum_kernel_buf_pa)) ||
2966                      (TRAP_PER_CPU_NONRESUM_MONDO_PA !=
2967                       offsetof(struct trap_per_cpu, nonresum_mondo_pa)) ||
2968                      (TRAP_PER_CPU_NONRESUM_KBUF_PA !=
2969                       offsetof(struct trap_per_cpu, nonresum_kernel_buf_pa)) ||
2970                      (TRAP_PER_CPU_FAULT_INFO !=
2971                       offsetof(struct trap_per_cpu, fault_info)) ||
2972                      (TRAP_PER_CPU_CPU_MONDO_BLOCK_PA !=
2973                       offsetof(struct trap_per_cpu, cpu_mondo_block_pa)) ||
2974                      (TRAP_PER_CPU_CPU_LIST_PA !=
2975                       offsetof(struct trap_per_cpu, cpu_list_pa)) ||
2976                      (TRAP_PER_CPU_TSB_HUGE !=
2977                       offsetof(struct trap_per_cpu, tsb_huge)) ||
2978                      (TRAP_PER_CPU_TSB_HUGE_TEMP !=
2979                       offsetof(struct trap_per_cpu, tsb_huge_temp)) ||
2980                      (TRAP_PER_CPU_IRQ_WORKLIST_PA !=
2981                       offsetof(struct trap_per_cpu, irq_worklist_pa)) ||
2982                      (TRAP_PER_CPU_CPU_MONDO_QMASK !=
2983                       offsetof(struct trap_per_cpu, cpu_mondo_qmask)) ||
2984                      (TRAP_PER_CPU_DEV_MONDO_QMASK !=
2985                       offsetof(struct trap_per_cpu, dev_mondo_qmask)) ||
2986                      (TRAP_PER_CPU_RESUM_QMASK !=
2987                       offsetof(struct trap_per_cpu, resum_qmask)) ||
2988                      (TRAP_PER_CPU_NONRESUM_QMASK !=
2989                       offsetof(struct trap_per_cpu, nonresum_qmask)) ||
2990                      (TRAP_PER_CPU_PER_CPU_BASE !=
2991                       offsetof(struct trap_per_cpu, __per_cpu_base)));
2992 
2993         BUILD_BUG_ON((TSB_CONFIG_TSB !=
2994                       offsetof(struct tsb_config, tsb)) ||
2995                      (TSB_CONFIG_RSS_LIMIT !=
2996                       offsetof(struct tsb_config, tsb_rss_limit)) ||
2997                      (TSB_CONFIG_NENTRIES !=
2998                       offsetof(struct tsb_config, tsb_nentries)) ||
2999                      (TSB_CONFIG_REG_VAL !=
3000                       offsetof(struct tsb_config, tsb_reg_val)) ||
3001                      (TSB_CONFIG_MAP_VADDR !=
3002                       offsetof(struct tsb_config, tsb_map_vaddr)) ||
3003                      (TSB_CONFIG_MAP_PTE !=
3004                       offsetof(struct tsb_config, tsb_map_pte)));
3005 
3006         /* Attach to the address space of init_task.  On SMP we
3007          * do this in smp.c:smp_callin for other cpus.
3008          */
3009         mmgrab(&init_mm);
3010         current->active_mm = &init_mm;
3011 }
3012 

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