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Linux/arch/sparc/math-emu/math_32.c

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  1 /*
  2  * arch/sparc/math-emu/math.c
  3  *
  4  * Copyright (C) 1998 Peter Maydell (pmaydell@chiark.greenend.org.uk)
  5  * Copyright (C) 1997, 1999 Jakub Jelinek (jj@ultra.linux.cz)
  6  * Copyright (C) 1999 David S. Miller (davem@redhat.com)
  7  *
  8  * This is a good place to start if you're trying to understand the
  9  * emulation code, because it's pretty simple. What we do is
 10  * essentially analyse the instruction to work out what the operation
 11  * is and which registers are involved. We then execute the appropriate
 12  * FXXXX function. [The floating point queue introduces a minor wrinkle;
 13  * see below...]
 14  * The fxxxxx.c files each emulate a single insn. They look relatively
 15  * simple because the complexity is hidden away in an unholy tangle
 16  * of preprocessor macros.
 17  *
 18  * The first layer of macros is single.h, double.h, quad.h. Generally
 19  * these files define macros for working with floating point numbers
 20  * of the three IEEE formats. FP_ADD_D(R,A,B) is for adding doubles,
 21  * for instance. These macros are usually defined as calls to more
 22  * generic macros (in this case _FP_ADD(D,2,R,X,Y) where the number
 23  * of machine words required to store the given IEEE format is passed
 24  * as a parameter. [double.h and co check the number of bits in a word
 25  * and define FP_ADD_D & co appropriately].
 26  * The generic macros are defined in op-common.h. This is where all
 27  * the grotty stuff like handling NaNs is coded. To handle the possible
 28  * word sizes macros in op-common.h use macros like _FP_FRAC_SLL_##wc()
 29  * where wc is the 'number of machine words' parameter (here 2).
 30  * These are defined in the third layer of macros: op-1.h, op-2.h
 31  * and op-4.h. These handle operations on floating point numbers composed
 32  * of 1,2 and 4 machine words respectively. [For example, on sparc64
 33  * doubles are one machine word so macros in double.h eventually use
 34  * constructs in op-1.h, but on sparc32 they use op-2.h definitions.]
 35  * soft-fp.h is on the same level as op-common.h, and defines some
 36  * macros which are independent of both word size and FP format.
 37  * Finally, sfp-machine.h is the machine dependent part of the
 38  * code: it defines the word size and what type a word is. It also
 39  * defines how _FP_MUL_MEAT_t() maps to _FP_MUL_MEAT_n_* : op-n.h
 40  * provide several possible flavours of multiply algorithm, most
 41  * of which require that you supply some form of asm or C primitive to
 42  * do the actual multiply. (such asm primitives should be defined
 43  * in sfp-machine.h too). udivmodti4.c is the same sort of thing.
 44  *
 45  * There may be some errors here because I'm working from a
 46  * SPARC architecture manual V9, and what I really want is V8...
 47  * Also, the insns which can generate exceptions seem to be a
 48  * greater subset of the FPops than for V9 (for example, FCMPED
 49  * has to be emulated on V8). So I think I'm going to have
 50  * to emulate them all just to be on the safe side...
 51  *
 52  * Emulation routines originate from soft-fp package, which is
 53  * part of glibc and has appropriate copyrights in it (allegedly).
 54  *
 55  * NB: on sparc int == long == 4 bytes, long long == 8 bytes.
 56  * Most bits of the kernel seem to go for long rather than int,
 57  * so we follow that practice...
 58  */
 59 
 60 /* TODO:
 61  * fpsave() saves the FP queue but fpload() doesn't reload it.
 62  * Therefore when we context switch or change FPU ownership
 63  * we have to check to see if the queue had anything in it and
 64  * emulate it if it did. This is going to be a pain.
 65  */
 66 
 67 #include <linux/types.h>
 68 #include <linux/sched.h>
 69 #include <linux/mm.h>
 70 #include <linux/perf_event.h>
 71 #include <asm/uaccess.h>
 72 
 73 #include "sfp-util_32.h"
 74 #include <math-emu/soft-fp.h>
 75 #include <math-emu/single.h>
 76 #include <math-emu/double.h>
 77 #include <math-emu/quad.h>
 78 
 79 #define FLOATFUNC(x) extern int x(void *,void *,void *)
 80 
 81 /* The Vn labels indicate what version of the SPARC architecture gas thinks
 82  * each insn is. This is from the binutils source :->
 83  */
 84 /* quadword instructions */
 85 #define FSQRTQ  0x02b           /* v8 */
 86 #define FADDQ   0x043           /* v8 */
 87 #define FSUBQ   0x047           /* v8 */
 88 #define FMULQ   0x04b           /* v8 */
 89 #define FDIVQ   0x04f           /* v8 */
 90 #define FDMULQ  0x06e           /* v8 */
 91 #define FQTOS   0x0c7           /* v8 */
 92 #define FQTOD   0x0cb           /* v8 */
 93 #define FITOQ   0x0cc           /* v8 */
 94 #define FSTOQ   0x0cd           /* v8 */
 95 #define FDTOQ   0x0ce           /* v8 */
 96 #define FQTOI   0x0d3           /* v8 */
 97 #define FCMPQ   0x053           /* v8 */
 98 #define FCMPEQ  0x057           /* v8 */
 99 /* single/double instructions (subnormal): should all work */
100 #define FSQRTS  0x029           /* v7 */
101 #define FSQRTD  0x02a           /* v7 */
102 #define FADDS   0x041           /* v6 */
103 #define FADDD   0x042           /* v6 */
104 #define FSUBS   0x045           /* v6 */
105 #define FSUBD   0x046           /* v6 */
106 #define FMULS   0x049           /* v6 */
107 #define FMULD   0x04a           /* v6 */
108 #define FDIVS   0x04d           /* v6 */
109 #define FDIVD   0x04e           /* v6 */
110 #define FSMULD  0x069           /* v6 */
111 #define FDTOS   0x0c6           /* v6 */
112 #define FSTOD   0x0c9           /* v6 */
113 #define FSTOI   0x0d1           /* v6 */
114 #define FDTOI   0x0d2           /* v6 */
115 #define FABSS   0x009           /* v6 */
116 #define FCMPS   0x051           /* v6 */
117 #define FCMPES  0x055           /* v6 */
118 #define FCMPD   0x052           /* v6 */
119 #define FCMPED  0x056           /* v6 */
120 #define FMOVS   0x001           /* v6 */
121 #define FNEGS   0x005           /* v6 */
122 #define FITOS   0x0c4           /* v6 */
123 #define FITOD   0x0c8           /* v6 */
124 
125 #define FSR_TEM_SHIFT   23UL
126 #define FSR_TEM_MASK    (0x1fUL << FSR_TEM_SHIFT)
127 #define FSR_AEXC_SHIFT  5UL
128 #define FSR_AEXC_MASK   (0x1fUL << FSR_AEXC_SHIFT)
129 #define FSR_CEXC_SHIFT  0UL
130 #define FSR_CEXC_MASK   (0x1fUL << FSR_CEXC_SHIFT)
131 
132 static int do_one_mathemu(u32 insn, unsigned long *fsr, unsigned long *fregs);
133 
134 /* Unlike the Sparc64 version (which has a struct fpustate), we
135  * pass the taskstruct corresponding to the task which currently owns the
136  * FPU. This is partly because we don't have the fpustate struct and
137  * partly because the task owning the FPU isn't always current (as is
138  * the case for the Sparc64 port). This is probably SMP-related...
139  * This function returns 1 if all queued insns were emulated successfully.
140  * The test for unimplemented FPop in kernel mode has been moved into
141  * kernel/traps.c for simplicity.
142  */
143 int do_mathemu(struct pt_regs *regs, struct task_struct *fpt)
144 {
145         /* regs->pc isn't necessarily the PC at which the offending insn is sitting.
146          * The FPU maintains a queue of FPops which cause traps.
147          * When it hits an instruction that requires that the trapped op succeeded
148          * (usually because it reads a reg. that the trapped op wrote) then it
149          * causes this exception. We need to emulate all the insns on the queue
150          * and then allow the op to proceed.
151          * This code should also handle the case where the trap was precise,
152          * in which case the queue length is zero and regs->pc points at the
153          * single FPop to be emulated. (this case is untested, though :->)
154          * You'll need this case if you want to be able to emulate all FPops
155          * because the FPU either doesn't exist or has been software-disabled.
156          * [The UltraSPARC makes FP a precise trap; this isn't as stupid as it
157          * might sound because the Ultra does funky things with a superscalar
158          * architecture.]
159          */
160 
161         /* You wouldn't believe how often I typed 'ftp' when I meant 'fpt' :-> */
162 
163         int i;
164         int retcode = 0;                               /* assume all succeed */
165         unsigned long insn;
166 
167         perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);
168 
169 #ifdef DEBUG_MATHEMU
170         printk("In do_mathemu()... pc is %08lx\n", regs->pc);
171         printk("fpqdepth is %ld\n", fpt->thread.fpqdepth);
172         for (i = 0; i < fpt->thread.fpqdepth; i++)
173                 printk("%d: %08lx at %08lx\n", i, fpt->thread.fpqueue[i].insn,
174                        (unsigned long)fpt->thread.fpqueue[i].insn_addr);
175 #endif
176 
177         if (fpt->thread.fpqdepth == 0) {                   /* no queue, guilty insn is at regs->pc */
178 #ifdef DEBUG_MATHEMU
179                 printk("precise trap at %08lx\n", regs->pc);
180 #endif
181                 if (!get_user(insn, (u32 __user *) regs->pc)) {
182                         retcode = do_one_mathemu(insn, &fpt->thread.fsr, fpt->thread.float_regs);
183                         if (retcode) {
184                                 /* in this case we need to fix up PC & nPC */
185                                 regs->pc = regs->npc;
186                                 regs->npc += 4;
187                         }
188                 }
189                 return retcode;
190         }
191 
192         /* Normal case: need to empty the queue... */
193         for (i = 0; i < fpt->thread.fpqdepth; i++) {
194                 retcode = do_one_mathemu(fpt->thread.fpqueue[i].insn, &(fpt->thread.fsr), fpt->thread.float_regs);
195                 if (!retcode)                               /* insn failed, no point doing any more */
196                         break;
197         }
198         /* Now empty the queue and clear the queue_not_empty flag */
199         if (retcode)
200                 fpt->thread.fsr &= ~(0x3000 | FSR_CEXC_MASK);
201         else
202                 fpt->thread.fsr &= ~0x3000;
203         fpt->thread.fpqdepth = 0;
204 
205         return retcode;
206 }
207 
208 /* All routines returning an exception to raise should detect
209  * such exceptions _before_ rounding to be consistent with
210  * the behavior of the hardware in the implemented cases
211  * (and thus with the recommendations in the V9 architecture
212  * manual).
213  *
214  * We return 0 if a SIGFPE should be sent, 1 otherwise.
215  */
216 static inline int record_exception(unsigned long *pfsr, int eflag)
217 {
218         unsigned long fsr = *pfsr;
219         int would_trap;
220 
221         /* Determine if this exception would have generated a trap. */
222         would_trap = (fsr & ((long)eflag << FSR_TEM_SHIFT)) != 0UL;
223 
224         /* If trapping, we only want to signal one bit. */
225         if (would_trap != 0) {
226                 eflag &= ((fsr & FSR_TEM_MASK) >> FSR_TEM_SHIFT);
227                 if ((eflag & (eflag - 1)) != 0) {
228                         if (eflag & FP_EX_INVALID)
229                                 eflag = FP_EX_INVALID;
230                         else if (eflag & FP_EX_OVERFLOW)
231                                 eflag = FP_EX_OVERFLOW;
232                         else if (eflag & FP_EX_UNDERFLOW)
233                                 eflag = FP_EX_UNDERFLOW;
234                         else if (eflag & FP_EX_DIVZERO)
235                                 eflag = FP_EX_DIVZERO;
236                         else if (eflag & FP_EX_INEXACT)
237                                 eflag = FP_EX_INEXACT;
238                 }
239         }
240 
241         /* Set CEXC, here is the rule:
242          *
243          *    In general all FPU ops will set one and only one
244          *    bit in the CEXC field, this is always the case
245          *    when the IEEE exception trap is enabled in TEM.
246          */
247         fsr &= ~(FSR_CEXC_MASK);
248         fsr |= ((long)eflag << FSR_CEXC_SHIFT);
249 
250         /* Set the AEXC field, rule is:
251          *
252          *    If a trap would not be generated, the
253          *    CEXC just generated is OR'd into the
254          *    existing value of AEXC.
255          */
256         if (would_trap == 0)
257                 fsr |= ((long)eflag << FSR_AEXC_SHIFT);
258 
259         /* If trapping, indicate fault trap type IEEE. */
260         if (would_trap != 0)
261                 fsr |= (1UL << 14);
262 
263         *pfsr = fsr;
264 
265         return (would_trap ? 0 : 1);
266 }
267 
268 typedef union {
269         u32 s;
270         u64 d;
271         u64 q[2];
272 } *argp;
273 
274 static int do_one_mathemu(u32 insn, unsigned long *pfsr, unsigned long *fregs)
275 {
276         /* Emulate the given insn, updating fsr and fregs appropriately. */
277         int type = 0;
278         /* r is rd, b is rs2 and a is rs1. The *u arg tells
279            whether the argument should be packed/unpacked (0 - do not unpack/pack, 1 - unpack/pack)
280            non-u args tells the size of the argument (0 - no argument, 1 - single, 2 - double, 3 - quad */
281 #define TYPE(dummy, r, ru, b, bu, a, au) type = (au << 2) | (a << 0) | (bu << 5) | (b << 3) | (ru << 8) | (r << 6)
282         int freg;
283         argp rs1 = NULL, rs2 = NULL, rd = NULL;
284         FP_DECL_EX;
285         FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR);
286         FP_DECL_D(DA); FP_DECL_D(DB); FP_DECL_D(DR);
287         FP_DECL_Q(QA); FP_DECL_Q(QB); FP_DECL_Q(QR);
288         int IR;
289         long fsr;
290 
291 #ifdef DEBUG_MATHEMU
292         printk("In do_mathemu(), emulating %08lx\n", insn);
293 #endif
294 
295         if ((insn & 0xc1f80000) == 0x81a00000)  /* FPOP1 */ {
296                 switch ((insn >> 5) & 0x1ff) {
297                 case FSQRTQ: TYPE(3,3,1,3,1,0,0); break;
298                 case FADDQ:
299                 case FSUBQ:
300                 case FMULQ:
301                 case FDIVQ: TYPE(3,3,1,3,1,3,1); break;
302                 case FDMULQ: TYPE(3,3,1,2,1,2,1); break;
303                 case FQTOS: TYPE(3,1,1,3,1,0,0); break;
304                 case FQTOD: TYPE(3,2,1,3,1,0,0); break;
305                 case FITOQ: TYPE(3,3,1,1,0,0,0); break;
306                 case FSTOQ: TYPE(3,3,1,1,1,0,0); break;
307                 case FDTOQ: TYPE(3,3,1,2,1,0,0); break;
308                 case FQTOI: TYPE(3,1,0,3,1,0,0); break;
309                 case FSQRTS: TYPE(2,1,1,1,1,0,0); break;
310                 case FSQRTD: TYPE(2,2,1,2,1,0,0); break;
311                 case FADDD:
312                 case FSUBD:
313                 case FMULD:
314                 case FDIVD: TYPE(2,2,1,2,1,2,1); break;
315                 case FADDS:
316                 case FSUBS:
317                 case FMULS:
318                 case FDIVS: TYPE(2,1,1,1,1,1,1); break;
319                 case FSMULD: TYPE(2,2,1,1,1,1,1); break;
320                 case FDTOS: TYPE(2,1,1,2,1,0,0); break;
321                 case FSTOD: TYPE(2,2,1,1,1,0,0); break;
322                 case FSTOI: TYPE(2,1,0,1,1,0,0); break;
323                 case FDTOI: TYPE(2,1,0,2,1,0,0); break;
324                 case FITOS: TYPE(2,1,1,1,0,0,0); break;
325                 case FITOD: TYPE(2,2,1,1,0,0,0); break;
326                 case FMOVS:
327                 case FABSS:
328                 case FNEGS: TYPE(2,1,0,1,0,0,0); break;
329                 }
330         } else if ((insn & 0xc1f80000) == 0x81a80000)   /* FPOP2 */ {
331                 switch ((insn >> 5) & 0x1ff) {
332                 case FCMPS: TYPE(3,0,0,1,1,1,1); break;
333                 case FCMPES: TYPE(3,0,0,1,1,1,1); break;
334                 case FCMPD: TYPE(3,0,0,2,1,2,1); break;
335                 case FCMPED: TYPE(3,0,0,2,1,2,1); break;
336                 case FCMPQ: TYPE(3,0,0,3,1,3,1); break;
337                 case FCMPEQ: TYPE(3,0,0,3,1,3,1); break;
338                 }
339         }
340 
341         if (!type) {    /* oops, didn't recognise that FPop */
342 #ifdef DEBUG_MATHEMU
343                 printk("attempt to emulate unrecognised FPop!\n");
344 #endif
345                 return 0;
346         }
347 
348         /* Decode the registers to be used */
349         freg = (*pfsr >> 14) & 0xf;
350 
351         *pfsr &= ~0x1c000;                              /* clear the traptype bits */
352         
353         freg = ((insn >> 14) & 0x1f);
354         switch (type & 0x3) {                           /* is rs1 single, double or quad? */
355         case 3:
356                 if (freg & 3) {                         /* quadwords must have bits 4&5 of the */
357                                                         /* encoded reg. number set to zero. */
358                         *pfsr |= (6 << 14);
359                         return 0;                       /* simulate invalid_fp_register exception */
360                 }
361         /* fall through */
362         case 2:
363                 if (freg & 1) {                         /* doublewords must have bit 5 zeroed */
364                         *pfsr |= (6 << 14);
365                         return 0;
366                 }
367         }
368         rs1 = (argp)&fregs[freg];
369         switch (type & 0x7) {
370         case 7: FP_UNPACK_QP (QA, rs1); break;
371         case 6: FP_UNPACK_DP (DA, rs1); break;
372         case 5: FP_UNPACK_SP (SA, rs1); break;
373         }
374         freg = (insn & 0x1f);
375         switch ((type >> 3) & 0x3) {                    /* same again for rs2 */
376         case 3:
377                 if (freg & 3) {                         /* quadwords must have bits 4&5 of the */
378                                                         /* encoded reg. number set to zero. */
379                         *pfsr |= (6 << 14);
380                         return 0;                       /* simulate invalid_fp_register exception */
381                 }
382         /* fall through */
383         case 2:
384                 if (freg & 1) {                         /* doublewords must have bit 5 zeroed */
385                         *pfsr |= (6 << 14);
386                         return 0;
387                 }
388         }
389         rs2 = (argp)&fregs[freg];
390         switch ((type >> 3) & 0x7) {
391         case 7: FP_UNPACK_QP (QB, rs2); break;
392         case 6: FP_UNPACK_DP (DB, rs2); break;
393         case 5: FP_UNPACK_SP (SB, rs2); break;
394         }
395         freg = ((insn >> 25) & 0x1f);
396         switch ((type >> 6) & 0x3) {                    /* and finally rd. This one's a bit different */
397         case 0:                                         /* dest is fcc. (this must be FCMPQ or FCMPEQ) */
398                 if (freg) {                             /* V8 has only one set of condition codes, so */
399                                                         /* anything but 0 in the rd field is an error */
400                         *pfsr |= (6 << 14);             /* (should probably flag as invalid opcode */
401                         return 0;                       /* but SIGFPE will do :-> ) */
402                 }
403                 break;
404         case 3:
405                 if (freg & 3) {                         /* quadwords must have bits 4&5 of the */
406                                                         /* encoded reg. number set to zero. */
407                         *pfsr |= (6 << 14);
408                         return 0;                       /* simulate invalid_fp_register exception */
409                 }
410         /* fall through */
411         case 2:
412                 if (freg & 1) {                         /* doublewords must have bit 5 zeroed */
413                         *pfsr |= (6 << 14);
414                         return 0;
415                 }
416         /* fall through */
417         case 1:
418                 rd = (void *)&fregs[freg];
419                 break;
420         }
421 #ifdef DEBUG_MATHEMU
422         printk("executing insn...\n");
423 #endif
424         /* do the Right Thing */
425         switch ((insn >> 5) & 0x1ff) {
426         /* + */
427         case FADDS: FP_ADD_S (SR, SA, SB); break;
428         case FADDD: FP_ADD_D (DR, DA, DB); break;
429         case FADDQ: FP_ADD_Q (QR, QA, QB); break;
430         /* - */
431         case FSUBS: FP_SUB_S (SR, SA, SB); break;
432         case FSUBD: FP_SUB_D (DR, DA, DB); break;
433         case FSUBQ: FP_SUB_Q (QR, QA, QB); break;
434         /* * */
435         case FMULS: FP_MUL_S (SR, SA, SB); break;
436         case FSMULD: FP_CONV (D, S, 2, 1, DA, SA);
437                      FP_CONV (D, S, 2, 1, DB, SB);
438         case FMULD: FP_MUL_D (DR, DA, DB); break;
439         case FDMULQ: FP_CONV (Q, D, 4, 2, QA, DA);
440                      FP_CONV (Q, D, 4, 2, QB, DB);
441         case FMULQ: FP_MUL_Q (QR, QA, QB); break;
442         /* / */
443         case FDIVS: FP_DIV_S (SR, SA, SB); break;
444         case FDIVD: FP_DIV_D (DR, DA, DB); break;
445         case FDIVQ: FP_DIV_Q (QR, QA, QB); break;
446         /* sqrt */
447         case FSQRTS: FP_SQRT_S (SR, SB); break;
448         case FSQRTD: FP_SQRT_D (DR, DB); break;
449         case FSQRTQ: FP_SQRT_Q (QR, QB); break;
450         /* mov */
451         case FMOVS: rd->s = rs2->s; break;
452         case FABSS: rd->s = rs2->s & 0x7fffffff; break;
453         case FNEGS: rd->s = rs2->s ^ 0x80000000; break;
454         /* float to int */
455         case FSTOI: FP_TO_INT_S (IR, SB, 32, 1); break;
456         case FDTOI: FP_TO_INT_D (IR, DB, 32, 1); break;
457         case FQTOI: FP_TO_INT_Q (IR, QB, 32, 1); break;
458         /* int to float */
459         case FITOS: IR = rs2->s; FP_FROM_INT_S (SR, IR, 32, int); break;
460         case FITOD: IR = rs2->s; FP_FROM_INT_D (DR, IR, 32, int); break;
461         case FITOQ: IR = rs2->s; FP_FROM_INT_Q (QR, IR, 32, int); break;
462         /* float to float */
463         case FSTOD: FP_CONV (D, S, 2, 1, DR, SB); break;
464         case FSTOQ: FP_CONV (Q, S, 4, 1, QR, SB); break;
465         case FDTOQ: FP_CONV (Q, D, 4, 2, QR, DB); break;
466         case FDTOS: FP_CONV (S, D, 1, 2, SR, DB); break;
467         case FQTOS: FP_CONV (S, Q, 1, 4, SR, QB); break;
468         case FQTOD: FP_CONV (D, Q, 2, 4, DR, QB); break;
469         /* comparison */
470         case FCMPS:
471         case FCMPES:
472                 FP_CMP_S(IR, SB, SA, 3);
473                 if (IR == 3 &&
474                     (((insn >> 5) & 0x1ff) == FCMPES ||
475                      FP_ISSIGNAN_S(SA) ||
476                      FP_ISSIGNAN_S(SB)))
477                         FP_SET_EXCEPTION (FP_EX_INVALID);
478                 break;
479         case FCMPD:
480         case FCMPED:
481                 FP_CMP_D(IR, DB, DA, 3);
482                 if (IR == 3 &&
483                     (((insn >> 5) & 0x1ff) == FCMPED ||
484                      FP_ISSIGNAN_D(DA) ||
485                      FP_ISSIGNAN_D(DB)))
486                         FP_SET_EXCEPTION (FP_EX_INVALID);
487                 break;
488         case FCMPQ:
489         case FCMPEQ:
490                 FP_CMP_Q(IR, QB, QA, 3);
491                 if (IR == 3 &&
492                     (((insn >> 5) & 0x1ff) == FCMPEQ ||
493                      FP_ISSIGNAN_Q(QA) ||
494                      FP_ISSIGNAN_Q(QB)))
495                         FP_SET_EXCEPTION (FP_EX_INVALID);
496         }
497         if (!FP_INHIBIT_RESULTS) {
498                 switch ((type >> 6) & 0x7) {
499                 case 0: fsr = *pfsr;
500                         if (IR == -1) IR = 2;
501                         /* fcc is always fcc0 */
502                         fsr &= ~0xc00; fsr |= (IR << 10);
503                         *pfsr = fsr;
504                         break;
505                 case 1: rd->s = IR; break;
506                 case 5: FP_PACK_SP (rd, SR); break;
507                 case 6: FP_PACK_DP (rd, DR); break;
508                 case 7: FP_PACK_QP (rd, QR); break;
509                 }
510         }
511         if (_fex == 0)
512                 return 1;                               /* success! */
513         return record_exception(pfsr, _fex);
514 }
515 

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