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Linux/arch/sparc/mm/init_64.c

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  1 /*
  2  *  arch/sparc64/mm/init.c
  3  *
  4  *  Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
  5  *  Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
  6  */
  7  
  8 #include <linux/module.h>
  9 #include <linux/kernel.h>
 10 #include <linux/sched.h>
 11 #include <linux/string.h>
 12 #include <linux/init.h>
 13 #include <linux/bootmem.h>
 14 #include <linux/mm.h>
 15 #include <linux/hugetlb.h>
 16 #include <linux/initrd.h>
 17 #include <linux/swap.h>
 18 #include <linux/pagemap.h>
 19 #include <linux/poison.h>
 20 #include <linux/fs.h>
 21 #include <linux/seq_file.h>
 22 #include <linux/kprobes.h>
 23 #include <linux/cache.h>
 24 #include <linux/sort.h>
 25 #include <linux/percpu.h>
 26 #include <linux/memblock.h>
 27 #include <linux/mmzone.h>
 28 #include <linux/gfp.h>
 29 
 30 #include <asm/head.h>
 31 #include <asm/page.h>
 32 #include <asm/pgalloc.h>
 33 #include <asm/pgtable.h>
 34 #include <asm/oplib.h>
 35 #include <asm/iommu.h>
 36 #include <asm/io.h>
 37 #include <asm/uaccess.h>
 38 #include <asm/mmu_context.h>
 39 #include <asm/tlbflush.h>
 40 #include <asm/dma.h>
 41 #include <asm/starfire.h>
 42 #include <asm/tlb.h>
 43 #include <asm/spitfire.h>
 44 #include <asm/sections.h>
 45 #include <asm/tsb.h>
 46 #include <asm/hypervisor.h>
 47 #include <asm/prom.h>
 48 #include <asm/mdesc.h>
 49 #include <asm/cpudata.h>
 50 #include <asm/irq.h>
 51 
 52 #include "init_64.h"
 53 
 54 unsigned long kern_linear_pte_xor[4] __read_mostly;
 55 
 56 /* A bitmap, two bits for every 256MB of physical memory.  These two
 57  * bits determine what page size we use for kernel linear
 58  * translations.  They form an index into kern_linear_pte_xor[].  The
 59  * value in the indexed slot is XOR'd with the TLB miss virtual
 60  * address to form the resulting TTE.  The mapping is:
 61  *
 62  *      0       ==>     4MB
 63  *      1       ==>     256MB
 64  *      2       ==>     2GB
 65  *      3       ==>     16GB
 66  *
 67  * All sun4v chips support 256MB pages.  Only SPARC-T4 and later
 68  * support 2GB pages, and hopefully future cpus will support the 16GB
 69  * pages as well.  For slots 2 and 3, we encode a 256MB TTE xor there
 70  * if these larger page sizes are not supported by the cpu.
 71  *
 72  * It would be nice to determine this from the machine description
 73  * 'cpu' properties, but we need to have this table setup before the
 74  * MDESC is initialized.
 75  */
 76 unsigned long kpte_linear_bitmap[KPTE_BITMAP_BYTES / sizeof(unsigned long)];
 77 
 78 #ifndef CONFIG_DEBUG_PAGEALLOC
 79 /* A special kernel TSB for 4MB, 256MB, 2GB and 16GB linear mappings.
 80  * Space is allocated for this right after the trap table in
 81  * arch/sparc64/kernel/head.S
 82  */
 83 extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
 84 #endif
 85 
 86 static unsigned long cpu_pgsz_mask;
 87 
 88 #define MAX_BANKS       32
 89 
 90 static struct linux_prom64_registers pavail[MAX_BANKS];
 91 static int pavail_ents;
 92 
 93 static int cmp_p64(const void *a, const void *b)
 94 {
 95         const struct linux_prom64_registers *x = a, *y = b;
 96 
 97         if (x->phys_addr > y->phys_addr)
 98                 return 1;
 99         if (x->phys_addr < y->phys_addr)
100                 return -1;
101         return 0;
102 }
103 
104 static void __init read_obp_memory(const char *property,
105                                    struct linux_prom64_registers *regs,
106                                    int *num_ents)
107 {
108         phandle node = prom_finddevice("/memory");
109         int prop_size = prom_getproplen(node, property);
110         int ents, ret, i;
111 
112         ents = prop_size / sizeof(struct linux_prom64_registers);
113         if (ents > MAX_BANKS) {
114                 prom_printf("The machine has more %s property entries than "
115                             "this kernel can support (%d).\n",
116                             property, MAX_BANKS);
117                 prom_halt();
118         }
119 
120         ret = prom_getproperty(node, property, (char *) regs, prop_size);
121         if (ret == -1) {
122                 prom_printf("Couldn't get %s property from /memory.\n",
123                                 property);
124                 prom_halt();
125         }
126 
127         /* Sanitize what we got from the firmware, by page aligning
128          * everything.
129          */
130         for (i = 0; i < ents; i++) {
131                 unsigned long base, size;
132 
133                 base = regs[i].phys_addr;
134                 size = regs[i].reg_size;
135 
136                 size &= PAGE_MASK;
137                 if (base & ~PAGE_MASK) {
138                         unsigned long new_base = PAGE_ALIGN(base);
139 
140                         size -= new_base - base;
141                         if ((long) size < 0L)
142                                 size = 0UL;
143                         base = new_base;
144                 }
145                 if (size == 0UL) {
146                         /* If it is empty, simply get rid of it.
147                          * This simplifies the logic of the other
148                          * functions that process these arrays.
149                          */
150                         memmove(&regs[i], &regs[i + 1],
151                                 (ents - i - 1) * sizeof(regs[0]));
152                         i--;
153                         ents--;
154                         continue;
155                 }
156                 regs[i].phys_addr = base;
157                 regs[i].reg_size = size;
158         }
159 
160         *num_ents = ents;
161 
162         sort(regs, ents, sizeof(struct linux_prom64_registers),
163              cmp_p64, NULL);
164 }
165 
166 unsigned long sparc64_valid_addr_bitmap[VALID_ADDR_BITMAP_BYTES /
167                                         sizeof(unsigned long)];
168 EXPORT_SYMBOL(sparc64_valid_addr_bitmap);
169 
170 /* Kernel physical address base and size in bytes.  */
171 unsigned long kern_base __read_mostly;
172 unsigned long kern_size __read_mostly;
173 
174 /* Initial ramdisk setup */
175 extern unsigned long sparc_ramdisk_image64;
176 extern unsigned int sparc_ramdisk_image;
177 extern unsigned int sparc_ramdisk_size;
178 
179 struct page *mem_map_zero __read_mostly;
180 EXPORT_SYMBOL(mem_map_zero);
181 
182 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
183 
184 unsigned long sparc64_kern_pri_context __read_mostly;
185 unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
186 unsigned long sparc64_kern_sec_context __read_mostly;
187 
188 int num_kernel_image_mappings;
189 
190 #ifdef CONFIG_DEBUG_DCFLUSH
191 atomic_t dcpage_flushes = ATOMIC_INIT(0);
192 #ifdef CONFIG_SMP
193 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
194 #endif
195 #endif
196 
197 inline void flush_dcache_page_impl(struct page *page)
198 {
199         BUG_ON(tlb_type == hypervisor);
200 #ifdef CONFIG_DEBUG_DCFLUSH
201         atomic_inc(&dcpage_flushes);
202 #endif
203 
204 #ifdef DCACHE_ALIASING_POSSIBLE
205         __flush_dcache_page(page_address(page),
206                             ((tlb_type == spitfire) &&
207                              page_mapping(page) != NULL));
208 #else
209         if (page_mapping(page) != NULL &&
210             tlb_type == spitfire)
211                 __flush_icache_page(__pa(page_address(page)));
212 #endif
213 }
214 
215 #define PG_dcache_dirty         PG_arch_1
216 #define PG_dcache_cpu_shift     32UL
217 #define PG_dcache_cpu_mask      \
218         ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
219 
220 #define dcache_dirty_cpu(page) \
221         (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
222 
223 static inline void set_dcache_dirty(struct page *page, int this_cpu)
224 {
225         unsigned long mask = this_cpu;
226         unsigned long non_cpu_bits;
227 
228         non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
229         mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
230 
231         __asm__ __volatile__("1:\n\t"
232                              "ldx       [%2], %%g7\n\t"
233                              "and       %%g7, %1, %%g1\n\t"
234                              "or        %%g1, %0, %%g1\n\t"
235                              "casx      [%2], %%g7, %%g1\n\t"
236                              "cmp       %%g7, %%g1\n\t"
237                              "bne,pn    %%xcc, 1b\n\t"
238                              " nop"
239                              : /* no outputs */
240                              : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
241                              : "g1", "g7");
242 }
243 
244 static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
245 {
246         unsigned long mask = (1UL << PG_dcache_dirty);
247 
248         __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
249                              "1:\n\t"
250                              "ldx       [%2], %%g7\n\t"
251                              "srlx      %%g7, %4, %%g1\n\t"
252                              "and       %%g1, %3, %%g1\n\t"
253                              "cmp       %%g1, %0\n\t"
254                              "bne,pn    %%icc, 2f\n\t"
255                              " andn     %%g7, %1, %%g1\n\t"
256                              "casx      [%2], %%g7, %%g1\n\t"
257                              "cmp       %%g7, %%g1\n\t"
258                              "bne,pn    %%xcc, 1b\n\t"
259                              " nop\n"
260                              "2:"
261                              : /* no outputs */
262                              : "r" (cpu), "r" (mask), "r" (&page->flags),
263                                "i" (PG_dcache_cpu_mask),
264                                "i" (PG_dcache_cpu_shift)
265                              : "g1", "g7");
266 }
267 
268 static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
269 {
270         unsigned long tsb_addr = (unsigned long) ent;
271 
272         if (tlb_type == cheetah_plus || tlb_type == hypervisor)
273                 tsb_addr = __pa(tsb_addr);
274 
275         __tsb_insert(tsb_addr, tag, pte);
276 }
277 
278 unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
279 
280 static void flush_dcache(unsigned long pfn)
281 {
282         struct page *page;
283 
284         page = pfn_to_page(pfn);
285         if (page) {
286                 unsigned long pg_flags;
287 
288                 pg_flags = page->flags;
289                 if (pg_flags & (1UL << PG_dcache_dirty)) {
290                         int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
291                                    PG_dcache_cpu_mask);
292                         int this_cpu = get_cpu();
293 
294                         /* This is just to optimize away some function calls
295                          * in the SMP case.
296                          */
297                         if (cpu == this_cpu)
298                                 flush_dcache_page_impl(page);
299                         else
300                                 smp_flush_dcache_page_impl(page, cpu);
301 
302                         clear_dcache_dirty_cpu(page, cpu);
303 
304                         put_cpu();
305                 }
306         }
307 }
308 
309 /* mm->context.lock must be held */
310 static void __update_mmu_tsb_insert(struct mm_struct *mm, unsigned long tsb_index,
311                                     unsigned long tsb_hash_shift, unsigned long address,
312                                     unsigned long tte)
313 {
314         struct tsb *tsb = mm->context.tsb_block[tsb_index].tsb;
315         unsigned long tag;
316 
317         if (unlikely(!tsb))
318                 return;
319 
320         tsb += ((address >> tsb_hash_shift) &
321                 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
322         tag = (address >> 22UL);
323         tsb_insert(tsb, tag, tte);
324 }
325 
326 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
327 static inline bool is_hugetlb_pte(pte_t pte)
328 {
329         if ((tlb_type == hypervisor &&
330              (pte_val(pte) & _PAGE_SZALL_4V) == _PAGE_SZHUGE_4V) ||
331             (tlb_type != hypervisor &&
332              (pte_val(pte) & _PAGE_SZALL_4U) == _PAGE_SZHUGE_4U))
333                 return true;
334         return false;
335 }
336 #endif
337 
338 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
339 {
340         struct mm_struct *mm;
341         unsigned long flags;
342         pte_t pte = *ptep;
343 
344         if (tlb_type != hypervisor) {
345                 unsigned long pfn = pte_pfn(pte);
346 
347                 if (pfn_valid(pfn))
348                         flush_dcache(pfn);
349         }
350 
351         mm = vma->vm_mm;
352 
353         spin_lock_irqsave(&mm->context.lock, flags);
354 
355 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
356         if (mm->context.huge_pte_count && is_hugetlb_pte(pte))
357                 __update_mmu_tsb_insert(mm, MM_TSB_HUGE, HPAGE_SHIFT,
358                                         address, pte_val(pte));
359         else
360 #endif
361                 __update_mmu_tsb_insert(mm, MM_TSB_BASE, PAGE_SHIFT,
362                                         address, pte_val(pte));
363 
364         spin_unlock_irqrestore(&mm->context.lock, flags);
365 }
366 
367 void flush_dcache_page(struct page *page)
368 {
369         struct address_space *mapping;
370         int this_cpu;
371 
372         if (tlb_type == hypervisor)
373                 return;
374 
375         /* Do not bother with the expensive D-cache flush if it
376          * is merely the zero page.  The 'bigcore' testcase in GDB
377          * causes this case to run millions of times.
378          */
379         if (page == ZERO_PAGE(0))
380                 return;
381 
382         this_cpu = get_cpu();
383 
384         mapping = page_mapping(page);
385         if (mapping && !mapping_mapped(mapping)) {
386                 int dirty = test_bit(PG_dcache_dirty, &page->flags);
387                 if (dirty) {
388                         int dirty_cpu = dcache_dirty_cpu(page);
389 
390                         if (dirty_cpu == this_cpu)
391                                 goto out;
392                         smp_flush_dcache_page_impl(page, dirty_cpu);
393                 }
394                 set_dcache_dirty(page, this_cpu);
395         } else {
396                 /* We could delay the flush for the !page_mapping
397                  * case too.  But that case is for exec env/arg
398                  * pages and those are %99 certainly going to get
399                  * faulted into the tlb (and thus flushed) anyways.
400                  */
401                 flush_dcache_page_impl(page);
402         }
403 
404 out:
405         put_cpu();
406 }
407 EXPORT_SYMBOL(flush_dcache_page);
408 
409 void __kprobes flush_icache_range(unsigned long start, unsigned long end)
410 {
411         /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
412         if (tlb_type == spitfire) {
413                 unsigned long kaddr;
414 
415                 /* This code only runs on Spitfire cpus so this is
416                  * why we can assume _PAGE_PADDR_4U.
417                  */
418                 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) {
419                         unsigned long paddr, mask = _PAGE_PADDR_4U;
420 
421                         if (kaddr >= PAGE_OFFSET)
422                                 paddr = kaddr & mask;
423                         else {
424                                 pgd_t *pgdp = pgd_offset_k(kaddr);
425                                 pud_t *pudp = pud_offset(pgdp, kaddr);
426                                 pmd_t *pmdp = pmd_offset(pudp, kaddr);
427                                 pte_t *ptep = pte_offset_kernel(pmdp, kaddr);
428 
429                                 paddr = pte_val(*ptep) & mask;
430                         }
431                         __flush_icache_page(paddr);
432                 }
433         }
434 }
435 EXPORT_SYMBOL(flush_icache_range);
436 
437 void mmu_info(struct seq_file *m)
438 {
439         static const char *pgsz_strings[] = {
440                 "8K", "64K", "512K", "4MB", "32MB",
441                 "256MB", "2GB", "16GB",
442         };
443         int i, printed;
444 
445         if (tlb_type == cheetah)
446                 seq_printf(m, "MMU Type\t: Cheetah\n");
447         else if (tlb_type == cheetah_plus)
448                 seq_printf(m, "MMU Type\t: Cheetah+\n");
449         else if (tlb_type == spitfire)
450                 seq_printf(m, "MMU Type\t: Spitfire\n");
451         else if (tlb_type == hypervisor)
452                 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
453         else
454                 seq_printf(m, "MMU Type\t: ???\n");
455 
456         seq_printf(m, "MMU PGSZs\t: ");
457         printed = 0;
458         for (i = 0; i < ARRAY_SIZE(pgsz_strings); i++) {
459                 if (cpu_pgsz_mask & (1UL << i)) {
460                         seq_printf(m, "%s%s",
461                                    printed ? "," : "", pgsz_strings[i]);
462                         printed++;
463                 }
464         }
465         seq_putc(m, '\n');
466 
467 #ifdef CONFIG_DEBUG_DCFLUSH
468         seq_printf(m, "DCPageFlushes\t: %d\n",
469                    atomic_read(&dcpage_flushes));
470 #ifdef CONFIG_SMP
471         seq_printf(m, "DCPageFlushesXC\t: %d\n",
472                    atomic_read(&dcpage_flushes_xcall));
473 #endif /* CONFIG_SMP */
474 #endif /* CONFIG_DEBUG_DCFLUSH */
475 }
476 
477 struct linux_prom_translation prom_trans[512] __read_mostly;
478 unsigned int prom_trans_ents __read_mostly;
479 
480 unsigned long kern_locked_tte_data;
481 
482 /* The obp translations are saved based on 8k pagesize, since obp can
483  * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
484  * HI_OBP_ADDRESS range are handled in ktlb.S.
485  */
486 static inline int in_obp_range(unsigned long vaddr)
487 {
488         return (vaddr >= LOW_OBP_ADDRESS &&
489                 vaddr < HI_OBP_ADDRESS);
490 }
491 
492 static int cmp_ptrans(const void *a, const void *b)
493 {
494         const struct linux_prom_translation *x = a, *y = b;
495 
496         if (x->virt > y->virt)
497                 return 1;
498         if (x->virt < y->virt)
499                 return -1;
500         return 0;
501 }
502 
503 /* Read OBP translations property into 'prom_trans[]'.  */
504 static void __init read_obp_translations(void)
505 {
506         int n, node, ents, first, last, i;
507 
508         node = prom_finddevice("/virtual-memory");
509         n = prom_getproplen(node, "translations");
510         if (unlikely(n == 0 || n == -1)) {
511                 prom_printf("prom_mappings: Couldn't get size.\n");
512                 prom_halt();
513         }
514         if (unlikely(n > sizeof(prom_trans))) {
515                 prom_printf("prom_mappings: Size %d is too big.\n", n);
516                 prom_halt();
517         }
518 
519         if ((n = prom_getproperty(node, "translations",
520                                   (char *)&prom_trans[0],
521                                   sizeof(prom_trans))) == -1) {
522                 prom_printf("prom_mappings: Couldn't get property.\n");
523                 prom_halt();
524         }
525 
526         n = n / sizeof(struct linux_prom_translation);
527 
528         ents = n;
529 
530         sort(prom_trans, ents, sizeof(struct linux_prom_translation),
531              cmp_ptrans, NULL);
532 
533         /* Now kick out all the non-OBP entries.  */
534         for (i = 0; i < ents; i++) {
535                 if (in_obp_range(prom_trans[i].virt))
536                         break;
537         }
538         first = i;
539         for (; i < ents; i++) {
540                 if (!in_obp_range(prom_trans[i].virt))
541                         break;
542         }
543         last = i;
544 
545         for (i = 0; i < (last - first); i++) {
546                 struct linux_prom_translation *src = &prom_trans[i + first];
547                 struct linux_prom_translation *dest = &prom_trans[i];
548 
549                 *dest = *src;
550         }
551         for (; i < ents; i++) {
552                 struct linux_prom_translation *dest = &prom_trans[i];
553                 dest->virt = dest->size = dest->data = 0x0UL;
554         }
555 
556         prom_trans_ents = last - first;
557 
558         if (tlb_type == spitfire) {
559                 /* Clear diag TTE bits. */
560                 for (i = 0; i < prom_trans_ents; i++)
561                         prom_trans[i].data &= ~0x0003fe0000000000UL;
562         }
563 
564         /* Force execute bit on.  */
565         for (i = 0; i < prom_trans_ents; i++)
566                 prom_trans[i].data |= (tlb_type == hypervisor ?
567                                        _PAGE_EXEC_4V : _PAGE_EXEC_4U);
568 }
569 
570 static void __init hypervisor_tlb_lock(unsigned long vaddr,
571                                        unsigned long pte,
572                                        unsigned long mmu)
573 {
574         unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu);
575 
576         if (ret != 0) {
577                 prom_printf("hypervisor_tlb_lock[%lx:%x:%lx:%lx]: "
578                             "errors with %lx\n", vaddr, 0, pte, mmu, ret);
579                 prom_halt();
580         }
581 }
582 
583 static unsigned long kern_large_tte(unsigned long paddr);
584 
585 static void __init remap_kernel(void)
586 {
587         unsigned long phys_page, tte_vaddr, tte_data;
588         int i, tlb_ent = sparc64_highest_locked_tlbent();
589 
590         tte_vaddr = (unsigned long) KERNBASE;
591         phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
592         tte_data = kern_large_tte(phys_page);
593 
594         kern_locked_tte_data = tte_data;
595 
596         /* Now lock us into the TLBs via Hypervisor or OBP. */
597         if (tlb_type == hypervisor) {
598                 for (i = 0; i < num_kernel_image_mappings; i++) {
599                         hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
600                         hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
601                         tte_vaddr += 0x400000;
602                         tte_data += 0x400000;
603                 }
604         } else {
605                 for (i = 0; i < num_kernel_image_mappings; i++) {
606                         prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr);
607                         prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr);
608                         tte_vaddr += 0x400000;
609                         tte_data += 0x400000;
610                 }
611                 sparc64_highest_unlocked_tlb_ent = tlb_ent - i;
612         }
613         if (tlb_type == cheetah_plus) {
614                 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
615                                             CTX_CHEETAH_PLUS_NUC);
616                 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
617                 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
618         }
619 }
620 
621 
622 static void __init inherit_prom_mappings(void)
623 {
624         /* Now fixup OBP's idea about where we really are mapped. */
625         printk("Remapping the kernel... ");
626         remap_kernel();
627         printk("done.\n");
628 }
629 
630 void prom_world(int enter)
631 {
632         if (!enter)
633                 set_fs(get_fs());
634 
635         __asm__ __volatile__("flushw");
636 }
637 
638 void __flush_dcache_range(unsigned long start, unsigned long end)
639 {
640         unsigned long va;
641 
642         if (tlb_type == spitfire) {
643                 int n = 0;
644 
645                 for (va = start; va < end; va += 32) {
646                         spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
647                         if (++n >= 512)
648                                 break;
649                 }
650         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
651                 start = __pa(start);
652                 end = __pa(end);
653                 for (va = start; va < end; va += 32)
654                         __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
655                                              "membar #Sync"
656                                              : /* no outputs */
657                                              : "r" (va),
658                                                "i" (ASI_DCACHE_INVALIDATE));
659         }
660 }
661 EXPORT_SYMBOL(__flush_dcache_range);
662 
663 /* get_new_mmu_context() uses "cache + 1".  */
664 DEFINE_SPINLOCK(ctx_alloc_lock);
665 unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
666 #define MAX_CTX_NR      (1UL << CTX_NR_BITS)
667 #define CTX_BMAP_SLOTS  BITS_TO_LONGS(MAX_CTX_NR)
668 DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR);
669 
670 /* Caller does TLB context flushing on local CPU if necessary.
671  * The caller also ensures that CTX_VALID(mm->context) is false.
672  *
673  * We must be careful about boundary cases so that we never
674  * let the user have CTX 0 (nucleus) or we ever use a CTX
675  * version of zero (and thus NO_CONTEXT would not be caught
676  * by version mis-match tests in mmu_context.h).
677  *
678  * Always invoked with interrupts disabled.
679  */
680 void get_new_mmu_context(struct mm_struct *mm)
681 {
682         unsigned long ctx, new_ctx;
683         unsigned long orig_pgsz_bits;
684         int new_version;
685 
686         spin_lock(&ctx_alloc_lock);
687         orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
688         ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
689         new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
690         new_version = 0;
691         if (new_ctx >= (1 << CTX_NR_BITS)) {
692                 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
693                 if (new_ctx >= ctx) {
694                         int i;
695                         new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
696                                 CTX_FIRST_VERSION;
697                         if (new_ctx == 1)
698                                 new_ctx = CTX_FIRST_VERSION;
699 
700                         /* Don't call memset, for 16 entries that's just
701                          * plain silly...
702                          */
703                         mmu_context_bmap[0] = 3;
704                         mmu_context_bmap[1] = 0;
705                         mmu_context_bmap[2] = 0;
706                         mmu_context_bmap[3] = 0;
707                         for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
708                                 mmu_context_bmap[i + 0] = 0;
709                                 mmu_context_bmap[i + 1] = 0;
710                                 mmu_context_bmap[i + 2] = 0;
711                                 mmu_context_bmap[i + 3] = 0;
712                         }
713                         new_version = 1;
714                         goto out;
715                 }
716         }
717         mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
718         new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
719 out:
720         tlb_context_cache = new_ctx;
721         mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
722         spin_unlock(&ctx_alloc_lock);
723 
724         if (unlikely(new_version))
725                 smp_new_mmu_context_version();
726 }
727 
728 static int numa_enabled = 1;
729 static int numa_debug;
730 
731 static int __init early_numa(char *p)
732 {
733         if (!p)
734                 return 0;
735 
736         if (strstr(p, "off"))
737                 numa_enabled = 0;
738 
739         if (strstr(p, "debug"))
740                 numa_debug = 1;
741 
742         return 0;
743 }
744 early_param("numa", early_numa);
745 
746 #define numadbg(f, a...) \
747 do {    if (numa_debug) \
748                 printk(KERN_INFO f, ## a); \
749 } while (0)
750 
751 static void __init find_ramdisk(unsigned long phys_base)
752 {
753 #ifdef CONFIG_BLK_DEV_INITRD
754         if (sparc_ramdisk_image || sparc_ramdisk_image64) {
755                 unsigned long ramdisk_image;
756 
757                 /* Older versions of the bootloader only supported a
758                  * 32-bit physical address for the ramdisk image
759                  * location, stored at sparc_ramdisk_image.  Newer
760                  * SILO versions set sparc_ramdisk_image to zero and
761                  * provide a full 64-bit physical address at
762                  * sparc_ramdisk_image64.
763                  */
764                 ramdisk_image = sparc_ramdisk_image;
765                 if (!ramdisk_image)
766                         ramdisk_image = sparc_ramdisk_image64;
767 
768                 /* Another bootloader quirk.  The bootloader normalizes
769                  * the physical address to KERNBASE, so we have to
770                  * factor that back out and add in the lowest valid
771                  * physical page address to get the true physical address.
772                  */
773                 ramdisk_image -= KERNBASE;
774                 ramdisk_image += phys_base;
775 
776                 numadbg("Found ramdisk at physical address 0x%lx, size %u\n",
777                         ramdisk_image, sparc_ramdisk_size);
778 
779                 initrd_start = ramdisk_image;
780                 initrd_end = ramdisk_image + sparc_ramdisk_size;
781 
782                 memblock_reserve(initrd_start, sparc_ramdisk_size);
783 
784                 initrd_start += PAGE_OFFSET;
785                 initrd_end += PAGE_OFFSET;
786         }
787 #endif
788 }
789 
790 struct node_mem_mask {
791         unsigned long mask;
792         unsigned long val;
793 };
794 static struct node_mem_mask node_masks[MAX_NUMNODES];
795 static int num_node_masks;
796 
797 int numa_cpu_lookup_table[NR_CPUS];
798 cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES];
799 
800 #ifdef CONFIG_NEED_MULTIPLE_NODES
801 
802 struct mdesc_mblock {
803         u64     base;
804         u64     size;
805         u64     offset; /* RA-to-PA */
806 };
807 static struct mdesc_mblock *mblocks;
808 static int num_mblocks;
809 
810 static unsigned long ra_to_pa(unsigned long addr)
811 {
812         int i;
813 
814         for (i = 0; i < num_mblocks; i++) {
815                 struct mdesc_mblock *m = &mblocks[i];
816 
817                 if (addr >= m->base &&
818                     addr < (m->base + m->size)) {
819                         addr += m->offset;
820                         break;
821                 }
822         }
823         return addr;
824 }
825 
826 static int find_node(unsigned long addr)
827 {
828         int i;
829 
830         addr = ra_to_pa(addr);
831         for (i = 0; i < num_node_masks; i++) {
832                 struct node_mem_mask *p = &node_masks[i];
833 
834                 if ((addr & p->mask) == p->val)
835                         return i;
836         }
837         return -1;
838 }
839 
840 static u64 memblock_nid_range(u64 start, u64 end, int *nid)
841 {
842         *nid = find_node(start);
843         start += PAGE_SIZE;
844         while (start < end) {
845                 int n = find_node(start);
846 
847                 if (n != *nid)
848                         break;
849                 start += PAGE_SIZE;
850         }
851 
852         if (start > end)
853                 start = end;
854 
855         return start;
856 }
857 #endif
858 
859 /* This must be invoked after performing all of the necessary
860  * memblock_set_node() calls for 'nid'.  We need to be able to get
861  * correct data from get_pfn_range_for_nid().
862  */
863 static void __init allocate_node_data(int nid)
864 {
865         struct pglist_data *p;
866         unsigned long start_pfn, end_pfn;
867 #ifdef CONFIG_NEED_MULTIPLE_NODES
868         unsigned long paddr;
869 
870         paddr = memblock_alloc_try_nid(sizeof(struct pglist_data), SMP_CACHE_BYTES, nid);
871         if (!paddr) {
872                 prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid);
873                 prom_halt();
874         }
875         NODE_DATA(nid) = __va(paddr);
876         memset(NODE_DATA(nid), 0, sizeof(struct pglist_data));
877 
878         NODE_DATA(nid)->node_id = nid;
879 #endif
880 
881         p = NODE_DATA(nid);
882 
883         get_pfn_range_for_nid(nid, &start_pfn, &end_pfn);
884         p->node_start_pfn = start_pfn;
885         p->node_spanned_pages = end_pfn - start_pfn;
886 }
887 
888 static void init_node_masks_nonnuma(void)
889 {
890         int i;
891 
892         numadbg("Initializing tables for non-numa.\n");
893 
894         node_masks[0].mask = node_masks[0].val = 0;
895         num_node_masks = 1;
896 
897         for (i = 0; i < NR_CPUS; i++)
898                 numa_cpu_lookup_table[i] = 0;
899 
900         cpumask_setall(&numa_cpumask_lookup_table[0]);
901 }
902 
903 #ifdef CONFIG_NEED_MULTIPLE_NODES
904 struct pglist_data *node_data[MAX_NUMNODES];
905 
906 EXPORT_SYMBOL(numa_cpu_lookup_table);
907 EXPORT_SYMBOL(numa_cpumask_lookup_table);
908 EXPORT_SYMBOL(node_data);
909 
910 struct mdesc_mlgroup {
911         u64     node;
912         u64     latency;
913         u64     match;
914         u64     mask;
915 };
916 static struct mdesc_mlgroup *mlgroups;
917 static int num_mlgroups;
918 
919 static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio,
920                                    u32 cfg_handle)
921 {
922         u64 arc;
923 
924         mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) {
925                 u64 target = mdesc_arc_target(md, arc);
926                 const u64 *val;
927 
928                 val = mdesc_get_property(md, target,
929                                          "cfg-handle", NULL);
930                 if (val && *val == cfg_handle)
931                         return 0;
932         }
933         return -ENODEV;
934 }
935 
936 static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp,
937                                     u32 cfg_handle)
938 {
939         u64 arc, candidate, best_latency = ~(u64)0;
940 
941         candidate = MDESC_NODE_NULL;
942         mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
943                 u64 target = mdesc_arc_target(md, arc);
944                 const char *name = mdesc_node_name(md, target);
945                 const u64 *val;
946 
947                 if (strcmp(name, "pio-latency-group"))
948                         continue;
949 
950                 val = mdesc_get_property(md, target, "latency", NULL);
951                 if (!val)
952                         continue;
953 
954                 if (*val < best_latency) {
955                         candidate = target;
956                         best_latency = *val;
957                 }
958         }
959 
960         if (candidate == MDESC_NODE_NULL)
961                 return -ENODEV;
962 
963         return scan_pio_for_cfg_handle(md, candidate, cfg_handle);
964 }
965 
966 int of_node_to_nid(struct device_node *dp)
967 {
968         const struct linux_prom64_registers *regs;
969         struct mdesc_handle *md;
970         u32 cfg_handle;
971         int count, nid;
972         u64 grp;
973 
974         /* This is the right thing to do on currently supported
975          * SUN4U NUMA platforms as well, as the PCI controller does
976          * not sit behind any particular memory controller.
977          */
978         if (!mlgroups)
979                 return -1;
980 
981         regs = of_get_property(dp, "reg", NULL);
982         if (!regs)
983                 return -1;
984 
985         cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff;
986 
987         md = mdesc_grab();
988 
989         count = 0;
990         nid = -1;
991         mdesc_for_each_node_by_name(md, grp, "group") {
992                 if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) {
993                         nid = count;
994                         break;
995                 }
996                 count++;
997         }
998 
999         mdesc_release(md);
1000 
1001         return nid;
1002 }
1003 
1004 static void __init add_node_ranges(void)
1005 {
1006         struct memblock_region *reg;
1007 
1008         for_each_memblock(memory, reg) {
1009                 unsigned long size = reg->size;
1010                 unsigned long start, end;
1011 
1012                 start = reg->base;
1013                 end = start + size;
1014                 while (start < end) {
1015                         unsigned long this_end;
1016                         int nid;
1017 
1018                         this_end = memblock_nid_range(start, end, &nid);
1019 
1020                         numadbg("Setting memblock NUMA node nid[%d] "
1021                                 "start[%lx] end[%lx]\n",
1022                                 nid, start, this_end);
1023 
1024                         memblock_set_node(start, this_end - start, nid);
1025                         start = this_end;
1026                 }
1027         }
1028 }
1029 
1030 static int __init grab_mlgroups(struct mdesc_handle *md)
1031 {
1032         unsigned long paddr;
1033         int count = 0;
1034         u64 node;
1035 
1036         mdesc_for_each_node_by_name(md, node, "memory-latency-group")
1037                 count++;
1038         if (!count)
1039                 return -ENOENT;
1040 
1041         paddr = memblock_alloc(count * sizeof(struct mdesc_mlgroup),
1042                           SMP_CACHE_BYTES);
1043         if (!paddr)
1044                 return -ENOMEM;
1045 
1046         mlgroups = __va(paddr);
1047         num_mlgroups = count;
1048 
1049         count = 0;
1050         mdesc_for_each_node_by_name(md, node, "memory-latency-group") {
1051                 struct mdesc_mlgroup *m = &mlgroups[count++];
1052                 const u64 *val;
1053 
1054                 m->node = node;
1055 
1056                 val = mdesc_get_property(md, node, "latency", NULL);
1057                 m->latency = *val;
1058                 val = mdesc_get_property(md, node, "address-match", NULL);
1059                 m->match = *val;
1060                 val = mdesc_get_property(md, node, "address-mask", NULL);
1061                 m->mask = *val;
1062 
1063                 numadbg("MLGROUP[%d]: node[%llx] latency[%llx] "
1064                         "match[%llx] mask[%llx]\n",
1065                         count - 1, m->node, m->latency, m->match, m->mask);
1066         }
1067 
1068         return 0;
1069 }
1070 
1071 static int __init grab_mblocks(struct mdesc_handle *md)
1072 {
1073         unsigned long paddr;
1074         int count = 0;
1075         u64 node;
1076 
1077         mdesc_for_each_node_by_name(md, node, "mblock")
1078                 count++;
1079         if (!count)
1080                 return -ENOENT;
1081 
1082         paddr = memblock_alloc(count * sizeof(struct mdesc_mblock),
1083                           SMP_CACHE_BYTES);
1084         if (!paddr)
1085                 return -ENOMEM;
1086 
1087         mblocks = __va(paddr);
1088         num_mblocks = count;
1089 
1090         count = 0;
1091         mdesc_for_each_node_by_name(md, node, "mblock") {
1092                 struct mdesc_mblock *m = &mblocks[count++];
1093                 const u64 *val;
1094 
1095                 val = mdesc_get_property(md, node, "base", NULL);
1096                 m->base = *val;
1097                 val = mdesc_get_property(md, node, "size", NULL);
1098                 m->size = *val;
1099                 val = mdesc_get_property(md, node,
1100                                          "address-congruence-offset", NULL);
1101 
1102                 /* The address-congruence-offset property is optional.
1103                  * Explicity zero it be identifty this.
1104                  */
1105                 if (val)
1106                         m->offset = *val;
1107                 else
1108                         m->offset = 0UL;
1109 
1110                 numadbg("MBLOCK[%d]: base[%llx] size[%llx] offset[%llx]\n",
1111                         count - 1, m->base, m->size, m->offset);
1112         }
1113 
1114         return 0;
1115 }
1116 
1117 static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md,
1118                                                u64 grp, cpumask_t *mask)
1119 {
1120         u64 arc;
1121 
1122         cpumask_clear(mask);
1123 
1124         mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) {
1125                 u64 target = mdesc_arc_target(md, arc);
1126                 const char *name = mdesc_node_name(md, target);
1127                 const u64 *id;
1128 
1129                 if (strcmp(name, "cpu"))
1130                         continue;
1131                 id = mdesc_get_property(md, target, "id", NULL);
1132                 if (*id < nr_cpu_ids)
1133                         cpumask_set_cpu(*id, mask);
1134         }
1135 }
1136 
1137 static struct mdesc_mlgroup * __init find_mlgroup(u64 node)
1138 {
1139         int i;
1140 
1141         for (i = 0; i < num_mlgroups; i++) {
1142                 struct mdesc_mlgroup *m = &mlgroups[i];
1143                 if (m->node == node)
1144                         return m;
1145         }
1146         return NULL;
1147 }
1148 
1149 static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp,
1150                                       int index)
1151 {
1152         struct mdesc_mlgroup *candidate = NULL;
1153         u64 arc, best_latency = ~(u64)0;
1154         struct node_mem_mask *n;
1155 
1156         mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1157                 u64 target = mdesc_arc_target(md, arc);
1158                 struct mdesc_mlgroup *m = find_mlgroup(target);
1159                 if (!m)
1160                         continue;
1161                 if (m->latency < best_latency) {
1162                         candidate = m;
1163                         best_latency = m->latency;
1164                 }
1165         }
1166         if (!candidate)
1167                 return -ENOENT;
1168 
1169         if (num_node_masks != index) {
1170                 printk(KERN_ERR "Inconsistent NUMA state, "
1171                        "index[%d] != num_node_masks[%d]\n",
1172                        index, num_node_masks);
1173                 return -EINVAL;
1174         }
1175 
1176         n = &node_masks[num_node_masks++];
1177 
1178         n->mask = candidate->mask;
1179         n->val = candidate->match;
1180 
1181         numadbg("NUMA NODE[%d]: mask[%lx] val[%lx] (latency[%llx])\n",
1182                 index, n->mask, n->val, candidate->latency);
1183 
1184         return 0;
1185 }
1186 
1187 static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp,
1188                                          int index)
1189 {
1190         cpumask_t mask;
1191         int cpu;
1192 
1193         numa_parse_mdesc_group_cpus(md, grp, &mask);
1194 
1195         for_each_cpu(cpu, &mask)
1196                 numa_cpu_lookup_table[cpu] = index;
1197         cpumask_copy(&numa_cpumask_lookup_table[index], &mask);
1198 
1199         if (numa_debug) {
1200                 printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index);
1201                 for_each_cpu(cpu, &mask)
1202                         printk("%d ", cpu);
1203                 printk("]\n");
1204         }
1205 
1206         return numa_attach_mlgroup(md, grp, index);
1207 }
1208 
1209 static int __init numa_parse_mdesc(void)
1210 {
1211         struct mdesc_handle *md = mdesc_grab();
1212         int i, err, count;
1213         u64 node;
1214 
1215         node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups");
1216         if (node == MDESC_NODE_NULL) {
1217                 mdesc_release(md);
1218                 return -ENOENT;
1219         }
1220 
1221         err = grab_mblocks(md);
1222         if (err < 0)
1223                 goto out;
1224 
1225         err = grab_mlgroups(md);
1226         if (err < 0)
1227                 goto out;
1228 
1229         count = 0;
1230         mdesc_for_each_node_by_name(md, node, "group") {
1231                 err = numa_parse_mdesc_group(md, node, count);
1232                 if (err < 0)
1233                         break;
1234                 count++;
1235         }
1236 
1237         add_node_ranges();
1238 
1239         for (i = 0; i < num_node_masks; i++) {
1240                 allocate_node_data(i);
1241                 node_set_online(i);
1242         }
1243 
1244         err = 0;
1245 out:
1246         mdesc_release(md);
1247         return err;
1248 }
1249 
1250 static int __init numa_parse_jbus(void)
1251 {
1252         unsigned long cpu, index;
1253 
1254         /* NUMA node id is encoded in bits 36 and higher, and there is
1255          * a 1-to-1 mapping from CPU ID to NUMA node ID.
1256          */
1257         index = 0;
1258         for_each_present_cpu(cpu) {
1259                 numa_cpu_lookup_table[cpu] = index;
1260                 cpumask_copy(&numa_cpumask_lookup_table[index], cpumask_of(cpu));
1261                 node_masks[index].mask = ~((1UL << 36UL) - 1UL);
1262                 node_masks[index].val = cpu << 36UL;
1263 
1264                 index++;
1265         }
1266         num_node_masks = index;
1267 
1268         add_node_ranges();
1269 
1270         for (index = 0; index < num_node_masks; index++) {
1271                 allocate_node_data(index);
1272                 node_set_online(index);
1273         }
1274 
1275         return 0;
1276 }
1277 
1278 static int __init numa_parse_sun4u(void)
1279 {
1280         if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1281                 unsigned long ver;
1282 
1283                 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
1284                 if ((ver >> 32UL) == __JALAPENO_ID ||
1285                     (ver >> 32UL) == __SERRANO_ID)
1286                         return numa_parse_jbus();
1287         }
1288         return -1;
1289 }
1290 
1291 static int __init bootmem_init_numa(void)
1292 {
1293         int err = -1;
1294 
1295         numadbg("bootmem_init_numa()\n");
1296 
1297         if (numa_enabled) {
1298                 if (tlb_type == hypervisor)
1299                         err = numa_parse_mdesc();
1300                 else
1301                         err = numa_parse_sun4u();
1302         }
1303         return err;
1304 }
1305 
1306 #else
1307 
1308 static int bootmem_init_numa(void)
1309 {
1310         return -1;
1311 }
1312 
1313 #endif
1314 
1315 static void __init bootmem_init_nonnuma(void)
1316 {
1317         unsigned long top_of_ram = memblock_end_of_DRAM();
1318         unsigned long total_ram = memblock_phys_mem_size();
1319 
1320         numadbg("bootmem_init_nonnuma()\n");
1321 
1322         printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n",
1323                top_of_ram, total_ram);
1324         printk(KERN_INFO "Memory hole size: %ldMB\n",
1325                (top_of_ram - total_ram) >> 20);
1326 
1327         init_node_masks_nonnuma();
1328         memblock_set_node(0, (phys_addr_t)ULLONG_MAX, 0);
1329         allocate_node_data(0);
1330         node_set_online(0);
1331 }
1332 
1333 static unsigned long __init bootmem_init(unsigned long phys_base)
1334 {
1335         unsigned long end_pfn;
1336 
1337         end_pfn = memblock_end_of_DRAM() >> PAGE_SHIFT;
1338         max_pfn = max_low_pfn = end_pfn;
1339         min_low_pfn = (phys_base >> PAGE_SHIFT);
1340 
1341         if (bootmem_init_numa() < 0)
1342                 bootmem_init_nonnuma();
1343 
1344         /* Dump memblock with node info. */
1345         memblock_dump_all();
1346 
1347         /* XXX cpu notifier XXX */
1348 
1349         sparse_memory_present_with_active_regions(MAX_NUMNODES);
1350         sparse_init();
1351 
1352         return end_pfn;
1353 }
1354 
1355 static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1356 static int pall_ents __initdata;
1357 
1358 #ifdef CONFIG_DEBUG_PAGEALLOC
1359 static unsigned long __ref kernel_map_range(unsigned long pstart,
1360                                             unsigned long pend, pgprot_t prot)
1361 {
1362         unsigned long vstart = PAGE_OFFSET + pstart;
1363         unsigned long vend = PAGE_OFFSET + pend;
1364         unsigned long alloc_bytes = 0UL;
1365 
1366         if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
1367                 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1368                             vstart, vend);
1369                 prom_halt();
1370         }
1371 
1372         while (vstart < vend) {
1373                 unsigned long this_end, paddr = __pa(vstart);
1374                 pgd_t *pgd = pgd_offset_k(vstart);
1375                 pud_t *pud;
1376                 pmd_t *pmd;
1377                 pte_t *pte;
1378 
1379                 pud = pud_offset(pgd, vstart);
1380                 if (pud_none(*pud)) {
1381                         pmd_t *new;
1382 
1383                         new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1384                         alloc_bytes += PAGE_SIZE;
1385                         pud_populate(&init_mm, pud, new);
1386                 }
1387 
1388                 pmd = pmd_offset(pud, vstart);
1389                 if (!pmd_present(*pmd)) {
1390                         pte_t *new;
1391 
1392                         new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1393                         alloc_bytes += PAGE_SIZE;
1394                         pmd_populate_kernel(&init_mm, pmd, new);
1395                 }
1396 
1397                 pte = pte_offset_kernel(pmd, vstart);
1398                 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1399                 if (this_end > vend)
1400                         this_end = vend;
1401 
1402                 while (vstart < this_end) {
1403                         pte_val(*pte) = (paddr | pgprot_val(prot));
1404 
1405                         vstart += PAGE_SIZE;
1406                         paddr += PAGE_SIZE;
1407                         pte++;
1408                 }
1409         }
1410 
1411         return alloc_bytes;
1412 }
1413 
1414 extern unsigned int kvmap_linear_patch[1];
1415 #endif /* CONFIG_DEBUG_PAGEALLOC */
1416 
1417 static void __init kpte_set_val(unsigned long index, unsigned long val)
1418 {
1419         unsigned long *ptr = kpte_linear_bitmap;
1420 
1421         val <<= ((index % (BITS_PER_LONG / 2)) * 2);
1422         ptr += (index / (BITS_PER_LONG / 2));
1423 
1424         *ptr |= val;
1425 }
1426 
1427 static const unsigned long kpte_shift_min = 28; /* 256MB */
1428 static const unsigned long kpte_shift_max = 34; /* 16GB */
1429 static const unsigned long kpte_shift_incr = 3;
1430 
1431 static unsigned long kpte_mark_using_shift(unsigned long start, unsigned long end,
1432                                            unsigned long shift)
1433 {
1434         unsigned long size = (1UL << shift);
1435         unsigned long mask = (size - 1UL);
1436         unsigned long remains = end - start;
1437         unsigned long val;
1438 
1439         if (remains < size || (start & mask))
1440                 return start;
1441 
1442         /* VAL maps:
1443          *
1444          *      shift 28 --> kern_linear_pte_xor index 1
1445          *      shift 31 --> kern_linear_pte_xor index 2
1446          *      shift 34 --> kern_linear_pte_xor index 3
1447          */
1448         val = ((shift - kpte_shift_min) / kpte_shift_incr) + 1;
1449 
1450         remains &= ~mask;
1451         if (shift != kpte_shift_max)
1452                 remains = size;
1453 
1454         while (remains) {
1455                 unsigned long index = start >> kpte_shift_min;
1456 
1457                 kpte_set_val(index, val);
1458 
1459                 start += 1UL << kpte_shift_min;
1460                 remains -= 1UL << kpte_shift_min;
1461         }
1462 
1463         return start;
1464 }
1465 
1466 static void __init mark_kpte_bitmap(unsigned long start, unsigned long end)
1467 {
1468         unsigned long smallest_size, smallest_mask;
1469         unsigned long s;
1470 
1471         smallest_size = (1UL << kpte_shift_min);
1472         smallest_mask = (smallest_size - 1UL);
1473 
1474         while (start < end) {
1475                 unsigned long orig_start = start;
1476 
1477                 for (s = kpte_shift_max; s >= kpte_shift_min; s -= kpte_shift_incr) {
1478                         start = kpte_mark_using_shift(start, end, s);
1479 
1480                         if (start != orig_start)
1481                                 break;
1482                 }
1483 
1484                 if (start == orig_start)
1485                         start = (start + smallest_size) & ~smallest_mask;
1486         }
1487 }
1488 
1489 static void __init init_kpte_bitmap(void)
1490 {
1491         unsigned long i;
1492 
1493         for (i = 0; i < pall_ents; i++) {
1494                 unsigned long phys_start, phys_end;
1495 
1496                 phys_start = pall[i].phys_addr;
1497                 phys_end = phys_start + pall[i].reg_size;
1498 
1499                 mark_kpte_bitmap(phys_start, phys_end);
1500         }
1501 }
1502 
1503 static void __init kernel_physical_mapping_init(void)
1504 {
1505 #ifdef CONFIG_DEBUG_PAGEALLOC
1506         unsigned long i, mem_alloced = 0UL;
1507 
1508         for (i = 0; i < pall_ents; i++) {
1509                 unsigned long phys_start, phys_end;
1510 
1511                 phys_start = pall[i].phys_addr;
1512                 phys_end = phys_start + pall[i].reg_size;
1513 
1514                 mem_alloced += kernel_map_range(phys_start, phys_end,
1515                                                 PAGE_KERNEL);
1516         }
1517 
1518         printk("Allocated %ld bytes for kernel page tables.\n",
1519                mem_alloced);
1520 
1521         kvmap_linear_patch[0] = 0x01000000; /* nop */
1522         flushi(&kvmap_linear_patch[0]);
1523 
1524         __flush_tlb_all();
1525 #endif
1526 }
1527 
1528 #ifdef CONFIG_DEBUG_PAGEALLOC
1529 void kernel_map_pages(struct page *page, int numpages, int enable)
1530 {
1531         unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1532         unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1533 
1534         kernel_map_range(phys_start, phys_end,
1535                          (enable ? PAGE_KERNEL : __pgprot(0)));
1536 
1537         flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1538                                PAGE_OFFSET + phys_end);
1539 
1540         /* we should perform an IPI and flush all tlbs,
1541          * but that can deadlock->flush only current cpu.
1542          */
1543         __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1544                                  PAGE_OFFSET + phys_end);
1545 }
1546 #endif
1547 
1548 unsigned long __init find_ecache_flush_span(unsigned long size)
1549 {
1550         int i;
1551 
1552         for (i = 0; i < pavail_ents; i++) {
1553                 if (pavail[i].reg_size >= size)
1554                         return pavail[i].phys_addr;
1555         }
1556 
1557         return ~0UL;
1558 }
1559 
1560 static void __init tsb_phys_patch(void)
1561 {
1562         struct tsb_ldquad_phys_patch_entry *pquad;
1563         struct tsb_phys_patch_entry *p;
1564 
1565         pquad = &__tsb_ldquad_phys_patch;
1566         while (pquad < &__tsb_ldquad_phys_patch_end) {
1567                 unsigned long addr = pquad->addr;
1568 
1569                 if (tlb_type == hypervisor)
1570                         *(unsigned int *) addr = pquad->sun4v_insn;
1571                 else
1572                         *(unsigned int *) addr = pquad->sun4u_insn;
1573                 wmb();
1574                 __asm__ __volatile__("flush     %0"
1575                                      : /* no outputs */
1576                                      : "r" (addr));
1577 
1578                 pquad++;
1579         }
1580 
1581         p = &__tsb_phys_patch;
1582         while (p < &__tsb_phys_patch_end) {
1583                 unsigned long addr = p->addr;
1584 
1585                 *(unsigned int *) addr = p->insn;
1586                 wmb();
1587                 __asm__ __volatile__("flush     %0"
1588                                      : /* no outputs */
1589                                      : "r" (addr));
1590 
1591                 p++;
1592         }
1593 }
1594 
1595 /* Don't mark as init, we give this to the Hypervisor.  */
1596 #ifndef CONFIG_DEBUG_PAGEALLOC
1597 #define NUM_KTSB_DESCR  2
1598 #else
1599 #define NUM_KTSB_DESCR  1
1600 #endif
1601 static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
1602 extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
1603 
1604 static void patch_one_ktsb_phys(unsigned int *start, unsigned int *end, unsigned long pa)
1605 {
1606         pa >>= KTSB_PHYS_SHIFT;
1607 
1608         while (start < end) {
1609                 unsigned int *ia = (unsigned int *)(unsigned long)*start;
1610 
1611                 ia[0] = (ia[0] & ~0x3fffff) | (pa >> 10);
1612                 __asm__ __volatile__("flush     %0" : : "r" (ia));
1613 
1614                 ia[1] = (ia[1] & ~0x3ff) | (pa & 0x3ff);
1615                 __asm__ __volatile__("flush     %0" : : "r" (ia + 1));
1616 
1617                 start++;
1618         }
1619 }
1620 
1621 static void ktsb_phys_patch(void)
1622 {
1623         extern unsigned int __swapper_tsb_phys_patch;
1624         extern unsigned int __swapper_tsb_phys_patch_end;
1625         unsigned long ktsb_pa;
1626 
1627         ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1628         patch_one_ktsb_phys(&__swapper_tsb_phys_patch,
1629                             &__swapper_tsb_phys_patch_end, ktsb_pa);
1630 #ifndef CONFIG_DEBUG_PAGEALLOC
1631         {
1632         extern unsigned int __swapper_4m_tsb_phys_patch;
1633         extern unsigned int __swapper_4m_tsb_phys_patch_end;
1634         ktsb_pa = (kern_base +
1635                    ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1636         patch_one_ktsb_phys(&__swapper_4m_tsb_phys_patch,
1637                             &__swapper_4m_tsb_phys_patch_end, ktsb_pa);
1638         }
1639 #endif
1640 }
1641 
1642 static void __init sun4v_ktsb_init(void)
1643 {
1644         unsigned long ktsb_pa;
1645 
1646         /* First KTSB for PAGE_SIZE mappings.  */
1647         ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1648 
1649         switch (PAGE_SIZE) {
1650         case 8 * 1024:
1651         default:
1652                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
1653                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
1654                 break;
1655 
1656         case 64 * 1024:
1657                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
1658                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
1659                 break;
1660 
1661         case 512 * 1024:
1662                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
1663                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
1664                 break;
1665 
1666         case 4 * 1024 * 1024:
1667                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
1668                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
1669                 break;
1670         }
1671 
1672         ktsb_descr[0].assoc = 1;
1673         ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
1674         ktsb_descr[0].ctx_idx = 0;
1675         ktsb_descr[0].tsb_base = ktsb_pa;
1676         ktsb_descr[0].resv = 0;
1677 
1678 #ifndef CONFIG_DEBUG_PAGEALLOC
1679         /* Second KTSB for 4MB/256MB/2GB/16GB mappings.  */
1680         ktsb_pa = (kern_base +
1681                    ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1682 
1683         ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
1684         ktsb_descr[1].pgsz_mask = ((HV_PGSZ_MASK_4MB |
1685                                     HV_PGSZ_MASK_256MB |
1686                                     HV_PGSZ_MASK_2GB |
1687                                     HV_PGSZ_MASK_16GB) &
1688                                    cpu_pgsz_mask);
1689         ktsb_descr[1].assoc = 1;
1690         ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
1691         ktsb_descr[1].ctx_idx = 0;
1692         ktsb_descr[1].tsb_base = ktsb_pa;
1693         ktsb_descr[1].resv = 0;
1694 #endif
1695 }
1696 
1697 void sun4v_ktsb_register(void)
1698 {
1699         unsigned long pa, ret;
1700 
1701         pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
1702 
1703         ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa);
1704         if (ret != 0) {
1705                 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
1706                             "errors with %lx\n", pa, ret);
1707                 prom_halt();
1708         }
1709 }
1710 
1711 static void __init sun4u_linear_pte_xor_finalize(void)
1712 {
1713 #ifndef CONFIG_DEBUG_PAGEALLOC
1714         /* This is where we would add Panther support for
1715          * 32MB and 256MB pages.
1716          */
1717 #endif
1718 }
1719 
1720 static void __init sun4v_linear_pte_xor_finalize(void)
1721 {
1722 #ifndef CONFIG_DEBUG_PAGEALLOC
1723         if (cpu_pgsz_mask & HV_PGSZ_MASK_256MB) {
1724                 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
1725                         0xfffff80000000000UL;
1726                 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1727                                            _PAGE_P_4V | _PAGE_W_4V);
1728         } else {
1729                 kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
1730         }
1731 
1732         if (cpu_pgsz_mask & HV_PGSZ_MASK_2GB) {
1733                 kern_linear_pte_xor[2] = (_PAGE_VALID | _PAGE_SZ2GB_4V) ^
1734                         0xfffff80000000000UL;
1735                 kern_linear_pte_xor[2] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1736                                            _PAGE_P_4V | _PAGE_W_4V);
1737         } else {
1738                 kern_linear_pte_xor[2] = kern_linear_pte_xor[1];
1739         }
1740 
1741         if (cpu_pgsz_mask & HV_PGSZ_MASK_16GB) {
1742                 kern_linear_pte_xor[3] = (_PAGE_VALID | _PAGE_SZ16GB_4V) ^
1743                         0xfffff80000000000UL;
1744                 kern_linear_pte_xor[3] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1745                                            _PAGE_P_4V | _PAGE_W_4V);
1746         } else {
1747                 kern_linear_pte_xor[3] = kern_linear_pte_xor[2];
1748         }
1749 #endif
1750 }
1751 
1752 /* paging_init() sets up the page tables */
1753 
1754 static unsigned long last_valid_pfn;
1755 pgd_t swapper_pg_dir[2048];
1756 
1757 static void sun4u_pgprot_init(void);
1758 static void sun4v_pgprot_init(void);
1759 
1760 void __init paging_init(void)
1761 {
1762         unsigned long end_pfn, shift, phys_base;
1763         unsigned long real_end, i;
1764         int node;
1765 
1766         /* These build time checkes make sure that the dcache_dirty_cpu()
1767          * page->flags usage will work.
1768          *
1769          * When a page gets marked as dcache-dirty, we store the
1770          * cpu number starting at bit 32 in the page->flags.  Also,
1771          * functions like clear_dcache_dirty_cpu use the cpu mask
1772          * in 13-bit signed-immediate instruction fields.
1773          */
1774 
1775         /*
1776          * Page flags must not reach into upper 32 bits that are used
1777          * for the cpu number
1778          */
1779         BUILD_BUG_ON(NR_PAGEFLAGS > 32);
1780 
1781         /*
1782          * The bit fields placed in the high range must not reach below
1783          * the 32 bit boundary. Otherwise we cannot place the cpu field
1784          * at the 32 bit boundary.
1785          */
1786         BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH +
1787                 ilog2(roundup_pow_of_two(NR_CPUS)) > 32);
1788 
1789         BUILD_BUG_ON(NR_CPUS > 4096);
1790 
1791         kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
1792         kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1793 
1794         /* Invalidate both kernel TSBs.  */
1795         memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
1796 #ifndef CONFIG_DEBUG_PAGEALLOC
1797         memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
1798 #endif
1799 
1800         if (tlb_type == hypervisor)
1801                 sun4v_pgprot_init();
1802         else
1803                 sun4u_pgprot_init();
1804 
1805         if (tlb_type == cheetah_plus ||
1806             tlb_type == hypervisor) {
1807                 tsb_phys_patch();
1808                 ktsb_phys_patch();
1809         }
1810 
1811         if (tlb_type == hypervisor)
1812                 sun4v_patch_tlb_handlers();
1813 
1814         /* Find available physical memory...
1815          *
1816          * Read it twice in order to work around a bug in openfirmware.
1817          * The call to grab this table itself can cause openfirmware to
1818          * allocate memory, which in turn can take away some space from
1819          * the list of available memory.  Reading it twice makes sure
1820          * we really do get the final value.
1821          */
1822         read_obp_translations();
1823         read_obp_memory("reg", &pall[0], &pall_ents);
1824         read_obp_memory("available", &pavail[0], &pavail_ents);
1825         read_obp_memory("available", &pavail[0], &pavail_ents);
1826 
1827         phys_base = 0xffffffffffffffffUL;
1828         for (i = 0; i < pavail_ents; i++) {
1829                 phys_base = min(phys_base, pavail[i].phys_addr);
1830                 memblock_add(pavail[i].phys_addr, pavail[i].reg_size);
1831         }
1832 
1833         memblock_reserve(kern_base, kern_size);
1834 
1835         find_ramdisk(phys_base);
1836 
1837         memblock_enforce_memory_limit(cmdline_memory_size);
1838 
1839         memblock_allow_resize();
1840         memblock_dump_all();
1841 
1842         set_bit(0, mmu_context_bmap);
1843 
1844         shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
1845 
1846         real_end = (unsigned long)_end;
1847         num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << 22);
1848         printk("Kernel: Using %d locked TLB entries for main kernel image.\n",
1849                num_kernel_image_mappings);
1850 
1851         /* Set kernel pgd to upper alias so physical page computations
1852          * work.
1853          */
1854         init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1855         
1856         memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir));
1857 
1858         /* Now can init the kernel/bad page tables. */
1859         pud_set(pud_offset(&swapper_pg_dir[0], 0),
1860                 swapper_low_pmd_dir + (shift / sizeof(pgd_t)));
1861         
1862         inherit_prom_mappings();
1863         
1864         init_kpte_bitmap();
1865 
1866         /* Ok, we can use our TLB miss and window trap handlers safely.  */
1867         setup_tba();
1868 
1869         __flush_tlb_all();
1870 
1871         prom_build_devicetree();
1872         of_populate_present_mask();
1873 #ifndef CONFIG_SMP
1874         of_fill_in_cpu_data();
1875 #endif
1876 
1877         if (tlb_type == hypervisor) {
1878                 sun4v_mdesc_init();
1879                 mdesc_populate_present_mask(cpu_all_mask);
1880 #ifndef CONFIG_SMP
1881                 mdesc_fill_in_cpu_data(cpu_all_mask);
1882 #endif
1883                 mdesc_get_page_sizes(cpu_all_mask, &cpu_pgsz_mask);
1884 
1885                 sun4v_linear_pte_xor_finalize();
1886 
1887                 sun4v_ktsb_init();
1888                 sun4v_ktsb_register();
1889         } else {
1890                 unsigned long impl, ver;
1891 
1892                 cpu_pgsz_mask = (HV_PGSZ_MASK_8K | HV_PGSZ_MASK_64K |
1893                                  HV_PGSZ_MASK_512K | HV_PGSZ_MASK_4MB);
1894 
1895                 __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
1896                 impl = ((ver >> 32) & 0xffff);
1897                 if (impl == PANTHER_IMPL)
1898                         cpu_pgsz_mask |= (HV_PGSZ_MASK_32MB |
1899                                           HV_PGSZ_MASK_256MB);
1900 
1901                 sun4u_linear_pte_xor_finalize();
1902         }
1903 
1904         /* Flush the TLBs and the 4M TSB so that the updated linear
1905          * pte XOR settings are realized for all mappings.
1906          */
1907         __flush_tlb_all();
1908 #ifndef CONFIG_DEBUG_PAGEALLOC
1909         memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
1910 #endif
1911         __flush_tlb_all();
1912 
1913         /* Setup bootmem... */
1914         last_valid_pfn = end_pfn = bootmem_init(phys_base);
1915 
1916         /* Once the OF device tree and MDESC have been setup, we know
1917          * the list of possible cpus.  Therefore we can allocate the
1918          * IRQ stacks.
1919          */
1920         for_each_possible_cpu(i) {
1921                 node = cpu_to_node(i);
1922 
1923                 softirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node),
1924                                                         THREAD_SIZE,
1925                                                         THREAD_SIZE, 0);
1926                 hardirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node),
1927                                                         THREAD_SIZE,
1928                                                         THREAD_SIZE, 0);
1929         }
1930 
1931         kernel_physical_mapping_init();
1932 
1933         {
1934                 unsigned long max_zone_pfns[MAX_NR_ZONES];
1935 
1936                 memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
1937 
1938                 max_zone_pfns[ZONE_NORMAL] = end_pfn;
1939 
1940                 free_area_init_nodes(max_zone_pfns);
1941         }
1942 
1943         printk("Booting Linux...\n");
1944 }
1945 
1946 int page_in_phys_avail(unsigned long paddr)
1947 {
1948         int i;
1949 
1950         paddr &= PAGE_MASK;
1951 
1952         for (i = 0; i < pavail_ents; i++) {
1953                 unsigned long start, end;
1954 
1955                 start = pavail[i].phys_addr;
1956                 end = start + pavail[i].reg_size;
1957 
1958                 if (paddr >= start && paddr < end)
1959                         return 1;
1960         }
1961         if (paddr >= kern_base && paddr < (kern_base + kern_size))
1962                 return 1;
1963 #ifdef CONFIG_BLK_DEV_INITRD
1964         if (paddr >= __pa(initrd_start) &&
1965             paddr < __pa(PAGE_ALIGN(initrd_end)))
1966                 return 1;
1967 #endif
1968 
1969         return 0;
1970 }
1971 
1972 static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata;
1973 static int pavail_rescan_ents __initdata;
1974 
1975 /* Certain OBP calls, such as fetching "available" properties, can
1976  * claim physical memory.  So, along with initializing the valid
1977  * address bitmap, what we do here is refetch the physical available
1978  * memory list again, and make sure it provides at least as much
1979  * memory as 'pavail' does.
1980  */
1981 static void __init setup_valid_addr_bitmap_from_pavail(unsigned long *bitmap)
1982 {
1983         int i;
1984 
1985         read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents);
1986 
1987         for (i = 0; i < pavail_ents; i++) {
1988                 unsigned long old_start, old_end;
1989 
1990                 old_start = pavail[i].phys_addr;
1991                 old_end = old_start + pavail[i].reg_size;
1992                 while (old_start < old_end) {
1993                         int n;
1994 
1995                         for (n = 0; n < pavail_rescan_ents; n++) {
1996                                 unsigned long new_start, new_end;
1997 
1998                                 new_start = pavail_rescan[n].phys_addr;
1999                                 new_end = new_start +
2000                                         pavail_rescan[n].reg_size;
2001 
2002                                 if (new_start <= old_start &&
2003                                     new_end >= (old_start + PAGE_SIZE)) {
2004                                         set_bit(old_start >> 22, bitmap);
2005                                         goto do_next_page;
2006                                 }
2007                         }
2008 
2009                         prom_printf("mem_init: Lost memory in pavail\n");
2010                         prom_printf("mem_init: OLD start[%lx] size[%lx]\n",
2011                                     pavail[i].phys_addr,
2012                                     pavail[i].reg_size);
2013                         prom_printf("mem_init: NEW start[%lx] size[%lx]\n",
2014                                     pavail_rescan[i].phys_addr,
2015                                     pavail_rescan[i].reg_size);
2016                         prom_printf("mem_init: Cannot continue, aborting.\n");
2017                         prom_halt();
2018 
2019                 do_next_page:
2020                         old_start += PAGE_SIZE;
2021                 }
2022         }
2023 }
2024 
2025 static void __init patch_tlb_miss_handler_bitmap(void)
2026 {
2027         extern unsigned int valid_addr_bitmap_insn[];
2028         extern unsigned int valid_addr_bitmap_patch[];
2029 
2030         valid_addr_bitmap_insn[1] = valid_addr_bitmap_patch[1];
2031         mb();
2032         valid_addr_bitmap_insn[0] = valid_addr_bitmap_patch[0];
2033         flushi(&valid_addr_bitmap_insn[0]);
2034 }
2035 
2036 static void __init register_page_bootmem_info(void)
2037 {
2038 #ifdef CONFIG_NEED_MULTIPLE_NODES
2039         int i;
2040 
2041         for_each_online_node(i)
2042                 if (NODE_DATA(i)->node_spanned_pages)
2043                         register_page_bootmem_info_node(NODE_DATA(i));
2044 #endif
2045 }
2046 void __init mem_init(void)
2047 {
2048         unsigned long addr, last;
2049 
2050         addr = PAGE_OFFSET + kern_base;
2051         last = PAGE_ALIGN(kern_size) + addr;
2052         while (addr < last) {
2053                 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
2054                 addr += PAGE_SIZE;
2055         }
2056 
2057         setup_valid_addr_bitmap_from_pavail(sparc64_valid_addr_bitmap);
2058         patch_tlb_miss_handler_bitmap();
2059 
2060         high_memory = __va(last_valid_pfn << PAGE_SHIFT);
2061 
2062         register_page_bootmem_info();
2063         free_all_bootmem();
2064 
2065         /*
2066          * Set up the zero page, mark it reserved, so that page count
2067          * is not manipulated when freeing the page from user ptes.
2068          */
2069         mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
2070         if (mem_map_zero == NULL) {
2071                 prom_printf("paging_init: Cannot alloc zero page.\n");
2072                 prom_halt();
2073         }
2074         mark_page_reserved(mem_map_zero);
2075 
2076         mem_init_print_info(NULL);
2077 
2078         if (tlb_type == cheetah || tlb_type == cheetah_plus)
2079                 cheetah_ecache_flush_init();
2080 }
2081 
2082 void free_initmem(void)
2083 {
2084         unsigned long addr, initend;
2085         int do_free = 1;
2086 
2087         /* If the physical memory maps were trimmed by kernel command
2088          * line options, don't even try freeing this initmem stuff up.
2089          * The kernel image could have been in the trimmed out region
2090          * and if so the freeing below will free invalid page structs.
2091          */
2092         if (cmdline_memory_size)
2093                 do_free = 0;
2094 
2095         /*
2096          * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
2097          */
2098         addr = PAGE_ALIGN((unsigned long)(__init_begin));
2099         initend = (unsigned long)(__init_end) & PAGE_MASK;
2100         for (; addr < initend; addr += PAGE_SIZE) {
2101                 unsigned long page;
2102 
2103                 page = (addr +
2104                         ((unsigned long) __va(kern_base)) -
2105                         ((unsigned long) KERNBASE));
2106                 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
2107 
2108                 if (do_free)
2109                         free_reserved_page(virt_to_page(page));
2110         }
2111 }
2112 
2113 #ifdef CONFIG_BLK_DEV_INITRD
2114 void free_initrd_mem(unsigned long start, unsigned long end)
2115 {
2116         free_reserved_area((void *)start, (void *)end, POISON_FREE_INITMEM,
2117                            "initrd");
2118 }
2119 #endif
2120 
2121 #define _PAGE_CACHE_4U  (_PAGE_CP_4U | _PAGE_CV_4U)
2122 #define _PAGE_CACHE_4V  (_PAGE_CP_4V | _PAGE_CV_4V)
2123 #define __DIRTY_BITS_4U  (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
2124 #define __DIRTY_BITS_4V  (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
2125 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
2126 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
2127 
2128 pgprot_t PAGE_KERNEL __read_mostly;
2129 EXPORT_SYMBOL(PAGE_KERNEL);
2130 
2131 pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
2132 pgprot_t PAGE_COPY __read_mostly;
2133 
2134 pgprot_t PAGE_SHARED __read_mostly;
2135 EXPORT_SYMBOL(PAGE_SHARED);
2136 
2137 unsigned long pg_iobits __read_mostly;
2138 
2139 unsigned long _PAGE_IE __read_mostly;
2140 EXPORT_SYMBOL(_PAGE_IE);
2141 
2142 unsigned long _PAGE_E __read_mostly;
2143 EXPORT_SYMBOL(_PAGE_E);
2144 
2145 unsigned long _PAGE_CACHE __read_mostly;
2146 EXPORT_SYMBOL(_PAGE_CACHE);
2147 
2148 #ifdef CONFIG_SPARSEMEM_VMEMMAP
2149 unsigned long vmemmap_table[VMEMMAP_SIZE];
2150 
2151 static long __meminitdata addr_start, addr_end;
2152 static int __meminitdata node_start;
2153 
2154 int __meminit vmemmap_populate(unsigned long vstart, unsigned long vend,
2155                                int node)
2156 {
2157         unsigned long phys_start = (vstart - VMEMMAP_BASE);
2158         unsigned long phys_end = (vend - VMEMMAP_BASE);
2159         unsigned long addr = phys_start & VMEMMAP_CHUNK_MASK;
2160         unsigned long end = VMEMMAP_ALIGN(phys_end);
2161         unsigned long pte_base;
2162 
2163         pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2164                     _PAGE_CP_4U | _PAGE_CV_4U |
2165                     _PAGE_P_4U | _PAGE_W_4U);
2166         if (tlb_type == hypervisor)
2167                 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2168                             _PAGE_CP_4V | _PAGE_CV_4V |
2169                             _PAGE_P_4V | _PAGE_W_4V);
2170 
2171         for (; addr < end; addr += VMEMMAP_CHUNK) {
2172                 unsigned long *vmem_pp =
2173                         vmemmap_table + (addr >> VMEMMAP_CHUNK_SHIFT);
2174                 void *block;
2175 
2176                 if (!(*vmem_pp & _PAGE_VALID)) {
2177                         block = vmemmap_alloc_block(1UL << 22, node);
2178                         if (!block)
2179                                 return -ENOMEM;
2180 
2181                         *vmem_pp = pte_base | __pa(block);
2182 
2183                         /* check to see if we have contiguous blocks */
2184                         if (addr_end != addr || node_start != node) {
2185                                 if (addr_start)
2186                                         printk(KERN_DEBUG " [%lx-%lx] on node %d\n",
2187                                                addr_start, addr_end-1, node_start);
2188                                 addr_start = addr;
2189                                 node_start = node;
2190                         }
2191                         addr_end = addr + VMEMMAP_CHUNK;
2192                 }
2193         }
2194         return 0;
2195 }
2196 
2197 void __meminit vmemmap_populate_print_last(void)
2198 {
2199         if (addr_start) {
2200                 printk(KERN_DEBUG " [%lx-%lx] on node %d\n",
2201                        addr_start, addr_end-1, node_start);
2202                 addr_start = 0;
2203                 addr_end = 0;
2204                 node_start = 0;
2205         }
2206 }
2207 
2208 void vmemmap_free(unsigned long start, unsigned long end)
2209 {
2210 }
2211 
2212 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
2213 
2214 static void prot_init_common(unsigned long page_none,
2215                              unsigned long page_shared,
2216                              unsigned long page_copy,
2217                              unsigned long page_readonly,
2218                              unsigned long page_exec_bit)
2219 {
2220         PAGE_COPY = __pgprot(page_copy);
2221         PAGE_SHARED = __pgprot(page_shared);
2222 
2223         protection_map[0x0] = __pgprot(page_none);
2224         protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
2225         protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
2226         protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
2227         protection_map[0x4] = __pgprot(page_readonly);
2228         protection_map[0x5] = __pgprot(page_readonly);
2229         protection_map[0x6] = __pgprot(page_copy);
2230         protection_map[0x7] = __pgprot(page_copy);
2231         protection_map[0x8] = __pgprot(page_none);
2232         protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
2233         protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
2234         protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
2235         protection_map[0xc] = __pgprot(page_readonly);
2236         protection_map[0xd] = __pgprot(page_readonly);
2237         protection_map[0xe] = __pgprot(page_shared);
2238         protection_map[0xf] = __pgprot(page_shared);
2239 }
2240 
2241 static void __init sun4u_pgprot_init(void)
2242 {
2243         unsigned long page_none, page_shared, page_copy, page_readonly;
2244         unsigned long page_exec_bit;
2245         int i;
2246 
2247         PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2248                                 _PAGE_CACHE_4U | _PAGE_P_4U |
2249                                 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2250                                 _PAGE_EXEC_4U);
2251         PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2252                                        _PAGE_CACHE_4U | _PAGE_P_4U |
2253                                        __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2254                                        _PAGE_EXEC_4U | _PAGE_L_4U);
2255 
2256         _PAGE_IE = _PAGE_IE_4U;
2257         _PAGE_E = _PAGE_E_4U;
2258         _PAGE_CACHE = _PAGE_CACHE_4U;
2259 
2260         pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
2261                      __ACCESS_BITS_4U | _PAGE_E_4U);
2262 
2263 #ifdef CONFIG_DEBUG_PAGEALLOC
2264         kern_linear_pte_xor[0] = _PAGE_VALID ^ 0xfffff80000000000UL;
2265 #else
2266         kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
2267                 0xfffff80000000000UL;
2268 #endif
2269         kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
2270                                    _PAGE_P_4U | _PAGE_W_4U);
2271 
2272         for (i = 1; i < 4; i++)
2273                 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
2274 
2275         _PAGE_ALL_SZ_BITS =  (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
2276                               _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
2277                               _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
2278 
2279 
2280         page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
2281         page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2282                        __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
2283         page_copy   = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2284                        __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2285         page_readonly   = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2286                            __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2287 
2288         page_exec_bit = _PAGE_EXEC_4U;
2289 
2290         prot_init_common(page_none, page_shared, page_copy, page_readonly,
2291                          page_exec_bit);
2292 }
2293 
2294 static void __init sun4v_pgprot_init(void)
2295 {
2296         unsigned long page_none, page_shared, page_copy, page_readonly;
2297         unsigned long page_exec_bit;
2298         int i;
2299 
2300         PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
2301                                 _PAGE_CACHE_4V | _PAGE_P_4V |
2302                                 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
2303                                 _PAGE_EXEC_4V);
2304         PAGE_KERNEL_LOCKED = PAGE_KERNEL;
2305 
2306         _PAGE_IE = _PAGE_IE_4V;
2307         _PAGE_E = _PAGE_E_4V;
2308         _PAGE_CACHE = _PAGE_CACHE_4V;
2309 
2310 #ifdef CONFIG_DEBUG_PAGEALLOC
2311         kern_linear_pte_xor[0] = _PAGE_VALID ^ 0xfffff80000000000UL;
2312 #else
2313         kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
2314                 0xfffff80000000000UL;
2315 #endif
2316         kern_linear_pte_xor[0] |= (_PAGE_CP_4V | _PAGE_CV_4V |
2317                                    _PAGE_P_4V | _PAGE_W_4V);
2318 
2319         for (i = 1; i < 4; i++)
2320                 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
2321 
2322         pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
2323                      __ACCESS_BITS_4V | _PAGE_E_4V);
2324 
2325         _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
2326                              _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
2327                              _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
2328                              _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
2329 
2330         page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | _PAGE_CACHE_4V;
2331         page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2332                        __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
2333         page_copy   = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2334                        __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2335         page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2336                          __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2337 
2338         page_exec_bit = _PAGE_EXEC_4V;
2339 
2340         prot_init_common(page_none, page_shared, page_copy, page_readonly,
2341                          page_exec_bit);
2342 }
2343 
2344 unsigned long pte_sz_bits(unsigned long sz)
2345 {
2346         if (tlb_type == hypervisor) {
2347                 switch (sz) {
2348                 case 8 * 1024:
2349                 default:
2350                         return _PAGE_SZ8K_4V;
2351                 case 64 * 1024:
2352                         return _PAGE_SZ64K_4V;
2353                 case 512 * 1024:
2354                         return _PAGE_SZ512K_4V;
2355                 case 4 * 1024 * 1024:
2356                         return _PAGE_SZ4MB_4V;
2357                 }
2358         } else {
2359                 switch (sz) {
2360                 case 8 * 1024:
2361                 default:
2362                         return _PAGE_SZ8K_4U;
2363                 case 64 * 1024:
2364                         return _PAGE_SZ64K_4U;
2365                 case 512 * 1024:
2366                         return _PAGE_SZ512K_4U;
2367                 case 4 * 1024 * 1024:
2368                         return _PAGE_SZ4MB_4U;
2369                 }
2370         }
2371 }
2372 
2373 pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
2374 {
2375         pte_t pte;
2376 
2377         pte_val(pte)  = page | pgprot_val(pgprot_noncached(prot));
2378         pte_val(pte) |= (((unsigned long)space) << 32);
2379         pte_val(pte) |= pte_sz_bits(page_size);
2380 
2381         return pte;
2382 }
2383 
2384 static unsigned long kern_large_tte(unsigned long paddr)
2385 {
2386         unsigned long val;
2387 
2388         val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2389                _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
2390                _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
2391         if (tlb_type == hypervisor)
2392                 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2393                        _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_P_4V |
2394                        _PAGE_EXEC_4V | _PAGE_W_4V);
2395 
2396         return val | paddr;
2397 }
2398 
2399 /* If not locked, zap it. */
2400 void __flush_tlb_all(void)
2401 {
2402         unsigned long pstate;
2403         int i;
2404 
2405         __asm__ __volatile__("flushw\n\t"
2406                              "rdpr      %%pstate, %0\n\t"
2407                              "wrpr      %0, %1, %%pstate"
2408                              : "=r" (pstate)
2409                              : "i" (PSTATE_IE));
2410         if (tlb_type == hypervisor) {
2411                 sun4v_mmu_demap_all();
2412         } else if (tlb_type == spitfire) {
2413                 for (i = 0; i < 64; i++) {
2414                         /* Spitfire Errata #32 workaround */
2415                         /* NOTE: Always runs on spitfire, so no
2416                          *       cheetah+ page size encodings.
2417                          */
2418                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
2419                                              "flush     %%g6"
2420                                              : /* No outputs */
2421                                              : "r" (0),
2422                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2423 
2424                         if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
2425                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2426                                                      "membar #Sync"
2427                                                      : /* no outputs */
2428                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
2429                                 spitfire_put_dtlb_data(i, 0x0UL);
2430                         }
2431 
2432                         /* Spitfire Errata #32 workaround */
2433                         /* NOTE: Always runs on spitfire, so no
2434                          *       cheetah+ page size encodings.
2435                          */
2436                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
2437                                              "flush     %%g6"
2438                                              : /* No outputs */
2439                                              : "r" (0),
2440                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2441 
2442                         if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
2443                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2444                                                      "membar #Sync"
2445                                                      : /* no outputs */
2446                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
2447                                 spitfire_put_itlb_data(i, 0x0UL);
2448                         }
2449                 }
2450         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
2451                 cheetah_flush_dtlb_all();
2452                 cheetah_flush_itlb_all();
2453         }
2454         __asm__ __volatile__("wrpr      %0, 0, %%pstate"
2455                              : : "r" (pstate));
2456 }
2457 
2458 static pte_t *get_from_cache(struct mm_struct *mm)
2459 {
2460         struct page *page;
2461         pte_t *ret;
2462 
2463         spin_lock(&mm->page_table_lock);
2464         page = mm->context.pgtable_page;
2465         ret = NULL;
2466         if (page) {
2467                 void *p = page_address(page);
2468 
2469                 mm->context.pgtable_page = NULL;
2470 
2471                 ret = (pte_t *) (p + (PAGE_SIZE / 2));
2472         }
2473         spin_unlock(&mm->page_table_lock);
2474 
2475         return ret;
2476 }
2477 
2478 static struct page *__alloc_for_cache(struct mm_struct *mm)
2479 {
2480         struct page *page = alloc_page(GFP_KERNEL | __GFP_NOTRACK |
2481                                        __GFP_REPEAT | __GFP_ZERO);
2482 
2483         if (page) {
2484                 spin_lock(&mm->page_table_lock);
2485                 if (!mm->context.pgtable_page) {
2486                         atomic_set(&page->_count, 2);
2487                         mm->context.pgtable_page = page;
2488                 }
2489                 spin_unlock(&mm->page_table_lock);
2490         }
2491         return page;
2492 }
2493 
2494 pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
2495                             unsigned long address)
2496 {
2497         struct page *page;
2498         pte_t *pte;
2499 
2500         pte = get_from_cache(mm);
2501         if (pte)
2502                 return pte;
2503 
2504         page = __alloc_for_cache(mm);
2505         if (page)
2506                 pte = (pte_t *) page_address(page);
2507 
2508         return pte;
2509 }
2510 
2511 pgtable_t pte_alloc_one(struct mm_struct *mm,
2512                         unsigned long address)
2513 {
2514         struct page *page;
2515         pte_t *pte;
2516 
2517         pte = get_from_cache(mm);
2518         if (pte)
2519                 return pte;
2520 
2521         page = __alloc_for_cache(mm);
2522         if (page) {
2523                 pgtable_page_ctor(page);
2524                 pte = (pte_t *) page_address(page);
2525         }
2526 
2527         return pte;
2528 }
2529 
2530 void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
2531 {
2532         struct page *page = virt_to_page(pte);
2533         if (put_page_testzero(page))
2534                 free_hot_cold_page(page, 0);
2535 }
2536 
2537 static void __pte_free(pgtable_t pte)
2538 {
2539         struct page *page = virt_to_page(pte);
2540         if (put_page_testzero(page)) {
2541                 pgtable_page_dtor(page);
2542                 free_hot_cold_page(page, 0);
2543         }
2544 }
2545 
2546 void pte_free(struct mm_struct *mm, pgtable_t pte)
2547 {
2548         __pte_free(pte);
2549 }
2550 
2551 void pgtable_free(void *table, bool is_page)
2552 {
2553         if (is_page)
2554                 __pte_free(table);
2555         else
2556                 kmem_cache_free(pgtable_cache, table);
2557 }
2558 
2559 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
2560 static pmd_t pmd_set_protbits(pmd_t pmd, pgprot_t pgprot, bool for_modify)
2561 {
2562         if (pgprot_val(pgprot) & _PAGE_VALID)
2563                 pmd_val(pmd) |= PMD_HUGE_PRESENT;
2564         if (tlb_type == hypervisor) {
2565                 if (pgprot_val(pgprot) & _PAGE_WRITE_4V)
2566                         pmd_val(pmd) |= PMD_HUGE_WRITE;
2567                 if (pgprot_val(pgprot) & _PAGE_EXEC_4V)
2568                         pmd_val(pmd) |= PMD_HUGE_EXEC;
2569 
2570                 if (!for_modify) {
2571                         if (pgprot_val(pgprot) & _PAGE_ACCESSED_4V)
2572                                 pmd_val(pmd) |= PMD_HUGE_ACCESSED;
2573                         if (pgprot_val(pgprot) & _PAGE_MODIFIED_4V)
2574                                 pmd_val(pmd) |= PMD_HUGE_DIRTY;
2575                 }
2576         } else {
2577                 if (pgprot_val(pgprot) & _PAGE_WRITE_4U)
2578                         pmd_val(pmd) |= PMD_HUGE_WRITE;
2579                 if (pgprot_val(pgprot) & _PAGE_EXEC_4U)
2580                         pmd_val(pmd) |= PMD_HUGE_EXEC;
2581 
2582                 if (!for_modify) {
2583                         if (pgprot_val(pgprot) & _PAGE_ACCESSED_4U)
2584                                 pmd_val(pmd) |= PMD_HUGE_ACCESSED;
2585                         if (pgprot_val(pgprot) & _PAGE_MODIFIED_4U)
2586                                 pmd_val(pmd) |= PMD_HUGE_DIRTY;
2587                 }
2588         }
2589 
2590         return pmd;
2591 }
2592 
2593 pmd_t pfn_pmd(unsigned long page_nr, pgprot_t pgprot)
2594 {
2595         pmd_t pmd;
2596 
2597         pmd_val(pmd) = (page_nr << ((PAGE_SHIFT - PMD_PADDR_SHIFT)));
2598         pmd_val(pmd) |= PMD_ISHUGE;
2599         pmd = pmd_set_protbits(pmd, pgprot, false);
2600         return pmd;
2601 }
2602 
2603 pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
2604 {
2605         pmd_val(pmd) &= ~(PMD_HUGE_PRESENT |
2606                           PMD_HUGE_WRITE |
2607                           PMD_HUGE_EXEC);
2608         pmd = pmd_set_protbits(pmd, newprot, true);
2609         return pmd;
2610 }
2611 
2612 pgprot_t pmd_pgprot(pmd_t entry)
2613 {
2614         unsigned long pte = 0;
2615 
2616         if (pmd_val(entry) & PMD_HUGE_PRESENT)
2617                 pte |= _PAGE_VALID;
2618 
2619         if (tlb_type == hypervisor) {
2620                 if (pmd_val(entry) & PMD_HUGE_PRESENT)
2621                         pte |= _PAGE_PRESENT_4V;
2622                 if (pmd_val(entry) & PMD_HUGE_EXEC)
2623                         pte |= _PAGE_EXEC_4V;
2624                 if (pmd_val(entry) & PMD_HUGE_WRITE)
2625                         pte |= _PAGE_W_4V;
2626                 if (pmd_val(entry) & PMD_HUGE_ACCESSED)
2627                         pte |= _PAGE_ACCESSED_4V;
2628                 if (pmd_val(entry) & PMD_HUGE_DIRTY)
2629                         pte |= _PAGE_MODIFIED_4V;
2630                 pte |= _PAGE_CP_4V|_PAGE_CV_4V;
2631         } else {
2632                 if (pmd_val(entry) & PMD_HUGE_PRESENT)
2633                         pte |= _PAGE_PRESENT_4U;
2634                 if (pmd_val(entry) & PMD_HUGE_EXEC)
2635                         pte |= _PAGE_EXEC_4U;
2636                 if (pmd_val(entry) & PMD_HUGE_WRITE)
2637                         pte |= _PAGE_W_4U;
2638                 if (pmd_val(entry) & PMD_HUGE_ACCESSED)
2639                         pte |= _PAGE_ACCESSED_4U;
2640                 if (pmd_val(entry) & PMD_HUGE_DIRTY)
2641                         pte |= _PAGE_MODIFIED_4U;
2642                 pte |= _PAGE_CP_4U|_PAGE_CV_4U;
2643         }
2644 
2645         return __pgprot(pte);
2646 }
2647 
2648 void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
2649                           pmd_t *pmd)
2650 {
2651         unsigned long pte, flags;
2652         struct mm_struct *mm;
2653         pmd_t entry = *pmd;
2654         pgprot_t prot;
2655 
2656         if (!pmd_large(entry) || !pmd_young(entry))
2657                 return;
2658 
2659         pte = (pmd_val(entry) & ~PMD_HUGE_PROTBITS);
2660         pte <<= PMD_PADDR_SHIFT;
2661         pte |= _PAGE_VALID;
2662 
2663         prot = pmd_pgprot(entry);
2664 
2665         if (tlb_type == hypervisor)
2666                 pgprot_val(prot) |= _PAGE_SZHUGE_4V;
2667         else
2668                 pgprot_val(prot) |= _PAGE_SZHUGE_4U;
2669 
2670         pte |= pgprot_val(prot);
2671 
2672         mm = vma->vm_mm;
2673 
2674         spin_lock_irqsave(&mm->context.lock, flags);
2675 
2676         if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL)
2677                 __update_mmu_tsb_insert(mm, MM_TSB_HUGE, HPAGE_SHIFT,
2678                                         addr, pte);
2679 
2680         spin_unlock_irqrestore(&mm->context.lock, flags);
2681 }
2682 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
2683 
2684 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
2685 static void context_reload(void *__data)
2686 {
2687         struct mm_struct *mm = __data;
2688 
2689         if (mm == current->mm)
2690                 load_secondary_context(mm);
2691 }
2692 
2693 void hugetlb_setup(struct pt_regs *regs)
2694 {
2695         struct mm_struct *mm = current->mm;
2696         struct tsb_config *tp;
2697 
2698         if (in_atomic() || !mm) {
2699                 const struct exception_table_entry *entry;
2700 
2701                 entry = search_exception_tables(regs->tpc);
2702                 if (entry) {
2703                         regs->tpc = entry->fixup;
2704                         regs->tnpc = regs->tpc + 4;
2705                         return;
2706                 }
2707                 pr_alert("Unexpected HugeTLB setup in atomic context.\n");
2708                 die_if_kernel("HugeTSB in atomic", regs);
2709         }
2710 
2711         tp = &mm->context.tsb_block[MM_TSB_HUGE];
2712         if (likely(tp->tsb == NULL))
2713                 tsb_grow(mm, MM_TSB_HUGE, 0);
2714 
2715         tsb_context_switch(mm);
2716         smp_tsb_sync(mm);
2717 
2718         /* On UltraSPARC-III+ and later, configure the second half of
2719          * the Data-TLB for huge pages.
2720          */
2721         if (tlb_type == cheetah_plus) {
2722                 unsigned long ctx;
2723 
2724                 spin_lock(&ctx_alloc_lock);
2725                 ctx = mm->context.sparc64_ctx_val;
2726                 ctx &= ~CTX_PGSZ_MASK;
2727                 ctx |= CTX_PGSZ_BASE << CTX_PGSZ0_SHIFT;
2728                 ctx |= CTX_PGSZ_HUGE << CTX_PGSZ1_SHIFT;
2729 
2730                 if (ctx != mm->context.sparc64_ctx_val) {
2731                         /* When changing the page size fields, we
2732                          * must perform a context flush so that no
2733                          * stale entries match.  This flush must
2734                          * occur with the original context register
2735                          * settings.
2736                          */
2737                         do_flush_tlb_mm(mm);
2738 
2739                         /* Reload the context register of all processors
2740                          * also executing in this address space.
2741                          */
2742                         mm->context.sparc64_ctx_val = ctx;
2743                         on_each_cpu(context_reload, mm, 0);
2744                 }
2745                 spin_unlock(&ctx_alloc_lock);
2746         }
2747 }
2748 #endif
2749 

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