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Linux/arch/sparc/mm/init_64.c

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  1 /*
  2  *  arch/sparc64/mm/init.c
  3  *
  4  *  Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
  5  *  Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
  6  */
  7  
  8 #include <linux/module.h>
  9 #include <linux/kernel.h>
 10 #include <linux/sched.h>
 11 #include <linux/string.h>
 12 #include <linux/init.h>
 13 #include <linux/bootmem.h>
 14 #include <linux/mm.h>
 15 #include <linux/hugetlb.h>
 16 #include <linux/initrd.h>
 17 #include <linux/swap.h>
 18 #include <linux/pagemap.h>
 19 #include <linux/poison.h>
 20 #include <linux/fs.h>
 21 #include <linux/seq_file.h>
 22 #include <linux/kprobes.h>
 23 #include <linux/cache.h>
 24 #include <linux/sort.h>
 25 #include <linux/percpu.h>
 26 #include <linux/memblock.h>
 27 #include <linux/mmzone.h>
 28 #include <linux/gfp.h>
 29 
 30 #include <asm/head.h>
 31 #include <asm/page.h>
 32 #include <asm/pgalloc.h>
 33 #include <asm/pgtable.h>
 34 #include <asm/oplib.h>
 35 #include <asm/iommu.h>
 36 #include <asm/io.h>
 37 #include <asm/uaccess.h>
 38 #include <asm/mmu_context.h>
 39 #include <asm/tlbflush.h>
 40 #include <asm/dma.h>
 41 #include <asm/starfire.h>
 42 #include <asm/tlb.h>
 43 #include <asm/spitfire.h>
 44 #include <asm/sections.h>
 45 #include <asm/tsb.h>
 46 #include <asm/hypervisor.h>
 47 #include <asm/prom.h>
 48 #include <asm/mdesc.h>
 49 #include <asm/cpudata.h>
 50 #include <asm/irq.h>
 51 
 52 #include "init_64.h"
 53 
 54 unsigned long kern_linear_pte_xor[4] __read_mostly;
 55 
 56 /* A bitmap, two bits for every 256MB of physical memory.  These two
 57  * bits determine what page size we use for kernel linear
 58  * translations.  They form an index into kern_linear_pte_xor[].  The
 59  * value in the indexed slot is XOR'd with the TLB miss virtual
 60  * address to form the resulting TTE.  The mapping is:
 61  *
 62  *      0       ==>     4MB
 63  *      1       ==>     256MB
 64  *      2       ==>     2GB
 65  *      3       ==>     16GB
 66  *
 67  * All sun4v chips support 256MB pages.  Only SPARC-T4 and later
 68  * support 2GB pages, and hopefully future cpus will support the 16GB
 69  * pages as well.  For slots 2 and 3, we encode a 256MB TTE xor there
 70  * if these larger page sizes are not supported by the cpu.
 71  *
 72  * It would be nice to determine this from the machine description
 73  * 'cpu' properties, but we need to have this table setup before the
 74  * MDESC is initialized.
 75  */
 76 
 77 #ifndef CONFIG_DEBUG_PAGEALLOC
 78 /* A special kernel TSB for 4MB, 256MB, 2GB and 16GB linear mappings.
 79  * Space is allocated for this right after the trap table in
 80  * arch/sparc64/kernel/head.S
 81  */
 82 extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
 83 #endif
 84 extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
 85 
 86 static unsigned long cpu_pgsz_mask;
 87 
 88 #define MAX_BANKS       1024
 89 
 90 static struct linux_prom64_registers pavail[MAX_BANKS];
 91 static int pavail_ents;
 92 
 93 static int cmp_p64(const void *a, const void *b)
 94 {
 95         const struct linux_prom64_registers *x = a, *y = b;
 96 
 97         if (x->phys_addr > y->phys_addr)
 98                 return 1;
 99         if (x->phys_addr < y->phys_addr)
100                 return -1;
101         return 0;
102 }
103 
104 static void __init read_obp_memory(const char *property,
105                                    struct linux_prom64_registers *regs,
106                                    int *num_ents)
107 {
108         phandle node = prom_finddevice("/memory");
109         int prop_size = prom_getproplen(node, property);
110         int ents, ret, i;
111 
112         ents = prop_size / sizeof(struct linux_prom64_registers);
113         if (ents > MAX_BANKS) {
114                 prom_printf("The machine has more %s property entries than "
115                             "this kernel can support (%d).\n",
116                             property, MAX_BANKS);
117                 prom_halt();
118         }
119 
120         ret = prom_getproperty(node, property, (char *) regs, prop_size);
121         if (ret == -1) {
122                 prom_printf("Couldn't get %s property from /memory.\n",
123                                 property);
124                 prom_halt();
125         }
126 
127         /* Sanitize what we got from the firmware, by page aligning
128          * everything.
129          */
130         for (i = 0; i < ents; i++) {
131                 unsigned long base, size;
132 
133                 base = regs[i].phys_addr;
134                 size = regs[i].reg_size;
135 
136                 size &= PAGE_MASK;
137                 if (base & ~PAGE_MASK) {
138                         unsigned long new_base = PAGE_ALIGN(base);
139 
140                         size -= new_base - base;
141                         if ((long) size < 0L)
142                                 size = 0UL;
143                         base = new_base;
144                 }
145                 if (size == 0UL) {
146                         /* If it is empty, simply get rid of it.
147                          * This simplifies the logic of the other
148                          * functions that process these arrays.
149                          */
150                         memmove(&regs[i], &regs[i + 1],
151                                 (ents - i - 1) * sizeof(regs[0]));
152                         i--;
153                         ents--;
154                         continue;
155                 }
156                 regs[i].phys_addr = base;
157                 regs[i].reg_size = size;
158         }
159 
160         *num_ents = ents;
161 
162         sort(regs, ents, sizeof(struct linux_prom64_registers),
163              cmp_p64, NULL);
164 }
165 
166 /* Kernel physical address base and size in bytes.  */
167 unsigned long kern_base __read_mostly;
168 unsigned long kern_size __read_mostly;
169 
170 /* Initial ramdisk setup */
171 extern unsigned long sparc_ramdisk_image64;
172 extern unsigned int sparc_ramdisk_image;
173 extern unsigned int sparc_ramdisk_size;
174 
175 struct page *mem_map_zero __read_mostly;
176 EXPORT_SYMBOL(mem_map_zero);
177 
178 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
179 
180 unsigned long sparc64_kern_pri_context __read_mostly;
181 unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
182 unsigned long sparc64_kern_sec_context __read_mostly;
183 
184 int num_kernel_image_mappings;
185 
186 #ifdef CONFIG_DEBUG_DCFLUSH
187 atomic_t dcpage_flushes = ATOMIC_INIT(0);
188 #ifdef CONFIG_SMP
189 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
190 #endif
191 #endif
192 
193 inline void flush_dcache_page_impl(struct page *page)
194 {
195         BUG_ON(tlb_type == hypervisor);
196 #ifdef CONFIG_DEBUG_DCFLUSH
197         atomic_inc(&dcpage_flushes);
198 #endif
199 
200 #ifdef DCACHE_ALIASING_POSSIBLE
201         __flush_dcache_page(page_address(page),
202                             ((tlb_type == spitfire) &&
203                              page_mapping(page) != NULL));
204 #else
205         if (page_mapping(page) != NULL &&
206             tlb_type == spitfire)
207                 __flush_icache_page(__pa(page_address(page)));
208 #endif
209 }
210 
211 #define PG_dcache_dirty         PG_arch_1
212 #define PG_dcache_cpu_shift     32UL
213 #define PG_dcache_cpu_mask      \
214         ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
215 
216 #define dcache_dirty_cpu(page) \
217         (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
218 
219 static inline void set_dcache_dirty(struct page *page, int this_cpu)
220 {
221         unsigned long mask = this_cpu;
222         unsigned long non_cpu_bits;
223 
224         non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
225         mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
226 
227         __asm__ __volatile__("1:\n\t"
228                              "ldx       [%2], %%g7\n\t"
229                              "and       %%g7, %1, %%g1\n\t"
230                              "or        %%g1, %0, %%g1\n\t"
231                              "casx      [%2], %%g7, %%g1\n\t"
232                              "cmp       %%g7, %%g1\n\t"
233                              "bne,pn    %%xcc, 1b\n\t"
234                              " nop"
235                              : /* no outputs */
236                              : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
237                              : "g1", "g7");
238 }
239 
240 static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
241 {
242         unsigned long mask = (1UL << PG_dcache_dirty);
243 
244         __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
245                              "1:\n\t"
246                              "ldx       [%2], %%g7\n\t"
247                              "srlx      %%g7, %4, %%g1\n\t"
248                              "and       %%g1, %3, %%g1\n\t"
249                              "cmp       %%g1, %0\n\t"
250                              "bne,pn    %%icc, 2f\n\t"
251                              " andn     %%g7, %1, %%g1\n\t"
252                              "casx      [%2], %%g7, %%g1\n\t"
253                              "cmp       %%g7, %%g1\n\t"
254                              "bne,pn    %%xcc, 1b\n\t"
255                              " nop\n"
256                              "2:"
257                              : /* no outputs */
258                              : "r" (cpu), "r" (mask), "r" (&page->flags),
259                                "i" (PG_dcache_cpu_mask),
260                                "i" (PG_dcache_cpu_shift)
261                              : "g1", "g7");
262 }
263 
264 static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
265 {
266         unsigned long tsb_addr = (unsigned long) ent;
267 
268         if (tlb_type == cheetah_plus || tlb_type == hypervisor)
269                 tsb_addr = __pa(tsb_addr);
270 
271         __tsb_insert(tsb_addr, tag, pte);
272 }
273 
274 unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
275 
276 static void flush_dcache(unsigned long pfn)
277 {
278         struct page *page;
279 
280         page = pfn_to_page(pfn);
281         if (page) {
282                 unsigned long pg_flags;
283 
284                 pg_flags = page->flags;
285                 if (pg_flags & (1UL << PG_dcache_dirty)) {
286                         int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
287                                    PG_dcache_cpu_mask);
288                         int this_cpu = get_cpu();
289 
290                         /* This is just to optimize away some function calls
291                          * in the SMP case.
292                          */
293                         if (cpu == this_cpu)
294                                 flush_dcache_page_impl(page);
295                         else
296                                 smp_flush_dcache_page_impl(page, cpu);
297 
298                         clear_dcache_dirty_cpu(page, cpu);
299 
300                         put_cpu();
301                 }
302         }
303 }
304 
305 /* mm->context.lock must be held */
306 static void __update_mmu_tsb_insert(struct mm_struct *mm, unsigned long tsb_index,
307                                     unsigned long tsb_hash_shift, unsigned long address,
308                                     unsigned long tte)
309 {
310         struct tsb *tsb = mm->context.tsb_block[tsb_index].tsb;
311         unsigned long tag;
312 
313         if (unlikely(!tsb))
314                 return;
315 
316         tsb += ((address >> tsb_hash_shift) &
317                 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
318         tag = (address >> 22UL);
319         tsb_insert(tsb, tag, tte);
320 }
321 
322 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
323 static inline bool is_hugetlb_pte(pte_t pte)
324 {
325         if ((tlb_type == hypervisor &&
326              (pte_val(pte) & _PAGE_SZALL_4V) == _PAGE_SZHUGE_4V) ||
327             (tlb_type != hypervisor &&
328              (pte_val(pte) & _PAGE_SZALL_4U) == _PAGE_SZHUGE_4U))
329                 return true;
330         return false;
331 }
332 #endif
333 
334 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
335 {
336         struct mm_struct *mm;
337         unsigned long flags;
338         pte_t pte = *ptep;
339 
340         if (tlb_type != hypervisor) {
341                 unsigned long pfn = pte_pfn(pte);
342 
343                 if (pfn_valid(pfn))
344                         flush_dcache(pfn);
345         }
346 
347         mm = vma->vm_mm;
348 
349         /* Don't insert a non-valid PTE into the TSB, we'll deadlock.  */
350         if (!pte_accessible(mm, pte))
351                 return;
352 
353         spin_lock_irqsave(&mm->context.lock, flags);
354 
355 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
356         if (mm->context.huge_pte_count && is_hugetlb_pte(pte))
357                 __update_mmu_tsb_insert(mm, MM_TSB_HUGE, REAL_HPAGE_SHIFT,
358                                         address, pte_val(pte));
359         else
360 #endif
361                 __update_mmu_tsb_insert(mm, MM_TSB_BASE, PAGE_SHIFT,
362                                         address, pte_val(pte));
363 
364         spin_unlock_irqrestore(&mm->context.lock, flags);
365 }
366 
367 void flush_dcache_page(struct page *page)
368 {
369         struct address_space *mapping;
370         int this_cpu;
371 
372         if (tlb_type == hypervisor)
373                 return;
374 
375         /* Do not bother with the expensive D-cache flush if it
376          * is merely the zero page.  The 'bigcore' testcase in GDB
377          * causes this case to run millions of times.
378          */
379         if (page == ZERO_PAGE(0))
380                 return;
381 
382         this_cpu = get_cpu();
383 
384         mapping = page_mapping(page);
385         if (mapping && !mapping_mapped(mapping)) {
386                 int dirty = test_bit(PG_dcache_dirty, &page->flags);
387                 if (dirty) {
388                         int dirty_cpu = dcache_dirty_cpu(page);
389 
390                         if (dirty_cpu == this_cpu)
391                                 goto out;
392                         smp_flush_dcache_page_impl(page, dirty_cpu);
393                 }
394                 set_dcache_dirty(page, this_cpu);
395         } else {
396                 /* We could delay the flush for the !page_mapping
397                  * case too.  But that case is for exec env/arg
398                  * pages and those are %99 certainly going to get
399                  * faulted into the tlb (and thus flushed) anyways.
400                  */
401                 flush_dcache_page_impl(page);
402         }
403 
404 out:
405         put_cpu();
406 }
407 EXPORT_SYMBOL(flush_dcache_page);
408 
409 void __kprobes flush_icache_range(unsigned long start, unsigned long end)
410 {
411         /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
412         if (tlb_type == spitfire) {
413                 unsigned long kaddr;
414 
415                 /* This code only runs on Spitfire cpus so this is
416                  * why we can assume _PAGE_PADDR_4U.
417                  */
418                 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) {
419                         unsigned long paddr, mask = _PAGE_PADDR_4U;
420 
421                         if (kaddr >= PAGE_OFFSET)
422                                 paddr = kaddr & mask;
423                         else {
424                                 pgd_t *pgdp = pgd_offset_k(kaddr);
425                                 pud_t *pudp = pud_offset(pgdp, kaddr);
426                                 pmd_t *pmdp = pmd_offset(pudp, kaddr);
427                                 pte_t *ptep = pte_offset_kernel(pmdp, kaddr);
428 
429                                 paddr = pte_val(*ptep) & mask;
430                         }
431                         __flush_icache_page(paddr);
432                 }
433         }
434 }
435 EXPORT_SYMBOL(flush_icache_range);
436 
437 void mmu_info(struct seq_file *m)
438 {
439         static const char *pgsz_strings[] = {
440                 "8K", "64K", "512K", "4MB", "32MB",
441                 "256MB", "2GB", "16GB",
442         };
443         int i, printed;
444 
445         if (tlb_type == cheetah)
446                 seq_printf(m, "MMU Type\t: Cheetah\n");
447         else if (tlb_type == cheetah_plus)
448                 seq_printf(m, "MMU Type\t: Cheetah+\n");
449         else if (tlb_type == spitfire)
450                 seq_printf(m, "MMU Type\t: Spitfire\n");
451         else if (tlb_type == hypervisor)
452                 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
453         else
454                 seq_printf(m, "MMU Type\t: ???\n");
455 
456         seq_printf(m, "MMU PGSZs\t: ");
457         printed = 0;
458         for (i = 0; i < ARRAY_SIZE(pgsz_strings); i++) {
459                 if (cpu_pgsz_mask & (1UL << i)) {
460                         seq_printf(m, "%s%s",
461                                    printed ? "," : "", pgsz_strings[i]);
462                         printed++;
463                 }
464         }
465         seq_putc(m, '\n');
466 
467 #ifdef CONFIG_DEBUG_DCFLUSH
468         seq_printf(m, "DCPageFlushes\t: %d\n",
469                    atomic_read(&dcpage_flushes));
470 #ifdef CONFIG_SMP
471         seq_printf(m, "DCPageFlushesXC\t: %d\n",
472                    atomic_read(&dcpage_flushes_xcall));
473 #endif /* CONFIG_SMP */
474 #endif /* CONFIG_DEBUG_DCFLUSH */
475 }
476 
477 struct linux_prom_translation prom_trans[512] __read_mostly;
478 unsigned int prom_trans_ents __read_mostly;
479 
480 unsigned long kern_locked_tte_data;
481 
482 /* The obp translations are saved based on 8k pagesize, since obp can
483  * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
484  * HI_OBP_ADDRESS range are handled in ktlb.S.
485  */
486 static inline int in_obp_range(unsigned long vaddr)
487 {
488         return (vaddr >= LOW_OBP_ADDRESS &&
489                 vaddr < HI_OBP_ADDRESS);
490 }
491 
492 static int cmp_ptrans(const void *a, const void *b)
493 {
494         const struct linux_prom_translation *x = a, *y = b;
495 
496         if (x->virt > y->virt)
497                 return 1;
498         if (x->virt < y->virt)
499                 return -1;
500         return 0;
501 }
502 
503 /* Read OBP translations property into 'prom_trans[]'.  */
504 static void __init read_obp_translations(void)
505 {
506         int n, node, ents, first, last, i;
507 
508         node = prom_finddevice("/virtual-memory");
509         n = prom_getproplen(node, "translations");
510         if (unlikely(n == 0 || n == -1)) {
511                 prom_printf("prom_mappings: Couldn't get size.\n");
512                 prom_halt();
513         }
514         if (unlikely(n > sizeof(prom_trans))) {
515                 prom_printf("prom_mappings: Size %d is too big.\n", n);
516                 prom_halt();
517         }
518 
519         if ((n = prom_getproperty(node, "translations",
520                                   (char *)&prom_trans[0],
521                                   sizeof(prom_trans))) == -1) {
522                 prom_printf("prom_mappings: Couldn't get property.\n");
523                 prom_halt();
524         }
525 
526         n = n / sizeof(struct linux_prom_translation);
527 
528         ents = n;
529 
530         sort(prom_trans, ents, sizeof(struct linux_prom_translation),
531              cmp_ptrans, NULL);
532 
533         /* Now kick out all the non-OBP entries.  */
534         for (i = 0; i < ents; i++) {
535                 if (in_obp_range(prom_trans[i].virt))
536                         break;
537         }
538         first = i;
539         for (; i < ents; i++) {
540                 if (!in_obp_range(prom_trans[i].virt))
541                         break;
542         }
543         last = i;
544 
545         for (i = 0; i < (last - first); i++) {
546                 struct linux_prom_translation *src = &prom_trans[i + first];
547                 struct linux_prom_translation *dest = &prom_trans[i];
548 
549                 *dest = *src;
550         }
551         for (; i < ents; i++) {
552                 struct linux_prom_translation *dest = &prom_trans[i];
553                 dest->virt = dest->size = dest->data = 0x0UL;
554         }
555 
556         prom_trans_ents = last - first;
557 
558         if (tlb_type == spitfire) {
559                 /* Clear diag TTE bits. */
560                 for (i = 0; i < prom_trans_ents; i++)
561                         prom_trans[i].data &= ~0x0003fe0000000000UL;
562         }
563 
564         /* Force execute bit on.  */
565         for (i = 0; i < prom_trans_ents; i++)
566                 prom_trans[i].data |= (tlb_type == hypervisor ?
567                                        _PAGE_EXEC_4V : _PAGE_EXEC_4U);
568 }
569 
570 static void __init hypervisor_tlb_lock(unsigned long vaddr,
571                                        unsigned long pte,
572                                        unsigned long mmu)
573 {
574         unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu);
575 
576         if (ret != 0) {
577                 prom_printf("hypervisor_tlb_lock[%lx:%x:%lx:%lx]: "
578                             "errors with %lx\n", vaddr, 0, pte, mmu, ret);
579                 prom_halt();
580         }
581 }
582 
583 static unsigned long kern_large_tte(unsigned long paddr);
584 
585 static void __init remap_kernel(void)
586 {
587         unsigned long phys_page, tte_vaddr, tte_data;
588         int i, tlb_ent = sparc64_highest_locked_tlbent();
589 
590         tte_vaddr = (unsigned long) KERNBASE;
591         phys_page = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB;
592         tte_data = kern_large_tte(phys_page);
593 
594         kern_locked_tte_data = tte_data;
595 
596         /* Now lock us into the TLBs via Hypervisor or OBP. */
597         if (tlb_type == hypervisor) {
598                 for (i = 0; i < num_kernel_image_mappings; i++) {
599                         hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
600                         hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
601                         tte_vaddr += 0x400000;
602                         tte_data += 0x400000;
603                 }
604         } else {
605                 for (i = 0; i < num_kernel_image_mappings; i++) {
606                         prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr);
607                         prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr);
608                         tte_vaddr += 0x400000;
609                         tte_data += 0x400000;
610                 }
611                 sparc64_highest_unlocked_tlb_ent = tlb_ent - i;
612         }
613         if (tlb_type == cheetah_plus) {
614                 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
615                                             CTX_CHEETAH_PLUS_NUC);
616                 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
617                 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
618         }
619 }
620 
621 
622 static void __init inherit_prom_mappings(void)
623 {
624         /* Now fixup OBP's idea about where we really are mapped. */
625         printk("Remapping the kernel... ");
626         remap_kernel();
627         printk("done.\n");
628 }
629 
630 void prom_world(int enter)
631 {
632         if (!enter)
633                 set_fs(get_fs());
634 
635         __asm__ __volatile__("flushw");
636 }
637 
638 void __flush_dcache_range(unsigned long start, unsigned long end)
639 {
640         unsigned long va;
641 
642         if (tlb_type == spitfire) {
643                 int n = 0;
644 
645                 for (va = start; va < end; va += 32) {
646                         spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
647                         if (++n >= 512)
648                                 break;
649                 }
650         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
651                 start = __pa(start);
652                 end = __pa(end);
653                 for (va = start; va < end; va += 32)
654                         __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
655                                              "membar #Sync"
656                                              : /* no outputs */
657                                              : "r" (va),
658                                                "i" (ASI_DCACHE_INVALIDATE));
659         }
660 }
661 EXPORT_SYMBOL(__flush_dcache_range);
662 
663 /* get_new_mmu_context() uses "cache + 1".  */
664 DEFINE_SPINLOCK(ctx_alloc_lock);
665 unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
666 #define MAX_CTX_NR      (1UL << CTX_NR_BITS)
667 #define CTX_BMAP_SLOTS  BITS_TO_LONGS(MAX_CTX_NR)
668 DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR);
669 
670 /* Caller does TLB context flushing on local CPU if necessary.
671  * The caller also ensures that CTX_VALID(mm->context) is false.
672  *
673  * We must be careful about boundary cases so that we never
674  * let the user have CTX 0 (nucleus) or we ever use a CTX
675  * version of zero (and thus NO_CONTEXT would not be caught
676  * by version mis-match tests in mmu_context.h).
677  *
678  * Always invoked with interrupts disabled.
679  */
680 void get_new_mmu_context(struct mm_struct *mm)
681 {
682         unsigned long ctx, new_ctx;
683         unsigned long orig_pgsz_bits;
684         int new_version;
685 
686         spin_lock(&ctx_alloc_lock);
687         orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
688         ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
689         new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
690         new_version = 0;
691         if (new_ctx >= (1 << CTX_NR_BITS)) {
692                 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
693                 if (new_ctx >= ctx) {
694                         int i;
695                         new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
696                                 CTX_FIRST_VERSION;
697                         if (new_ctx == 1)
698                                 new_ctx = CTX_FIRST_VERSION;
699 
700                         /* Don't call memset, for 16 entries that's just
701                          * plain silly...
702                          */
703                         mmu_context_bmap[0] = 3;
704                         mmu_context_bmap[1] = 0;
705                         mmu_context_bmap[2] = 0;
706                         mmu_context_bmap[3] = 0;
707                         for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
708                                 mmu_context_bmap[i + 0] = 0;
709                                 mmu_context_bmap[i + 1] = 0;
710                                 mmu_context_bmap[i + 2] = 0;
711                                 mmu_context_bmap[i + 3] = 0;
712                         }
713                         new_version = 1;
714                         goto out;
715                 }
716         }
717         mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
718         new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
719 out:
720         tlb_context_cache = new_ctx;
721         mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
722         spin_unlock(&ctx_alloc_lock);
723 
724         if (unlikely(new_version))
725                 smp_new_mmu_context_version();
726 }
727 
728 static int numa_enabled = 1;
729 static int numa_debug;
730 
731 static int __init early_numa(char *p)
732 {
733         if (!p)
734                 return 0;
735 
736         if (strstr(p, "off"))
737                 numa_enabled = 0;
738 
739         if (strstr(p, "debug"))
740                 numa_debug = 1;
741 
742         return 0;
743 }
744 early_param("numa", early_numa);
745 
746 #define numadbg(f, a...) \
747 do {    if (numa_debug) \
748                 printk(KERN_INFO f, ## a); \
749 } while (0)
750 
751 static void __init find_ramdisk(unsigned long phys_base)
752 {
753 #ifdef CONFIG_BLK_DEV_INITRD
754         if (sparc_ramdisk_image || sparc_ramdisk_image64) {
755                 unsigned long ramdisk_image;
756 
757                 /* Older versions of the bootloader only supported a
758                  * 32-bit physical address for the ramdisk image
759                  * location, stored at sparc_ramdisk_image.  Newer
760                  * SILO versions set sparc_ramdisk_image to zero and
761                  * provide a full 64-bit physical address at
762                  * sparc_ramdisk_image64.
763                  */
764                 ramdisk_image = sparc_ramdisk_image;
765                 if (!ramdisk_image)
766                         ramdisk_image = sparc_ramdisk_image64;
767 
768                 /* Another bootloader quirk.  The bootloader normalizes
769                  * the physical address to KERNBASE, so we have to
770                  * factor that back out and add in the lowest valid
771                  * physical page address to get the true physical address.
772                  */
773                 ramdisk_image -= KERNBASE;
774                 ramdisk_image += phys_base;
775 
776                 numadbg("Found ramdisk at physical address 0x%lx, size %u\n",
777                         ramdisk_image, sparc_ramdisk_size);
778 
779                 initrd_start = ramdisk_image;
780                 initrd_end = ramdisk_image + sparc_ramdisk_size;
781 
782                 memblock_reserve(initrd_start, sparc_ramdisk_size);
783 
784                 initrd_start += PAGE_OFFSET;
785                 initrd_end += PAGE_OFFSET;
786         }
787 #endif
788 }
789 
790 struct node_mem_mask {
791         unsigned long mask;
792         unsigned long val;
793 };
794 static struct node_mem_mask node_masks[MAX_NUMNODES];
795 static int num_node_masks;
796 
797 int numa_cpu_lookup_table[NR_CPUS];
798 cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES];
799 
800 #ifdef CONFIG_NEED_MULTIPLE_NODES
801 
802 struct mdesc_mblock {
803         u64     base;
804         u64     size;
805         u64     offset; /* RA-to-PA */
806 };
807 static struct mdesc_mblock *mblocks;
808 static int num_mblocks;
809 
810 static unsigned long ra_to_pa(unsigned long addr)
811 {
812         int i;
813 
814         for (i = 0; i < num_mblocks; i++) {
815                 struct mdesc_mblock *m = &mblocks[i];
816 
817                 if (addr >= m->base &&
818                     addr < (m->base + m->size)) {
819                         addr += m->offset;
820                         break;
821                 }
822         }
823         return addr;
824 }
825 
826 static int find_node(unsigned long addr)
827 {
828         int i;
829 
830         addr = ra_to_pa(addr);
831         for (i = 0; i < num_node_masks; i++) {
832                 struct node_mem_mask *p = &node_masks[i];
833 
834                 if ((addr & p->mask) == p->val)
835                         return i;
836         }
837         /* The following condition has been observed on LDOM guests.*/
838         WARN_ONCE(1, "find_node: A physical address doesn't match a NUMA node"
839                 " rule. Some physical memory will be owned by node 0.");
840         return 0;
841 }
842 
843 static u64 memblock_nid_range(u64 start, u64 end, int *nid)
844 {
845         *nid = find_node(start);
846         start += PAGE_SIZE;
847         while (start < end) {
848                 int n = find_node(start);
849 
850                 if (n != *nid)
851                         break;
852                 start += PAGE_SIZE;
853         }
854 
855         if (start > end)
856                 start = end;
857 
858         return start;
859 }
860 #endif
861 
862 /* This must be invoked after performing all of the necessary
863  * memblock_set_node() calls for 'nid'.  We need to be able to get
864  * correct data from get_pfn_range_for_nid().
865  */
866 static void __init allocate_node_data(int nid)
867 {
868         struct pglist_data *p;
869         unsigned long start_pfn, end_pfn;
870 #ifdef CONFIG_NEED_MULTIPLE_NODES
871         unsigned long paddr;
872 
873         paddr = memblock_alloc_try_nid(sizeof(struct pglist_data), SMP_CACHE_BYTES, nid);
874         if (!paddr) {
875                 prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid);
876                 prom_halt();
877         }
878         NODE_DATA(nid) = __va(paddr);
879         memset(NODE_DATA(nid), 0, sizeof(struct pglist_data));
880 
881         NODE_DATA(nid)->node_id = nid;
882 #endif
883 
884         p = NODE_DATA(nid);
885 
886         get_pfn_range_for_nid(nid, &start_pfn, &end_pfn);
887         p->node_start_pfn = start_pfn;
888         p->node_spanned_pages = end_pfn - start_pfn;
889 }
890 
891 static void init_node_masks_nonnuma(void)
892 {
893         int i;
894 
895         numadbg("Initializing tables for non-numa.\n");
896 
897         node_masks[0].mask = node_masks[0].val = 0;
898         num_node_masks = 1;
899 
900         for (i = 0; i < NR_CPUS; i++)
901                 numa_cpu_lookup_table[i] = 0;
902 
903         cpumask_setall(&numa_cpumask_lookup_table[0]);
904 }
905 
906 #ifdef CONFIG_NEED_MULTIPLE_NODES
907 struct pglist_data *node_data[MAX_NUMNODES];
908 
909 EXPORT_SYMBOL(numa_cpu_lookup_table);
910 EXPORT_SYMBOL(numa_cpumask_lookup_table);
911 EXPORT_SYMBOL(node_data);
912 
913 struct mdesc_mlgroup {
914         u64     node;
915         u64     latency;
916         u64     match;
917         u64     mask;
918 };
919 static struct mdesc_mlgroup *mlgroups;
920 static int num_mlgroups;
921 
922 static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio,
923                                    u32 cfg_handle)
924 {
925         u64 arc;
926 
927         mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) {
928                 u64 target = mdesc_arc_target(md, arc);
929                 const u64 *val;
930 
931                 val = mdesc_get_property(md, target,
932                                          "cfg-handle", NULL);
933                 if (val && *val == cfg_handle)
934                         return 0;
935         }
936         return -ENODEV;
937 }
938 
939 static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp,
940                                     u32 cfg_handle)
941 {
942         u64 arc, candidate, best_latency = ~(u64)0;
943 
944         candidate = MDESC_NODE_NULL;
945         mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
946                 u64 target = mdesc_arc_target(md, arc);
947                 const char *name = mdesc_node_name(md, target);
948                 const u64 *val;
949 
950                 if (strcmp(name, "pio-latency-group"))
951                         continue;
952 
953                 val = mdesc_get_property(md, target, "latency", NULL);
954                 if (!val)
955                         continue;
956 
957                 if (*val < best_latency) {
958                         candidate = target;
959                         best_latency = *val;
960                 }
961         }
962 
963         if (candidate == MDESC_NODE_NULL)
964                 return -ENODEV;
965 
966         return scan_pio_for_cfg_handle(md, candidate, cfg_handle);
967 }
968 
969 int of_node_to_nid(struct device_node *dp)
970 {
971         const struct linux_prom64_registers *regs;
972         struct mdesc_handle *md;
973         u32 cfg_handle;
974         int count, nid;
975         u64 grp;
976 
977         /* This is the right thing to do on currently supported
978          * SUN4U NUMA platforms as well, as the PCI controller does
979          * not sit behind any particular memory controller.
980          */
981         if (!mlgroups)
982                 return -1;
983 
984         regs = of_get_property(dp, "reg", NULL);
985         if (!regs)
986                 return -1;
987 
988         cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff;
989 
990         md = mdesc_grab();
991 
992         count = 0;
993         nid = -1;
994         mdesc_for_each_node_by_name(md, grp, "group") {
995                 if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) {
996                         nid = count;
997                         break;
998                 }
999                 count++;
1000         }
1001 
1002         mdesc_release(md);
1003 
1004         return nid;
1005 }
1006 
1007 static void __init add_node_ranges(void)
1008 {
1009         struct memblock_region *reg;
1010 
1011         for_each_memblock(memory, reg) {
1012                 unsigned long size = reg->size;
1013                 unsigned long start, end;
1014 
1015                 start = reg->base;
1016                 end = start + size;
1017                 while (start < end) {
1018                         unsigned long this_end;
1019                         int nid;
1020 
1021                         this_end = memblock_nid_range(start, end, &nid);
1022 
1023                         numadbg("Setting memblock NUMA node nid[%d] "
1024                                 "start[%lx] end[%lx]\n",
1025                                 nid, start, this_end);
1026 
1027                         memblock_set_node(start, this_end - start,
1028                                           &memblock.memory, nid);
1029                         start = this_end;
1030                 }
1031         }
1032 }
1033 
1034 static int __init grab_mlgroups(struct mdesc_handle *md)
1035 {
1036         unsigned long paddr;
1037         int count = 0;
1038         u64 node;
1039 
1040         mdesc_for_each_node_by_name(md, node, "memory-latency-group")
1041                 count++;
1042         if (!count)
1043                 return -ENOENT;
1044 
1045         paddr = memblock_alloc(count * sizeof(struct mdesc_mlgroup),
1046                           SMP_CACHE_BYTES);
1047         if (!paddr)
1048                 return -ENOMEM;
1049 
1050         mlgroups = __va(paddr);
1051         num_mlgroups = count;
1052 
1053         count = 0;
1054         mdesc_for_each_node_by_name(md, node, "memory-latency-group") {
1055                 struct mdesc_mlgroup *m = &mlgroups[count++];
1056                 const u64 *val;
1057 
1058                 m->node = node;
1059 
1060                 val = mdesc_get_property(md, node, "latency", NULL);
1061                 m->latency = *val;
1062                 val = mdesc_get_property(md, node, "address-match", NULL);
1063                 m->match = *val;
1064                 val = mdesc_get_property(md, node, "address-mask", NULL);
1065                 m->mask = *val;
1066 
1067                 numadbg("MLGROUP[%d]: node[%llx] latency[%llx] "
1068                         "match[%llx] mask[%llx]\n",
1069                         count - 1, m->node, m->latency, m->match, m->mask);
1070         }
1071 
1072         return 0;
1073 }
1074 
1075 static int __init grab_mblocks(struct mdesc_handle *md)
1076 {
1077         unsigned long paddr;
1078         int count = 0;
1079         u64 node;
1080 
1081         mdesc_for_each_node_by_name(md, node, "mblock")
1082                 count++;
1083         if (!count)
1084                 return -ENOENT;
1085 
1086         paddr = memblock_alloc(count * sizeof(struct mdesc_mblock),
1087                           SMP_CACHE_BYTES);
1088         if (!paddr)
1089                 return -ENOMEM;
1090 
1091         mblocks = __va(paddr);
1092         num_mblocks = count;
1093 
1094         count = 0;
1095         mdesc_for_each_node_by_name(md, node, "mblock") {
1096                 struct mdesc_mblock *m = &mblocks[count++];
1097                 const u64 *val;
1098 
1099                 val = mdesc_get_property(md, node, "base", NULL);
1100                 m->base = *val;
1101                 val = mdesc_get_property(md, node, "size", NULL);
1102                 m->size = *val;
1103                 val = mdesc_get_property(md, node,
1104                                          "address-congruence-offset", NULL);
1105 
1106                 /* The address-congruence-offset property is optional.
1107                  * Explicity zero it be identifty this.
1108                  */
1109                 if (val)
1110                         m->offset = *val;
1111                 else
1112                         m->offset = 0UL;
1113 
1114                 numadbg("MBLOCK[%d]: base[%llx] size[%llx] offset[%llx]\n",
1115                         count - 1, m->base, m->size, m->offset);
1116         }
1117 
1118         return 0;
1119 }
1120 
1121 static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md,
1122                                                u64 grp, cpumask_t *mask)
1123 {
1124         u64 arc;
1125 
1126         cpumask_clear(mask);
1127 
1128         mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) {
1129                 u64 target = mdesc_arc_target(md, arc);
1130                 const char *name = mdesc_node_name(md, target);
1131                 const u64 *id;
1132 
1133                 if (strcmp(name, "cpu"))
1134                         continue;
1135                 id = mdesc_get_property(md, target, "id", NULL);
1136                 if (*id < nr_cpu_ids)
1137                         cpumask_set_cpu(*id, mask);
1138         }
1139 }
1140 
1141 static struct mdesc_mlgroup * __init find_mlgroup(u64 node)
1142 {
1143         int i;
1144 
1145         for (i = 0; i < num_mlgroups; i++) {
1146                 struct mdesc_mlgroup *m = &mlgroups[i];
1147                 if (m->node == node)
1148                         return m;
1149         }
1150         return NULL;
1151 }
1152 
1153 static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp,
1154                                       int index)
1155 {
1156         struct mdesc_mlgroup *candidate = NULL;
1157         u64 arc, best_latency = ~(u64)0;
1158         struct node_mem_mask *n;
1159 
1160         mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1161                 u64 target = mdesc_arc_target(md, arc);
1162                 struct mdesc_mlgroup *m = find_mlgroup(target);
1163                 if (!m)
1164                         continue;
1165                 if (m->latency < best_latency) {
1166                         candidate = m;
1167                         best_latency = m->latency;
1168                 }
1169         }
1170         if (!candidate)
1171                 return -ENOENT;
1172 
1173         if (num_node_masks != index) {
1174                 printk(KERN_ERR "Inconsistent NUMA state, "
1175                        "index[%d] != num_node_masks[%d]\n",
1176                        index, num_node_masks);
1177                 return -EINVAL;
1178         }
1179 
1180         n = &node_masks[num_node_masks++];
1181 
1182         n->mask = candidate->mask;
1183         n->val = candidate->match;
1184 
1185         numadbg("NUMA NODE[%d]: mask[%lx] val[%lx] (latency[%llx])\n",
1186                 index, n->mask, n->val, candidate->latency);
1187 
1188         return 0;
1189 }
1190 
1191 static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp,
1192                                          int index)
1193 {
1194         cpumask_t mask;
1195         int cpu;
1196 
1197         numa_parse_mdesc_group_cpus(md, grp, &mask);
1198 
1199         for_each_cpu(cpu, &mask)
1200                 numa_cpu_lookup_table[cpu] = index;
1201         cpumask_copy(&numa_cpumask_lookup_table[index], &mask);
1202 
1203         if (numa_debug) {
1204                 printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index);
1205                 for_each_cpu(cpu, &mask)
1206                         printk("%d ", cpu);
1207                 printk("]\n");
1208         }
1209 
1210         return numa_attach_mlgroup(md, grp, index);
1211 }
1212 
1213 static int __init numa_parse_mdesc(void)
1214 {
1215         struct mdesc_handle *md = mdesc_grab();
1216         int i, err, count;
1217         u64 node;
1218 
1219         node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups");
1220         if (node == MDESC_NODE_NULL) {
1221                 mdesc_release(md);
1222                 return -ENOENT;
1223         }
1224 
1225         err = grab_mblocks(md);
1226         if (err < 0)
1227                 goto out;
1228 
1229         err = grab_mlgroups(md);
1230         if (err < 0)
1231                 goto out;
1232 
1233         count = 0;
1234         mdesc_for_each_node_by_name(md, node, "group") {
1235                 err = numa_parse_mdesc_group(md, node, count);
1236                 if (err < 0)
1237                         break;
1238                 count++;
1239         }
1240 
1241         add_node_ranges();
1242 
1243         for (i = 0; i < num_node_masks; i++) {
1244                 allocate_node_data(i);
1245                 node_set_online(i);
1246         }
1247 
1248         err = 0;
1249 out:
1250         mdesc_release(md);
1251         return err;
1252 }
1253 
1254 static int __init numa_parse_jbus(void)
1255 {
1256         unsigned long cpu, index;
1257 
1258         /* NUMA node id is encoded in bits 36 and higher, and there is
1259          * a 1-to-1 mapping from CPU ID to NUMA node ID.
1260          */
1261         index = 0;
1262         for_each_present_cpu(cpu) {
1263                 numa_cpu_lookup_table[cpu] = index;
1264                 cpumask_copy(&numa_cpumask_lookup_table[index], cpumask_of(cpu));
1265                 node_masks[index].mask = ~((1UL << 36UL) - 1UL);
1266                 node_masks[index].val = cpu << 36UL;
1267 
1268                 index++;
1269         }
1270         num_node_masks = index;
1271 
1272         add_node_ranges();
1273 
1274         for (index = 0; index < num_node_masks; index++) {
1275                 allocate_node_data(index);
1276                 node_set_online(index);
1277         }
1278 
1279         return 0;
1280 }
1281 
1282 static int __init numa_parse_sun4u(void)
1283 {
1284         if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1285                 unsigned long ver;
1286 
1287                 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
1288                 if ((ver >> 32UL) == __JALAPENO_ID ||
1289                     (ver >> 32UL) == __SERRANO_ID)
1290                         return numa_parse_jbus();
1291         }
1292         return -1;
1293 }
1294 
1295 static int __init bootmem_init_numa(void)
1296 {
1297         int err = -1;
1298 
1299         numadbg("bootmem_init_numa()\n");
1300 
1301         if (numa_enabled) {
1302                 if (tlb_type == hypervisor)
1303                         err = numa_parse_mdesc();
1304                 else
1305                         err = numa_parse_sun4u();
1306         }
1307         return err;
1308 }
1309 
1310 #else
1311 
1312 static int bootmem_init_numa(void)
1313 {
1314         return -1;
1315 }
1316 
1317 #endif
1318 
1319 static void __init bootmem_init_nonnuma(void)
1320 {
1321         unsigned long top_of_ram = memblock_end_of_DRAM();
1322         unsigned long total_ram = memblock_phys_mem_size();
1323 
1324         numadbg("bootmem_init_nonnuma()\n");
1325 
1326         printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n",
1327                top_of_ram, total_ram);
1328         printk(KERN_INFO "Memory hole size: %ldMB\n",
1329                (top_of_ram - total_ram) >> 20);
1330 
1331         init_node_masks_nonnuma();
1332         memblock_set_node(0, (phys_addr_t)ULLONG_MAX, &memblock.memory, 0);
1333         allocate_node_data(0);
1334         node_set_online(0);
1335 }
1336 
1337 static unsigned long __init bootmem_init(unsigned long phys_base)
1338 {
1339         unsigned long end_pfn;
1340 
1341         end_pfn = memblock_end_of_DRAM() >> PAGE_SHIFT;
1342         max_pfn = max_low_pfn = end_pfn;
1343         min_low_pfn = (phys_base >> PAGE_SHIFT);
1344 
1345         if (bootmem_init_numa() < 0)
1346                 bootmem_init_nonnuma();
1347 
1348         /* Dump memblock with node info. */
1349         memblock_dump_all();
1350 
1351         /* XXX cpu notifier XXX */
1352 
1353         sparse_memory_present_with_active_regions(MAX_NUMNODES);
1354         sparse_init();
1355 
1356         return end_pfn;
1357 }
1358 
1359 static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1360 static int pall_ents __initdata;
1361 
1362 static unsigned long max_phys_bits = 40;
1363 
1364 bool kern_addr_valid(unsigned long addr)
1365 {
1366         pgd_t *pgd;
1367         pud_t *pud;
1368         pmd_t *pmd;
1369         pte_t *pte;
1370 
1371         if ((long)addr < 0L) {
1372                 unsigned long pa = __pa(addr);
1373 
1374                 if ((addr >> max_phys_bits) != 0UL)
1375                         return false;
1376 
1377                 return pfn_valid(pa >> PAGE_SHIFT);
1378         }
1379 
1380         if (addr >= (unsigned long) KERNBASE &&
1381             addr < (unsigned long)&_end)
1382                 return true;
1383 
1384         pgd = pgd_offset_k(addr);
1385         if (pgd_none(*pgd))
1386                 return 0;
1387 
1388         pud = pud_offset(pgd, addr);
1389         if (pud_none(*pud))
1390                 return 0;
1391 
1392         if (pud_large(*pud))
1393                 return pfn_valid(pud_pfn(*pud));
1394 
1395         pmd = pmd_offset(pud, addr);
1396         if (pmd_none(*pmd))
1397                 return 0;
1398 
1399         if (pmd_large(*pmd))
1400                 return pfn_valid(pmd_pfn(*pmd));
1401 
1402         pte = pte_offset_kernel(pmd, addr);
1403         if (pte_none(*pte))
1404                 return 0;
1405 
1406         return pfn_valid(pte_pfn(*pte));
1407 }
1408 EXPORT_SYMBOL(kern_addr_valid);
1409 
1410 static unsigned long __ref kernel_map_hugepud(unsigned long vstart,
1411                                               unsigned long vend,
1412                                               pud_t *pud)
1413 {
1414         const unsigned long mask16gb = (1UL << 34) - 1UL;
1415         u64 pte_val = vstart;
1416 
1417         /* Each PUD is 8GB */
1418         if ((vstart & mask16gb) ||
1419             (vend - vstart <= mask16gb)) {
1420                 pte_val ^= kern_linear_pte_xor[2];
1421                 pud_val(*pud) = pte_val | _PAGE_PUD_HUGE;
1422 
1423                 return vstart + PUD_SIZE;
1424         }
1425 
1426         pte_val ^= kern_linear_pte_xor[3];
1427         pte_val |= _PAGE_PUD_HUGE;
1428 
1429         vend = vstart + mask16gb + 1UL;
1430         while (vstart < vend) {
1431                 pud_val(*pud) = pte_val;
1432 
1433                 pte_val += PUD_SIZE;
1434                 vstart += PUD_SIZE;
1435                 pud++;
1436         }
1437         return vstart;
1438 }
1439 
1440 static bool kernel_can_map_hugepud(unsigned long vstart, unsigned long vend,
1441                                    bool guard)
1442 {
1443         if (guard && !(vstart & ~PUD_MASK) && (vend - vstart) >= PUD_SIZE)
1444                 return true;
1445 
1446         return false;
1447 }
1448 
1449 static unsigned long __ref kernel_map_hugepmd(unsigned long vstart,
1450                                               unsigned long vend,
1451                                               pmd_t *pmd)
1452 {
1453         const unsigned long mask256mb = (1UL << 28) - 1UL;
1454         const unsigned long mask2gb = (1UL << 31) - 1UL;
1455         u64 pte_val = vstart;
1456 
1457         /* Each PMD is 8MB */
1458         if ((vstart & mask256mb) ||
1459             (vend - vstart <= mask256mb)) {
1460                 pte_val ^= kern_linear_pte_xor[0];
1461                 pmd_val(*pmd) = pte_val | _PAGE_PMD_HUGE;
1462 
1463                 return vstart + PMD_SIZE;
1464         }
1465 
1466         if ((vstart & mask2gb) ||
1467             (vend - vstart <= mask2gb)) {
1468                 pte_val ^= kern_linear_pte_xor[1];
1469                 pte_val |= _PAGE_PMD_HUGE;
1470                 vend = vstart + mask256mb + 1UL;
1471         } else {
1472                 pte_val ^= kern_linear_pte_xor[2];
1473                 pte_val |= _PAGE_PMD_HUGE;
1474                 vend = vstart + mask2gb + 1UL;
1475         }
1476 
1477         while (vstart < vend) {
1478                 pmd_val(*pmd) = pte_val;
1479 
1480                 pte_val += PMD_SIZE;
1481                 vstart += PMD_SIZE;
1482                 pmd++;
1483         }
1484 
1485         return vstart;
1486 }
1487 
1488 static bool kernel_can_map_hugepmd(unsigned long vstart, unsigned long vend,
1489                                    bool guard)
1490 {
1491         if (guard && !(vstart & ~PMD_MASK) && (vend - vstart) >= PMD_SIZE)
1492                 return true;
1493 
1494         return false;
1495 }
1496 
1497 static unsigned long __ref kernel_map_range(unsigned long pstart,
1498                                             unsigned long pend, pgprot_t prot,
1499                                             bool use_huge)
1500 {
1501         unsigned long vstart = PAGE_OFFSET + pstart;
1502         unsigned long vend = PAGE_OFFSET + pend;
1503         unsigned long alloc_bytes = 0UL;
1504 
1505         if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
1506                 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1507                             vstart, vend);
1508                 prom_halt();
1509         }
1510 
1511         while (vstart < vend) {
1512                 unsigned long this_end, paddr = __pa(vstart);
1513                 pgd_t *pgd = pgd_offset_k(vstart);
1514                 pud_t *pud;
1515                 pmd_t *pmd;
1516                 pte_t *pte;
1517 
1518                 if (pgd_none(*pgd)) {
1519                         pud_t *new;
1520 
1521                         new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1522                         alloc_bytes += PAGE_SIZE;
1523                         pgd_populate(&init_mm, pgd, new);
1524                 }
1525                 pud = pud_offset(pgd, vstart);
1526                 if (pud_none(*pud)) {
1527                         pmd_t *new;
1528 
1529                         if (kernel_can_map_hugepud(vstart, vend, use_huge)) {
1530                                 vstart = kernel_map_hugepud(vstart, vend, pud);
1531                                 continue;
1532                         }
1533                         new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1534                         alloc_bytes += PAGE_SIZE;
1535                         pud_populate(&init_mm, pud, new);
1536                 }
1537 
1538                 pmd = pmd_offset(pud, vstart);
1539                 if (pmd_none(*pmd)) {
1540                         pte_t *new;
1541 
1542                         if (kernel_can_map_hugepmd(vstart, vend, use_huge)) {
1543                                 vstart = kernel_map_hugepmd(vstart, vend, pmd);
1544                                 continue;
1545                         }
1546                         new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1547                         alloc_bytes += PAGE_SIZE;
1548                         pmd_populate_kernel(&init_mm, pmd, new);
1549                 }
1550 
1551                 pte = pte_offset_kernel(pmd, vstart);
1552                 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1553                 if (this_end > vend)
1554                         this_end = vend;
1555 
1556                 while (vstart < this_end) {
1557                         pte_val(*pte) = (paddr | pgprot_val(prot));
1558 
1559                         vstart += PAGE_SIZE;
1560                         paddr += PAGE_SIZE;
1561                         pte++;
1562                 }
1563         }
1564 
1565         return alloc_bytes;
1566 }
1567 
1568 static void __init flush_all_kernel_tsbs(void)
1569 {
1570         int i;
1571 
1572         for (i = 0; i < KERNEL_TSB_NENTRIES; i++) {
1573                 struct tsb *ent = &swapper_tsb[i];
1574 
1575                 ent->tag = (1UL << TSB_TAG_INVALID_BIT);
1576         }
1577 #ifndef CONFIG_DEBUG_PAGEALLOC
1578         for (i = 0; i < KERNEL_TSB4M_NENTRIES; i++) {
1579                 struct tsb *ent = &swapper_4m_tsb[i];
1580 
1581                 ent->tag = (1UL << TSB_TAG_INVALID_BIT);
1582         }
1583 #endif
1584 }
1585 
1586 extern unsigned int kvmap_linear_patch[1];
1587 
1588 static void __init kernel_physical_mapping_init(void)
1589 {
1590         unsigned long i, mem_alloced = 0UL;
1591         bool use_huge = true;
1592 
1593 #ifdef CONFIG_DEBUG_PAGEALLOC
1594         use_huge = false;
1595 #endif
1596         for (i = 0; i < pall_ents; i++) {
1597                 unsigned long phys_start, phys_end;
1598 
1599                 phys_start = pall[i].phys_addr;
1600                 phys_end = phys_start + pall[i].reg_size;
1601 
1602                 mem_alloced += kernel_map_range(phys_start, phys_end,
1603                                                 PAGE_KERNEL, use_huge);
1604         }
1605 
1606         printk("Allocated %ld bytes for kernel page tables.\n",
1607                mem_alloced);
1608 
1609         kvmap_linear_patch[0] = 0x01000000; /* nop */
1610         flushi(&kvmap_linear_patch[0]);
1611 
1612         flush_all_kernel_tsbs();
1613 
1614         __flush_tlb_all();
1615 }
1616 
1617 #ifdef CONFIG_DEBUG_PAGEALLOC
1618 void kernel_map_pages(struct page *page, int numpages, int enable)
1619 {
1620         unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1621         unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1622 
1623         kernel_map_range(phys_start, phys_end,
1624                          (enable ? PAGE_KERNEL : __pgprot(0)), false);
1625 
1626         flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1627                                PAGE_OFFSET + phys_end);
1628 
1629         /* we should perform an IPI and flush all tlbs,
1630          * but that can deadlock->flush only current cpu.
1631          */
1632         __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1633                                  PAGE_OFFSET + phys_end);
1634 }
1635 #endif
1636 
1637 unsigned long __init find_ecache_flush_span(unsigned long size)
1638 {
1639         int i;
1640 
1641         for (i = 0; i < pavail_ents; i++) {
1642                 if (pavail[i].reg_size >= size)
1643                         return pavail[i].phys_addr;
1644         }
1645 
1646         return ~0UL;
1647 }
1648 
1649 unsigned long PAGE_OFFSET;
1650 EXPORT_SYMBOL(PAGE_OFFSET);
1651 
1652 unsigned long VMALLOC_END   = 0x0000010000000000UL;
1653 EXPORT_SYMBOL(VMALLOC_END);
1654 
1655 unsigned long sparc64_va_hole_top =    0xfffff80000000000UL;
1656 unsigned long sparc64_va_hole_bottom = 0x0000080000000000UL;
1657 
1658 static void __init setup_page_offset(void)
1659 {
1660         if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1661                 /* Cheetah/Panther support a full 64-bit virtual
1662                  * address, so we can use all that our page tables
1663                  * support.
1664                  */
1665                 sparc64_va_hole_top =    0xfff0000000000000UL;
1666                 sparc64_va_hole_bottom = 0x0010000000000000UL;
1667 
1668                 max_phys_bits = 42;
1669         } else if (tlb_type == hypervisor) {
1670                 switch (sun4v_chip_type) {
1671                 case SUN4V_CHIP_NIAGARA1:
1672                 case SUN4V_CHIP_NIAGARA2:
1673                         /* T1 and T2 support 48-bit virtual addresses.  */
1674                         sparc64_va_hole_top =    0xffff800000000000UL;
1675                         sparc64_va_hole_bottom = 0x0000800000000000UL;
1676 
1677                         max_phys_bits = 39;
1678                         break;
1679                 case SUN4V_CHIP_NIAGARA3:
1680                         /* T3 supports 48-bit virtual addresses.  */
1681                         sparc64_va_hole_top =    0xffff800000000000UL;
1682                         sparc64_va_hole_bottom = 0x0000800000000000UL;
1683 
1684                         max_phys_bits = 43;
1685                         break;
1686                 case SUN4V_CHIP_NIAGARA4:
1687                 case SUN4V_CHIP_NIAGARA5:
1688                 case SUN4V_CHIP_SPARC64X:
1689                 case SUN4V_CHIP_SPARC_M6:
1690                         /* T4 and later support 52-bit virtual addresses.  */
1691                         sparc64_va_hole_top =    0xfff8000000000000UL;
1692                         sparc64_va_hole_bottom = 0x0008000000000000UL;
1693                         max_phys_bits = 47;
1694                         break;
1695                 case SUN4V_CHIP_SPARC_M7:
1696                 default:
1697                         /* M7 and later support 52-bit virtual addresses.  */
1698                         sparc64_va_hole_top =    0xfff8000000000000UL;
1699                         sparc64_va_hole_bottom = 0x0008000000000000UL;
1700                         max_phys_bits = 49;
1701                         break;
1702                 }
1703         }
1704 
1705         if (max_phys_bits > MAX_PHYS_ADDRESS_BITS) {
1706                 prom_printf("MAX_PHYS_ADDRESS_BITS is too small, need %lu\n",
1707                             max_phys_bits);
1708                 prom_halt();
1709         }
1710 
1711         PAGE_OFFSET = sparc64_va_hole_top;
1712         VMALLOC_END = ((sparc64_va_hole_bottom >> 1) +
1713                        (sparc64_va_hole_bottom >> 2));
1714 
1715         pr_info("MM: PAGE_OFFSET is 0x%016lx (max_phys_bits == %lu)\n",
1716                 PAGE_OFFSET, max_phys_bits);
1717         pr_info("MM: VMALLOC [0x%016lx --> 0x%016lx]\n",
1718                 VMALLOC_START, VMALLOC_END);
1719         pr_info("MM: VMEMMAP [0x%016lx --> 0x%016lx]\n",
1720                 VMEMMAP_BASE, VMEMMAP_BASE << 1);
1721 }
1722 
1723 static void __init tsb_phys_patch(void)
1724 {
1725         struct tsb_ldquad_phys_patch_entry *pquad;
1726         struct tsb_phys_patch_entry *p;
1727 
1728         pquad = &__tsb_ldquad_phys_patch;
1729         while (pquad < &__tsb_ldquad_phys_patch_end) {
1730                 unsigned long addr = pquad->addr;
1731 
1732                 if (tlb_type == hypervisor)
1733                         *(unsigned int *) addr = pquad->sun4v_insn;
1734                 else
1735                         *(unsigned int *) addr = pquad->sun4u_insn;
1736                 wmb();
1737                 __asm__ __volatile__("flush     %0"
1738                                      : /* no outputs */
1739                                      : "r" (addr));
1740 
1741                 pquad++;
1742         }
1743 
1744         p = &__tsb_phys_patch;
1745         while (p < &__tsb_phys_patch_end) {
1746                 unsigned long addr = p->addr;
1747 
1748                 *(unsigned int *) addr = p->insn;
1749                 wmb();
1750                 __asm__ __volatile__("flush     %0"
1751                                      : /* no outputs */
1752                                      : "r" (addr));
1753 
1754                 p++;
1755         }
1756 }
1757 
1758 /* Don't mark as init, we give this to the Hypervisor.  */
1759 #ifndef CONFIG_DEBUG_PAGEALLOC
1760 #define NUM_KTSB_DESCR  2
1761 #else
1762 #define NUM_KTSB_DESCR  1
1763 #endif
1764 static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
1765 
1766 /* The swapper TSBs are loaded with a base sequence of:
1767  *
1768  *      sethi   %uhi(SYMBOL), REG1
1769  *      sethi   %hi(SYMBOL), REG2
1770  *      or      REG1, %ulo(SYMBOL), REG1
1771  *      or      REG2, %lo(SYMBOL), REG2
1772  *      sllx    REG1, 32, REG1
1773  *      or      REG1, REG2, REG1
1774  *
1775  * When we use physical addressing for the TSB accesses, we patch the
1776  * first four instructions in the above sequence.
1777  */
1778 
1779 static void patch_one_ktsb_phys(unsigned int *start, unsigned int *end, unsigned long pa)
1780 {
1781         unsigned long high_bits, low_bits;
1782 
1783         high_bits = (pa >> 32) & 0xffffffff;
1784         low_bits = (pa >> 0) & 0xffffffff;
1785 
1786         while (start < end) {
1787                 unsigned int *ia = (unsigned int *)(unsigned long)*start;
1788 
1789                 ia[0] = (ia[0] & ~0x3fffff) | (high_bits >> 10);
1790                 __asm__ __volatile__("flush     %0" : : "r" (ia));
1791 
1792                 ia[1] = (ia[1] & ~0x3fffff) | (low_bits >> 10);
1793                 __asm__ __volatile__("flush     %0" : : "r" (ia + 1));
1794 
1795                 ia[2] = (ia[2] & ~0x1fff) | (high_bits & 0x3ff);
1796                 __asm__ __volatile__("flush     %0" : : "r" (ia + 2));
1797 
1798                 ia[3] = (ia[3] & ~0x1fff) | (low_bits & 0x3ff);
1799                 __asm__ __volatile__("flush     %0" : : "r" (ia + 3));
1800 
1801                 start++;
1802         }
1803 }
1804 
1805 static void ktsb_phys_patch(void)
1806 {
1807         extern unsigned int __swapper_tsb_phys_patch;
1808         extern unsigned int __swapper_tsb_phys_patch_end;
1809         unsigned long ktsb_pa;
1810 
1811         ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1812         patch_one_ktsb_phys(&__swapper_tsb_phys_patch,
1813                             &__swapper_tsb_phys_patch_end, ktsb_pa);
1814 #ifndef CONFIG_DEBUG_PAGEALLOC
1815         {
1816         extern unsigned int __swapper_4m_tsb_phys_patch;
1817         extern unsigned int __swapper_4m_tsb_phys_patch_end;
1818         ktsb_pa = (kern_base +
1819                    ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1820         patch_one_ktsb_phys(&__swapper_4m_tsb_phys_patch,
1821                             &__swapper_4m_tsb_phys_patch_end, ktsb_pa);
1822         }
1823 #endif
1824 }
1825 
1826 static void __init sun4v_ktsb_init(void)
1827 {
1828         unsigned long ktsb_pa;
1829 
1830         /* First KTSB for PAGE_SIZE mappings.  */
1831         ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1832 
1833         switch (PAGE_SIZE) {
1834         case 8 * 1024:
1835         default:
1836                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
1837                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
1838                 break;
1839 
1840         case 64 * 1024:
1841                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
1842                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
1843                 break;
1844 
1845         case 512 * 1024:
1846                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
1847                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
1848                 break;
1849 
1850         case 4 * 1024 * 1024:
1851                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
1852                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
1853                 break;
1854         }
1855 
1856         ktsb_descr[0].assoc = 1;
1857         ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
1858         ktsb_descr[0].ctx_idx = 0;
1859         ktsb_descr[0].tsb_base = ktsb_pa;
1860         ktsb_descr[0].resv = 0;
1861 
1862 #ifndef CONFIG_DEBUG_PAGEALLOC
1863         /* Second KTSB for 4MB/256MB/2GB/16GB mappings.  */
1864         ktsb_pa = (kern_base +
1865                    ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1866 
1867         ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
1868         ktsb_descr[1].pgsz_mask = ((HV_PGSZ_MASK_4MB |
1869                                     HV_PGSZ_MASK_256MB |
1870                                     HV_PGSZ_MASK_2GB |
1871                                     HV_PGSZ_MASK_16GB) &
1872                                    cpu_pgsz_mask);
1873         ktsb_descr[1].assoc = 1;
1874         ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
1875         ktsb_descr[1].ctx_idx = 0;
1876         ktsb_descr[1].tsb_base = ktsb_pa;
1877         ktsb_descr[1].resv = 0;
1878 #endif
1879 }
1880 
1881 void sun4v_ktsb_register(void)
1882 {
1883         unsigned long pa, ret;
1884 
1885         pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
1886 
1887         ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa);
1888         if (ret != 0) {
1889                 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
1890                             "errors with %lx\n", pa, ret);
1891                 prom_halt();
1892         }
1893 }
1894 
1895 static void __init sun4u_linear_pte_xor_finalize(void)
1896 {
1897 #ifndef CONFIG_DEBUG_PAGEALLOC
1898         /* This is where we would add Panther support for
1899          * 32MB and 256MB pages.
1900          */
1901 #endif
1902 }
1903 
1904 static void __init sun4v_linear_pte_xor_finalize(void)
1905 {
1906 #ifndef CONFIG_DEBUG_PAGEALLOC
1907         if (cpu_pgsz_mask & HV_PGSZ_MASK_256MB) {
1908                 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
1909                         PAGE_OFFSET;
1910                 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1911                                            _PAGE_P_4V | _PAGE_W_4V);
1912         } else {
1913                 kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
1914         }
1915 
1916         if (cpu_pgsz_mask & HV_PGSZ_MASK_2GB) {
1917                 kern_linear_pte_xor[2] = (_PAGE_VALID | _PAGE_SZ2GB_4V) ^
1918                         PAGE_OFFSET;
1919                 kern_linear_pte_xor[2] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1920                                            _PAGE_P_4V | _PAGE_W_4V);
1921         } else {
1922                 kern_linear_pte_xor[2] = kern_linear_pte_xor[1];
1923         }
1924 
1925         if (cpu_pgsz_mask & HV_PGSZ_MASK_16GB) {
1926                 kern_linear_pte_xor[3] = (_PAGE_VALID | _PAGE_SZ16GB_4V) ^
1927                         PAGE_OFFSET;
1928                 kern_linear_pte_xor[3] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1929                                            _PAGE_P_4V | _PAGE_W_4V);
1930         } else {
1931                 kern_linear_pte_xor[3] = kern_linear_pte_xor[2];
1932         }
1933 #endif
1934 }
1935 
1936 /* paging_init() sets up the page tables */
1937 
1938 static unsigned long last_valid_pfn;
1939 
1940 static void sun4u_pgprot_init(void);
1941 static void sun4v_pgprot_init(void);
1942 
1943 void __init paging_init(void)
1944 {
1945         unsigned long end_pfn, shift, phys_base;
1946         unsigned long real_end, i;
1947         int node;
1948 
1949         setup_page_offset();
1950 
1951         /* These build time checkes make sure that the dcache_dirty_cpu()
1952          * page->flags usage will work.
1953          *
1954          * When a page gets marked as dcache-dirty, we store the
1955          * cpu number starting at bit 32 in the page->flags.  Also,
1956          * functions like clear_dcache_dirty_cpu use the cpu mask
1957          * in 13-bit signed-immediate instruction fields.
1958          */
1959 
1960         /*
1961          * Page flags must not reach into upper 32 bits that are used
1962          * for the cpu number
1963          */
1964         BUILD_BUG_ON(NR_PAGEFLAGS > 32);
1965 
1966         /*
1967          * The bit fields placed in the high range must not reach below
1968          * the 32 bit boundary. Otherwise we cannot place the cpu field
1969          * at the 32 bit boundary.
1970          */
1971         BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH +
1972                 ilog2(roundup_pow_of_two(NR_CPUS)) > 32);
1973 
1974         BUILD_BUG_ON(NR_CPUS > 4096);
1975 
1976         kern_base = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB;
1977         kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1978 
1979         /* Invalidate both kernel TSBs.  */
1980         memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
1981 #ifndef CONFIG_DEBUG_PAGEALLOC
1982         memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
1983 #endif
1984 
1985         if (tlb_type == hypervisor)
1986                 sun4v_pgprot_init();
1987         else
1988                 sun4u_pgprot_init();
1989 
1990         if (tlb_type == cheetah_plus ||
1991             tlb_type == hypervisor) {
1992                 tsb_phys_patch();
1993                 ktsb_phys_patch();
1994         }
1995 
1996         if (tlb_type == hypervisor)
1997                 sun4v_patch_tlb_handlers();
1998 
1999         /* Find available physical memory...
2000          *
2001          * Read it twice in order to work around a bug in openfirmware.
2002          * The call to grab this table itself can cause openfirmware to
2003          * allocate memory, which in turn can take away some space from
2004          * the list of available memory.  Reading it twice makes sure
2005          * we really do get the final value.
2006          */
2007         read_obp_translations();
2008         read_obp_memory("reg", &pall[0], &pall_ents);
2009         read_obp_memory("available", &pavail[0], &pavail_ents);
2010         read_obp_memory("available", &pavail[0], &pavail_ents);
2011 
2012         phys_base = 0xffffffffffffffffUL;
2013         for (i = 0; i < pavail_ents; i++) {
2014                 phys_base = min(phys_base, pavail[i].phys_addr);
2015                 memblock_add(pavail[i].phys_addr, pavail[i].reg_size);
2016         }
2017 
2018         memblock_reserve(kern_base, kern_size);
2019 
2020         find_ramdisk(phys_base);
2021 
2022         memblock_enforce_memory_limit(cmdline_memory_size);
2023 
2024         memblock_allow_resize();
2025         memblock_dump_all();
2026 
2027         set_bit(0, mmu_context_bmap);
2028 
2029         shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
2030 
2031         real_end = (unsigned long)_end;
2032         num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << ILOG2_4MB);
2033         printk("Kernel: Using %d locked TLB entries for main kernel image.\n",
2034                num_kernel_image_mappings);
2035 
2036         /* Set kernel pgd to upper alias so physical page computations
2037          * work.
2038          */
2039         init_mm.pgd += ((shift) / (sizeof(pgd_t)));
2040         
2041         memset(swapper_pg_dir, 0, sizeof(swapper_pg_dir));
2042 
2043         inherit_prom_mappings();
2044         
2045         /* Ok, we can use our TLB miss and window trap handlers safely.  */
2046         setup_tba();
2047 
2048         __flush_tlb_all();
2049 
2050         prom_build_devicetree();
2051         of_populate_present_mask();
2052 #ifndef CONFIG_SMP
2053         of_fill_in_cpu_data();
2054 #endif
2055 
2056         if (tlb_type == hypervisor) {
2057                 sun4v_mdesc_init();
2058                 mdesc_populate_present_mask(cpu_all_mask);
2059 #ifndef CONFIG_SMP
2060                 mdesc_fill_in_cpu_data(cpu_all_mask);
2061 #endif
2062                 mdesc_get_page_sizes(cpu_all_mask, &cpu_pgsz_mask);
2063 
2064                 sun4v_linear_pte_xor_finalize();
2065 
2066                 sun4v_ktsb_init();
2067                 sun4v_ktsb_register();
2068         } else {
2069                 unsigned long impl, ver;
2070 
2071                 cpu_pgsz_mask = (HV_PGSZ_MASK_8K | HV_PGSZ_MASK_64K |
2072                                  HV_PGSZ_MASK_512K | HV_PGSZ_MASK_4MB);
2073 
2074                 __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
2075                 impl = ((ver >> 32) & 0xffff);
2076                 if (impl == PANTHER_IMPL)
2077                         cpu_pgsz_mask |= (HV_PGSZ_MASK_32MB |
2078                                           HV_PGSZ_MASK_256MB);
2079 
2080                 sun4u_linear_pte_xor_finalize();
2081         }
2082 
2083         /* Flush the TLBs and the 4M TSB so that the updated linear
2084          * pte XOR settings are realized for all mappings.
2085          */
2086         __flush_tlb_all();
2087 #ifndef CONFIG_DEBUG_PAGEALLOC
2088         memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
2089 #endif
2090         __flush_tlb_all();
2091 
2092         /* Setup bootmem... */
2093         last_valid_pfn = end_pfn = bootmem_init(phys_base);
2094 
2095         /* Once the OF device tree and MDESC have been setup, we know
2096          * the list of possible cpus.  Therefore we can allocate the
2097          * IRQ stacks.
2098          */
2099         for_each_possible_cpu(i) {
2100                 node = cpu_to_node(i);
2101 
2102                 softirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node),
2103                                                         THREAD_SIZE,
2104                                                         THREAD_SIZE, 0);
2105                 hardirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node),
2106                                                         THREAD_SIZE,
2107                                                         THREAD_SIZE, 0);
2108         }
2109 
2110         kernel_physical_mapping_init();
2111 
2112         {
2113                 unsigned long max_zone_pfns[MAX_NR_ZONES];
2114 
2115                 memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
2116 
2117                 max_zone_pfns[ZONE_NORMAL] = end_pfn;
2118 
2119                 free_area_init_nodes(max_zone_pfns);
2120         }
2121 
2122         printk("Booting Linux...\n");
2123 }
2124 
2125 int page_in_phys_avail(unsigned long paddr)
2126 {
2127         int i;
2128 
2129         paddr &= PAGE_MASK;
2130 
2131         for (i = 0; i < pavail_ents; i++) {
2132                 unsigned long start, end;
2133 
2134                 start = pavail[i].phys_addr;
2135                 end = start + pavail[i].reg_size;
2136 
2137                 if (paddr >= start && paddr < end)
2138                         return 1;
2139         }
2140         if (paddr >= kern_base && paddr < (kern_base + kern_size))
2141                 return 1;
2142 #ifdef CONFIG_BLK_DEV_INITRD
2143         if (paddr >= __pa(initrd_start) &&
2144             paddr < __pa(PAGE_ALIGN(initrd_end)))
2145                 return 1;
2146 #endif
2147 
2148         return 0;
2149 }
2150 
2151 static void __init register_page_bootmem_info(void)
2152 {
2153 #ifdef CONFIG_NEED_MULTIPLE_NODES
2154         int i;
2155 
2156         for_each_online_node(i)
2157                 if (NODE_DATA(i)->node_spanned_pages)
2158                         register_page_bootmem_info_node(NODE_DATA(i));
2159 #endif
2160 }
2161 void __init mem_init(void)
2162 {
2163         high_memory = __va(last_valid_pfn << PAGE_SHIFT);
2164 
2165         register_page_bootmem_info();
2166         free_all_bootmem();
2167 
2168         /*
2169          * Set up the zero page, mark it reserved, so that page count
2170          * is not manipulated when freeing the page from user ptes.
2171          */
2172         mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
2173         if (mem_map_zero == NULL) {
2174                 prom_printf("paging_init: Cannot alloc zero page.\n");
2175                 prom_halt();
2176         }
2177         mark_page_reserved(mem_map_zero);
2178 
2179         mem_init_print_info(NULL);
2180 
2181         if (tlb_type == cheetah || tlb_type == cheetah_plus)
2182                 cheetah_ecache_flush_init();
2183 }
2184 
2185 void free_initmem(void)
2186 {
2187         unsigned long addr, initend;
2188         int do_free = 1;
2189 
2190         /* If the physical memory maps were trimmed by kernel command
2191          * line options, don't even try freeing this initmem stuff up.
2192          * The kernel image could have been in the trimmed out region
2193          * and if so the freeing below will free invalid page structs.
2194          */
2195         if (cmdline_memory_size)
2196                 do_free = 0;
2197 
2198         /*
2199          * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
2200          */
2201         addr = PAGE_ALIGN((unsigned long)(__init_begin));
2202         initend = (unsigned long)(__init_end) & PAGE_MASK;
2203         for (; addr < initend; addr += PAGE_SIZE) {
2204                 unsigned long page;
2205 
2206                 page = (addr +
2207                         ((unsigned long) __va(kern_base)) -
2208                         ((unsigned long) KERNBASE));
2209                 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
2210 
2211                 if (do_free)
2212                         free_reserved_page(virt_to_page(page));
2213         }
2214 }
2215 
2216 #ifdef CONFIG_BLK_DEV_INITRD
2217 void free_initrd_mem(unsigned long start, unsigned long end)
2218 {
2219         free_reserved_area((void *)start, (void *)end, POISON_FREE_INITMEM,
2220                            "initrd");
2221 }
2222 #endif
2223 
2224 #define _PAGE_CACHE_4U  (_PAGE_CP_4U | _PAGE_CV_4U)
2225 #define _PAGE_CACHE_4V  (_PAGE_CP_4V | _PAGE_CV_4V)
2226 #define __DIRTY_BITS_4U  (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
2227 #define __DIRTY_BITS_4V  (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
2228 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
2229 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
2230 
2231 pgprot_t PAGE_KERNEL __read_mostly;
2232 EXPORT_SYMBOL(PAGE_KERNEL);
2233 
2234 pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
2235 pgprot_t PAGE_COPY __read_mostly;
2236 
2237 pgprot_t PAGE_SHARED __read_mostly;
2238 EXPORT_SYMBOL(PAGE_SHARED);
2239 
2240 unsigned long pg_iobits __read_mostly;
2241 
2242 unsigned long _PAGE_IE __read_mostly;
2243 EXPORT_SYMBOL(_PAGE_IE);
2244 
2245 unsigned long _PAGE_E __read_mostly;
2246 EXPORT_SYMBOL(_PAGE_E);
2247 
2248 unsigned long _PAGE_CACHE __read_mostly;
2249 EXPORT_SYMBOL(_PAGE_CACHE);
2250 
2251 #ifdef CONFIG_SPARSEMEM_VMEMMAP
2252 int __meminit vmemmap_populate(unsigned long vstart, unsigned long vend,
2253                                int node)
2254 {
2255         unsigned long pte_base;
2256 
2257         pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2258                     _PAGE_CP_4U | _PAGE_CV_4U |
2259                     _PAGE_P_4U | _PAGE_W_4U);
2260         if (tlb_type == hypervisor)
2261                 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2262                             _PAGE_CP_4V | _PAGE_CV_4V |
2263                             _PAGE_P_4V | _PAGE_W_4V);
2264 
2265         pte_base |= _PAGE_PMD_HUGE;
2266 
2267         vstart = vstart & PMD_MASK;
2268         vend = ALIGN(vend, PMD_SIZE);
2269         for (; vstart < vend; vstart += PMD_SIZE) {
2270                 pgd_t *pgd = pgd_offset_k(vstart);
2271                 unsigned long pte;
2272                 pud_t *pud;
2273                 pmd_t *pmd;
2274 
2275                 if (pgd_none(*pgd)) {
2276                         pud_t *new = vmemmap_alloc_block(PAGE_SIZE, node);
2277 
2278                         if (!new)
2279                                 return -ENOMEM;
2280                         pgd_populate(&init_mm, pgd, new);
2281                 }
2282 
2283                 pud = pud_offset(pgd, vstart);
2284                 if (pud_none(*pud)) {
2285                         pmd_t *new = vmemmap_alloc_block(PAGE_SIZE, node);
2286 
2287                         if (!new)
2288                                 return -ENOMEM;
2289                         pud_populate(&init_mm, pud, new);
2290                 }
2291 
2292                 pmd = pmd_offset(pud, vstart);
2293 
2294                 pte = pmd_val(*pmd);
2295                 if (!(pte & _PAGE_VALID)) {
2296                         void *block = vmemmap_alloc_block(PMD_SIZE, node);
2297 
2298                         if (!block)
2299                                 return -ENOMEM;
2300 
2301                         pmd_val(*pmd) = pte_base | __pa(block);
2302                 }
2303         }
2304 
2305         return 0;
2306 }
2307 
2308 void vmemmap_free(unsigned long start, unsigned long end)
2309 {
2310 }
2311 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
2312 
2313 static void prot_init_common(unsigned long page_none,
2314                              unsigned long page_shared,
2315                              unsigned long page_copy,
2316                              unsigned long page_readonly,
2317                              unsigned long page_exec_bit)
2318 {
2319         PAGE_COPY = __pgprot(page_copy);
2320         PAGE_SHARED = __pgprot(page_shared);
2321 
2322         protection_map[0x0] = __pgprot(page_none);
2323         protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
2324         protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
2325         protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
2326         protection_map[0x4] = __pgprot(page_readonly);
2327         protection_map[0x5] = __pgprot(page_readonly);
2328         protection_map[0x6] = __pgprot(page_copy);
2329         protection_map[0x7] = __pgprot(page_copy);
2330         protection_map[0x8] = __pgprot(page_none);
2331         protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
2332         protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
2333         protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
2334         protection_map[0xc] = __pgprot(page_readonly);
2335         protection_map[0xd] = __pgprot(page_readonly);
2336         protection_map[0xe] = __pgprot(page_shared);
2337         protection_map[0xf] = __pgprot(page_shared);
2338 }
2339 
2340 static void __init sun4u_pgprot_init(void)
2341 {
2342         unsigned long page_none, page_shared, page_copy, page_readonly;
2343         unsigned long page_exec_bit;
2344         int i;
2345 
2346         PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2347                                 _PAGE_CACHE_4U | _PAGE_P_4U |
2348                                 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2349                                 _PAGE_EXEC_4U);
2350         PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2351                                        _PAGE_CACHE_4U | _PAGE_P_4U |
2352                                        __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2353                                        _PAGE_EXEC_4U | _PAGE_L_4U);
2354 
2355         _PAGE_IE = _PAGE_IE_4U;
2356         _PAGE_E = _PAGE_E_4U;
2357         _PAGE_CACHE = _PAGE_CACHE_4U;
2358 
2359         pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
2360                      __ACCESS_BITS_4U | _PAGE_E_4U);
2361 
2362 #ifdef CONFIG_DEBUG_PAGEALLOC
2363         kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET;
2364 #else
2365         kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
2366                 PAGE_OFFSET;
2367 #endif
2368         kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
2369                                    _PAGE_P_4U | _PAGE_W_4U);
2370 
2371         for (i = 1; i < 4; i++)
2372                 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
2373 
2374         _PAGE_ALL_SZ_BITS =  (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
2375                               _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
2376                               _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
2377 
2378 
2379         page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
2380         page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2381                        __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
2382         page_copy   = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2383                        __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2384         page_readonly   = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2385                            __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2386 
2387         page_exec_bit = _PAGE_EXEC_4U;
2388 
2389         prot_init_common(page_none, page_shared, page_copy, page_readonly,
2390                          page_exec_bit);
2391 }
2392 
2393 static void __init sun4v_pgprot_init(void)
2394 {
2395         unsigned long page_none, page_shared, page_copy, page_readonly;
2396         unsigned long page_exec_bit;
2397         int i;
2398 
2399         PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
2400                                 _PAGE_CACHE_4V | _PAGE_P_4V |
2401                                 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
2402                                 _PAGE_EXEC_4V);
2403         PAGE_KERNEL_LOCKED = PAGE_KERNEL;
2404 
2405         _PAGE_IE = _PAGE_IE_4V;
2406         _PAGE_E = _PAGE_E_4V;
2407         _PAGE_CACHE = _PAGE_CACHE_4V;
2408 
2409 #ifdef CONFIG_DEBUG_PAGEALLOC
2410         kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET;
2411 #else
2412         kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
2413                 PAGE_OFFSET;
2414 #endif
2415         kern_linear_pte_xor[0] |= (_PAGE_CP_4V | _PAGE_CV_4V |
2416                                    _PAGE_P_4V | _PAGE_W_4V);
2417 
2418         for (i = 1; i < 4; i++)
2419                 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
2420 
2421         pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
2422                      __ACCESS_BITS_4V | _PAGE_E_4V);
2423 
2424         _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
2425                              _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
2426                              _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
2427                              _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
2428 
2429         page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | _PAGE_CACHE_4V;
2430         page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2431                        __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
2432         page_copy   = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2433                        __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2434         page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2435                          __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2436 
2437         page_exec_bit = _PAGE_EXEC_4V;
2438 
2439         prot_init_common(page_none, page_shared, page_copy, page_readonly,
2440                          page_exec_bit);
2441 }
2442 
2443 unsigned long pte_sz_bits(unsigned long sz)
2444 {
2445         if (tlb_type == hypervisor) {
2446                 switch (sz) {
2447                 case 8 * 1024:
2448                 default:
2449                         return _PAGE_SZ8K_4V;
2450                 case 64 * 1024:
2451                         return _PAGE_SZ64K_4V;
2452                 case 512 * 1024:
2453                         return _PAGE_SZ512K_4V;
2454                 case 4 * 1024 * 1024:
2455                         return _PAGE_SZ4MB_4V;
2456                 }
2457         } else {
2458                 switch (sz) {
2459                 case 8 * 1024:
2460                 default:
2461                         return _PAGE_SZ8K_4U;
2462                 case 64 * 1024:
2463                         return _PAGE_SZ64K_4U;
2464                 case 512 * 1024:
2465                         return _PAGE_SZ512K_4U;
2466                 case 4 * 1024 * 1024:
2467                         return _PAGE_SZ4MB_4U;
2468                 }
2469         }
2470 }
2471 
2472 pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
2473 {
2474         pte_t pte;
2475 
2476         pte_val(pte)  = page | pgprot_val(pgprot_noncached(prot));
2477         pte_val(pte) |= (((unsigned long)space) << 32);
2478         pte_val(pte) |= pte_sz_bits(page_size);
2479 
2480         return pte;
2481 }
2482 
2483 static unsigned long kern_large_tte(unsigned long paddr)
2484 {
2485         unsigned long val;
2486 
2487         val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2488                _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
2489                _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
2490         if (tlb_type == hypervisor)
2491                 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2492                        _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_P_4V |
2493                        _PAGE_EXEC_4V | _PAGE_W_4V);
2494 
2495         return val | paddr;
2496 }
2497 
2498 /* If not locked, zap it. */
2499 void __flush_tlb_all(void)
2500 {
2501         unsigned long pstate;
2502         int i;
2503 
2504         __asm__ __volatile__("flushw\n\t"
2505                              "rdpr      %%pstate, %0\n\t"
2506                              "wrpr      %0, %1, %%pstate"
2507                              : "=r" (pstate)
2508                              : "i" (PSTATE_IE));
2509         if (tlb_type == hypervisor) {
2510                 sun4v_mmu_demap_all();
2511         } else if (tlb_type == spitfire) {
2512                 for (i = 0; i < 64; i++) {
2513                         /* Spitfire Errata #32 workaround */
2514                         /* NOTE: Always runs on spitfire, so no
2515                          *       cheetah+ page size encodings.
2516                          */
2517                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
2518                                              "flush     %%g6"
2519                                              : /* No outputs */
2520                                              : "r" (0),
2521                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2522 
2523                         if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
2524                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2525                                                      "membar #Sync"
2526                                                      : /* no outputs */
2527                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
2528                                 spitfire_put_dtlb_data(i, 0x0UL);
2529                         }
2530 
2531                         /* Spitfire Errata #32 workaround */
2532                         /* NOTE: Always runs on spitfire, so no
2533                          *       cheetah+ page size encodings.
2534                          */
2535                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
2536                                              "flush     %%g6"
2537                                              : /* No outputs */
2538                                              : "r" (0),
2539                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2540 
2541                         if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
2542                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2543                                                      "membar #Sync"
2544                                                      : /* no outputs */
2545                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
2546                                 spitfire_put_itlb_data(i, 0x0UL);
2547                         }
2548                 }
2549         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
2550                 cheetah_flush_dtlb_all();
2551                 cheetah_flush_itlb_all();
2552         }
2553         __asm__ __volatile__("wrpr      %0, 0, %%pstate"
2554                              : : "r" (pstate));
2555 }
2556 
2557 pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
2558                             unsigned long address)
2559 {
2560         struct page *page = alloc_page(GFP_KERNEL | __GFP_NOTRACK |
2561                                        __GFP_REPEAT | __GFP_ZERO);
2562         pte_t *pte = NULL;
2563 
2564         if (page)
2565                 pte = (pte_t *) page_address(page);
2566 
2567         return pte;
2568 }
2569 
2570 pgtable_t pte_alloc_one(struct mm_struct *mm,
2571                         unsigned long address)
2572 {
2573         struct page *page = alloc_page(GFP_KERNEL | __GFP_NOTRACK |
2574                                        __GFP_REPEAT | __GFP_ZERO);
2575         if (!page)
2576                 return NULL;
2577         if (!pgtable_page_ctor(page)) {
2578                 free_hot_cold_page(page, 0);
2579                 return NULL;
2580         }
2581         return (pte_t *) page_address(page);
2582 }
2583 
2584 void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
2585 {
2586         free_page((unsigned long)pte);
2587 }
2588 
2589 static void __pte_free(pgtable_t pte)
2590 {
2591         struct page *page = virt_to_page(pte);
2592 
2593         pgtable_page_dtor(page);
2594         __free_page(page);
2595 }
2596 
2597 void pte_free(struct mm_struct *mm, pgtable_t pte)
2598 {
2599         __pte_free(pte);
2600 }
2601 
2602 void pgtable_free(void *table, bool is_page)
2603 {
2604         if (is_page)
2605                 __pte_free(table);
2606         else
2607                 kmem_cache_free(pgtable_cache, table);
2608 }
2609 
2610 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
2611 void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
2612                           pmd_t *pmd)
2613 {
2614         unsigned long pte, flags;
2615         struct mm_struct *mm;
2616         pmd_t entry = *pmd;
2617 
2618         if (!pmd_large(entry) || !pmd_young(entry))
2619                 return;
2620 
2621         pte = pmd_val(entry);
2622 
2623         /* Don't insert a non-valid PMD into the TSB, we'll deadlock.  */
2624         if (!(pte & _PAGE_VALID))
2625                 return;
2626 
2627         /* We are fabricating 8MB pages using 4MB real hw pages.  */
2628         pte |= (addr & (1UL << REAL_HPAGE_SHIFT));
2629 
2630         mm = vma->vm_mm;
2631 
2632         spin_lock_irqsave(&mm->context.lock, flags);
2633 
2634         if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL)
2635                 __update_mmu_tsb_insert(mm, MM_TSB_HUGE, REAL_HPAGE_SHIFT,
2636                                         addr, pte);
2637 
2638         spin_unlock_irqrestore(&mm->context.lock, flags);
2639 }
2640 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
2641 
2642 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
2643 static void context_reload(void *__data)
2644 {
2645         struct mm_struct *mm = __data;
2646 
2647         if (mm == current->mm)
2648                 load_secondary_context(mm);
2649 }
2650 
2651 void hugetlb_setup(struct pt_regs *regs)
2652 {
2653         struct mm_struct *mm = current->mm;
2654         struct tsb_config *tp;
2655 
2656         if (in_atomic() || !mm) {
2657                 const struct exception_table_entry *entry;
2658 
2659                 entry = search_exception_tables(regs->tpc);
2660                 if (entry) {
2661                         regs->tpc = entry->fixup;
2662                         regs->tnpc = regs->tpc + 4;
2663                         return;
2664                 }
2665                 pr_alert("Unexpected HugeTLB setup in atomic context.\n");
2666                 die_if_kernel("HugeTSB in atomic", regs);
2667         }
2668 
2669         tp = &mm->context.tsb_block[MM_TSB_HUGE];
2670         if (likely(tp->tsb == NULL))
2671                 tsb_grow(mm, MM_TSB_HUGE, 0);
2672 
2673         tsb_context_switch(mm);
2674         smp_tsb_sync(mm);
2675 
2676         /* On UltraSPARC-III+ and later, configure the second half of
2677          * the Data-TLB for huge pages.
2678          */
2679         if (tlb_type == cheetah_plus) {
2680                 unsigned long ctx;
2681 
2682                 spin_lock(&ctx_alloc_lock);
2683                 ctx = mm->context.sparc64_ctx_val;
2684                 ctx &= ~CTX_PGSZ_MASK;
2685                 ctx |= CTX_PGSZ_BASE << CTX_PGSZ0_SHIFT;
2686                 ctx |= CTX_PGSZ_HUGE << CTX_PGSZ1_SHIFT;
2687 
2688                 if (ctx != mm->context.sparc64_ctx_val) {
2689                         /* When changing the page size fields, we
2690                          * must perform a context flush so that no
2691                          * stale entries match.  This flush must
2692                          * occur with the original context register
2693                          * settings.
2694                          */
2695                         do_flush_tlb_mm(mm);
2696 
2697                         /* Reload the context register of all processors
2698                          * also executing in this address space.
2699                          */
2700                         mm->context.sparc64_ctx_val = ctx;
2701                         on_each_cpu(context_reload, mm, 0);
2702                 }
2703                 spin_unlock(&ctx_alloc_lock);
2704         }
2705 }
2706 #endif
2707 
2708 #ifdef CONFIG_SMP
2709 #define do_flush_tlb_kernel_range       smp_flush_tlb_kernel_range
2710 #else
2711 #define do_flush_tlb_kernel_range       __flush_tlb_kernel_range
2712 #endif
2713 
2714 void flush_tlb_kernel_range(unsigned long start, unsigned long end)
2715 {
2716         if (start < HI_OBP_ADDRESS && end > LOW_OBP_ADDRESS) {
2717                 if (start < LOW_OBP_ADDRESS) {
2718                         flush_tsb_kernel_range(start, LOW_OBP_ADDRESS);
2719                         do_flush_tlb_kernel_range(start, LOW_OBP_ADDRESS);
2720                 }
2721                 if (end > HI_OBP_ADDRESS) {
2722                         flush_tsb_kernel_range(HI_OBP_ADDRESS, end);
2723                         do_flush_tlb_kernel_range(HI_OBP_ADDRESS, end);
2724                 }
2725         } else {
2726                 flush_tsb_kernel_range(start, end);
2727                 do_flush_tlb_kernel_range(start, end);
2728         }
2729 }
2730 

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