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Linux/arch/sparc/mm/init_64.c

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  1 /*
  2  *  arch/sparc64/mm/init.c
  3  *
  4  *  Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
  5  *  Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
  6  */
  7  
  8 #include <linux/module.h>
  9 #include <linux/kernel.h>
 10 #include <linux/sched.h>
 11 #include <linux/string.h>
 12 #include <linux/init.h>
 13 #include <linux/bootmem.h>
 14 #include <linux/mm.h>
 15 #include <linux/hugetlb.h>
 16 #include <linux/initrd.h>
 17 #include <linux/swap.h>
 18 #include <linux/pagemap.h>
 19 #include <linux/poison.h>
 20 #include <linux/fs.h>
 21 #include <linux/seq_file.h>
 22 #include <linux/kprobes.h>
 23 #include <linux/cache.h>
 24 #include <linux/sort.h>
 25 #include <linux/ioport.h>
 26 #include <linux/percpu.h>
 27 #include <linux/memblock.h>
 28 #include <linux/mmzone.h>
 29 #include <linux/gfp.h>
 30 
 31 #include <asm/head.h>
 32 #include <asm/page.h>
 33 #include <asm/pgalloc.h>
 34 #include <asm/pgtable.h>
 35 #include <asm/oplib.h>
 36 #include <asm/iommu.h>
 37 #include <asm/io.h>
 38 #include <asm/uaccess.h>
 39 #include <asm/mmu_context.h>
 40 #include <asm/tlbflush.h>
 41 #include <asm/dma.h>
 42 #include <asm/starfire.h>
 43 #include <asm/tlb.h>
 44 #include <asm/spitfire.h>
 45 #include <asm/sections.h>
 46 #include <asm/tsb.h>
 47 #include <asm/hypervisor.h>
 48 #include <asm/prom.h>
 49 #include <asm/mdesc.h>
 50 #include <asm/cpudata.h>
 51 #include <asm/setup.h>
 52 #include <asm/irq.h>
 53 
 54 #include "init_64.h"
 55 
 56 unsigned long kern_linear_pte_xor[4] __read_mostly;
 57 static unsigned long page_cache4v_flag;
 58 
 59 /* A bitmap, two bits for every 256MB of physical memory.  These two
 60  * bits determine what page size we use for kernel linear
 61  * translations.  They form an index into kern_linear_pte_xor[].  The
 62  * value in the indexed slot is XOR'd with the TLB miss virtual
 63  * address to form the resulting TTE.  The mapping is:
 64  *
 65  *      0       ==>     4MB
 66  *      1       ==>     256MB
 67  *      2       ==>     2GB
 68  *      3       ==>     16GB
 69  *
 70  * All sun4v chips support 256MB pages.  Only SPARC-T4 and later
 71  * support 2GB pages, and hopefully future cpus will support the 16GB
 72  * pages as well.  For slots 2 and 3, we encode a 256MB TTE xor there
 73  * if these larger page sizes are not supported by the cpu.
 74  *
 75  * It would be nice to determine this from the machine description
 76  * 'cpu' properties, but we need to have this table setup before the
 77  * MDESC is initialized.
 78  */
 79 
 80 #ifndef CONFIG_DEBUG_PAGEALLOC
 81 /* A special kernel TSB for 4MB, 256MB, 2GB and 16GB linear mappings.
 82  * Space is allocated for this right after the trap table in
 83  * arch/sparc64/kernel/head.S
 84  */
 85 extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
 86 #endif
 87 extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
 88 
 89 static unsigned long cpu_pgsz_mask;
 90 
 91 #define MAX_BANKS       1024
 92 
 93 static struct linux_prom64_registers pavail[MAX_BANKS];
 94 static int pavail_ents;
 95 
 96 static int cmp_p64(const void *a, const void *b)
 97 {
 98         const struct linux_prom64_registers *x = a, *y = b;
 99 
100         if (x->phys_addr > y->phys_addr)
101                 return 1;
102         if (x->phys_addr < y->phys_addr)
103                 return -1;
104         return 0;
105 }
106 
107 static void __init read_obp_memory(const char *property,
108                                    struct linux_prom64_registers *regs,
109                                    int *num_ents)
110 {
111         phandle node = prom_finddevice("/memory");
112         int prop_size = prom_getproplen(node, property);
113         int ents, ret, i;
114 
115         ents = prop_size / sizeof(struct linux_prom64_registers);
116         if (ents > MAX_BANKS) {
117                 prom_printf("The machine has more %s property entries than "
118                             "this kernel can support (%d).\n",
119                             property, MAX_BANKS);
120                 prom_halt();
121         }
122 
123         ret = prom_getproperty(node, property, (char *) regs, prop_size);
124         if (ret == -1) {
125                 prom_printf("Couldn't get %s property from /memory.\n",
126                                 property);
127                 prom_halt();
128         }
129 
130         /* Sanitize what we got from the firmware, by page aligning
131          * everything.
132          */
133         for (i = 0; i < ents; i++) {
134                 unsigned long base, size;
135 
136                 base = regs[i].phys_addr;
137                 size = regs[i].reg_size;
138 
139                 size &= PAGE_MASK;
140                 if (base & ~PAGE_MASK) {
141                         unsigned long new_base = PAGE_ALIGN(base);
142 
143                         size -= new_base - base;
144                         if ((long) size < 0L)
145                                 size = 0UL;
146                         base = new_base;
147                 }
148                 if (size == 0UL) {
149                         /* If it is empty, simply get rid of it.
150                          * This simplifies the logic of the other
151                          * functions that process these arrays.
152                          */
153                         memmove(&regs[i], &regs[i + 1],
154                                 (ents - i - 1) * sizeof(regs[0]));
155                         i--;
156                         ents--;
157                         continue;
158                 }
159                 regs[i].phys_addr = base;
160                 regs[i].reg_size = size;
161         }
162 
163         *num_ents = ents;
164 
165         sort(regs, ents, sizeof(struct linux_prom64_registers),
166              cmp_p64, NULL);
167 }
168 
169 /* Kernel physical address base and size in bytes.  */
170 unsigned long kern_base __read_mostly;
171 unsigned long kern_size __read_mostly;
172 
173 /* Initial ramdisk setup */
174 extern unsigned long sparc_ramdisk_image64;
175 extern unsigned int sparc_ramdisk_image;
176 extern unsigned int sparc_ramdisk_size;
177 
178 struct page *mem_map_zero __read_mostly;
179 EXPORT_SYMBOL(mem_map_zero);
180 
181 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
182 
183 unsigned long sparc64_kern_pri_context __read_mostly;
184 unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
185 unsigned long sparc64_kern_sec_context __read_mostly;
186 
187 int num_kernel_image_mappings;
188 
189 #ifdef CONFIG_DEBUG_DCFLUSH
190 atomic_t dcpage_flushes = ATOMIC_INIT(0);
191 #ifdef CONFIG_SMP
192 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
193 #endif
194 #endif
195 
196 inline void flush_dcache_page_impl(struct page *page)
197 {
198         BUG_ON(tlb_type == hypervisor);
199 #ifdef CONFIG_DEBUG_DCFLUSH
200         atomic_inc(&dcpage_flushes);
201 #endif
202 
203 #ifdef DCACHE_ALIASING_POSSIBLE
204         __flush_dcache_page(page_address(page),
205                             ((tlb_type == spitfire) &&
206                              page_mapping(page) != NULL));
207 #else
208         if (page_mapping(page) != NULL &&
209             tlb_type == spitfire)
210                 __flush_icache_page(__pa(page_address(page)));
211 #endif
212 }
213 
214 #define PG_dcache_dirty         PG_arch_1
215 #define PG_dcache_cpu_shift     32UL
216 #define PG_dcache_cpu_mask      \
217         ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
218 
219 #define dcache_dirty_cpu(page) \
220         (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
221 
222 static inline void set_dcache_dirty(struct page *page, int this_cpu)
223 {
224         unsigned long mask = this_cpu;
225         unsigned long non_cpu_bits;
226 
227         non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
228         mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
229 
230         __asm__ __volatile__("1:\n\t"
231                              "ldx       [%2], %%g7\n\t"
232                              "and       %%g7, %1, %%g1\n\t"
233                              "or        %%g1, %0, %%g1\n\t"
234                              "casx      [%2], %%g7, %%g1\n\t"
235                              "cmp       %%g7, %%g1\n\t"
236                              "bne,pn    %%xcc, 1b\n\t"
237                              " nop"
238                              : /* no outputs */
239                              : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
240                              : "g1", "g7");
241 }
242 
243 static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
244 {
245         unsigned long mask = (1UL << PG_dcache_dirty);
246 
247         __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
248                              "1:\n\t"
249                              "ldx       [%2], %%g7\n\t"
250                              "srlx      %%g7, %4, %%g1\n\t"
251                              "and       %%g1, %3, %%g1\n\t"
252                              "cmp       %%g1, %0\n\t"
253                              "bne,pn    %%icc, 2f\n\t"
254                              " andn     %%g7, %1, %%g1\n\t"
255                              "casx      [%2], %%g7, %%g1\n\t"
256                              "cmp       %%g7, %%g1\n\t"
257                              "bne,pn    %%xcc, 1b\n\t"
258                              " nop\n"
259                              "2:"
260                              : /* no outputs */
261                              : "r" (cpu), "r" (mask), "r" (&page->flags),
262                                "i" (PG_dcache_cpu_mask),
263                                "i" (PG_dcache_cpu_shift)
264                              : "g1", "g7");
265 }
266 
267 static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
268 {
269         unsigned long tsb_addr = (unsigned long) ent;
270 
271         if (tlb_type == cheetah_plus || tlb_type == hypervisor)
272                 tsb_addr = __pa(tsb_addr);
273 
274         __tsb_insert(tsb_addr, tag, pte);
275 }
276 
277 unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
278 
279 static void flush_dcache(unsigned long pfn)
280 {
281         struct page *page;
282 
283         page = pfn_to_page(pfn);
284         if (page) {
285                 unsigned long pg_flags;
286 
287                 pg_flags = page->flags;
288                 if (pg_flags & (1UL << PG_dcache_dirty)) {
289                         int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
290                                    PG_dcache_cpu_mask);
291                         int this_cpu = get_cpu();
292 
293                         /* This is just to optimize away some function calls
294                          * in the SMP case.
295                          */
296                         if (cpu == this_cpu)
297                                 flush_dcache_page_impl(page);
298                         else
299                                 smp_flush_dcache_page_impl(page, cpu);
300 
301                         clear_dcache_dirty_cpu(page, cpu);
302 
303                         put_cpu();
304                 }
305         }
306 }
307 
308 /* mm->context.lock must be held */
309 static void __update_mmu_tsb_insert(struct mm_struct *mm, unsigned long tsb_index,
310                                     unsigned long tsb_hash_shift, unsigned long address,
311                                     unsigned long tte)
312 {
313         struct tsb *tsb = mm->context.tsb_block[tsb_index].tsb;
314         unsigned long tag;
315 
316         if (unlikely(!tsb))
317                 return;
318 
319         tsb += ((address >> tsb_hash_shift) &
320                 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
321         tag = (address >> 22UL);
322         tsb_insert(tsb, tag, tte);
323 }
324 
325 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
326 static inline bool is_hugetlb_pte(pte_t pte)
327 {
328         if ((tlb_type == hypervisor &&
329              (pte_val(pte) & _PAGE_SZALL_4V) == _PAGE_SZHUGE_4V) ||
330             (tlb_type != hypervisor &&
331              (pte_val(pte) & _PAGE_SZALL_4U) == _PAGE_SZHUGE_4U))
332                 return true;
333         return false;
334 }
335 #endif
336 
337 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
338 {
339         struct mm_struct *mm;
340         unsigned long flags;
341         pte_t pte = *ptep;
342 
343         if (tlb_type != hypervisor) {
344                 unsigned long pfn = pte_pfn(pte);
345 
346                 if (pfn_valid(pfn))
347                         flush_dcache(pfn);
348         }
349 
350         mm = vma->vm_mm;
351 
352         /* Don't insert a non-valid PTE into the TSB, we'll deadlock.  */
353         if (!pte_accessible(mm, pte))
354                 return;
355 
356         spin_lock_irqsave(&mm->context.lock, flags);
357 
358 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
359         if (mm->context.huge_pte_count && is_hugetlb_pte(pte))
360                 __update_mmu_tsb_insert(mm, MM_TSB_HUGE, REAL_HPAGE_SHIFT,
361                                         address, pte_val(pte));
362         else
363 #endif
364                 __update_mmu_tsb_insert(mm, MM_TSB_BASE, PAGE_SHIFT,
365                                         address, pte_val(pte));
366 
367         spin_unlock_irqrestore(&mm->context.lock, flags);
368 }
369 
370 void flush_dcache_page(struct page *page)
371 {
372         struct address_space *mapping;
373         int this_cpu;
374 
375         if (tlb_type == hypervisor)
376                 return;
377 
378         /* Do not bother with the expensive D-cache flush if it
379          * is merely the zero page.  The 'bigcore' testcase in GDB
380          * causes this case to run millions of times.
381          */
382         if (page == ZERO_PAGE(0))
383                 return;
384 
385         this_cpu = get_cpu();
386 
387         mapping = page_mapping(page);
388         if (mapping && !mapping_mapped(mapping)) {
389                 int dirty = test_bit(PG_dcache_dirty, &page->flags);
390                 if (dirty) {
391                         int dirty_cpu = dcache_dirty_cpu(page);
392 
393                         if (dirty_cpu == this_cpu)
394                                 goto out;
395                         smp_flush_dcache_page_impl(page, dirty_cpu);
396                 }
397                 set_dcache_dirty(page, this_cpu);
398         } else {
399                 /* We could delay the flush for the !page_mapping
400                  * case too.  But that case is for exec env/arg
401                  * pages and those are %99 certainly going to get
402                  * faulted into the tlb (and thus flushed) anyways.
403                  */
404                 flush_dcache_page_impl(page);
405         }
406 
407 out:
408         put_cpu();
409 }
410 EXPORT_SYMBOL(flush_dcache_page);
411 
412 void __kprobes flush_icache_range(unsigned long start, unsigned long end)
413 {
414         /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
415         if (tlb_type == spitfire) {
416                 unsigned long kaddr;
417 
418                 /* This code only runs on Spitfire cpus so this is
419                  * why we can assume _PAGE_PADDR_4U.
420                  */
421                 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) {
422                         unsigned long paddr, mask = _PAGE_PADDR_4U;
423 
424                         if (kaddr >= PAGE_OFFSET)
425                                 paddr = kaddr & mask;
426                         else {
427                                 pgd_t *pgdp = pgd_offset_k(kaddr);
428                                 pud_t *pudp = pud_offset(pgdp, kaddr);
429                                 pmd_t *pmdp = pmd_offset(pudp, kaddr);
430                                 pte_t *ptep = pte_offset_kernel(pmdp, kaddr);
431 
432                                 paddr = pte_val(*ptep) & mask;
433                         }
434                         __flush_icache_page(paddr);
435                 }
436         }
437 }
438 EXPORT_SYMBOL(flush_icache_range);
439 
440 void mmu_info(struct seq_file *m)
441 {
442         static const char *pgsz_strings[] = {
443                 "8K", "64K", "512K", "4MB", "32MB",
444                 "256MB", "2GB", "16GB",
445         };
446         int i, printed;
447 
448         if (tlb_type == cheetah)
449                 seq_printf(m, "MMU Type\t: Cheetah\n");
450         else if (tlb_type == cheetah_plus)
451                 seq_printf(m, "MMU Type\t: Cheetah+\n");
452         else if (tlb_type == spitfire)
453                 seq_printf(m, "MMU Type\t: Spitfire\n");
454         else if (tlb_type == hypervisor)
455                 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
456         else
457                 seq_printf(m, "MMU Type\t: ???\n");
458 
459         seq_printf(m, "MMU PGSZs\t: ");
460         printed = 0;
461         for (i = 0; i < ARRAY_SIZE(pgsz_strings); i++) {
462                 if (cpu_pgsz_mask & (1UL << i)) {
463                         seq_printf(m, "%s%s",
464                                    printed ? "," : "", pgsz_strings[i]);
465                         printed++;
466                 }
467         }
468         seq_putc(m, '\n');
469 
470 #ifdef CONFIG_DEBUG_DCFLUSH
471         seq_printf(m, "DCPageFlushes\t: %d\n",
472                    atomic_read(&dcpage_flushes));
473 #ifdef CONFIG_SMP
474         seq_printf(m, "DCPageFlushesXC\t: %d\n",
475                    atomic_read(&dcpage_flushes_xcall));
476 #endif /* CONFIG_SMP */
477 #endif /* CONFIG_DEBUG_DCFLUSH */
478 }
479 
480 struct linux_prom_translation prom_trans[512] __read_mostly;
481 unsigned int prom_trans_ents __read_mostly;
482 
483 unsigned long kern_locked_tte_data;
484 
485 /* The obp translations are saved based on 8k pagesize, since obp can
486  * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
487  * HI_OBP_ADDRESS range are handled in ktlb.S.
488  */
489 static inline int in_obp_range(unsigned long vaddr)
490 {
491         return (vaddr >= LOW_OBP_ADDRESS &&
492                 vaddr < HI_OBP_ADDRESS);
493 }
494 
495 static int cmp_ptrans(const void *a, const void *b)
496 {
497         const struct linux_prom_translation *x = a, *y = b;
498 
499         if (x->virt > y->virt)
500                 return 1;
501         if (x->virt < y->virt)
502                 return -1;
503         return 0;
504 }
505 
506 /* Read OBP translations property into 'prom_trans[]'.  */
507 static void __init read_obp_translations(void)
508 {
509         int n, node, ents, first, last, i;
510 
511         node = prom_finddevice("/virtual-memory");
512         n = prom_getproplen(node, "translations");
513         if (unlikely(n == 0 || n == -1)) {
514                 prom_printf("prom_mappings: Couldn't get size.\n");
515                 prom_halt();
516         }
517         if (unlikely(n > sizeof(prom_trans))) {
518                 prom_printf("prom_mappings: Size %d is too big.\n", n);
519                 prom_halt();
520         }
521 
522         if ((n = prom_getproperty(node, "translations",
523                                   (char *)&prom_trans[0],
524                                   sizeof(prom_trans))) == -1) {
525                 prom_printf("prom_mappings: Couldn't get property.\n");
526                 prom_halt();
527         }
528 
529         n = n / sizeof(struct linux_prom_translation);
530 
531         ents = n;
532 
533         sort(prom_trans, ents, sizeof(struct linux_prom_translation),
534              cmp_ptrans, NULL);
535 
536         /* Now kick out all the non-OBP entries.  */
537         for (i = 0; i < ents; i++) {
538                 if (in_obp_range(prom_trans[i].virt))
539                         break;
540         }
541         first = i;
542         for (; i < ents; i++) {
543                 if (!in_obp_range(prom_trans[i].virt))
544                         break;
545         }
546         last = i;
547 
548         for (i = 0; i < (last - first); i++) {
549                 struct linux_prom_translation *src = &prom_trans[i + first];
550                 struct linux_prom_translation *dest = &prom_trans[i];
551 
552                 *dest = *src;
553         }
554         for (; i < ents; i++) {
555                 struct linux_prom_translation *dest = &prom_trans[i];
556                 dest->virt = dest->size = dest->data = 0x0UL;
557         }
558 
559         prom_trans_ents = last - first;
560 
561         if (tlb_type == spitfire) {
562                 /* Clear diag TTE bits. */
563                 for (i = 0; i < prom_trans_ents; i++)
564                         prom_trans[i].data &= ~0x0003fe0000000000UL;
565         }
566 
567         /* Force execute bit on.  */
568         for (i = 0; i < prom_trans_ents; i++)
569                 prom_trans[i].data |= (tlb_type == hypervisor ?
570                                        _PAGE_EXEC_4V : _PAGE_EXEC_4U);
571 }
572 
573 static void __init hypervisor_tlb_lock(unsigned long vaddr,
574                                        unsigned long pte,
575                                        unsigned long mmu)
576 {
577         unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu);
578 
579         if (ret != 0) {
580                 prom_printf("hypervisor_tlb_lock[%lx:%x:%lx:%lx]: "
581                             "errors with %lx\n", vaddr, 0, pte, mmu, ret);
582                 prom_halt();
583         }
584 }
585 
586 static unsigned long kern_large_tte(unsigned long paddr);
587 
588 static void __init remap_kernel(void)
589 {
590         unsigned long phys_page, tte_vaddr, tte_data;
591         int i, tlb_ent = sparc64_highest_locked_tlbent();
592 
593         tte_vaddr = (unsigned long) KERNBASE;
594         phys_page = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB;
595         tte_data = kern_large_tte(phys_page);
596 
597         kern_locked_tte_data = tte_data;
598 
599         /* Now lock us into the TLBs via Hypervisor or OBP. */
600         if (tlb_type == hypervisor) {
601                 for (i = 0; i < num_kernel_image_mappings; i++) {
602                         hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
603                         hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
604                         tte_vaddr += 0x400000;
605                         tte_data += 0x400000;
606                 }
607         } else {
608                 for (i = 0; i < num_kernel_image_mappings; i++) {
609                         prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr);
610                         prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr);
611                         tte_vaddr += 0x400000;
612                         tte_data += 0x400000;
613                 }
614                 sparc64_highest_unlocked_tlb_ent = tlb_ent - i;
615         }
616         if (tlb_type == cheetah_plus) {
617                 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
618                                             CTX_CHEETAH_PLUS_NUC);
619                 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
620                 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
621         }
622 }
623 
624 
625 static void __init inherit_prom_mappings(void)
626 {
627         /* Now fixup OBP's idea about where we really are mapped. */
628         printk("Remapping the kernel... ");
629         remap_kernel();
630         printk("done.\n");
631 }
632 
633 void prom_world(int enter)
634 {
635         if (!enter)
636                 set_fs(get_fs());
637 
638         __asm__ __volatile__("flushw");
639 }
640 
641 void __flush_dcache_range(unsigned long start, unsigned long end)
642 {
643         unsigned long va;
644 
645         if (tlb_type == spitfire) {
646                 int n = 0;
647 
648                 for (va = start; va < end; va += 32) {
649                         spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
650                         if (++n >= 512)
651                                 break;
652                 }
653         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
654                 start = __pa(start);
655                 end = __pa(end);
656                 for (va = start; va < end; va += 32)
657                         __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
658                                              "membar #Sync"
659                                              : /* no outputs */
660                                              : "r" (va),
661                                                "i" (ASI_DCACHE_INVALIDATE));
662         }
663 }
664 EXPORT_SYMBOL(__flush_dcache_range);
665 
666 /* get_new_mmu_context() uses "cache + 1".  */
667 DEFINE_SPINLOCK(ctx_alloc_lock);
668 unsigned long tlb_context_cache = CTX_FIRST_VERSION;
669 #define MAX_CTX_NR      (1UL << CTX_NR_BITS)
670 #define CTX_BMAP_SLOTS  BITS_TO_LONGS(MAX_CTX_NR)
671 DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR);
672 DEFINE_PER_CPU(struct mm_struct *, per_cpu_secondary_mm) = {0};
673 
674 static void mmu_context_wrap(void)
675 {
676         unsigned long old_ver = tlb_context_cache & CTX_VERSION_MASK;
677         unsigned long new_ver, new_ctx, old_ctx;
678         struct mm_struct *mm;
679         int cpu;
680 
681         bitmap_zero(mmu_context_bmap, 1 << CTX_NR_BITS);
682 
683         /* Reserve kernel context */
684         set_bit(0, mmu_context_bmap);
685 
686         new_ver = (tlb_context_cache & CTX_VERSION_MASK) + CTX_FIRST_VERSION;
687         if (unlikely(new_ver == 0))
688                 new_ver = CTX_FIRST_VERSION;
689         tlb_context_cache = new_ver;
690 
691         /*
692          * Make sure that any new mm that are added into per_cpu_secondary_mm,
693          * are going to go through get_new_mmu_context() path.
694          */
695         mb();
696 
697         /*
698          * Updated versions to current on those CPUs that had valid secondary
699          * contexts
700          */
701         for_each_online_cpu(cpu) {
702                 /*
703                  * If a new mm is stored after we took this mm from the array,
704                  * it will go into get_new_mmu_context() path, because we
705                  * already bumped the version in tlb_context_cache.
706                  */
707                 mm = per_cpu(per_cpu_secondary_mm, cpu);
708 
709                 if (unlikely(!mm || mm == &init_mm))
710                         continue;
711 
712                 old_ctx = mm->context.sparc64_ctx_val;
713                 if (likely((old_ctx & CTX_VERSION_MASK) == old_ver)) {
714                         new_ctx = (old_ctx & ~CTX_VERSION_MASK) | new_ver;
715                         set_bit(new_ctx & CTX_NR_MASK, mmu_context_bmap);
716                         mm->context.sparc64_ctx_val = new_ctx;
717                 }
718         }
719 }
720 
721 /* Caller does TLB context flushing on local CPU if necessary.
722  * The caller also ensures that CTX_VALID(mm->context) is false.
723  *
724  * We must be careful about boundary cases so that we never
725  * let the user have CTX 0 (nucleus) or we ever use a CTX
726  * version of zero (and thus NO_CONTEXT would not be caught
727  * by version mis-match tests in mmu_context.h).
728  *
729  * Always invoked with interrupts disabled.
730  */
731 void get_new_mmu_context(struct mm_struct *mm)
732 {
733         unsigned long ctx, new_ctx;
734         unsigned long orig_pgsz_bits;
735 
736         spin_lock(&ctx_alloc_lock);
737 retry:
738         /* wrap might have happened, test again if our context became valid */
739         if (unlikely(CTX_VALID(mm->context)))
740                 goto out;
741         orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
742         ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
743         new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
744         if (new_ctx >= (1 << CTX_NR_BITS)) {
745                 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
746                 if (new_ctx >= ctx) {
747                         mmu_context_wrap();
748                         goto retry;
749                 }
750         }
751         if (mm->context.sparc64_ctx_val)
752                 cpumask_clear(mm_cpumask(mm));
753         mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
754         new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
755         tlb_context_cache = new_ctx;
756         mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
757 out:
758         spin_unlock(&ctx_alloc_lock);
759 }
760 
761 static int numa_enabled = 1;
762 static int numa_debug;
763 
764 static int __init early_numa(char *p)
765 {
766         if (!p)
767                 return 0;
768 
769         if (strstr(p, "off"))
770                 numa_enabled = 0;
771 
772         if (strstr(p, "debug"))
773                 numa_debug = 1;
774 
775         return 0;
776 }
777 early_param("numa", early_numa);
778 
779 #define numadbg(f, a...) \
780 do {    if (numa_debug) \
781                 printk(KERN_INFO f, ## a); \
782 } while (0)
783 
784 static void __init find_ramdisk(unsigned long phys_base)
785 {
786 #ifdef CONFIG_BLK_DEV_INITRD
787         if (sparc_ramdisk_image || sparc_ramdisk_image64) {
788                 unsigned long ramdisk_image;
789 
790                 /* Older versions of the bootloader only supported a
791                  * 32-bit physical address for the ramdisk image
792                  * location, stored at sparc_ramdisk_image.  Newer
793                  * SILO versions set sparc_ramdisk_image to zero and
794                  * provide a full 64-bit physical address at
795                  * sparc_ramdisk_image64.
796                  */
797                 ramdisk_image = sparc_ramdisk_image;
798                 if (!ramdisk_image)
799                         ramdisk_image = sparc_ramdisk_image64;
800 
801                 /* Another bootloader quirk.  The bootloader normalizes
802                  * the physical address to KERNBASE, so we have to
803                  * factor that back out and add in the lowest valid
804                  * physical page address to get the true physical address.
805                  */
806                 ramdisk_image -= KERNBASE;
807                 ramdisk_image += phys_base;
808 
809                 numadbg("Found ramdisk at physical address 0x%lx, size %u\n",
810                         ramdisk_image, sparc_ramdisk_size);
811 
812                 initrd_start = ramdisk_image;
813                 initrd_end = ramdisk_image + sparc_ramdisk_size;
814 
815                 memblock_reserve(initrd_start, sparc_ramdisk_size);
816 
817                 initrd_start += PAGE_OFFSET;
818                 initrd_end += PAGE_OFFSET;
819         }
820 #endif
821 }
822 
823 struct node_mem_mask {
824         unsigned long mask;
825         unsigned long val;
826 };
827 static struct node_mem_mask node_masks[MAX_NUMNODES];
828 static int num_node_masks;
829 
830 #ifdef CONFIG_NEED_MULTIPLE_NODES
831 
832 int numa_cpu_lookup_table[NR_CPUS];
833 cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES];
834 
835 struct mdesc_mblock {
836         u64     base;
837         u64     size;
838         u64     offset; /* RA-to-PA */
839 };
840 static struct mdesc_mblock *mblocks;
841 static int num_mblocks;
842 
843 static unsigned long ra_to_pa(unsigned long addr)
844 {
845         int i;
846 
847         for (i = 0; i < num_mblocks; i++) {
848                 struct mdesc_mblock *m = &mblocks[i];
849 
850                 if (addr >= m->base &&
851                     addr < (m->base + m->size)) {
852                         addr += m->offset;
853                         break;
854                 }
855         }
856         return addr;
857 }
858 
859 static int find_node(unsigned long addr)
860 {
861         int i;
862 
863         addr = ra_to_pa(addr);
864         for (i = 0; i < num_node_masks; i++) {
865                 struct node_mem_mask *p = &node_masks[i];
866 
867                 if ((addr & p->mask) == p->val)
868                         return i;
869         }
870         /* The following condition has been observed on LDOM guests.*/
871         WARN_ONCE(1, "find_node: A physical address doesn't match a NUMA node"
872                 " rule. Some physical memory will be owned by node 0.");
873         return 0;
874 }
875 
876 static u64 memblock_nid_range(u64 start, u64 end, int *nid)
877 {
878         *nid = find_node(start);
879         start += PAGE_SIZE;
880         while (start < end) {
881                 int n = find_node(start);
882 
883                 if (n != *nid)
884                         break;
885                 start += PAGE_SIZE;
886         }
887 
888         if (start > end)
889                 start = end;
890 
891         return start;
892 }
893 #endif
894 
895 /* This must be invoked after performing all of the necessary
896  * memblock_set_node() calls for 'nid'.  We need to be able to get
897  * correct data from get_pfn_range_for_nid().
898  */
899 static void __init allocate_node_data(int nid)
900 {
901         struct pglist_data *p;
902         unsigned long start_pfn, end_pfn;
903 #ifdef CONFIG_NEED_MULTIPLE_NODES
904         unsigned long paddr;
905 
906         paddr = memblock_alloc_try_nid(sizeof(struct pglist_data), SMP_CACHE_BYTES, nid);
907         if (!paddr) {
908                 prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid);
909                 prom_halt();
910         }
911         NODE_DATA(nid) = __va(paddr);
912         memset(NODE_DATA(nid), 0, sizeof(struct pglist_data));
913 
914         NODE_DATA(nid)->node_id = nid;
915 #endif
916 
917         p = NODE_DATA(nid);
918 
919         get_pfn_range_for_nid(nid, &start_pfn, &end_pfn);
920         p->node_start_pfn = start_pfn;
921         p->node_spanned_pages = end_pfn - start_pfn;
922 }
923 
924 static void init_node_masks_nonnuma(void)
925 {
926 #ifdef CONFIG_NEED_MULTIPLE_NODES
927         int i;
928 #endif
929 
930         numadbg("Initializing tables for non-numa.\n");
931 
932         node_masks[0].mask = node_masks[0].val = 0;
933         num_node_masks = 1;
934 
935 #ifdef CONFIG_NEED_MULTIPLE_NODES
936         for (i = 0; i < NR_CPUS; i++)
937                 numa_cpu_lookup_table[i] = 0;
938 
939         cpumask_setall(&numa_cpumask_lookup_table[0]);
940 #endif
941 }
942 
943 #ifdef CONFIG_NEED_MULTIPLE_NODES
944 struct pglist_data *node_data[MAX_NUMNODES];
945 
946 EXPORT_SYMBOL(numa_cpu_lookup_table);
947 EXPORT_SYMBOL(numa_cpumask_lookup_table);
948 EXPORT_SYMBOL(node_data);
949 
950 struct mdesc_mlgroup {
951         u64     node;
952         u64     latency;
953         u64     match;
954         u64     mask;
955 };
956 static struct mdesc_mlgroup *mlgroups;
957 static int num_mlgroups;
958 
959 static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio,
960                                    u32 cfg_handle)
961 {
962         u64 arc;
963 
964         mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) {
965                 u64 target = mdesc_arc_target(md, arc);
966                 const u64 *val;
967 
968                 val = mdesc_get_property(md, target,
969                                          "cfg-handle", NULL);
970                 if (val && *val == cfg_handle)
971                         return 0;
972         }
973         return -ENODEV;
974 }
975 
976 static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp,
977                                     u32 cfg_handle)
978 {
979         u64 arc, candidate, best_latency = ~(u64)0;
980 
981         candidate = MDESC_NODE_NULL;
982         mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
983                 u64 target = mdesc_arc_target(md, arc);
984                 const char *name = mdesc_node_name(md, target);
985                 const u64 *val;
986 
987                 if (strcmp(name, "pio-latency-group"))
988                         continue;
989 
990                 val = mdesc_get_property(md, target, "latency", NULL);
991                 if (!val)
992                         continue;
993 
994                 if (*val < best_latency) {
995                         candidate = target;
996                         best_latency = *val;
997                 }
998         }
999 
1000         if (candidate == MDESC_NODE_NULL)
1001                 return -ENODEV;
1002 
1003         return scan_pio_for_cfg_handle(md, candidate, cfg_handle);
1004 }
1005 
1006 int of_node_to_nid(struct device_node *dp)
1007 {
1008         const struct linux_prom64_registers *regs;
1009         struct mdesc_handle *md;
1010         u32 cfg_handle;
1011         int count, nid;
1012         u64 grp;
1013 
1014         /* This is the right thing to do on currently supported
1015          * SUN4U NUMA platforms as well, as the PCI controller does
1016          * not sit behind any particular memory controller.
1017          */
1018         if (!mlgroups)
1019                 return -1;
1020 
1021         regs = of_get_property(dp, "reg", NULL);
1022         if (!regs)
1023                 return -1;
1024 
1025         cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff;
1026 
1027         md = mdesc_grab();
1028 
1029         count = 0;
1030         nid = -1;
1031         mdesc_for_each_node_by_name(md, grp, "group") {
1032                 if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) {
1033                         nid = count;
1034                         break;
1035                 }
1036                 count++;
1037         }
1038 
1039         mdesc_release(md);
1040 
1041         return nid;
1042 }
1043 
1044 static void __init add_node_ranges(void)
1045 {
1046         struct memblock_region *reg;
1047 
1048         for_each_memblock(memory, reg) {
1049                 unsigned long size = reg->size;
1050                 unsigned long start, end;
1051 
1052                 start = reg->base;
1053                 end = start + size;
1054                 while (start < end) {
1055                         unsigned long this_end;
1056                         int nid;
1057 
1058                         this_end = memblock_nid_range(start, end, &nid);
1059 
1060                         numadbg("Setting memblock NUMA node nid[%d] "
1061                                 "start[%lx] end[%lx]\n",
1062                                 nid, start, this_end);
1063 
1064                         memblock_set_node(start, this_end - start,
1065                                           &memblock.memory, nid);
1066                         start = this_end;
1067                 }
1068         }
1069 }
1070 
1071 static int __init grab_mlgroups(struct mdesc_handle *md)
1072 {
1073         unsigned long paddr;
1074         int count = 0;
1075         u64 node;
1076 
1077         mdesc_for_each_node_by_name(md, node, "memory-latency-group")
1078                 count++;
1079         if (!count)
1080                 return -ENOENT;
1081 
1082         paddr = memblock_alloc(count * sizeof(struct mdesc_mlgroup),
1083                           SMP_CACHE_BYTES);
1084         if (!paddr)
1085                 return -ENOMEM;
1086 
1087         mlgroups = __va(paddr);
1088         num_mlgroups = count;
1089 
1090         count = 0;
1091         mdesc_for_each_node_by_name(md, node, "memory-latency-group") {
1092                 struct mdesc_mlgroup *m = &mlgroups[count++];
1093                 const u64 *val;
1094 
1095                 m->node = node;
1096 
1097                 val = mdesc_get_property(md, node, "latency", NULL);
1098                 m->latency = *val;
1099                 val = mdesc_get_property(md, node, "address-match", NULL);
1100                 m->match = *val;
1101                 val = mdesc_get_property(md, node, "address-mask", NULL);
1102                 m->mask = *val;
1103 
1104                 numadbg("MLGROUP[%d]: node[%llx] latency[%llx] "
1105                         "match[%llx] mask[%llx]\n",
1106                         count - 1, m->node, m->latency, m->match, m->mask);
1107         }
1108 
1109         return 0;
1110 }
1111 
1112 static int __init grab_mblocks(struct mdesc_handle *md)
1113 {
1114         unsigned long paddr;
1115         int count = 0;
1116         u64 node;
1117 
1118         mdesc_for_each_node_by_name(md, node, "mblock")
1119                 count++;
1120         if (!count)
1121                 return -ENOENT;
1122 
1123         paddr = memblock_alloc(count * sizeof(struct mdesc_mblock),
1124                           SMP_CACHE_BYTES);
1125         if (!paddr)
1126                 return -ENOMEM;
1127 
1128         mblocks = __va(paddr);
1129         num_mblocks = count;
1130 
1131         count = 0;
1132         mdesc_for_each_node_by_name(md, node, "mblock") {
1133                 struct mdesc_mblock *m = &mblocks[count++];
1134                 const u64 *val;
1135 
1136                 val = mdesc_get_property(md, node, "base", NULL);
1137                 m->base = *val;
1138                 val = mdesc_get_property(md, node, "size", NULL);
1139                 m->size = *val;
1140                 val = mdesc_get_property(md, node,
1141                                          "address-congruence-offset", NULL);
1142 
1143                 /* The address-congruence-offset property is optional.
1144                  * Explicity zero it be identifty this.
1145                  */
1146                 if (val)
1147                         m->offset = *val;
1148                 else
1149                         m->offset = 0UL;
1150 
1151                 numadbg("MBLOCK[%d]: base[%llx] size[%llx] offset[%llx]\n",
1152                         count - 1, m->base, m->size, m->offset);
1153         }
1154 
1155         return 0;
1156 }
1157 
1158 static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md,
1159                                                u64 grp, cpumask_t *mask)
1160 {
1161         u64 arc;
1162 
1163         cpumask_clear(mask);
1164 
1165         mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) {
1166                 u64 target = mdesc_arc_target(md, arc);
1167                 const char *name = mdesc_node_name(md, target);
1168                 const u64 *id;
1169 
1170                 if (strcmp(name, "cpu"))
1171                         continue;
1172                 id = mdesc_get_property(md, target, "id", NULL);
1173                 if (*id < nr_cpu_ids)
1174                         cpumask_set_cpu(*id, mask);
1175         }
1176 }
1177 
1178 static struct mdesc_mlgroup * __init find_mlgroup(u64 node)
1179 {
1180         int i;
1181 
1182         for (i = 0; i < num_mlgroups; i++) {
1183                 struct mdesc_mlgroup *m = &mlgroups[i];
1184                 if (m->node == node)
1185                         return m;
1186         }
1187         return NULL;
1188 }
1189 
1190 static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp,
1191                                       int index)
1192 {
1193         struct mdesc_mlgroup *candidate = NULL;
1194         u64 arc, best_latency = ~(u64)0;
1195         struct node_mem_mask *n;
1196 
1197         mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1198                 u64 target = mdesc_arc_target(md, arc);
1199                 struct mdesc_mlgroup *m = find_mlgroup(target);
1200                 if (!m)
1201                         continue;
1202                 if (m->latency < best_latency) {
1203                         candidate = m;
1204                         best_latency = m->latency;
1205                 }
1206         }
1207         if (!candidate)
1208                 return -ENOENT;
1209 
1210         if (num_node_masks != index) {
1211                 printk(KERN_ERR "Inconsistent NUMA state, "
1212                        "index[%d] != num_node_masks[%d]\n",
1213                        index, num_node_masks);
1214                 return -EINVAL;
1215         }
1216 
1217         n = &node_masks[num_node_masks++];
1218 
1219         n->mask = candidate->mask;
1220         n->val = candidate->match;
1221 
1222         numadbg("NUMA NODE[%d]: mask[%lx] val[%lx] (latency[%llx])\n",
1223                 index, n->mask, n->val, candidate->latency);
1224 
1225         return 0;
1226 }
1227 
1228 static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp,
1229                                          int index)
1230 {
1231         cpumask_t mask;
1232         int cpu;
1233 
1234         numa_parse_mdesc_group_cpus(md, grp, &mask);
1235 
1236         for_each_cpu(cpu, &mask)
1237                 numa_cpu_lookup_table[cpu] = index;
1238         cpumask_copy(&numa_cpumask_lookup_table[index], &mask);
1239 
1240         if (numa_debug) {
1241                 printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index);
1242                 for_each_cpu(cpu, &mask)
1243                         printk("%d ", cpu);
1244                 printk("]\n");
1245         }
1246 
1247         return numa_attach_mlgroup(md, grp, index);
1248 }
1249 
1250 static int __init numa_parse_mdesc(void)
1251 {
1252         struct mdesc_handle *md = mdesc_grab();
1253         int i, err, count;
1254         u64 node;
1255 
1256         node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups");
1257         if (node == MDESC_NODE_NULL) {
1258                 mdesc_release(md);
1259                 return -ENOENT;
1260         }
1261 
1262         err = grab_mblocks(md);
1263         if (err < 0)
1264                 goto out;
1265 
1266         err = grab_mlgroups(md);
1267         if (err < 0)
1268                 goto out;
1269 
1270         count = 0;
1271         mdesc_for_each_node_by_name(md, node, "group") {
1272                 err = numa_parse_mdesc_group(md, node, count);
1273                 if (err < 0)
1274                         break;
1275                 count++;
1276         }
1277 
1278         add_node_ranges();
1279 
1280         for (i = 0; i < num_node_masks; i++) {
1281                 allocate_node_data(i);
1282                 node_set_online(i);
1283         }
1284 
1285         err = 0;
1286 out:
1287         mdesc_release(md);
1288         return err;
1289 }
1290 
1291 static int __init numa_parse_jbus(void)
1292 {
1293         unsigned long cpu, index;
1294 
1295         /* NUMA node id is encoded in bits 36 and higher, and there is
1296          * a 1-to-1 mapping from CPU ID to NUMA node ID.
1297          */
1298         index = 0;
1299         for_each_present_cpu(cpu) {
1300                 numa_cpu_lookup_table[cpu] = index;
1301                 cpumask_copy(&numa_cpumask_lookup_table[index], cpumask_of(cpu));
1302                 node_masks[index].mask = ~((1UL << 36UL) - 1UL);
1303                 node_masks[index].val = cpu << 36UL;
1304 
1305                 index++;
1306         }
1307         num_node_masks = index;
1308 
1309         add_node_ranges();
1310 
1311         for (index = 0; index < num_node_masks; index++) {
1312                 allocate_node_data(index);
1313                 node_set_online(index);
1314         }
1315 
1316         return 0;
1317 }
1318 
1319 static int __init numa_parse_sun4u(void)
1320 {
1321         if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1322                 unsigned long ver;
1323 
1324                 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
1325                 if ((ver >> 32UL) == __JALAPENO_ID ||
1326                     (ver >> 32UL) == __SERRANO_ID)
1327                         return numa_parse_jbus();
1328         }
1329         return -1;
1330 }
1331 
1332 static int __init bootmem_init_numa(void)
1333 {
1334         int err = -1;
1335 
1336         numadbg("bootmem_init_numa()\n");
1337 
1338         if (numa_enabled) {
1339                 if (tlb_type == hypervisor)
1340                         err = numa_parse_mdesc();
1341                 else
1342                         err = numa_parse_sun4u();
1343         }
1344         return err;
1345 }
1346 
1347 #else
1348 
1349 static int bootmem_init_numa(void)
1350 {
1351         return -1;
1352 }
1353 
1354 #endif
1355 
1356 static void __init bootmem_init_nonnuma(void)
1357 {
1358         unsigned long top_of_ram = memblock_end_of_DRAM();
1359         unsigned long total_ram = memblock_phys_mem_size();
1360 
1361         numadbg("bootmem_init_nonnuma()\n");
1362 
1363         printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n",
1364                top_of_ram, total_ram);
1365         printk(KERN_INFO "Memory hole size: %ldMB\n",
1366                (top_of_ram - total_ram) >> 20);
1367 
1368         init_node_masks_nonnuma();
1369         memblock_set_node(0, (phys_addr_t)ULLONG_MAX, &memblock.memory, 0);
1370         allocate_node_data(0);
1371         node_set_online(0);
1372 }
1373 
1374 static unsigned long __init bootmem_init(unsigned long phys_base)
1375 {
1376         unsigned long end_pfn;
1377 
1378         end_pfn = memblock_end_of_DRAM() >> PAGE_SHIFT;
1379         max_pfn = max_low_pfn = end_pfn;
1380         min_low_pfn = (phys_base >> PAGE_SHIFT);
1381 
1382         if (bootmem_init_numa() < 0)
1383                 bootmem_init_nonnuma();
1384 
1385         /* Dump memblock with node info. */
1386         memblock_dump_all();
1387 
1388         /* XXX cpu notifier XXX */
1389 
1390         sparse_memory_present_with_active_regions(MAX_NUMNODES);
1391         sparse_init();
1392 
1393         return end_pfn;
1394 }
1395 
1396 static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1397 static int pall_ents __initdata;
1398 
1399 static unsigned long max_phys_bits = 40;
1400 
1401 bool kern_addr_valid(unsigned long addr)
1402 {
1403         pgd_t *pgd;
1404         pud_t *pud;
1405         pmd_t *pmd;
1406         pte_t *pte;
1407 
1408         if ((long)addr < 0L) {
1409                 unsigned long pa = __pa(addr);
1410 
1411                 if ((pa >> max_phys_bits) != 0UL)
1412                         return false;
1413 
1414                 return pfn_valid(pa >> PAGE_SHIFT);
1415         }
1416 
1417         if (addr >= (unsigned long) KERNBASE &&
1418             addr < (unsigned long)&_end)
1419                 return true;
1420 
1421         pgd = pgd_offset_k(addr);
1422         if (pgd_none(*pgd))
1423                 return 0;
1424 
1425         pud = pud_offset(pgd, addr);
1426         if (pud_none(*pud))
1427                 return 0;
1428 
1429         if (pud_large(*pud))
1430                 return pfn_valid(pud_pfn(*pud));
1431 
1432         pmd = pmd_offset(pud, addr);
1433         if (pmd_none(*pmd))
1434                 return 0;
1435 
1436         if (pmd_large(*pmd))
1437                 return pfn_valid(pmd_pfn(*pmd));
1438 
1439         pte = pte_offset_kernel(pmd, addr);
1440         if (pte_none(*pte))
1441                 return 0;
1442 
1443         return pfn_valid(pte_pfn(*pte));
1444 }
1445 EXPORT_SYMBOL(kern_addr_valid);
1446 
1447 static unsigned long __ref kernel_map_hugepud(unsigned long vstart,
1448                                               unsigned long vend,
1449                                               pud_t *pud)
1450 {
1451         const unsigned long mask16gb = (1UL << 34) - 1UL;
1452         u64 pte_val = vstart;
1453 
1454         /* Each PUD is 8GB */
1455         if ((vstart & mask16gb) ||
1456             (vend - vstart <= mask16gb)) {
1457                 pte_val ^= kern_linear_pte_xor[2];
1458                 pud_val(*pud) = pte_val | _PAGE_PUD_HUGE;
1459 
1460                 return vstart + PUD_SIZE;
1461         }
1462 
1463         pte_val ^= kern_linear_pte_xor[3];
1464         pte_val |= _PAGE_PUD_HUGE;
1465 
1466         vend = vstart + mask16gb + 1UL;
1467         while (vstart < vend) {
1468                 pud_val(*pud) = pte_val;
1469 
1470                 pte_val += PUD_SIZE;
1471                 vstart += PUD_SIZE;
1472                 pud++;
1473         }
1474         return vstart;
1475 }
1476 
1477 static bool kernel_can_map_hugepud(unsigned long vstart, unsigned long vend,
1478                                    bool guard)
1479 {
1480         if (guard && !(vstart & ~PUD_MASK) && (vend - vstart) >= PUD_SIZE)
1481                 return true;
1482 
1483         return false;
1484 }
1485 
1486 static unsigned long __ref kernel_map_hugepmd(unsigned long vstart,
1487                                               unsigned long vend,
1488                                               pmd_t *pmd)
1489 {
1490         const unsigned long mask256mb = (1UL << 28) - 1UL;
1491         const unsigned long mask2gb = (1UL << 31) - 1UL;
1492         u64 pte_val = vstart;
1493 
1494         /* Each PMD is 8MB */
1495         if ((vstart & mask256mb) ||
1496             (vend - vstart <= mask256mb)) {
1497                 pte_val ^= kern_linear_pte_xor[0];
1498                 pmd_val(*pmd) = pte_val | _PAGE_PMD_HUGE;
1499 
1500                 return vstart + PMD_SIZE;
1501         }
1502 
1503         if ((vstart & mask2gb) ||
1504             (vend - vstart <= mask2gb)) {
1505                 pte_val ^= kern_linear_pte_xor[1];
1506                 pte_val |= _PAGE_PMD_HUGE;
1507                 vend = vstart + mask256mb + 1UL;
1508         } else {
1509                 pte_val ^= kern_linear_pte_xor[2];
1510                 pte_val |= _PAGE_PMD_HUGE;
1511                 vend = vstart + mask2gb + 1UL;
1512         }
1513 
1514         while (vstart < vend) {
1515                 pmd_val(*pmd) = pte_val;
1516 
1517                 pte_val += PMD_SIZE;
1518                 vstart += PMD_SIZE;
1519                 pmd++;
1520         }
1521 
1522         return vstart;
1523 }
1524 
1525 static bool kernel_can_map_hugepmd(unsigned long vstart, unsigned long vend,
1526                                    bool guard)
1527 {
1528         if (guard && !(vstart & ~PMD_MASK) && (vend - vstart) >= PMD_SIZE)
1529                 return true;
1530 
1531         return false;
1532 }
1533 
1534 static unsigned long __ref kernel_map_range(unsigned long pstart,
1535                                             unsigned long pend, pgprot_t prot,
1536                                             bool use_huge)
1537 {
1538         unsigned long vstart = PAGE_OFFSET + pstart;
1539         unsigned long vend = PAGE_OFFSET + pend;
1540         unsigned long alloc_bytes = 0UL;
1541 
1542         if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
1543                 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1544                             vstart, vend);
1545                 prom_halt();
1546         }
1547 
1548         while (vstart < vend) {
1549                 unsigned long this_end, paddr = __pa(vstart);
1550                 pgd_t *pgd = pgd_offset_k(vstart);
1551                 pud_t *pud;
1552                 pmd_t *pmd;
1553                 pte_t *pte;
1554 
1555                 if (pgd_none(*pgd)) {
1556                         pud_t *new;
1557 
1558                         new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1559                         alloc_bytes += PAGE_SIZE;
1560                         pgd_populate(&init_mm, pgd, new);
1561                 }
1562                 pud = pud_offset(pgd, vstart);
1563                 if (pud_none(*pud)) {
1564                         pmd_t *new;
1565 
1566                         if (kernel_can_map_hugepud(vstart, vend, use_huge)) {
1567                                 vstart = kernel_map_hugepud(vstart, vend, pud);
1568                                 continue;
1569                         }
1570                         new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1571                         alloc_bytes += PAGE_SIZE;
1572                         pud_populate(&init_mm, pud, new);
1573                 }
1574 
1575                 pmd = pmd_offset(pud, vstart);
1576                 if (pmd_none(*pmd)) {
1577                         pte_t *new;
1578 
1579                         if (kernel_can_map_hugepmd(vstart, vend, use_huge)) {
1580                                 vstart = kernel_map_hugepmd(vstart, vend, pmd);
1581                                 continue;
1582                         }
1583                         new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1584                         alloc_bytes += PAGE_SIZE;
1585                         pmd_populate_kernel(&init_mm, pmd, new);
1586                 }
1587 
1588                 pte = pte_offset_kernel(pmd, vstart);
1589                 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1590                 if (this_end > vend)
1591                         this_end = vend;
1592 
1593                 while (vstart < this_end) {
1594                         pte_val(*pte) = (paddr | pgprot_val(prot));
1595 
1596                         vstart += PAGE_SIZE;
1597                         paddr += PAGE_SIZE;
1598                         pte++;
1599                 }
1600         }
1601 
1602         return alloc_bytes;
1603 }
1604 
1605 static void __init flush_all_kernel_tsbs(void)
1606 {
1607         int i;
1608 
1609         for (i = 0; i < KERNEL_TSB_NENTRIES; i++) {
1610                 struct tsb *ent = &swapper_tsb[i];
1611 
1612                 ent->tag = (1UL << TSB_TAG_INVALID_BIT);
1613         }
1614 #ifndef CONFIG_DEBUG_PAGEALLOC
1615         for (i = 0; i < KERNEL_TSB4M_NENTRIES; i++) {
1616                 struct tsb *ent = &swapper_4m_tsb[i];
1617 
1618                 ent->tag = (1UL << TSB_TAG_INVALID_BIT);
1619         }
1620 #endif
1621 }
1622 
1623 extern unsigned int kvmap_linear_patch[1];
1624 
1625 static void __init kernel_physical_mapping_init(void)
1626 {
1627         unsigned long i, mem_alloced = 0UL;
1628         bool use_huge = true;
1629 
1630 #ifdef CONFIG_DEBUG_PAGEALLOC
1631         use_huge = false;
1632 #endif
1633         for (i = 0; i < pall_ents; i++) {
1634                 unsigned long phys_start, phys_end;
1635 
1636                 phys_start = pall[i].phys_addr;
1637                 phys_end = phys_start + pall[i].reg_size;
1638 
1639                 mem_alloced += kernel_map_range(phys_start, phys_end,
1640                                                 PAGE_KERNEL, use_huge);
1641         }
1642 
1643         printk("Allocated %ld bytes for kernel page tables.\n",
1644                mem_alloced);
1645 
1646         kvmap_linear_patch[0] = 0x01000000; /* nop */
1647         flushi(&kvmap_linear_patch[0]);
1648 
1649         flush_all_kernel_tsbs();
1650 
1651         __flush_tlb_all();
1652 }
1653 
1654 #ifdef CONFIG_DEBUG_PAGEALLOC
1655 void __kernel_map_pages(struct page *page, int numpages, int enable)
1656 {
1657         unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1658         unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1659 
1660         kernel_map_range(phys_start, phys_end,
1661                          (enable ? PAGE_KERNEL : __pgprot(0)), false);
1662 
1663         flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1664                                PAGE_OFFSET + phys_end);
1665 
1666         /* we should perform an IPI and flush all tlbs,
1667          * but that can deadlock->flush only current cpu.
1668          */
1669         __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1670                                  PAGE_OFFSET + phys_end);
1671 }
1672 #endif
1673 
1674 unsigned long __init find_ecache_flush_span(unsigned long size)
1675 {
1676         int i;
1677 
1678         for (i = 0; i < pavail_ents; i++) {
1679                 if (pavail[i].reg_size >= size)
1680                         return pavail[i].phys_addr;
1681         }
1682 
1683         return ~0UL;
1684 }
1685 
1686 unsigned long PAGE_OFFSET;
1687 EXPORT_SYMBOL(PAGE_OFFSET);
1688 
1689 unsigned long VMALLOC_END   = 0x0000010000000000UL;
1690 EXPORT_SYMBOL(VMALLOC_END);
1691 
1692 unsigned long sparc64_va_hole_top =    0xfffff80000000000UL;
1693 unsigned long sparc64_va_hole_bottom = 0x0000080000000000UL;
1694 
1695 static void __init setup_page_offset(void)
1696 {
1697         if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1698                 /* Cheetah/Panther support a full 64-bit virtual
1699                  * address, so we can use all that our page tables
1700                  * support.
1701                  */
1702                 sparc64_va_hole_top =    0xfff0000000000000UL;
1703                 sparc64_va_hole_bottom = 0x0010000000000000UL;
1704 
1705                 max_phys_bits = 42;
1706         } else if (tlb_type == hypervisor) {
1707                 switch (sun4v_chip_type) {
1708                 case SUN4V_CHIP_NIAGARA1:
1709                 case SUN4V_CHIP_NIAGARA2:
1710                         /* T1 and T2 support 48-bit virtual addresses.  */
1711                         sparc64_va_hole_top =    0xffff800000000000UL;
1712                         sparc64_va_hole_bottom = 0x0000800000000000UL;
1713 
1714                         max_phys_bits = 39;
1715                         break;
1716                 case SUN4V_CHIP_NIAGARA3:
1717                         /* T3 supports 48-bit virtual addresses.  */
1718                         sparc64_va_hole_top =    0xffff800000000000UL;
1719                         sparc64_va_hole_bottom = 0x0000800000000000UL;
1720 
1721                         max_phys_bits = 43;
1722                         break;
1723                 case SUN4V_CHIP_NIAGARA4:
1724                 case SUN4V_CHIP_NIAGARA5:
1725                 case SUN4V_CHIP_SPARC64X:
1726                 case SUN4V_CHIP_SPARC_M6:
1727                         /* T4 and later support 52-bit virtual addresses.  */
1728                         sparc64_va_hole_top =    0xfff8000000000000UL;
1729                         sparc64_va_hole_bottom = 0x0008000000000000UL;
1730                         max_phys_bits = 47;
1731                         break;
1732                 case SUN4V_CHIP_SPARC_M7:
1733                 default:
1734                         /* M7 and later support 52-bit virtual addresses.  */
1735                         sparc64_va_hole_top =    0xfff8000000000000UL;
1736                         sparc64_va_hole_bottom = 0x0008000000000000UL;
1737                         max_phys_bits = 49;
1738                         break;
1739                 }
1740         }
1741 
1742         if (max_phys_bits > MAX_PHYS_ADDRESS_BITS) {
1743                 prom_printf("MAX_PHYS_ADDRESS_BITS is too small, need %lu\n",
1744                             max_phys_bits);
1745                 prom_halt();
1746         }
1747 
1748         PAGE_OFFSET = sparc64_va_hole_top;
1749         VMALLOC_END = ((sparc64_va_hole_bottom >> 1) +
1750                        (sparc64_va_hole_bottom >> 2));
1751 
1752         pr_info("MM: PAGE_OFFSET is 0x%016lx (max_phys_bits == %lu)\n",
1753                 PAGE_OFFSET, max_phys_bits);
1754         pr_info("MM: VMALLOC [0x%016lx --> 0x%016lx]\n",
1755                 VMALLOC_START, VMALLOC_END);
1756         pr_info("MM: VMEMMAP [0x%016lx --> 0x%016lx]\n",
1757                 VMEMMAP_BASE, VMEMMAP_BASE << 1);
1758 }
1759 
1760 static void __init tsb_phys_patch(void)
1761 {
1762         struct tsb_ldquad_phys_patch_entry *pquad;
1763         struct tsb_phys_patch_entry *p;
1764 
1765         pquad = &__tsb_ldquad_phys_patch;
1766         while (pquad < &__tsb_ldquad_phys_patch_end) {
1767                 unsigned long addr = pquad->addr;
1768 
1769                 if (tlb_type == hypervisor)
1770                         *(unsigned int *) addr = pquad->sun4v_insn;
1771                 else
1772                         *(unsigned int *) addr = pquad->sun4u_insn;
1773                 wmb();
1774                 __asm__ __volatile__("flush     %0"
1775                                      : /* no outputs */
1776                                      : "r" (addr));
1777 
1778                 pquad++;
1779         }
1780 
1781         p = &__tsb_phys_patch;
1782         while (p < &__tsb_phys_patch_end) {
1783                 unsigned long addr = p->addr;
1784 
1785                 *(unsigned int *) addr = p->insn;
1786                 wmb();
1787                 __asm__ __volatile__("flush     %0"
1788                                      : /* no outputs */
1789                                      : "r" (addr));
1790 
1791                 p++;
1792         }
1793 }
1794 
1795 /* Don't mark as init, we give this to the Hypervisor.  */
1796 #ifndef CONFIG_DEBUG_PAGEALLOC
1797 #define NUM_KTSB_DESCR  2
1798 #else
1799 #define NUM_KTSB_DESCR  1
1800 #endif
1801 static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
1802 
1803 /* The swapper TSBs are loaded with a base sequence of:
1804  *
1805  *      sethi   %uhi(SYMBOL), REG1
1806  *      sethi   %hi(SYMBOL), REG2
1807  *      or      REG1, %ulo(SYMBOL), REG1
1808  *      or      REG2, %lo(SYMBOL), REG2
1809  *      sllx    REG1, 32, REG1
1810  *      or      REG1, REG2, REG1
1811  *
1812  * When we use physical addressing for the TSB accesses, we patch the
1813  * first four instructions in the above sequence.
1814  */
1815 
1816 static void patch_one_ktsb_phys(unsigned int *start, unsigned int *end, unsigned long pa)
1817 {
1818         unsigned long high_bits, low_bits;
1819 
1820         high_bits = (pa >> 32) & 0xffffffff;
1821         low_bits = (pa >> 0) & 0xffffffff;
1822 
1823         while (start < end) {
1824                 unsigned int *ia = (unsigned int *)(unsigned long)*start;
1825 
1826                 ia[0] = (ia[0] & ~0x3fffff) | (high_bits >> 10);
1827                 __asm__ __volatile__("flush     %0" : : "r" (ia));
1828 
1829                 ia[1] = (ia[1] & ~0x3fffff) | (low_bits >> 10);
1830                 __asm__ __volatile__("flush     %0" : : "r" (ia + 1));
1831 
1832                 ia[2] = (ia[2] & ~0x1fff) | (high_bits & 0x3ff);
1833                 __asm__ __volatile__("flush     %0" : : "r" (ia + 2));
1834 
1835                 ia[3] = (ia[3] & ~0x1fff) | (low_bits & 0x3ff);
1836                 __asm__ __volatile__("flush     %0" : : "r" (ia + 3));
1837 
1838                 start++;
1839         }
1840 }
1841 
1842 static void ktsb_phys_patch(void)
1843 {
1844         extern unsigned int __swapper_tsb_phys_patch;
1845         extern unsigned int __swapper_tsb_phys_patch_end;
1846         unsigned long ktsb_pa;
1847 
1848         ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1849         patch_one_ktsb_phys(&__swapper_tsb_phys_patch,
1850                             &__swapper_tsb_phys_patch_end, ktsb_pa);
1851 #ifndef CONFIG_DEBUG_PAGEALLOC
1852         {
1853         extern unsigned int __swapper_4m_tsb_phys_patch;
1854         extern unsigned int __swapper_4m_tsb_phys_patch_end;
1855         ktsb_pa = (kern_base +
1856                    ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1857         patch_one_ktsb_phys(&__swapper_4m_tsb_phys_patch,
1858                             &__swapper_4m_tsb_phys_patch_end, ktsb_pa);
1859         }
1860 #endif
1861 }
1862 
1863 static void __init sun4v_ktsb_init(void)
1864 {
1865         unsigned long ktsb_pa;
1866 
1867         /* First KTSB for PAGE_SIZE mappings.  */
1868         ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1869 
1870         switch (PAGE_SIZE) {
1871         case 8 * 1024:
1872         default:
1873                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
1874                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
1875                 break;
1876 
1877         case 64 * 1024:
1878                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
1879                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
1880                 break;
1881 
1882         case 512 * 1024:
1883                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
1884                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
1885                 break;
1886 
1887         case 4 * 1024 * 1024:
1888                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
1889                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
1890                 break;
1891         }
1892 
1893         ktsb_descr[0].assoc = 1;
1894         ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
1895         ktsb_descr[0].ctx_idx = 0;
1896         ktsb_descr[0].tsb_base = ktsb_pa;
1897         ktsb_descr[0].resv = 0;
1898 
1899 #ifndef CONFIG_DEBUG_PAGEALLOC
1900         /* Second KTSB for 4MB/256MB/2GB/16GB mappings.  */
1901         ktsb_pa = (kern_base +
1902                    ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1903 
1904         ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
1905         ktsb_descr[1].pgsz_mask = ((HV_PGSZ_MASK_4MB |
1906                                     HV_PGSZ_MASK_256MB |
1907                                     HV_PGSZ_MASK_2GB |
1908                                     HV_PGSZ_MASK_16GB) &
1909                                    cpu_pgsz_mask);
1910         ktsb_descr[1].assoc = 1;
1911         ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
1912         ktsb_descr[1].ctx_idx = 0;
1913         ktsb_descr[1].tsb_base = ktsb_pa;
1914         ktsb_descr[1].resv = 0;
1915 #endif
1916 }
1917 
1918 void sun4v_ktsb_register(void)
1919 {
1920         unsigned long pa, ret;
1921 
1922         pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
1923 
1924         ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa);
1925         if (ret != 0) {
1926                 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
1927                             "errors with %lx\n", pa, ret);
1928                 prom_halt();
1929         }
1930 }
1931 
1932 static void __init sun4u_linear_pte_xor_finalize(void)
1933 {
1934 #ifndef CONFIG_DEBUG_PAGEALLOC
1935         /* This is where we would add Panther support for
1936          * 32MB and 256MB pages.
1937          */
1938 #endif
1939 }
1940 
1941 static void __init sun4v_linear_pte_xor_finalize(void)
1942 {
1943         unsigned long pagecv_flag;
1944 
1945         /* Bit 9 of TTE is no longer CV bit on M7 processor and it instead
1946          * enables MCD error. Do not set bit 9 on M7 processor.
1947          */
1948         switch (sun4v_chip_type) {
1949         case SUN4V_CHIP_SPARC_M7:
1950                 pagecv_flag = 0x00;
1951                 break;
1952         default:
1953                 pagecv_flag = _PAGE_CV_4V;
1954                 break;
1955         }
1956 #ifndef CONFIG_DEBUG_PAGEALLOC
1957         if (cpu_pgsz_mask & HV_PGSZ_MASK_256MB) {
1958                 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
1959                         PAGE_OFFSET;
1960                 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | pagecv_flag |
1961                                            _PAGE_P_4V | _PAGE_W_4V);
1962         } else {
1963                 kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
1964         }
1965 
1966         if (cpu_pgsz_mask & HV_PGSZ_MASK_2GB) {
1967                 kern_linear_pte_xor[2] = (_PAGE_VALID | _PAGE_SZ2GB_4V) ^
1968                         PAGE_OFFSET;
1969                 kern_linear_pte_xor[2] |= (_PAGE_CP_4V | pagecv_flag |
1970                                            _PAGE_P_4V | _PAGE_W_4V);
1971         } else {
1972                 kern_linear_pte_xor[2] = kern_linear_pte_xor[1];
1973         }
1974 
1975         if (cpu_pgsz_mask & HV_PGSZ_MASK_16GB) {
1976                 kern_linear_pte_xor[3] = (_PAGE_VALID | _PAGE_SZ16GB_4V) ^
1977                         PAGE_OFFSET;
1978                 kern_linear_pte_xor[3] |= (_PAGE_CP_4V | pagecv_flag |
1979                                            _PAGE_P_4V | _PAGE_W_4V);
1980         } else {
1981                 kern_linear_pte_xor[3] = kern_linear_pte_xor[2];
1982         }
1983 #endif
1984 }
1985 
1986 /* paging_init() sets up the page tables */
1987 
1988 static unsigned long last_valid_pfn;
1989 
1990 static void sun4u_pgprot_init(void);
1991 static void sun4v_pgprot_init(void);
1992 
1993 static phys_addr_t __init available_memory(void)
1994 {
1995         phys_addr_t available = 0ULL;
1996         phys_addr_t pa_start, pa_end;
1997         u64 i;
1998 
1999         for_each_free_mem_range(i, NUMA_NO_NODE, &pa_start, &pa_end, NULL)
2000                 available = available + (pa_end  - pa_start);
2001 
2002         return available;
2003 }
2004 
2005 #define _PAGE_CACHE_4U  (_PAGE_CP_4U | _PAGE_CV_4U)
2006 #define _PAGE_CACHE_4V  (_PAGE_CP_4V | _PAGE_CV_4V)
2007 #define __DIRTY_BITS_4U  (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
2008 #define __DIRTY_BITS_4V  (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
2009 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
2010 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
2011 
2012 /* We need to exclude reserved regions. This exclusion will include
2013  * vmlinux and initrd. To be more precise the initrd size could be used to
2014  * compute a new lower limit because it is freed later during initialization.
2015  */
2016 static void __init reduce_memory(phys_addr_t limit_ram)
2017 {
2018         phys_addr_t avail_ram = available_memory();
2019         phys_addr_t pa_start, pa_end;
2020         u64 i;
2021 
2022         if (limit_ram >= avail_ram)
2023                 return;
2024 
2025         for_each_free_mem_range(i, NUMA_NO_NODE, &pa_start, &pa_end, NULL) {
2026                 phys_addr_t region_size = pa_end - pa_start;
2027                 phys_addr_t clip_start = pa_start;
2028 
2029                 avail_ram = avail_ram - region_size;
2030                 /* Are we consuming too much? */
2031                 if (avail_ram < limit_ram) {
2032                         phys_addr_t give_back = limit_ram - avail_ram;
2033 
2034                         region_size = region_size - give_back;
2035                         clip_start = clip_start + give_back;
2036                 }
2037 
2038                 memblock_remove(clip_start, region_size);
2039 
2040                 if (avail_ram <= limit_ram)
2041                         break;
2042                 i = 0UL;
2043         }
2044 }
2045 
2046 void __init paging_init(void)
2047 {
2048         unsigned long end_pfn, shift, phys_base;
2049         unsigned long real_end, i;
2050         int node;
2051 
2052         setup_page_offset();
2053 
2054         /* These build time checkes make sure that the dcache_dirty_cpu()
2055          * page->flags usage will work.
2056          *
2057          * When a page gets marked as dcache-dirty, we store the
2058          * cpu number starting at bit 32 in the page->flags.  Also,
2059          * functions like clear_dcache_dirty_cpu use the cpu mask
2060          * in 13-bit signed-immediate instruction fields.
2061          */
2062 
2063         /*
2064          * Page flags must not reach into upper 32 bits that are used
2065          * for the cpu number
2066          */
2067         BUILD_BUG_ON(NR_PAGEFLAGS > 32);
2068 
2069         /*
2070          * The bit fields placed in the high range must not reach below
2071          * the 32 bit boundary. Otherwise we cannot place the cpu field
2072          * at the 32 bit boundary.
2073          */
2074         BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH +
2075                 ilog2(roundup_pow_of_two(NR_CPUS)) > 32);
2076 
2077         BUILD_BUG_ON(NR_CPUS > 4096);
2078 
2079         kern_base = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB;
2080         kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
2081 
2082         /* Invalidate both kernel TSBs.  */
2083         memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
2084 #ifndef CONFIG_DEBUG_PAGEALLOC
2085         memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
2086 #endif
2087 
2088         /* TTE.cv bit on sparc v9 occupies the same position as TTE.mcde
2089          * bit on M7 processor. This is a conflicting usage of the same
2090          * bit. Enabling TTE.cv on M7 would turn on Memory Corruption
2091          * Detection error on all pages and this will lead to problems
2092          * later. Kernel does not run with MCD enabled and hence rest
2093          * of the required steps to fully configure memory corruption
2094          * detection are not taken. We need to ensure TTE.mcde is not
2095          * set on M7 processor. Compute the value of cacheability
2096          * flag for use later taking this into consideration.
2097          */
2098         switch (sun4v_chip_type) {
2099         case SUN4V_CHIP_SPARC_M7:
2100                 page_cache4v_flag = _PAGE_CP_4V;
2101                 break;
2102         default:
2103                 page_cache4v_flag = _PAGE_CACHE_4V;
2104                 break;
2105         }
2106 
2107         if (tlb_type == hypervisor)
2108                 sun4v_pgprot_init();
2109         else
2110                 sun4u_pgprot_init();
2111 
2112         if (tlb_type == cheetah_plus ||
2113             tlb_type == hypervisor) {
2114                 tsb_phys_patch();
2115                 ktsb_phys_patch();
2116         }
2117 
2118         if (tlb_type == hypervisor)
2119                 sun4v_patch_tlb_handlers();
2120 
2121         /* Find available physical memory...
2122          *
2123          * Read it twice in order to work around a bug in openfirmware.
2124          * The call to grab this table itself can cause openfirmware to
2125          * allocate memory, which in turn can take away some space from
2126          * the list of available memory.  Reading it twice makes sure
2127          * we really do get the final value.
2128          */
2129         read_obp_translations();
2130         read_obp_memory("reg", &pall[0], &pall_ents);
2131         read_obp_memory("available", &pavail[0], &pavail_ents);
2132         read_obp_memory("available", &pavail[0], &pavail_ents);
2133 
2134         phys_base = 0xffffffffffffffffUL;
2135         for (i = 0; i < pavail_ents; i++) {
2136                 phys_base = min(phys_base, pavail[i].phys_addr);
2137                 memblock_add(pavail[i].phys_addr, pavail[i].reg_size);
2138         }
2139 
2140         memblock_reserve(kern_base, kern_size);
2141 
2142         find_ramdisk(phys_base);
2143 
2144         if (cmdline_memory_size)
2145                 reduce_memory(cmdline_memory_size);
2146 
2147         memblock_allow_resize();
2148         memblock_dump_all();
2149 
2150         set_bit(0, mmu_context_bmap);
2151 
2152         shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
2153 
2154         real_end = (unsigned long)_end;
2155         num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << ILOG2_4MB);
2156         printk("Kernel: Using %d locked TLB entries for main kernel image.\n",
2157                num_kernel_image_mappings);
2158 
2159         /* Set kernel pgd to upper alias so physical page computations
2160          * work.
2161          */
2162         init_mm.pgd += ((shift) / (sizeof(pgd_t)));
2163         
2164         memset(swapper_pg_dir, 0, sizeof(swapper_pg_dir));
2165 
2166         inherit_prom_mappings();
2167         
2168         /* Ok, we can use our TLB miss and window trap handlers safely.  */
2169         setup_tba();
2170 
2171         __flush_tlb_all();
2172 
2173         prom_build_devicetree();
2174         of_populate_present_mask();
2175 #ifndef CONFIG_SMP
2176         of_fill_in_cpu_data();
2177 #endif
2178 
2179         if (tlb_type == hypervisor) {
2180                 sun4v_mdesc_init();
2181                 mdesc_populate_present_mask(cpu_all_mask);
2182 #ifndef CONFIG_SMP
2183                 mdesc_fill_in_cpu_data(cpu_all_mask);
2184 #endif
2185                 mdesc_get_page_sizes(cpu_all_mask, &cpu_pgsz_mask);
2186 
2187                 sun4v_linear_pte_xor_finalize();
2188 
2189                 sun4v_ktsb_init();
2190                 sun4v_ktsb_register();
2191         } else {
2192                 unsigned long impl, ver;
2193 
2194                 cpu_pgsz_mask = (HV_PGSZ_MASK_8K | HV_PGSZ_MASK_64K |
2195                                  HV_PGSZ_MASK_512K | HV_PGSZ_MASK_4MB);
2196 
2197                 __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
2198                 impl = ((ver >> 32) & 0xffff);
2199                 if (impl == PANTHER_IMPL)
2200                         cpu_pgsz_mask |= (HV_PGSZ_MASK_32MB |
2201                                           HV_PGSZ_MASK_256MB);
2202 
2203                 sun4u_linear_pte_xor_finalize();
2204         }
2205 
2206         /* Flush the TLBs and the 4M TSB so that the updated linear
2207          * pte XOR settings are realized for all mappings.
2208          */
2209         __flush_tlb_all();
2210 #ifndef CONFIG_DEBUG_PAGEALLOC
2211         memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
2212 #endif
2213         __flush_tlb_all();
2214 
2215         /* Setup bootmem... */
2216         last_valid_pfn = end_pfn = bootmem_init(phys_base);
2217 
2218         /* Once the OF device tree and MDESC have been setup, we know
2219          * the list of possible cpus.  Therefore we can allocate the
2220          * IRQ stacks.
2221          */
2222         for_each_possible_cpu(i) {
2223                 node = cpu_to_node(i);
2224 
2225                 softirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node),
2226                                                         THREAD_SIZE,
2227                                                         THREAD_SIZE, 0);
2228                 hardirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node),
2229                                                         THREAD_SIZE,
2230                                                         THREAD_SIZE, 0);
2231         }
2232 
2233         kernel_physical_mapping_init();
2234 
2235         {
2236                 unsigned long max_zone_pfns[MAX_NR_ZONES];
2237 
2238                 memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
2239 
2240                 max_zone_pfns[ZONE_NORMAL] = end_pfn;
2241 
2242                 free_area_init_nodes(max_zone_pfns);
2243         }
2244 
2245         printk("Booting Linux...\n");
2246 }
2247 
2248 int page_in_phys_avail(unsigned long paddr)
2249 {
2250         int i;
2251 
2252         paddr &= PAGE_MASK;
2253 
2254         for (i = 0; i < pavail_ents; i++) {
2255                 unsigned long start, end;
2256 
2257                 start = pavail[i].phys_addr;
2258                 end = start + pavail[i].reg_size;
2259 
2260                 if (paddr >= start && paddr < end)
2261                         return 1;
2262         }
2263         if (paddr >= kern_base && paddr < (kern_base + kern_size))
2264                 return 1;
2265 #ifdef CONFIG_BLK_DEV_INITRD
2266         if (paddr >= __pa(initrd_start) &&
2267             paddr < __pa(PAGE_ALIGN(initrd_end)))
2268                 return 1;
2269 #endif
2270 
2271         return 0;
2272 }
2273 
2274 static void __init register_page_bootmem_info(void)
2275 {
2276 #ifdef CONFIG_NEED_MULTIPLE_NODES
2277         int i;
2278 
2279         for_each_online_node(i)
2280                 if (NODE_DATA(i)->node_spanned_pages)
2281                         register_page_bootmem_info_node(NODE_DATA(i));
2282 #endif
2283 }
2284 void __init mem_init(void)
2285 {
2286         high_memory = __va(last_valid_pfn << PAGE_SHIFT);
2287 
2288         free_all_bootmem();
2289 
2290         /*
2291          * Must be done after boot memory is put on freelist, because here we
2292          * might set fields in deferred struct pages that have not yet been
2293          * initialized, and free_all_bootmem() initializes all the reserved
2294          * deferred pages for us.
2295          */
2296         register_page_bootmem_info();
2297 
2298         /*
2299          * Set up the zero page, mark it reserved, so that page count
2300          * is not manipulated when freeing the page from user ptes.
2301          */
2302         mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
2303         if (mem_map_zero == NULL) {
2304                 prom_printf("paging_init: Cannot alloc zero page.\n");
2305                 prom_halt();
2306         }
2307         mark_page_reserved(mem_map_zero);
2308 
2309         mem_init_print_info(NULL);
2310 
2311         if (tlb_type == cheetah || tlb_type == cheetah_plus)
2312                 cheetah_ecache_flush_init();
2313 }
2314 
2315 void free_initmem(void)
2316 {
2317         unsigned long addr, initend;
2318         int do_free = 1;
2319 
2320         /* If the physical memory maps were trimmed by kernel command
2321          * line options, don't even try freeing this initmem stuff up.
2322          * The kernel image could have been in the trimmed out region
2323          * and if so the freeing below will free invalid page structs.
2324          */
2325         if (cmdline_memory_size)
2326                 do_free = 0;
2327 
2328         /*
2329          * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
2330          */
2331         addr = PAGE_ALIGN((unsigned long)(__init_begin));
2332         initend = (unsigned long)(__init_end) & PAGE_MASK;
2333         for (; addr < initend; addr += PAGE_SIZE) {
2334                 unsigned long page;
2335 
2336                 page = (addr +
2337                         ((unsigned long) __va(kern_base)) -
2338                         ((unsigned long) KERNBASE));
2339                 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
2340 
2341                 if (do_free)
2342                         free_reserved_page(virt_to_page(page));
2343         }
2344 }
2345 
2346 #ifdef CONFIG_BLK_DEV_INITRD
2347 void free_initrd_mem(unsigned long start, unsigned long end)
2348 {
2349         free_reserved_area((void *)start, (void *)end, POISON_FREE_INITMEM,
2350                            "initrd");
2351 }
2352 #endif
2353 
2354 pgprot_t PAGE_KERNEL __read_mostly;
2355 EXPORT_SYMBOL(PAGE_KERNEL);
2356 
2357 pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
2358 pgprot_t PAGE_COPY __read_mostly;
2359 
2360 pgprot_t PAGE_SHARED __read_mostly;
2361 EXPORT_SYMBOL(PAGE_SHARED);
2362 
2363 unsigned long pg_iobits __read_mostly;
2364 
2365 unsigned long _PAGE_IE __read_mostly;
2366 EXPORT_SYMBOL(_PAGE_IE);
2367 
2368 unsigned long _PAGE_E __read_mostly;
2369 EXPORT_SYMBOL(_PAGE_E);
2370 
2371 unsigned long _PAGE_CACHE __read_mostly;
2372 EXPORT_SYMBOL(_PAGE_CACHE);
2373 
2374 #ifdef CONFIG_SPARSEMEM_VMEMMAP
2375 int __meminit vmemmap_populate(unsigned long vstart, unsigned long vend,
2376                                int node)
2377 {
2378         unsigned long pte_base;
2379 
2380         pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2381                     _PAGE_CP_4U | _PAGE_CV_4U |
2382                     _PAGE_P_4U | _PAGE_W_4U);
2383         if (tlb_type == hypervisor)
2384                 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2385                             page_cache4v_flag | _PAGE_P_4V | _PAGE_W_4V);
2386 
2387         pte_base |= _PAGE_PMD_HUGE;
2388 
2389         vstart = vstart & PMD_MASK;
2390         vend = ALIGN(vend, PMD_SIZE);
2391         for (; vstart < vend; vstart += PMD_SIZE) {
2392                 pgd_t *pgd = pgd_offset_k(vstart);
2393                 unsigned long pte;
2394                 pud_t *pud;
2395                 pmd_t *pmd;
2396 
2397                 if (pgd_none(*pgd)) {
2398                         pud_t *new = vmemmap_alloc_block(PAGE_SIZE, node);
2399 
2400                         if (!new)
2401                                 return -ENOMEM;
2402                         pgd_populate(&init_mm, pgd, new);
2403                 }
2404 
2405                 pud = pud_offset(pgd, vstart);
2406                 if (pud_none(*pud)) {
2407                         pmd_t *new = vmemmap_alloc_block(PAGE_SIZE, node);
2408 
2409                         if (!new)
2410                                 return -ENOMEM;
2411                         pud_populate(&init_mm, pud, new);
2412                 }
2413 
2414                 pmd = pmd_offset(pud, vstart);
2415 
2416                 pte = pmd_val(*pmd);
2417                 if (!(pte & _PAGE_VALID)) {
2418                         void *block = vmemmap_alloc_block(PMD_SIZE, node);
2419 
2420                         if (!block)
2421                                 return -ENOMEM;
2422 
2423                         pmd_val(*pmd) = pte_base | __pa(block);
2424                 }
2425         }
2426 
2427         return 0;
2428 }
2429 
2430 void vmemmap_free(unsigned long start, unsigned long end)
2431 {
2432 }
2433 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
2434 
2435 static void prot_init_common(unsigned long page_none,
2436                              unsigned long page_shared,
2437                              unsigned long page_copy,
2438                              unsigned long page_readonly,
2439                              unsigned long page_exec_bit)
2440 {
2441         PAGE_COPY = __pgprot(page_copy);
2442         PAGE_SHARED = __pgprot(page_shared);
2443 
2444         protection_map[0x0] = __pgprot(page_none);
2445         protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
2446         protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
2447         protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
2448         protection_map[0x4] = __pgprot(page_readonly);
2449         protection_map[0x5] = __pgprot(page_readonly);
2450         protection_map[0x6] = __pgprot(page_copy);
2451         protection_map[0x7] = __pgprot(page_copy);
2452         protection_map[0x8] = __pgprot(page_none);
2453         protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
2454         protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
2455         protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
2456         protection_map[0xc] = __pgprot(page_readonly);
2457         protection_map[0xd] = __pgprot(page_readonly);
2458         protection_map[0xe] = __pgprot(page_shared);
2459         protection_map[0xf] = __pgprot(page_shared);
2460 }
2461 
2462 static void __init sun4u_pgprot_init(void)
2463 {
2464         unsigned long page_none, page_shared, page_copy, page_readonly;
2465         unsigned long page_exec_bit;
2466         int i;
2467 
2468         PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2469                                 _PAGE_CACHE_4U | _PAGE_P_4U |
2470                                 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2471                                 _PAGE_EXEC_4U);
2472         PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2473                                        _PAGE_CACHE_4U | _PAGE_P_4U |
2474                                        __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2475                                        _PAGE_EXEC_4U | _PAGE_L_4U);
2476 
2477         _PAGE_IE = _PAGE_IE_4U;
2478         _PAGE_E = _PAGE_E_4U;
2479         _PAGE_CACHE = _PAGE_CACHE_4U;
2480 
2481         pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
2482                      __ACCESS_BITS_4U | _PAGE_E_4U);
2483 
2484 #ifdef CONFIG_DEBUG_PAGEALLOC
2485         kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET;
2486 #else
2487         kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
2488                 PAGE_OFFSET;
2489 #endif
2490         kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
2491                                    _PAGE_P_4U | _PAGE_W_4U);
2492 
2493         for (i = 1; i < 4; i++)
2494                 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
2495 
2496         _PAGE_ALL_SZ_BITS =  (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
2497                               _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
2498                               _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
2499 
2500 
2501         page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
2502         page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2503                        __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
2504         page_copy   = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2505                        __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2506         page_readonly   = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2507                            __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2508 
2509         page_exec_bit = _PAGE_EXEC_4U;
2510 
2511         prot_init_common(page_none, page_shared, page_copy, page_readonly,
2512                          page_exec_bit);
2513 }
2514 
2515 static void __init sun4v_pgprot_init(void)
2516 {
2517         unsigned long page_none, page_shared, page_copy, page_readonly;
2518         unsigned long page_exec_bit;
2519         int i;
2520 
2521         PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
2522                                 page_cache4v_flag | _PAGE_P_4V |
2523                                 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
2524                                 _PAGE_EXEC_4V);
2525         PAGE_KERNEL_LOCKED = PAGE_KERNEL;
2526 
2527         _PAGE_IE = _PAGE_IE_4V;
2528         _PAGE_E = _PAGE_E_4V;
2529         _PAGE_CACHE = page_cache4v_flag;
2530 
2531 #ifdef CONFIG_DEBUG_PAGEALLOC
2532         kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET;
2533 #else
2534         kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
2535                 PAGE_OFFSET;
2536 #endif
2537         kern_linear_pte_xor[0] |= (page_cache4v_flag | _PAGE_P_4V |
2538                                    _PAGE_W_4V);
2539 
2540         for (i = 1; i < 4; i++)
2541                 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
2542 
2543         pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
2544                      __ACCESS_BITS_4V | _PAGE_E_4V);
2545 
2546         _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
2547                              _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
2548                              _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
2549                              _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
2550 
2551         page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | page_cache4v_flag;
2552         page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
2553                        __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
2554         page_copy   = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
2555                        __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2556         page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
2557                          __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2558 
2559         page_exec_bit = _PAGE_EXEC_4V;
2560 
2561         prot_init_common(page_none, page_shared, page_copy, page_readonly,
2562                          page_exec_bit);
2563 }
2564 
2565 unsigned long pte_sz_bits(unsigned long sz)
2566 {
2567         if (tlb_type == hypervisor) {
2568                 switch (sz) {
2569                 case 8 * 1024:
2570                 default:
2571                         return _PAGE_SZ8K_4V;
2572                 case 64 * 1024:
2573                         return _PAGE_SZ64K_4V;
2574                 case 512 * 1024:
2575                         return _PAGE_SZ512K_4V;
2576                 case 4 * 1024 * 1024:
2577                         return _PAGE_SZ4MB_4V;
2578                 }
2579         } else {
2580                 switch (sz) {
2581                 case 8 * 1024:
2582                 default:
2583                         return _PAGE_SZ8K_4U;
2584                 case 64 * 1024:
2585                         return _PAGE_SZ64K_4U;
2586                 case 512 * 1024:
2587                         return _PAGE_SZ512K_4U;
2588                 case 4 * 1024 * 1024:
2589                         return _PAGE_SZ4MB_4U;
2590                 }
2591         }
2592 }
2593 
2594 pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
2595 {
2596         pte_t pte;
2597 
2598         pte_val(pte)  = page | pgprot_val(pgprot_noncached(prot));
2599         pte_val(pte) |= (((unsigned long)space) << 32);
2600         pte_val(pte) |= pte_sz_bits(page_size);
2601 
2602         return pte;
2603 }
2604 
2605 static unsigned long kern_large_tte(unsigned long paddr)
2606 {
2607         unsigned long val;
2608 
2609         val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2610                _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
2611                _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
2612         if (tlb_type == hypervisor)
2613                 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2614                        page_cache4v_flag | _PAGE_P_4V |
2615                        _PAGE_EXEC_4V | _PAGE_W_4V);
2616 
2617         return val | paddr;
2618 }
2619 
2620 /* If not locked, zap it. */
2621 void __flush_tlb_all(void)
2622 {
2623         unsigned long pstate;
2624         int i;
2625 
2626         __asm__ __volatile__("flushw\n\t"
2627                              "rdpr      %%pstate, %0\n\t"
2628                              "wrpr      %0, %1, %%pstate"
2629                              : "=r" (pstate)
2630                              : "i" (PSTATE_IE));
2631         if (tlb_type == hypervisor) {
2632                 sun4v_mmu_demap_all();
2633         } else if (tlb_type == spitfire) {
2634                 for (i = 0; i < 64; i++) {
2635                         /* Spitfire Errata #32 workaround */
2636                         /* NOTE: Always runs on spitfire, so no
2637                          *       cheetah+ page size encodings.
2638                          */
2639                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
2640                                              "flush     %%g6"
2641                                              : /* No outputs */
2642                                              : "r" (0),
2643                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2644 
2645                         if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
2646                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2647                                                      "membar #Sync"
2648                                                      : /* no outputs */
2649                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
2650                                 spitfire_put_dtlb_data(i, 0x0UL);
2651                         }
2652 
2653                         /* Spitfire Errata #32 workaround */
2654                         /* NOTE: Always runs on spitfire, so no
2655                          *       cheetah+ page size encodings.
2656                          */
2657                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
2658                                              "flush     %%g6"
2659                                              : /* No outputs */
2660                                              : "r" (0),
2661                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2662 
2663                         if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
2664                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2665                                                      "membar #Sync"
2666                                                      : /* no outputs */
2667                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
2668                                 spitfire_put_itlb_data(i, 0x0UL);
2669                         }
2670                 }
2671         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
2672                 cheetah_flush_dtlb_all();
2673                 cheetah_flush_itlb_all();
2674         }
2675         __asm__ __volatile__("wrpr      %0, 0, %%pstate"
2676                              : : "r" (pstate));
2677 }
2678 
2679 pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
2680                             unsigned long address)
2681 {
2682         struct page *page = alloc_page(GFP_KERNEL | __GFP_NOTRACK |
2683                                        __GFP_REPEAT | __GFP_ZERO);
2684         pte_t *pte = NULL;
2685 
2686         if (page)
2687                 pte = (pte_t *) page_address(page);
2688 
2689         return pte;
2690 }
2691 
2692 pgtable_t pte_alloc_one(struct mm_struct *mm,
2693                         unsigned long address)
2694 {
2695         struct page *page = alloc_page(GFP_KERNEL | __GFP_NOTRACK |
2696                                        __GFP_REPEAT | __GFP_ZERO);
2697         if (!page)
2698                 return NULL;
2699         if (!pgtable_page_ctor(page)) {
2700                 free_hot_cold_page(page, 0);
2701                 return NULL;
2702         }
2703         return (pte_t *) page_address(page);
2704 }
2705 
2706 void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
2707 {
2708         free_page((unsigned long)pte);
2709 }
2710 
2711 static void __pte_free(pgtable_t pte)
2712 {
2713         struct page *page = virt_to_page(pte);
2714 
2715         pgtable_page_dtor(page);
2716         __free_page(page);
2717 }
2718 
2719 void pte_free(struct mm_struct *mm, pgtable_t pte)
2720 {
2721         __pte_free(pte);
2722 }
2723 
2724 void pgtable_free(void *table, bool is_page)
2725 {
2726         if (is_page)
2727                 __pte_free(table);
2728         else
2729                 kmem_cache_free(pgtable_cache, table);
2730 }
2731 
2732 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
2733 void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
2734                           pmd_t *pmd)
2735 {
2736         unsigned long pte, flags;
2737         struct mm_struct *mm;
2738         pmd_t entry = *pmd;
2739 
2740         if (!pmd_large(entry) || !pmd_young(entry))
2741                 return;
2742 
2743         pte = pmd_val(entry);
2744 
2745         /* Don't insert a non-valid PMD into the TSB, we'll deadlock.  */
2746         if (!(pte & _PAGE_VALID))
2747                 return;
2748 
2749         /* We are fabricating 8MB pages using 4MB real hw pages.  */
2750         pte |= (addr & (1UL << REAL_HPAGE_SHIFT));
2751 
2752         mm = vma->vm_mm;
2753 
2754         spin_lock_irqsave(&mm->context.lock, flags);
2755 
2756         if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL)
2757                 __update_mmu_tsb_insert(mm, MM_TSB_HUGE, REAL_HPAGE_SHIFT,
2758                                         addr, pte);
2759 
2760         spin_unlock_irqrestore(&mm->context.lock, flags);
2761 }
2762 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
2763 
2764 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
2765 static void context_reload(void *__data)
2766 {
2767         struct mm_struct *mm = __data;
2768 
2769         if (mm == current->mm)
2770                 load_secondary_context(mm);
2771 }
2772 
2773 void hugetlb_setup(struct pt_regs *regs)
2774 {
2775         struct mm_struct *mm = current->mm;
2776         struct tsb_config *tp;
2777 
2778         if (in_atomic() || !mm) {
2779                 const struct exception_table_entry *entry;
2780 
2781                 entry = search_exception_tables(regs->tpc);
2782                 if (entry) {
2783                         regs->tpc = entry->fixup;
2784                         regs->tnpc = regs->tpc + 4;
2785                         return;
2786                 }
2787                 pr_alert("Unexpected HugeTLB setup in atomic context.\n");
2788                 die_if_kernel("HugeTSB in atomic", regs);
2789         }
2790 
2791         tp = &mm->context.tsb_block[MM_TSB_HUGE];
2792         if (likely(tp->tsb == NULL))
2793                 tsb_grow(mm, MM_TSB_HUGE, 0);
2794 
2795         tsb_context_switch(mm);
2796         smp_tsb_sync(mm);
2797 
2798         /* On UltraSPARC-III+ and later, configure the second half of
2799          * the Data-TLB for huge pages.
2800          */
2801         if (tlb_type == cheetah_plus) {
2802                 bool need_context_reload = false;
2803                 unsigned long ctx;
2804 
2805                 spin_lock_irq(&ctx_alloc_lock);
2806                 ctx = mm->context.sparc64_ctx_val;
2807                 ctx &= ~CTX_PGSZ_MASK;
2808                 ctx |= CTX_PGSZ_BASE << CTX_PGSZ0_SHIFT;
2809                 ctx |= CTX_PGSZ_HUGE << CTX_PGSZ1_SHIFT;
2810 
2811                 if (ctx != mm->context.sparc64_ctx_val) {
2812                         /* When changing the page size fields, we
2813                          * must perform a context flush so that no
2814                          * stale entries match.  This flush must
2815                          * occur with the original context register
2816                          * settings.
2817                          */
2818                         do_flush_tlb_mm(mm);
2819 
2820                         /* Reload the context register of all processors
2821                          * also executing in this address space.
2822                          */
2823                         mm->context.sparc64_ctx_val = ctx;
2824                         need_context_reload = true;
2825                 }
2826                 spin_unlock_irq(&ctx_alloc_lock);
2827 
2828                 if (need_context_reload)
2829                         on_each_cpu(context_reload, mm, 0);
2830         }
2831 }
2832 #endif
2833 
2834 static struct resource code_resource = {
2835         .name   = "Kernel code",
2836         .flags  = IORESOURCE_BUSY | IORESOURCE_MEM
2837 };
2838 
2839 static struct resource data_resource = {
2840         .name   = "Kernel data",
2841         .flags  = IORESOURCE_BUSY | IORESOURCE_MEM
2842 };
2843 
2844 static struct resource bss_resource = {
2845         .name   = "Kernel bss",
2846         .flags  = IORESOURCE_BUSY | IORESOURCE_MEM
2847 };
2848 
2849 static inline resource_size_t compute_kern_paddr(void *addr)
2850 {
2851         return (resource_size_t) (addr - KERNBASE + kern_base);
2852 }
2853 
2854 static void __init kernel_lds_init(void)
2855 {
2856         code_resource.start = compute_kern_paddr(_text);
2857         code_resource.end   = compute_kern_paddr(_etext - 1);
2858         data_resource.start = compute_kern_paddr(_etext);
2859         data_resource.end   = compute_kern_paddr(_edata - 1);
2860         bss_resource.start  = compute_kern_paddr(__bss_start);
2861         bss_resource.end    = compute_kern_paddr(_end - 1);
2862 }
2863 
2864 static int __init report_memory(void)
2865 {
2866         int i;
2867         struct resource *res;
2868 
2869         kernel_lds_init();
2870 
2871         for (i = 0; i < pavail_ents; i++) {
2872                 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
2873 
2874                 if (!res) {
2875                         pr_warn("Failed to allocate source.\n");
2876                         break;
2877                 }
2878 
2879                 res->name = "System RAM";
2880                 res->start = pavail[i].phys_addr;
2881                 res->end = pavail[i].phys_addr + pavail[i].reg_size - 1;
2882                 res->flags = IORESOURCE_BUSY | IORESOURCE_MEM;
2883 
2884                 if (insert_resource(&iomem_resource, res) < 0) {
2885                         pr_warn("Resource insertion failed.\n");
2886                         break;
2887                 }
2888 
2889                 insert_resource(res, &code_resource);
2890                 insert_resource(res, &data_resource);
2891                 insert_resource(res, &bss_resource);
2892         }
2893 
2894         return 0;
2895 }
2896 arch_initcall(report_memory);
2897 
2898 #ifdef CONFIG_SMP
2899 #define do_flush_tlb_kernel_range       smp_flush_tlb_kernel_range
2900 #else
2901 #define do_flush_tlb_kernel_range       __flush_tlb_kernel_range
2902 #endif
2903 
2904 void flush_tlb_kernel_range(unsigned long start, unsigned long end)
2905 {
2906         if (start < HI_OBP_ADDRESS && end > LOW_OBP_ADDRESS) {
2907                 if (start < LOW_OBP_ADDRESS) {
2908                         flush_tsb_kernel_range(start, LOW_OBP_ADDRESS);
2909                         do_flush_tlb_kernel_range(start, LOW_OBP_ADDRESS);
2910                 }
2911                 if (end > HI_OBP_ADDRESS) {
2912                         flush_tsb_kernel_range(HI_OBP_ADDRESS, end);
2913                         do_flush_tlb_kernel_range(HI_OBP_ADDRESS, end);
2914                 }
2915         } else {
2916                 flush_tsb_kernel_range(start, end);
2917                 do_flush_tlb_kernel_range(start, end);
2918         }
2919 }
2920 

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