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Linux/arch/sparc/mm/iommu.c

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  1 // SPDX-License-Identifier: GPL-2.0
  2 /*
  3  * iommu.c:  IOMMU specific routines for memory management.
  4  *
  5  * Copyright (C) 1995 David S. Miller  (davem@caip.rutgers.edu)
  6  * Copyright (C) 1995,2002 Pete Zaitcev     (zaitcev@yahoo.com)
  7  * Copyright (C) 1996 Eddie C. Dost    (ecd@skynet.be)
  8  * Copyright (C) 1997,1998 Jakub Jelinek    (jj@sunsite.mff.cuni.cz)
  9  */
 10  
 11 #include <linux/kernel.h>
 12 #include <linux/init.h>
 13 #include <linux/mm.h>
 14 #include <linux/slab.h>
 15 #include <linux/highmem.h>      /* pte_offset_map => kmap_atomic */
 16 #include <linux/dma-mapping.h>
 17 #include <linux/of.h>
 18 #include <linux/of_device.h>
 19 
 20 #include <asm/pgalloc.h>
 21 #include <asm/pgtable.h>
 22 #include <asm/io.h>
 23 #include <asm/mxcc.h>
 24 #include <asm/mbus.h>
 25 #include <asm/cacheflush.h>
 26 #include <asm/tlbflush.h>
 27 #include <asm/bitext.h>
 28 #include <asm/iommu.h>
 29 #include <asm/dma.h>
 30 
 31 #include "mm_32.h"
 32 
 33 /*
 34  * This can be sized dynamically, but we will do this
 35  * only when we have a guidance about actual I/O pressures.
 36  */
 37 #define IOMMU_RNGE      IOMMU_RNGE_256MB
 38 #define IOMMU_START     0xF0000000
 39 #define IOMMU_WINSIZE   (256*1024*1024U)
 40 #define IOMMU_NPTES     (IOMMU_WINSIZE/PAGE_SIZE)       /* 64K PTEs, 256KB */
 41 #define IOMMU_ORDER     6                               /* 4096 * (1<<6) */
 42 
 43 static int viking_flush;
 44 /* viking.S */
 45 extern void viking_flush_page(unsigned long page);
 46 extern void viking_mxcc_flush_page(unsigned long page);
 47 
 48 /*
 49  * Values precomputed according to CPU type.
 50  */
 51 static unsigned int ioperm_noc;         /* Consistent mapping iopte flags */
 52 static pgprot_t dvma_prot;              /* Consistent mapping pte flags */
 53 
 54 #define IOPERM        (IOPTE_CACHE | IOPTE_WRITE | IOPTE_VALID)
 55 #define MKIOPTE(pfn, perm) (((((pfn)<<8) & IOPTE_PAGE) | (perm)) & ~IOPTE_WAZ)
 56 
 57 static void __init sbus_iommu_init(struct platform_device *op)
 58 {
 59         struct iommu_struct *iommu;
 60         unsigned int impl, vers;
 61         unsigned long *bitmap;
 62         unsigned long control;
 63         unsigned long base;
 64         unsigned long tmp;
 65 
 66         iommu = kmalloc(sizeof(struct iommu_struct), GFP_KERNEL);
 67         if (!iommu) {
 68                 prom_printf("Unable to allocate iommu structure\n");
 69                 prom_halt();
 70         }
 71 
 72         iommu->regs = of_ioremap(&op->resource[0], 0, PAGE_SIZE * 3,
 73                                  "iommu_regs");
 74         if (!iommu->regs) {
 75                 prom_printf("Cannot map IOMMU registers\n");
 76                 prom_halt();
 77         }
 78 
 79         control = sbus_readl(&iommu->regs->control);
 80         impl = (control & IOMMU_CTRL_IMPL) >> 28;
 81         vers = (control & IOMMU_CTRL_VERS) >> 24;
 82         control &= ~(IOMMU_CTRL_RNGE);
 83         control |= (IOMMU_RNGE_256MB | IOMMU_CTRL_ENAB);
 84         sbus_writel(control, &iommu->regs->control);
 85 
 86         iommu_invalidate(iommu->regs);
 87         iommu->start = IOMMU_START;
 88         iommu->end = 0xffffffff;
 89 
 90         /* Allocate IOMMU page table */
 91         /* Stupid alignment constraints give me a headache. 
 92            We need 256K or 512K or 1M or 2M area aligned to
 93            its size and current gfp will fortunately give
 94            it to us. */
 95         tmp = __get_free_pages(GFP_KERNEL, IOMMU_ORDER);
 96         if (!tmp) {
 97                 prom_printf("Unable to allocate iommu table [0x%lx]\n",
 98                             IOMMU_NPTES * sizeof(iopte_t));
 99                 prom_halt();
100         }
101         iommu->page_table = (iopte_t *)tmp;
102 
103         /* Initialize new table. */
104         memset(iommu->page_table, 0, IOMMU_NPTES*sizeof(iopte_t));
105         flush_cache_all();
106         flush_tlb_all();
107 
108         base = __pa((unsigned long)iommu->page_table) >> 4;
109         sbus_writel(base, &iommu->regs->base);
110         iommu_invalidate(iommu->regs);
111 
112         bitmap = kmalloc(IOMMU_NPTES>>3, GFP_KERNEL);
113         if (!bitmap) {
114                 prom_printf("Unable to allocate iommu bitmap [%d]\n",
115                             (int)(IOMMU_NPTES>>3));
116                 prom_halt();
117         }
118         bit_map_init(&iommu->usemap, bitmap, IOMMU_NPTES);
119         /* To be coherent on HyperSparc, the page color of DVMA
120          * and physical addresses must match.
121          */
122         if (srmmu_modtype == HyperSparc)
123                 iommu->usemap.num_colors = vac_cache_size >> PAGE_SHIFT;
124         else
125                 iommu->usemap.num_colors = 1;
126 
127         printk(KERN_INFO "IOMMU: impl %d vers %d table 0x%p[%d B] map [%d b]\n",
128                impl, vers, iommu->page_table,
129                (int)(IOMMU_NPTES*sizeof(iopte_t)), (int)IOMMU_NPTES);
130 
131         op->dev.archdata.iommu = iommu;
132 }
133 
134 static int __init iommu_init(void)
135 {
136         struct device_node *dp;
137 
138         for_each_node_by_name(dp, "iommu") {
139                 struct platform_device *op = of_find_device_by_node(dp);
140 
141                 sbus_iommu_init(op);
142                 of_propagate_archdata(op);
143         }
144 
145         return 0;
146 }
147 
148 subsys_initcall(iommu_init);
149 
150 /* Flush the iotlb entries to ram. */
151 /* This could be better if we didn't have to flush whole pages. */
152 static void iommu_flush_iotlb(iopte_t *iopte, unsigned int niopte)
153 {
154         unsigned long start;
155         unsigned long end;
156 
157         start = (unsigned long)iopte;
158         end = PAGE_ALIGN(start + niopte*sizeof(iopte_t));
159         start &= PAGE_MASK;
160         if (viking_mxcc_present) {
161                 while(start < end) {
162                         viking_mxcc_flush_page(start);
163                         start += PAGE_SIZE;
164                 }
165         } else if (viking_flush) {
166                 while(start < end) {
167                         viking_flush_page(start);
168                         start += PAGE_SIZE;
169                 }
170         } else {
171                 while(start < end) {
172                         __flush_page_to_ram(start);
173                         start += PAGE_SIZE;
174                 }
175         }
176 }
177 
178 static dma_addr_t __sbus_iommu_map_page(struct device *dev, struct page *page,
179                 unsigned long offset, size_t len, bool per_page_flush)
180 {
181         struct iommu_struct *iommu = dev->archdata.iommu;
182         phys_addr_t paddr = page_to_phys(page) + offset;
183         unsigned long off = paddr & ~PAGE_MASK;
184         unsigned long npages = (off + len + PAGE_SIZE - 1) >> PAGE_SHIFT;
185         unsigned long pfn = __phys_to_pfn(paddr);
186         unsigned int busa, busa0;
187         iopte_t *iopte, *iopte0;
188         int ioptex, i;
189 
190         /* XXX So what is maxphys for us and how do drivers know it? */
191         if (!len || len > 256 * 1024)
192                 return DMA_MAPPING_ERROR;
193 
194         /*
195          * We expect unmapped highmem pages to be not in the cache.
196          * XXX Is this a good assumption?
197          * XXX What if someone else unmaps it here and races us?
198          */
199         if (per_page_flush && !PageHighMem(page)) {
200                 unsigned long vaddr, p;
201 
202                 vaddr = (unsigned long)page_address(page) + offset;
203                 for (p = vaddr & PAGE_MASK; p < vaddr + len; p += PAGE_SIZE)
204                         flush_page_for_dma(p);
205         }
206 
207         /* page color = pfn of page */
208         ioptex = bit_map_string_get(&iommu->usemap, npages, pfn);
209         if (ioptex < 0)
210                 panic("iommu out");
211         busa0 = iommu->start + (ioptex << PAGE_SHIFT);
212         iopte0 = &iommu->page_table[ioptex];
213 
214         busa = busa0;
215         iopte = iopte0;
216         for (i = 0; i < npages; i++) {
217                 iopte_val(*iopte) = MKIOPTE(pfn, IOPERM);
218                 iommu_invalidate_page(iommu->regs, busa);
219                 busa += PAGE_SIZE;
220                 iopte++;
221                 pfn++;
222         }
223 
224         iommu_flush_iotlb(iopte0, npages);
225         return busa0 + off;
226 }
227 
228 static dma_addr_t sbus_iommu_map_page_gflush(struct device *dev,
229                 struct page *page, unsigned long offset, size_t len,
230                 enum dma_data_direction dir, unsigned long attrs)
231 {
232         flush_page_for_dma(0);
233         return __sbus_iommu_map_page(dev, page, offset, len, false);
234 }
235 
236 static dma_addr_t sbus_iommu_map_page_pflush(struct device *dev,
237                 struct page *page, unsigned long offset, size_t len,
238                 enum dma_data_direction dir, unsigned long attrs)
239 {
240         return __sbus_iommu_map_page(dev, page, offset, len, true);
241 }
242 
243 static int __sbus_iommu_map_sg(struct device *dev, struct scatterlist *sgl,
244                 int nents, enum dma_data_direction dir, unsigned long attrs,
245                 bool per_page_flush)
246 {
247         struct scatterlist *sg;
248         int j;
249 
250         for_each_sg(sgl, sg, nents, j) {
251                 sg->dma_address =__sbus_iommu_map_page(dev, sg_page(sg),
252                                 sg->offset, sg->length, per_page_flush);
253                 if (sg->dma_address == DMA_MAPPING_ERROR)
254                         return 0;
255                 sg->dma_length = sg->length;
256         }
257 
258         return nents;
259 }
260 
261 static int sbus_iommu_map_sg_gflush(struct device *dev, struct scatterlist *sgl,
262                 int nents, enum dma_data_direction dir, unsigned long attrs)
263 {
264         flush_page_for_dma(0);
265         return __sbus_iommu_map_sg(dev, sgl, nents, dir, attrs, false);
266 }
267 
268 static int sbus_iommu_map_sg_pflush(struct device *dev, struct scatterlist *sgl,
269                 int nents, enum dma_data_direction dir, unsigned long attrs)
270 {
271         return __sbus_iommu_map_sg(dev, sgl, nents, dir, attrs, true);
272 }
273 
274 static void sbus_iommu_unmap_page(struct device *dev, dma_addr_t dma_addr,
275                 size_t len, enum dma_data_direction dir, unsigned long attrs)
276 {
277         struct iommu_struct *iommu = dev->archdata.iommu;
278         unsigned int busa = dma_addr & PAGE_MASK;
279         unsigned long off = dma_addr & ~PAGE_MASK;
280         unsigned int npages = (off + len + PAGE_SIZE-1) >> PAGE_SHIFT;
281         unsigned int ioptex = (busa - iommu->start) >> PAGE_SHIFT;
282         unsigned int i;
283 
284         BUG_ON(busa < iommu->start);
285         for (i = 0; i < npages; i++) {
286                 iopte_val(iommu->page_table[ioptex + i]) = 0;
287                 iommu_invalidate_page(iommu->regs, busa);
288                 busa += PAGE_SIZE;
289         }
290         bit_map_clear(&iommu->usemap, ioptex, npages);
291 }
292 
293 static void sbus_iommu_unmap_sg(struct device *dev, struct scatterlist *sgl,
294                 int nents, enum dma_data_direction dir, unsigned long attrs)
295 {
296         struct scatterlist *sg;
297         int i;
298 
299         for_each_sg(sgl, sg, nents, i) {
300                 sbus_iommu_unmap_page(dev, sg->dma_address, sg->length, dir,
301                                 attrs);
302                 sg->dma_address = 0x21212121;
303         }
304 }
305 
306 #ifdef CONFIG_SBUS
307 static void *sbus_iommu_alloc(struct device *dev, size_t len,
308                 dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs)
309 {
310         struct iommu_struct *iommu = dev->archdata.iommu;
311         unsigned long va, addr, page, end, ret;
312         iopte_t *iopte = iommu->page_table;
313         iopte_t *first;
314         int ioptex;
315 
316         /* XXX So what is maxphys for us and how do drivers know it? */
317         if (!len || len > 256 * 1024)
318                 return NULL;
319 
320         len = PAGE_ALIGN(len);
321         va = __get_free_pages(gfp | __GFP_ZERO, get_order(len));
322         if (va == 0)
323                 return NULL;
324 
325         addr = ret = sparc_dma_alloc_resource(dev, len);
326         if (!addr)
327                 goto out_free_pages;
328 
329         BUG_ON((va & ~PAGE_MASK) != 0);
330         BUG_ON((addr & ~PAGE_MASK) != 0);
331         BUG_ON((len & ~PAGE_MASK) != 0);
332 
333         /* page color = physical address */
334         ioptex = bit_map_string_get(&iommu->usemap, len >> PAGE_SHIFT,
335                 addr >> PAGE_SHIFT);
336         if (ioptex < 0)
337                 panic("iommu out");
338 
339         iopte += ioptex;
340         first = iopte;
341         end = addr + len;
342         while(addr < end) {
343                 page = va;
344                 {
345                         pgd_t *pgdp;
346                         pmd_t *pmdp;
347                         pte_t *ptep;
348 
349                         if (viking_mxcc_present)
350                                 viking_mxcc_flush_page(page);
351                         else if (viking_flush)
352                                 viking_flush_page(page);
353                         else
354                                 __flush_page_to_ram(page);
355 
356                         pgdp = pgd_offset(&init_mm, addr);
357                         pmdp = pmd_offset(pgdp, addr);
358                         ptep = pte_offset_map(pmdp, addr);
359 
360                         set_pte(ptep, mk_pte(virt_to_page(page), dvma_prot));
361                 }
362                 iopte_val(*iopte++) =
363                     MKIOPTE(page_to_pfn(virt_to_page(page)), ioperm_noc);
364                 addr += PAGE_SIZE;
365                 va += PAGE_SIZE;
366         }
367         /* P3: why do we need this?
368          *
369          * DAVEM: Because there are several aspects, none of which
370          *        are handled by a single interface.  Some cpus are
371          *        completely not I/O DMA coherent, and some have
372          *        virtually indexed caches.  The driver DMA flushing
373          *        methods handle the former case, but here during
374          *        IOMMU page table modifications, and usage of non-cacheable
375          *        cpu mappings of pages potentially in the cpu caches, we have
376          *        to handle the latter case as well.
377          */
378         flush_cache_all();
379         iommu_flush_iotlb(first, len >> PAGE_SHIFT);
380         flush_tlb_all();
381         iommu_invalidate(iommu->regs);
382 
383         *dma_handle = iommu->start + (ioptex << PAGE_SHIFT);
384         return (void *)ret;
385 
386 out_free_pages:
387         free_pages(va, get_order(len));
388         return NULL;
389 }
390 
391 static void sbus_iommu_free(struct device *dev, size_t len, void *cpu_addr,
392                                dma_addr_t busa, unsigned long attrs)
393 {
394         struct iommu_struct *iommu = dev->archdata.iommu;
395         iopte_t *iopte = iommu->page_table;
396         struct page *page = virt_to_page(cpu_addr);
397         int ioptex = (busa - iommu->start) >> PAGE_SHIFT;
398         unsigned long end;
399 
400         if (!sparc_dma_free_resource(cpu_addr, len))
401                 return;
402 
403         BUG_ON((busa & ~PAGE_MASK) != 0);
404         BUG_ON((len & ~PAGE_MASK) != 0);
405 
406         iopte += ioptex;
407         end = busa + len;
408         while (busa < end) {
409                 iopte_val(*iopte++) = 0;
410                 busa += PAGE_SIZE;
411         }
412         flush_tlb_all();
413         iommu_invalidate(iommu->regs);
414         bit_map_clear(&iommu->usemap, ioptex, len >> PAGE_SHIFT);
415 
416         __free_pages(page, get_order(len));
417 }
418 #endif
419 
420 static const struct dma_map_ops sbus_iommu_dma_gflush_ops = {
421 #ifdef CONFIG_SBUS
422         .alloc                  = sbus_iommu_alloc,
423         .free                   = sbus_iommu_free,
424 #endif
425         .map_page               = sbus_iommu_map_page_gflush,
426         .unmap_page             = sbus_iommu_unmap_page,
427         .map_sg                 = sbus_iommu_map_sg_gflush,
428         .unmap_sg               = sbus_iommu_unmap_sg,
429 };
430 
431 static const struct dma_map_ops sbus_iommu_dma_pflush_ops = {
432 #ifdef CONFIG_SBUS
433         .alloc                  = sbus_iommu_alloc,
434         .free                   = sbus_iommu_free,
435 #endif
436         .map_page               = sbus_iommu_map_page_pflush,
437         .unmap_page             = sbus_iommu_unmap_page,
438         .map_sg                 = sbus_iommu_map_sg_pflush,
439         .unmap_sg               = sbus_iommu_unmap_sg,
440 };
441 
442 void __init ld_mmu_iommu(void)
443 {
444         if (flush_page_for_dma_global) {
445                 /* flush_page_for_dma flushes everything, no matter of what page is it */
446                 dma_ops = &sbus_iommu_dma_gflush_ops;
447         } else {
448                 dma_ops = &sbus_iommu_dma_pflush_ops;
449         }
450 
451         if (viking_mxcc_present || srmmu_modtype == HyperSparc) {
452                 dvma_prot = __pgprot(SRMMU_CACHE | SRMMU_ET_PTE | SRMMU_PRIV);
453                 ioperm_noc = IOPTE_CACHE | IOPTE_WRITE | IOPTE_VALID;
454         } else {
455                 dvma_prot = __pgprot(SRMMU_ET_PTE | SRMMU_PRIV);
456                 ioperm_noc = IOPTE_WRITE | IOPTE_VALID;
457         }
458 }
459 

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