1 /*
2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15 #ifndef _ASM_TILE_PROCESSOR_H
16 #define _ASM_TILE_PROCESSOR_H
17
18 #include <arch/chip.h>
19
20 #ifndef __ASSEMBLY__
21
22 /*
23 * NOTE: we don't include <linux/ptrace.h> or <linux/percpu.h> as one
24 * normally would, due to #include dependencies.
25 */
26 #include <linux/types.h>
27 #include <asm/ptrace.h>
28 #include <asm/percpu.h>
29
30 #include <arch/spr_def.h>
31
32 struct task_struct;
33 struct thread_struct;
34
35 typedef struct {
36 unsigned long seg;
37 } mm_segment_t;
38
39 /*
40 * Default implementation of macro that returns current
41 * instruction pointer ("program counter").
42 */
43 void *current_text_addr(void);
44
45 #if CHIP_HAS_TILE_DMA()
46 /* Capture the state of a suspended DMA. */
47 struct tile_dma_state {
48 int enabled;
49 unsigned long src;
50 unsigned long dest;
51 unsigned long strides;
52 unsigned long chunk_size;
53 unsigned long src_chunk;
54 unsigned long dest_chunk;
55 unsigned long byte;
56 unsigned long status;
57 };
58
59 /*
60 * A mask of the DMA status register for selecting only the 'running'
61 * and 'done' bits.
62 */
63 #define DMA_STATUS_MASK \
64 (SPR_DMA_STATUS__RUNNING_MASK | SPR_DMA_STATUS__DONE_MASK)
65 #endif
66
67 /*
68 * Track asynchronous TLB events (faults and access violations)
69 * that occur while we are in kernel mode from DMA or the SN processor.
70 */
71 struct async_tlb {
72 short fault_num; /* original fault number; 0 if none */
73 char is_fault; /* was it a fault (vs an access violation) */
74 char is_write; /* for fault: was it caused by a write? */
75 unsigned long address; /* what address faulted? */
76 };
77
78 #ifdef CONFIG_HARDWALL
79 struct hardwall_info;
80 struct hardwall_task {
81 /* Which hardwall is this task tied to? (or NULL if none) */
82 struct hardwall_info *info;
83 /* Chains this task into the list at info->task_head. */
84 struct list_head list;
85 };
86 #ifdef __tilepro__
87 #define HARDWALL_TYPES 1 /* udn */
88 #else
89 #define HARDWALL_TYPES 3 /* udn, idn, and ipi */
90 #endif
91 #endif
92
93 struct thread_struct {
94 /* kernel stack pointer */
95 unsigned long ksp;
96 /* kernel PC */
97 unsigned long pc;
98 /* starting user stack pointer (for page migration) */
99 unsigned long usp0;
100 /* pid of process that created this one */
101 pid_t creator_pid;
102 #if CHIP_HAS_TILE_DMA()
103 /* DMA info for suspended threads (byte == 0 means no DMA state) */
104 struct tile_dma_state tile_dma_state;
105 #endif
106 /* User EX_CONTEXT registers */
107 unsigned long ex_context[2];
108 /* User SYSTEM_SAVE registers */
109 unsigned long system_save[4];
110 /* User interrupt mask */
111 unsigned long long interrupt_mask;
112 /* User interrupt-control 0 state */
113 unsigned long intctrl_0;
114 /* Any other miscellaneous processor state bits */
115 unsigned long proc_status;
116 #if !CHIP_HAS_FIXED_INTVEC_BASE()
117 /* Interrupt base for PL0 interrupts */
118 unsigned long interrupt_vector_base;
119 #endif
120 /* Tile cache retry fifo high-water mark */
121 unsigned long tile_rtf_hwm;
122 #if CHIP_HAS_DSTREAM_PF()
123 /* Data stream prefetch control */
124 unsigned long dstream_pf;
125 #endif
126 #ifdef CONFIG_HARDWALL
127 /* Hardwall information for various resources. */
128 struct hardwall_task hardwall[HARDWALL_TYPES];
129 #endif
130 #if CHIP_HAS_TILE_DMA()
131 /* Async DMA TLB fault information */
132 struct async_tlb dma_async_tlb;
133 #endif
134 };
135
136 #endif /* !__ASSEMBLY__ */
137
138 /*
139 * Start with "sp" this many bytes below the top of the kernel stack.
140 * This allows us to be cache-aware when handling the initial save
141 * of the pt_regs value to the stack.
142 */
143 #define STACK_TOP_DELTA 64
144
145 /*
146 * When entering the kernel via a fault, start with the top of the
147 * pt_regs structure this many bytes below the top of the page.
148 * This aligns the pt_regs structure optimally for cache-line access.
149 */
150 #ifdef __tilegx__
151 #define KSTK_PTREGS_GAP 48
152 #else
153 #define KSTK_PTREGS_GAP 56
154 #endif
155
156 #ifndef __ASSEMBLY__
157
158 #ifdef __tilegx__
159 #define TASK_SIZE_MAX (_AC(1, UL) << (MAX_VA_WIDTH - 1))
160 #else
161 #define TASK_SIZE_MAX PAGE_OFFSET
162 #endif
163
164 /* TASK_SIZE and related variables are always checked in "current" context. */
165 #ifdef CONFIG_COMPAT
166 #define COMPAT_TASK_SIZE (1UL << 31)
167 #define TASK_SIZE ((current_thread_info()->status & TS_COMPAT) ?\
168 COMPAT_TASK_SIZE : TASK_SIZE_MAX)
169 #else
170 #define TASK_SIZE TASK_SIZE_MAX
171 #endif
172
173 #define VDSO_BASE ((unsigned long)current->active_mm->context.vdso_base)
174 #define VDSO_SYM(x) (VDSO_BASE + (unsigned long)(x))
175
176 #define STACK_TOP TASK_SIZE
177
178 /* STACK_TOP_MAX is used temporarily in execve and should not check COMPAT. */
179 #define STACK_TOP_MAX TASK_SIZE_MAX
180
181 /*
182 * This decides where the kernel will search for a free chunk of vm
183 * space during mmap's, if it is using bottom-up mapping.
184 */
185 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
186
187 #define HAVE_ARCH_PICK_MMAP_LAYOUT
188
189 #define INIT_THREAD { \
190 .ksp = (unsigned long)init_stack + THREAD_SIZE - STACK_TOP_DELTA, \
191 .interrupt_mask = -1ULL \
192 }
193
194 /* Kernel stack top for the task that first boots on this cpu. */
195 DECLARE_PER_CPU(unsigned long, boot_sp);
196
197 /* PC to boot from on this cpu. */
198 DECLARE_PER_CPU(unsigned long, boot_pc);
199
200 /* Do necessary setup to start up a newly executed thread. */
201 static inline void start_thread(struct pt_regs *regs,
202 unsigned long pc, unsigned long usp)
203 {
204 regs->pc = pc;
205 regs->sp = usp;
206 single_step_execve();
207 }
208
209 /* Free all resources held by a thread. */
210 static inline void release_thread(struct task_struct *dead_task)
211 {
212 /* Nothing for now */
213 }
214
215 extern void prepare_exit_to_usermode(struct pt_regs *regs, u32 flags);
216
217 unsigned long get_wchan(struct task_struct *p);
218
219 /* Return initial ksp value for given task. */
220 #define task_ksp0(task) \
221 ((unsigned long)(task)->stack + THREAD_SIZE - STACK_TOP_DELTA)
222
223 /* Return some info about the user process TASK. */
224 #define task_pt_regs(task) \
225 ((struct pt_regs *)(task_ksp0(task) - KSTK_PTREGS_GAP) - 1)
226 #define current_pt_regs() \
227 ((struct pt_regs *)((stack_pointer | (THREAD_SIZE - 1)) - \
228 STACK_TOP_DELTA - (KSTK_PTREGS_GAP - 1)) - 1)
229 #define task_sp(task) (task_pt_regs(task)->sp)
230 #define task_pc(task) (task_pt_regs(task)->pc)
231 /* Aliases for pc and sp (used in fs/proc/array.c) */
232 #define KSTK_EIP(task) task_pc(task)
233 #define KSTK_ESP(task) task_sp(task)
234
235 /* Fine-grained unaligned JIT support */
236 #define GET_UNALIGN_CTL(tsk, adr) get_unalign_ctl((tsk), (adr))
237 #define SET_UNALIGN_CTL(tsk, val) set_unalign_ctl((tsk), (val))
238
239 extern int get_unalign_ctl(struct task_struct *tsk, unsigned long adr);
240 extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val);
241
242 /* Standard format for printing registers and other word-size data. */
243 #ifdef __tilegx__
244 # define REGFMT "0x%016lx"
245 #else
246 # define REGFMT "0x%08lx"
247 #endif
248
249 /*
250 * Do some slow action (e.g. read a slow SPR).
251 * Note that this must also have compiler-barrier semantics since
252 * it may be used in a busy loop reading memory.
253 */
254 static inline void cpu_relax(void)
255 {
256 __insn_mfspr(SPR_PASS);
257 barrier();
258 }
259
260 /* Info on this processor (see fs/proc/cpuinfo.c) */
261 struct seq_operations;
262 extern const struct seq_operations cpuinfo_op;
263
264 /* Provide information about the chip model. */
265 extern char chip_model[64];
266
267 /* Data on which physical memory controller corresponds to which NUMA node. */
268 extern int node_controller[];
269
270 /* Does the heap allocator return hash-for-home pages by default? */
271 extern int hash_default;
272
273 /* Should kernel stack pages be hash-for-home? */
274 extern int kstack_hash;
275
276 /* Does MAP_ANONYMOUS return hash-for-home pages by default? */
277 #define uheap_hash hash_default
278
279
280 /* Are we using huge pages in the TLB for kernel data? */
281 extern int kdata_huge;
282
283 /* Support standard Linux prefetching. */
284 #define ARCH_HAS_PREFETCH
285 #define prefetch(x) __builtin_prefetch(x)
286 #define PREFETCH_STRIDE CHIP_L2_LINE_SIZE()
287
288 /* Bring a value into the L1D, faulting the TLB if necessary. */
289 #ifdef __tilegx__
290 #define prefetch_L1(x) __insn_prefetch_l1_fault((void *)(x))
291 #else
292 #define prefetch_L1(x) __insn_prefetch_L1((void *)(x))
293 #endif
294
295 #else /* __ASSEMBLY__ */
296
297 /* Do some slow action (e.g. read a slow SPR). */
298 #define CPU_RELAX mfspr zero, SPR_PASS
299
300 #endif /* !__ASSEMBLY__ */
301
302 /* Assembly code assumes that the PL is in the low bits. */
303 #if SPR_EX_CONTEXT_1_1__PL_SHIFT != 0
304 # error Fix assembly assumptions about PL
305 #endif
306
307 /* We sometimes use these macros for EX_CONTEXT_0_1 as well. */
308 #if SPR_EX_CONTEXT_1_1__PL_SHIFT != SPR_EX_CONTEXT_0_1__PL_SHIFT || \
309 SPR_EX_CONTEXT_1_1__PL_RMASK != SPR_EX_CONTEXT_0_1__PL_RMASK || \
310 SPR_EX_CONTEXT_1_1__ICS_SHIFT != SPR_EX_CONTEXT_0_1__ICS_SHIFT || \
311 SPR_EX_CONTEXT_1_1__ICS_RMASK != SPR_EX_CONTEXT_0_1__ICS_RMASK
312 # error Fix assumptions that EX1 macros work for both PL0 and PL1
313 #endif
314
315 /* Allow pulling apart and recombining the PL and ICS bits in EX_CONTEXT. */
316 #define EX1_PL(ex1) \
317 (((ex1) >> SPR_EX_CONTEXT_1_1__PL_SHIFT) & SPR_EX_CONTEXT_1_1__PL_RMASK)
318 #define EX1_ICS(ex1) \
319 (((ex1) >> SPR_EX_CONTEXT_1_1__ICS_SHIFT) & SPR_EX_CONTEXT_1_1__ICS_RMASK)
320 #define PL_ICS_EX1(pl, ics) \
321 (((pl) << SPR_EX_CONTEXT_1_1__PL_SHIFT) | \
322 ((ics) << SPR_EX_CONTEXT_1_1__ICS_SHIFT))
323
324 /*
325 * Provide symbolic constants for PLs.
326 */
327 #define USER_PL 0
328 #if CONFIG_KERNEL_PL == 2
329 #define GUEST_PL 1
330 #endif
331 #define KERNEL_PL CONFIG_KERNEL_PL
332
333 /* SYSTEM_SAVE_K_0 holds the current cpu number ORed with ksp0. */
334 #ifdef __tilegx__
335 #define CPU_SHIFT 48
336 #if CHIP_VA_WIDTH() > CPU_SHIFT
337 # error Too many VA bits!
338 #endif
339 #define MAX_CPU_ID ((1 << (64 - CPU_SHIFT)) - 1)
340 #define raw_smp_processor_id() \
341 ((int)(__insn_mfspr(SPR_SYSTEM_SAVE_K_0) >> CPU_SHIFT))
342 #define get_current_ksp0() \
343 ((unsigned long)(((long)__insn_mfspr(SPR_SYSTEM_SAVE_K_0) << \
344 (64 - CPU_SHIFT)) >> (64 - CPU_SHIFT)))
345 #define next_current_ksp0(task) ({ \
346 unsigned long __ksp0 = task_ksp0(task) & ((1UL << CPU_SHIFT) - 1); \
347 unsigned long __cpu = (long)raw_smp_processor_id() << CPU_SHIFT; \
348 __ksp0 | __cpu; \
349 })
350 #else
351 #define LOG2_NR_CPU_IDS 6
352 #define MAX_CPU_ID ((1 << LOG2_NR_CPU_IDS) - 1)
353 #define raw_smp_processor_id() \
354 ((int)__insn_mfspr(SPR_SYSTEM_SAVE_K_0) & MAX_CPU_ID)
355 #define get_current_ksp0() \
356 (__insn_mfspr(SPR_SYSTEM_SAVE_K_0) & ~MAX_CPU_ID)
357 #define next_current_ksp0(task) ({ \
358 unsigned long __ksp0 = task_ksp0(task); \
359 int __cpu = raw_smp_processor_id(); \
360 BUG_ON(__ksp0 & MAX_CPU_ID); \
361 __ksp0 | __cpu; \
362 })
363 #endif
364 #if CONFIG_NR_CPUS > (MAX_CPU_ID + 1)
365 # error Too many cpus!
366 #endif
367
368 #endif /* _ASM_TILE_PROCESSOR_H */
369
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