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Linux/arch/tile/kernel/irq.c

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  1 /*
  2  * Copyright 2010 Tilera Corporation. All Rights Reserved.
  3  *
  4  *   This program is free software; you can redistribute it and/or
  5  *   modify it under the terms of the GNU General Public License
  6  *   as published by the Free Software Foundation, version 2.
  7  *
  8  *   This program is distributed in the hope that it will be useful, but
  9  *   WITHOUT ANY WARRANTY; without even the implied warranty of
 10  *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
 11  *   NON INFRINGEMENT.  See the GNU General Public License for
 12  *   more details.
 13  */
 14 
 15 #include <linux/module.h>
 16 #include <linux/seq_file.h>
 17 #include <linux/interrupt.h>
 18 #include <linux/irq.h>
 19 #include <linux/kernel_stat.h>
 20 #include <linux/uaccess.h>
 21 #include <hv/drv_pcie_rc_intf.h>
 22 #include <arch/spr_def.h>
 23 #include <asm/traps.h>
 24 #include <linux/perf_event.h>
 25 
 26 /* Bit-flag stored in irq_desc->chip_data to indicate HW-cleared irqs. */
 27 #define IS_HW_CLEARED 1
 28 
 29 /*
 30  * The set of interrupts we enable for arch_local_irq_enable().
 31  * This is initialized to have just a single interrupt that the kernel
 32  * doesn't actually use as a sentinel.  During kernel init,
 33  * interrupts are added as the kernel gets prepared to support them.
 34  * NOTE: we could probably initialize them all statically up front.
 35  */
 36 DEFINE_PER_CPU(unsigned long long, interrupts_enabled_mask) =
 37   INITIAL_INTERRUPTS_ENABLED;
 38 EXPORT_PER_CPU_SYMBOL(interrupts_enabled_mask);
 39 
 40 /* Define per-tile device interrupt statistics state. */
 41 DEFINE_PER_CPU(irq_cpustat_t, irq_stat) ____cacheline_internodealigned_in_smp;
 42 EXPORT_PER_CPU_SYMBOL(irq_stat);
 43 
 44 /*
 45  * Define per-tile irq disable mask; the hardware/HV only has a single
 46  * mask that we use to implement both masking and disabling.
 47  */
 48 static DEFINE_PER_CPU(unsigned long, irq_disable_mask)
 49         ____cacheline_internodealigned_in_smp;
 50 
 51 /*
 52  * Per-tile IRQ nesting depth.  Used to make sure we enable newly
 53  * enabled IRQs before exiting the outermost interrupt.
 54  */
 55 static DEFINE_PER_CPU(int, irq_depth);
 56 
 57 #if CHIP_HAS_IPI()
 58 /* Use SPRs to manipulate device interrupts. */
 59 #define mask_irqs(irq_mask) __insn_mtspr(SPR_IPI_MASK_SET_K, irq_mask)
 60 #define unmask_irqs(irq_mask) __insn_mtspr(SPR_IPI_MASK_RESET_K, irq_mask)
 61 #define clear_irqs(irq_mask) __insn_mtspr(SPR_IPI_EVENT_RESET_K, irq_mask)
 62 #else
 63 /* Use HV to manipulate device interrupts. */
 64 #define mask_irqs(irq_mask) hv_disable_intr(irq_mask)
 65 #define unmask_irqs(irq_mask) hv_enable_intr(irq_mask)
 66 #define clear_irqs(irq_mask) hv_clear_intr(irq_mask)
 67 #endif
 68 
 69 /*
 70  * The interrupt handling path, implemented in terms of HV interrupt
 71  * emulation on TILEPro, and IPI hardware on TILE-Gx.
 72  * Entered with interrupts disabled.
 73  */
 74 void tile_dev_intr(struct pt_regs *regs, int intnum)
 75 {
 76         int depth = __this_cpu_inc_return(irq_depth);
 77         unsigned long original_irqs;
 78         unsigned long remaining_irqs;
 79         struct pt_regs *old_regs;
 80 
 81 #if CHIP_HAS_IPI()
 82         /*
 83          * Pending interrupts are listed in an SPR.  We might be
 84          * nested, so be sure to only handle irqs that weren't already
 85          * masked by a previous interrupt.  Then, mask out the ones
 86          * we're going to handle.
 87          */
 88         unsigned long masked = __insn_mfspr(SPR_IPI_MASK_K);
 89         original_irqs = __insn_mfspr(SPR_IPI_EVENT_K) & ~masked;
 90         __insn_mtspr(SPR_IPI_MASK_SET_K, original_irqs);
 91 #else
 92         /*
 93          * Hypervisor performs the equivalent of the Gx code above and
 94          * then puts the pending interrupt mask into a system save reg
 95          * for us to find.
 96          */
 97         original_irqs = __insn_mfspr(SPR_SYSTEM_SAVE_K_3);
 98 #endif
 99         remaining_irqs = original_irqs;
100 
101         /* Track time spent here in an interrupt context. */
102         old_regs = set_irq_regs(regs);
103         irq_enter();
104 
105 #ifdef CONFIG_DEBUG_STACKOVERFLOW
106         /* Debugging check for stack overflow: less than 1/8th stack free? */
107         {
108                 long sp = stack_pointer - (long) current_thread_info();
109                 if (unlikely(sp < (sizeof(struct thread_info) + STACK_WARN))) {
110                         pr_emerg("tile_dev_intr: "
111                                "stack overflow: %ld\n",
112                                sp - sizeof(struct thread_info));
113                         dump_stack();
114                 }
115         }
116 #endif
117         while (remaining_irqs) {
118                 unsigned long irq = __ffs(remaining_irqs);
119                 remaining_irqs &= ~(1UL << irq);
120 
121                 /* Count device irqs; Linux IPIs are counted elsewhere. */
122                 if (irq != IRQ_RESCHEDULE)
123                         __this_cpu_inc(irq_stat.irq_dev_intr_count);
124 
125                 generic_handle_irq(irq);
126         }
127 
128         /*
129          * If we weren't nested, turn on all enabled interrupts,
130          * including any that were reenabled during interrupt
131          * handling.
132          */
133         if (depth == 1)
134                 unmask_irqs(~__this_cpu_read(irq_disable_mask));
135 
136         __this_cpu_dec(irq_depth);
137 
138         /*
139          * Track time spent against the current process again and
140          * process any softirqs if they are waiting.
141          */
142         irq_exit();
143         set_irq_regs(old_regs);
144 }
145 
146 
147 /*
148  * Remove an irq from the disabled mask.  If we're in an interrupt
149  * context, defer enabling the HW interrupt until we leave.
150  */
151 static void tile_irq_chip_enable(struct irq_data *d)
152 {
153         get_cpu_var(irq_disable_mask) &= ~(1UL << d->irq);
154         if (__this_cpu_read(irq_depth) == 0)
155                 unmask_irqs(1UL << d->irq);
156         put_cpu_var(irq_disable_mask);
157 }
158 
159 /*
160  * Add an irq to the disabled mask.  We disable the HW interrupt
161  * immediately so that there's no possibility of it firing.  If we're
162  * in an interrupt context, the return path is careful to avoid
163  * unmasking a newly disabled interrupt.
164  */
165 static void tile_irq_chip_disable(struct irq_data *d)
166 {
167         get_cpu_var(irq_disable_mask) |= (1UL << d->irq);
168         mask_irqs(1UL << d->irq);
169         put_cpu_var(irq_disable_mask);
170 }
171 
172 /* Mask an interrupt. */
173 static void tile_irq_chip_mask(struct irq_data *d)
174 {
175         mask_irqs(1UL << d->irq);
176 }
177 
178 /* Unmask an interrupt. */
179 static void tile_irq_chip_unmask(struct irq_data *d)
180 {
181         unmask_irqs(1UL << d->irq);
182 }
183 
184 /*
185  * Clear an interrupt before processing it so that any new assertions
186  * will trigger another irq.
187  */
188 static void tile_irq_chip_ack(struct irq_data *d)
189 {
190         if ((unsigned long)irq_data_get_irq_chip_data(d) != IS_HW_CLEARED)
191                 clear_irqs(1UL << d->irq);
192 }
193 
194 /*
195  * For per-cpu interrupts, we need to avoid unmasking any interrupts
196  * that we disabled via disable_percpu_irq().
197  */
198 static void tile_irq_chip_eoi(struct irq_data *d)
199 {
200         if (!(__this_cpu_read(irq_disable_mask) & (1UL << d->irq)))
201                 unmask_irqs(1UL << d->irq);
202 }
203 
204 static struct irq_chip tile_irq_chip = {
205         .name = "tile_irq_chip",
206         .irq_enable = tile_irq_chip_enable,
207         .irq_disable = tile_irq_chip_disable,
208         .irq_ack = tile_irq_chip_ack,
209         .irq_eoi = tile_irq_chip_eoi,
210         .irq_mask = tile_irq_chip_mask,
211         .irq_unmask = tile_irq_chip_unmask,
212 };
213 
214 void __init init_IRQ(void)
215 {
216         ipi_init();
217 }
218 
219 void setup_irq_regs(void)
220 {
221         /* Enable interrupt delivery. */
222         unmask_irqs(~0UL);
223 #if CHIP_HAS_IPI()
224         arch_local_irq_unmask(INT_IPI_K);
225 #endif
226 }
227 
228 void tile_irq_activate(unsigned int irq, int tile_irq_type)
229 {
230         /*
231          * We use handle_level_irq() by default because the pending
232          * interrupt vector (whether modeled by the HV on
233          * TILEPro or implemented in hardware on TILE-Gx) has
234          * level-style semantics for each bit.  An interrupt fires
235          * whenever a bit is high, not just at edges.
236          */
237         irq_flow_handler_t handle = handle_level_irq;
238         if (tile_irq_type == TILE_IRQ_PERCPU)
239                 handle = handle_percpu_irq;
240         irq_set_chip_and_handler(irq, &tile_irq_chip, handle);
241 
242         /*
243          * Flag interrupts that are hardware-cleared so that ack()
244          * won't clear them.
245          */
246         if (tile_irq_type == TILE_IRQ_HW_CLEAR)
247                 irq_set_chip_data(irq, (void *)IS_HW_CLEARED);
248 }
249 EXPORT_SYMBOL(tile_irq_activate);
250 
251 
252 void ack_bad_irq(unsigned int irq)
253 {
254         pr_err("unexpected IRQ trap at vector %02x\n", irq);
255 }
256 
257 /*
258  * /proc/interrupts printing:
259  */
260 int arch_show_interrupts(struct seq_file *p, int prec)
261 {
262 #ifdef CONFIG_PERF_EVENTS
263         int i;
264 
265         seq_printf(p, "%*s: ", prec, "PMI");
266 
267         for_each_online_cpu(i)
268                 seq_printf(p, "%10llu ", per_cpu(perf_irqs, i));
269         seq_puts(p, "  perf_events\n");
270 #endif
271         return 0;
272 }
273 
274 #if CHIP_HAS_IPI()
275 int arch_setup_hwirq(unsigned int irq, int node)
276 {
277         return irq >= NR_IRQS ? -EINVAL : 0;
278 }
279 
280 void arch_teardown_hwirq(unsigned int irq) { }
281 #endif
282 

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