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TOMOYO Linux Cross Reference
Linux/arch/tile/kernel/pci.c

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  1 /*
  2  * Copyright 2011 Tilera Corporation. All Rights Reserved.
  3  *
  4  *   This program is free software; you can redistribute it and/or
  5  *   modify it under the terms of the GNU General Public License
  6  *   as published by the Free Software Foundation, version 2.
  7  *
  8  *   This program is distributed in the hope that it will be useful, but
  9  *   WITHOUT ANY WARRANTY; without even the implied warranty of
 10  *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
 11  *   NON INFRINGEMENT.  See the GNU General Public License for
 12  *   more details.
 13  */
 14 
 15 #include <linux/kernel.h>
 16 #include <linux/pci.h>
 17 #include <linux/delay.h>
 18 #include <linux/string.h>
 19 #include <linux/init.h>
 20 #include <linux/capability.h>
 21 #include <linux/sched.h>
 22 #include <linux/errno.h>
 23 #include <linux/bootmem.h>
 24 #include <linux/irq.h>
 25 #include <linux/io.h>
 26 #include <linux/uaccess.h>
 27 #include <linux/export.h>
 28 
 29 #include <asm/processor.h>
 30 #include <asm/sections.h>
 31 #include <asm/byteorder.h>
 32 #include <asm/hv_driver.h>
 33 #include <hv/drv_pcie_rc_intf.h>
 34 
 35 
 36 /*
 37  * Initialization flow and process
 38  * -------------------------------
 39  *
 40  * This files contains the routines to search for PCI buses,
 41  * enumerate the buses, and configure any attached devices.
 42  *
 43  * There are two entry points here:
 44  * 1) tile_pci_init
 45  *    This sets up the pci_controller structs, and opens the
 46  *    FDs to the hypervisor.  This is called from setup_arch() early
 47  *    in the boot process.
 48  * 2) pcibios_init
 49  *    This probes the PCI bus(es) for any attached hardware.  It's
 50  *    called by subsys_initcall.  All of the real work is done by the
 51  *    generic Linux PCI layer.
 52  *
 53  */
 54 
 55 /*
 56  * This flag tells if the platform is TILEmpower that needs
 57  * special configuration for the PLX switch chip.
 58  */
 59 int __write_once tile_plx_gen1;
 60 
 61 static struct pci_controller controllers[TILE_NUM_PCIE];
 62 static int num_controllers;
 63 static int pci_scan_flags[TILE_NUM_PCIE];
 64 
 65 static struct pci_ops tile_cfg_ops;
 66 
 67 
 68 /*
 69  * We don't need to worry about the alignment of resources.
 70  */
 71 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
 72                             resource_size_t size, resource_size_t align)
 73 {
 74         return res->start;
 75 }
 76 EXPORT_SYMBOL(pcibios_align_resource);
 77 
 78 /*
 79  * Open a FD to the hypervisor PCI device.
 80  *
 81  * controller_id is the controller number, config type is 0 or 1 for
 82  * config0 or config1 operations.
 83  */
 84 static int tile_pcie_open(int controller_id, int config_type)
 85 {
 86         char filename[32];
 87         int fd;
 88 
 89         sprintf(filename, "pcie/%d/config%d", controller_id, config_type);
 90 
 91         fd = hv_dev_open((HV_VirtAddr)filename, 0);
 92 
 93         return fd;
 94 }
 95 
 96 
 97 /*
 98  * Get the IRQ numbers from the HV and set up the handlers for them.
 99  */
100 static int tile_init_irqs(int controller_id, struct pci_controller *controller)
101 {
102         char filename[32];
103         int fd;
104         int ret;
105         int x;
106         struct pcie_rc_config rc_config;
107 
108         sprintf(filename, "pcie/%d/ctl", controller_id);
109         fd = hv_dev_open((HV_VirtAddr)filename, 0);
110         if (fd < 0) {
111                 pr_err("PCI: hv_dev_open(%s) failed\n", filename);
112                 return -1;
113         }
114         ret = hv_dev_pread(fd, 0, (HV_VirtAddr)(&rc_config),
115                            sizeof(rc_config), PCIE_RC_CONFIG_MASK_OFF);
116         hv_dev_close(fd);
117         if (ret != sizeof(rc_config)) {
118                 pr_err("PCI: wanted %zd bytes, got %d\n",
119                        sizeof(rc_config), ret);
120                 return -1;
121         }
122         /* Record irq_base so that we can map INTx to IRQ # later. */
123         controller->irq_base = rc_config.intr;
124 
125         for (x = 0; x < 4; x++)
126                 tile_irq_activate(rc_config.intr + x,
127                                   TILE_IRQ_HW_CLEAR);
128 
129         if (rc_config.plx_gen1)
130                 controller->plx_gen1 = 1;
131 
132         return 0;
133 }
134 
135 /*
136  * First initialization entry point, called from setup_arch().
137  *
138  * Find valid controllers and fill in pci_controller structs for each
139  * of them.
140  *
141  * Returns the number of controllers discovered.
142  */
143 int __init tile_pci_init(void)
144 {
145         int i;
146 
147         pr_info("PCI: Searching for controllers...\n");
148 
149         /* Re-init number of PCIe controllers to support hot-plug feature. */
150         num_controllers = 0;
151 
152         /* Do any configuration we need before using the PCIe */
153 
154         for (i = 0; i < TILE_NUM_PCIE; i++) {
155                 /*
156                  * To see whether we need a real config op based on
157                  * the results of pcibios_init(), to support PCIe hot-plug.
158                  */
159                 if (pci_scan_flags[i] == 0) {
160                         int hv_cfg_fd0 = -1;
161                         int hv_cfg_fd1 = -1;
162                         int hv_mem_fd = -1;
163                         char name[32];
164                         struct pci_controller *controller;
165 
166                         /*
167                          * Open the fd to the HV.  If it fails then this
168                          * device doesn't exist.
169                          */
170                         hv_cfg_fd0 = tile_pcie_open(i, 0);
171                         if (hv_cfg_fd0 < 0)
172                                 continue;
173                         hv_cfg_fd1 = tile_pcie_open(i, 1);
174                         if (hv_cfg_fd1 < 0) {
175                                 pr_err("PCI: Couldn't open config fd to HV "
176                                     "for controller %d\n", i);
177                                 goto err_cont;
178                         }
179 
180                         sprintf(name, "pcie/%d/mem", i);
181                         hv_mem_fd = hv_dev_open((HV_VirtAddr)name, 0);
182                         if (hv_mem_fd < 0) {
183                                 pr_err("PCI: Could not open mem fd to HV!\n");
184                                 goto err_cont;
185                         }
186 
187                         pr_info("PCI: Found PCI controller #%d\n", i);
188 
189                         controller = &controllers[i];
190 
191                         controller->index = i;
192                         controller->hv_cfg_fd[0] = hv_cfg_fd0;
193                         controller->hv_cfg_fd[1] = hv_cfg_fd1;
194                         controller->hv_mem_fd = hv_mem_fd;
195                         controller->first_busno = 0;
196                         controller->last_busno = 0xff;
197                         controller->ops = &tile_cfg_ops;
198 
199                         num_controllers++;
200                         continue;
201 
202 err_cont:
203                         if (hv_cfg_fd0 >= 0)
204                                 hv_dev_close(hv_cfg_fd0);
205                         if (hv_cfg_fd1 >= 0)
206                                 hv_dev_close(hv_cfg_fd1);
207                         if (hv_mem_fd >= 0)
208                                 hv_dev_close(hv_mem_fd);
209                         continue;
210                 }
211         }
212 
213         /*
214          * Before using the PCIe, see if we need to do any platform-specific
215          * configuration, such as the PLX switch Gen 1 issue on TILEmpower.
216          */
217         for (i = 0; i < num_controllers; i++) {
218                 struct pci_controller *controller = &controllers[i];
219 
220                 if (controller->plx_gen1)
221                         tile_plx_gen1 = 1;
222         }
223 
224         return num_controllers;
225 }
226 
227 /*
228  * (pin - 1) converts from the PCI standard's [1:4] convention to
229  * a normal [0:3] range.
230  */
231 static int tile_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
232 {
233         struct pci_controller *controller =
234                 (struct pci_controller *)dev->sysdata;
235         return (pin - 1) + controller->irq_base;
236 }
237 
238 
239 static void fixup_read_and_payload_sizes(void)
240 {
241         struct pci_dev *dev = NULL;
242         int smallest_max_payload = 0x1; /* Tile maxes out at 256 bytes. */
243         int max_read_size = 0x2; /* Limit to 512 byte reads. */
244         u16 new_values;
245 
246         /* Scan for the smallest maximum payload size. */
247         for_each_pci_dev(dev) {
248                 u32 devcap;
249                 int max_payload;
250 
251                 if (!pci_is_pcie(dev))
252                         continue;
253 
254                 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &devcap);
255                 max_payload = devcap & PCI_EXP_DEVCAP_PAYLOAD;
256                 if (max_payload < smallest_max_payload)
257                         smallest_max_payload = max_payload;
258         }
259 
260         /* Now, set the max_payload_size for all devices to that value. */
261         new_values = (max_read_size << 12) | (smallest_max_payload << 5);
262         for_each_pci_dev(dev)
263                 pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
264                                 PCI_EXP_DEVCTL_PAYLOAD | PCI_EXP_DEVCTL_READRQ,
265                                 new_values);
266 }
267 
268 
269 /*
270  * Second PCI initialization entry point, called by subsys_initcall.
271  *
272  * The controllers have been set up by the time we get here, by a call to
273  * tile_pci_init.
274  */
275 int __init pcibios_init(void)
276 {
277         int i;
278 
279         pr_info("PCI: Probing PCI hardware\n");
280 
281         /*
282          * Delay a bit in case devices aren't ready.  Some devices are
283          * known to require at least 20ms here, but we use a more
284          * conservative value.
285          */
286         mdelay(250);
287 
288         /* Scan all of the recorded PCI controllers.  */
289         for (i = 0; i < TILE_NUM_PCIE; i++) {
290                 /*
291                  * Do real pcibios init ops if the controller is initialized
292                  * by tile_pci_init() successfully and not initialized by
293                  * pcibios_init() yet to support PCIe hot-plug.
294                  */
295                 if (pci_scan_flags[i] == 0 && controllers[i].ops != NULL) {
296                         struct pci_controller *controller = &controllers[i];
297                         struct pci_bus *bus;
298                         LIST_HEAD(resources);
299 
300                         if (tile_init_irqs(i, controller)) {
301                                 pr_err("PCI: Could not initialize IRQs\n");
302                                 continue;
303                         }
304 
305                         pr_info("PCI: initializing controller #%d\n", i);
306 
307                         /*
308                          * This comes from the generic Linux PCI driver.
309                          *
310                          * It reads the PCI tree for this bus into the Linux
311                          * data structures.
312                          *
313                          * This is inlined in linux/pci.h and calls into
314                          * pci_scan_bus_parented() in probe.c.
315                          */
316                         pci_add_resource(&resources, &ioport_resource);
317                         pci_add_resource(&resources, &iomem_resource);
318                         bus = pci_scan_root_bus(NULL, 0, controller->ops, controller, &resources);
319                         controller->root_bus = bus;
320                         controller->last_busno = bus->busn_res.end;
321                 }
322         }
323 
324         /* Do machine dependent PCI interrupt routing */
325         pci_fixup_irqs(pci_common_swizzle, tile_map_irq);
326 
327         /*
328          * This comes from the generic Linux PCI driver.
329          *
330          * It allocates all of the resources (I/O memory, etc)
331          * associated with the devices read in above.
332          */
333         pci_assign_unassigned_resources();
334 
335         /* Configure the max_read_size and max_payload_size values. */
336         fixup_read_and_payload_sizes();
337 
338         /* Record the I/O resources in the PCI controller structure. */
339         for (i = 0; i < TILE_NUM_PCIE; i++) {
340                 /*
341                  * Do real pcibios init ops if the controller is initialized
342                  * by tile_pci_init() successfully and not initialized by
343                  * pcibios_init() yet to support PCIe hot-plug.
344                  */
345                 if (pci_scan_flags[i] == 0 && controllers[i].ops != NULL) {
346                         struct pci_bus *root_bus = controllers[i].root_bus;
347                         struct pci_bus *next_bus;
348                         struct pci_dev *dev;
349 
350                         list_for_each_entry(dev, &root_bus->devices, bus_list) {
351                                 /*
352                                  * Find the PCI host controller, ie. the 1st
353                                  * bridge.
354                                  */
355                                 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI &&
356                                         (PCI_SLOT(dev->devfn) == 0)) {
357                                         next_bus = dev->subordinate;
358                                         controllers[i].mem_resources[0] =
359                                                 *next_bus->resource[0];
360                                         controllers[i].mem_resources[1] =
361                                                  *next_bus->resource[1];
362                                         controllers[i].mem_resources[2] =
363                                                  *next_bus->resource[2];
364 
365                                         /* Setup flags. */
366                                         pci_scan_flags[i] = 1;
367 
368                                         break;
369                                 }
370                         }
371                 }
372         }
373 
374         return 0;
375 }
376 subsys_initcall(pcibios_init);
377 
378 /*
379  * No bus fixups needed.
380  */
381 void pcibios_fixup_bus(struct pci_bus *bus)
382 {
383         /* Nothing needs to be done. */
384 }
385 
386 void pcibios_set_master(struct pci_dev *dev)
387 {
388         /* No special bus mastering setup handling. */
389 }
390 
391 /*
392  * Enable memory and/or address decoding, as appropriate, for the
393  * device described by the 'dev' struct.
394  *
395  * This is called from the generic PCI layer, and can be called
396  * for bridges or endpoints.
397  */
398 int pcibios_enable_device(struct pci_dev *dev, int mask)
399 {
400         u16 cmd, old_cmd;
401         u8 header_type;
402         int i;
403         struct resource *r;
404 
405         pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type);
406 
407         pci_read_config_word(dev, PCI_COMMAND, &cmd);
408         old_cmd = cmd;
409         if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) {
410                 /*
411                  * For bridges, we enable both memory and I/O decoding
412                  * in call cases.
413                  */
414                 cmd |= PCI_COMMAND_IO;
415                 cmd |= PCI_COMMAND_MEMORY;
416         } else {
417                 /*
418                  * For endpoints, we enable memory and/or I/O decoding
419                  * only if they have a memory resource of that type.
420                  */
421                 for (i = 0; i < 6; i++) {
422                         r = &dev->resource[i];
423                         if (r->flags & IORESOURCE_UNSET) {
424                                 pr_err("PCI: Device %s not available "
425                                        "because of resource collisions\n",
426                                        pci_name(dev));
427                                 return -EINVAL;
428                         }
429                         if (r->flags & IORESOURCE_IO)
430                                 cmd |= PCI_COMMAND_IO;
431                         if (r->flags & IORESOURCE_MEM)
432                                 cmd |= PCI_COMMAND_MEMORY;
433                 }
434         }
435 
436         /*
437          * We only write the command if it changed.
438          */
439         if (cmd != old_cmd)
440                 pci_write_config_word(dev, PCI_COMMAND, cmd);
441         return 0;
442 }
443 
444 /****************************************************************
445  *
446  * Tile PCI config space read/write routines
447  *
448  ****************************************************************/
449 
450 /*
451  * These are the normal read and write ops
452  * These are expanded with macros from  pci_bus_read_config_byte() etc.
453  *
454  * devfn is the combined PCI slot & function.
455  *
456  * offset is in bytes, from the start of config space for the
457  * specified bus & slot.
458  */
459 
460 static int tile_cfg_read(struct pci_bus *bus, unsigned int devfn, int offset,
461                          int size, u32 *val)
462 {
463         struct pci_controller *controller = bus->sysdata;
464         int busnum = bus->number & 0xff;
465         int slot = (devfn >> 3) & 0x1f;
466         int function = devfn & 0x7;
467         u32 addr;
468         int config_mode = 1;
469 
470         /*
471          * There is no bridge between the Tile and bus 0, so we
472          * use config0 to talk to bus 0.
473          *
474          * If we're talking to a bus other than zero then we
475          * must have found a bridge.
476          */
477         if (busnum == 0) {
478                 /*
479                  * We fake an empty slot for (busnum == 0) && (slot > 0),
480                  * since there is only one slot on bus 0.
481                  */
482                 if (slot) {
483                         *val = 0xFFFFFFFF;
484                         return 0;
485                 }
486                 config_mode = 0;
487         }
488 
489         addr = busnum << 20;            /* Bus in 27:20 */
490         addr |= slot << 15;             /* Slot (device) in 19:15 */
491         addr |= function << 12;         /* Function is in 14:12 */
492         addr |= (offset & 0xFFF);       /* byte address in 0:11 */
493 
494         return hv_dev_pread(controller->hv_cfg_fd[config_mode], 0,
495                             (HV_VirtAddr)(val), size, addr);
496 }
497 
498 
499 /*
500  * See tile_cfg_read() for relevant comments.
501  * Note that "val" is the value to write, not a pointer to that value.
502  */
503 static int tile_cfg_write(struct pci_bus *bus, unsigned int devfn, int offset,
504                           int size, u32 val)
505 {
506         struct pci_controller *controller = bus->sysdata;
507         int busnum = bus->number & 0xff;
508         int slot = (devfn >> 3) & 0x1f;
509         int function = devfn & 0x7;
510         u32 addr;
511         int config_mode = 1;
512         HV_VirtAddr valp = (HV_VirtAddr)&val;
513 
514         /*
515          * For bus 0 slot 0 we use config 0 accesses.
516          */
517         if (busnum == 0) {
518                 /*
519                  * We fake an empty slot for (busnum == 0) && (slot > 0),
520                  * since there is only one slot on bus 0.
521                  */
522                 if (slot)
523                         return 0;
524                 config_mode = 0;
525         }
526 
527         addr = busnum << 20;            /* Bus in 27:20 */
528         addr |= slot << 15;             /* Slot (device) in 19:15 */
529         addr |= function << 12;         /* Function is in 14:12 */
530         addr |= (offset & 0xFFF);       /* byte address in 0:11 */
531 
532 #ifdef __BIG_ENDIAN
533         /* Point to the correct part of the 32-bit "val". */
534         valp += 4 - size;
535 #endif
536 
537         return hv_dev_pwrite(controller->hv_cfg_fd[config_mode], 0,
538                              valp, size, addr);
539 }
540 
541 
542 static struct pci_ops tile_cfg_ops = {
543         .read =         tile_cfg_read,
544         .write =        tile_cfg_write,
545 };
546 
547 
548 /*
549  * In the following, each PCI controller's mem_resources[1]
550  * represents its (non-prefetchable) PCI memory resource.
551  * mem_resources[0] and mem_resources[2] refer to its PCI I/O and
552  * prefetchable PCI memory resources, respectively.
553  * For more details, see pci_setup_bridge() in setup-bus.c.
554  * By comparing the target PCI memory address against the
555  * end address of controller 0, we can determine the controller
556  * that should accept the PCI memory access.
557  */
558 #define TILE_READ(size, type)                                           \
559 type _tile_read##size(unsigned long addr)                               \
560 {                                                                       \
561         type val;                                                       \
562         int idx = 0;                                                    \
563         if (addr > controllers[0].mem_resources[1].end &&               \
564             addr > controllers[0].mem_resources[2].end)                 \
565                 idx = 1;                                                \
566         if (hv_dev_pread(controllers[idx].hv_mem_fd, 0,                 \
567                          (HV_VirtAddr)(&val), sizeof(type), addr))      \
568                 pr_err("PCI: read %zd bytes at 0x%lX failed\n",         \
569                        sizeof(type), addr);                             \
570         return val;                                                     \
571 }                                                                       \
572 EXPORT_SYMBOL(_tile_read##size)
573 
574 TILE_READ(b, u8);
575 TILE_READ(w, u16);
576 TILE_READ(l, u32);
577 TILE_READ(q, u64);
578 
579 #define TILE_WRITE(size, type)                                          \
580 void _tile_write##size(type val, unsigned long addr)                    \
581 {                                                                       \
582         int idx = 0;                                                    \
583         if (addr > controllers[0].mem_resources[1].end &&               \
584             addr > controllers[0].mem_resources[2].end)                 \
585                 idx = 1;                                                \
586         if (hv_dev_pwrite(controllers[idx].hv_mem_fd, 0,                \
587                           (HV_VirtAddr)(&val), sizeof(type), addr))     \
588                 pr_err("PCI: write %zd bytes at 0x%lX failed\n",        \
589                        sizeof(type), addr);                             \
590 }                                                                       \
591 EXPORT_SYMBOL(_tile_write##size)
592 
593 TILE_WRITE(b, u8);
594 TILE_WRITE(w, u16);
595 TILE_WRITE(l, u32);
596 TILE_WRITE(q, u64);
597 

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