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TOMOYO Linux Cross Reference
Linux/arch/tile/kernel/pci_gx.c

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  1 /*
  2  * Copyright 2012 Tilera Corporation. All Rights Reserved.
  3  *
  4  *   This program is free software; you can redistribute it and/or
  5  *   modify it under the terms of the GNU General Public License
  6  *   as published by the Free Software Foundation, version 2.
  7  *
  8  *   This program is distributed in the hope that it will be useful, but
  9  *   WITHOUT ANY WARRANTY; without even the implied warranty of
 10  *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
 11  *   NON INFRINGEMENT.  See the GNU General Public License for
 12  *   more details.
 13  */
 14 
 15 #include <linux/kernel.h>
 16 #include <linux/mmzone.h>
 17 #include <linux/pci.h>
 18 #include <linux/delay.h>
 19 #include <linux/string.h>
 20 #include <linux/init.h>
 21 #include <linux/capability.h>
 22 #include <linux/sched.h>
 23 #include <linux/errno.h>
 24 #include <linux/irq.h>
 25 #include <linux/msi.h>
 26 #include <linux/io.h>
 27 #include <linux/uaccess.h>
 28 #include <linux/ctype.h>
 29 
 30 #include <asm/processor.h>
 31 #include <asm/sections.h>
 32 #include <asm/byteorder.h>
 33 
 34 #include <gxio/iorpc_globals.h>
 35 #include <gxio/kiorpc.h>
 36 #include <gxio/trio.h>
 37 #include <gxio/iorpc_trio.h>
 38 #include <hv/drv_trio_intf.h>
 39 
 40 #include <arch/sim.h>
 41 
 42 /*
 43  * This file contains the routines to search for PCI buses,
 44  * enumerate the buses, and configure any attached devices.
 45  */
 46 
 47 #define DEBUG_PCI_CFG   0
 48 
 49 #if DEBUG_PCI_CFG
 50 #define TRACE_CFG_WR(size, val, bus, dev, func, offset) \
 51         pr_info("CFG WR %d-byte VAL %#x to bus %d dev %d func %d addr %u\n", \
 52                 size, val, bus, dev, func, offset & 0xFFF);
 53 #define TRACE_CFG_RD(size, val, bus, dev, func, offset) \
 54         pr_info("CFG RD %d-byte VAL %#x from bus %d dev %d func %d addr %u\n", \
 55                 size, val, bus, dev, func, offset & 0xFFF);
 56 #else
 57 #define TRACE_CFG_WR(...)
 58 #define TRACE_CFG_RD(...)
 59 #endif
 60 
 61 static int pci_probe = 1;
 62 
 63 /* Information on the PCIe RC ports configuration. */
 64 static int pcie_rc[TILEGX_NUM_TRIO][TILEGX_TRIO_PCIES];
 65 
 66 /*
 67  * On some platforms with one or more Gx endpoint ports, we need to
 68  * delay the PCIe RC port probe for a few seconds to work around
 69  * a HW PCIe link-training bug. The exact delay is specified with
 70  * a kernel boot argument in the form of "pcie_rc_delay=T,P,S",
 71  * where T is the TRIO instance number, P is the port number and S is
 72  * the delay in seconds. If the argument is specified, but the delay is
 73  * not provided, the value will be DEFAULT_RC_DELAY.
 74  */
 75 static int rc_delay[TILEGX_NUM_TRIO][TILEGX_TRIO_PCIES];
 76 
 77 /* Default number of seconds that the PCIe RC port probe can be delayed. */
 78 #define DEFAULT_RC_DELAY        10
 79 
 80 /* The PCI I/O space size in each PCI domain. */
 81 #define IO_SPACE_SIZE           0x10000
 82 
 83 /* Provide shorter versions of some very long constant names. */
 84 #define AUTO_CONFIG_RC  \
 85         TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_RC
 86 #define AUTO_CONFIG_RC_G1       \
 87         TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_RC_G1
 88 #define AUTO_CONFIG_EP  \
 89         TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_ENDPOINT
 90 #define AUTO_CONFIG_EP_G1       \
 91         TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_ENDPOINT_G1
 92 
 93 /* Array of the PCIe ports configuration info obtained from the BIB. */
 94 struct pcie_trio_ports_property pcie_ports[TILEGX_NUM_TRIO];
 95 
 96 /* Number of configured TRIO instances. */
 97 int num_trio_shims;
 98 
 99 /* All drivers share the TRIO contexts defined here. */
100 gxio_trio_context_t trio_contexts[TILEGX_NUM_TRIO];
101 
102 /* Pointer to an array of PCIe RC controllers. */
103 struct pci_controller pci_controllers[TILEGX_NUM_TRIO * TILEGX_TRIO_PCIES];
104 int num_rc_controllers;
105 
106 static struct pci_ops tile_cfg_ops;
107 
108 /* Mask of CPUs that should receive PCIe interrupts. */
109 static struct cpumask intr_cpus_map;
110 
111 /*
112  * Pick a CPU to receive and handle the PCIe interrupts, based on the IRQ #.
113  * For now, we simply send interrupts to non-dataplane CPUs.
114  * We may implement methods to allow user to specify the target CPUs,
115  * e.g. via boot arguments.
116  */
117 static int tile_irq_cpu(int irq)
118 {
119         unsigned int count;
120         int i = 0;
121         int cpu;
122 
123         count = cpumask_weight(&intr_cpus_map);
124         if (unlikely(count == 0)) {
125                 pr_warn("intr_cpus_map empty, interrupts will be delivered to dataplane tiles\n");
126                 return irq % (smp_height * smp_width);
127         }
128 
129         count = irq % count;
130         for_each_cpu(cpu, &intr_cpus_map) {
131                 if (i++ == count)
132                         break;
133         }
134         return cpu;
135 }
136 
137 /* Open a file descriptor to the TRIO shim. */
138 static int tile_pcie_open(int trio_index)
139 {
140         gxio_trio_context_t *context = &trio_contexts[trio_index];
141         int ret;
142         int mac;
143 
144         /* This opens a file descriptor to the TRIO shim. */
145         ret = gxio_trio_init(context, trio_index);
146         if (ret < 0)
147                 goto gxio_trio_init_failure;
148 
149         /* Allocate an ASID for the kernel. */
150         ret = gxio_trio_alloc_asids(context, 1, 0, 0);
151         if (ret < 0) {
152                 pr_err("PCI: ASID alloc failure on TRIO %d, give up\n",
153                         trio_index);
154                 goto asid_alloc_failure;
155         }
156 
157         context->asid = ret;
158 
159 #ifdef USE_SHARED_PCIE_CONFIG_REGION
160         /*
161          * Alloc a PIO region for config access, shared by all MACs per TRIO.
162          * This shouldn't fail since the kernel is supposed to the first
163          * client of the TRIO's PIO regions.
164          */
165         ret = gxio_trio_alloc_pio_regions(context, 1, 0, 0);
166         if (ret < 0) {
167                 pr_err("PCI: CFG PIO alloc failure on TRIO %d, give up\n",
168                         trio_index);
169                 goto pio_alloc_failure;
170         }
171 
172         context->pio_cfg_index = ret;
173 
174         /*
175          * For PIO CFG, the bus_address_hi parameter is 0. The mac parameter
176          * is also 0 because it is specified in PIO_REGION_SETUP_CFG_ADDR.
177          */
178         ret = gxio_trio_init_pio_region_aux(context, context->pio_cfg_index,
179                 0, 0, HV_TRIO_PIO_FLAG_CONFIG_SPACE);
180         if (ret < 0) {
181                 pr_err("PCI: CFG PIO init failure on TRIO %d, give up\n",
182                         trio_index);
183                 goto pio_alloc_failure;
184         }
185 #endif
186 
187         /* Get the properties of the PCIe ports on this TRIO instance. */
188         ret = gxio_trio_get_port_property(context, &pcie_ports[trio_index]);
189         if (ret < 0) {
190                 pr_err("PCI: PCIE_GET_PORT_PROPERTY failure, error %d, on TRIO %d\n",
191                        ret, trio_index);
192                 goto get_port_property_failure;
193         }
194 
195         context->mmio_base_mac =
196                 iorpc_ioremap(context->fd, 0, HV_TRIO_CONFIG_IOREMAP_SIZE);
197         if (context->mmio_base_mac == NULL) {
198                 pr_err("PCI: TRIO config space mapping failure, error %d, on TRIO %d\n",
199                        ret, trio_index);
200                 ret = -ENOMEM;
201 
202                 goto trio_mmio_mapping_failure;
203         }
204 
205         /* Check the port strap state which will override the BIB setting. */
206         for (mac = 0; mac < TILEGX_TRIO_PCIES; mac++) {
207                 TRIO_PCIE_INTFC_PORT_CONFIG_t port_config;
208                 unsigned int reg_offset;
209 
210                 /* Ignore ports that are not specified in the BIB. */
211                 if (!pcie_ports[trio_index].ports[mac].allow_rc &&
212                     !pcie_ports[trio_index].ports[mac].allow_ep)
213                         continue;
214 
215                 reg_offset =
216                         (TRIO_PCIE_INTFC_PORT_CONFIG <<
217                                 TRIO_CFG_REGION_ADDR__REG_SHIFT) |
218                         (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_INTERFACE <<
219                                 TRIO_CFG_REGION_ADDR__INTFC_SHIFT) |
220                         (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
221 
222                 port_config.word =
223                         __gxio_mmio_read(context->mmio_base_mac + reg_offset);
224 
225                 if (port_config.strap_state != AUTO_CONFIG_RC &&
226                     port_config.strap_state != AUTO_CONFIG_RC_G1) {
227                         /*
228                          * If this is really intended to be an EP port, record
229                          * it so that the endpoint driver will know about it.
230                          */
231                         if (port_config.strap_state == AUTO_CONFIG_EP ||
232                             port_config.strap_state == AUTO_CONFIG_EP_G1)
233                                 pcie_ports[trio_index].ports[mac].allow_ep = 1;
234                 }
235         }
236 
237         return ret;
238 
239 trio_mmio_mapping_failure:
240 get_port_property_failure:
241 asid_alloc_failure:
242 #ifdef USE_SHARED_PCIE_CONFIG_REGION
243 pio_alloc_failure:
244 #endif
245         hv_dev_close(context->fd);
246 gxio_trio_init_failure:
247         context->fd = -1;
248 
249         return ret;
250 }
251 
252 static int __init tile_trio_init(void)
253 {
254         int i;
255 
256         /* We loop over all the TRIO shims. */
257         for (i = 0; i < TILEGX_NUM_TRIO; i++) {
258                 if (tile_pcie_open(i) < 0)
259                         continue;
260                 num_trio_shims++;
261         }
262 
263         return 0;
264 }
265 postcore_initcall(tile_trio_init);
266 
267 static void tilegx_legacy_irq_ack(struct irq_data *d)
268 {
269         __insn_mtspr(SPR_IPI_EVENT_RESET_K, 1UL << d->irq);
270 }
271 
272 static void tilegx_legacy_irq_mask(struct irq_data *d)
273 {
274         __insn_mtspr(SPR_IPI_MASK_SET_K, 1UL << d->irq);
275 }
276 
277 static void tilegx_legacy_irq_unmask(struct irq_data *d)
278 {
279         __insn_mtspr(SPR_IPI_MASK_RESET_K, 1UL << d->irq);
280 }
281 
282 static struct irq_chip tilegx_legacy_irq_chip = {
283         .name                   = "tilegx_legacy_irq",
284         .irq_ack                = tilegx_legacy_irq_ack,
285         .irq_mask               = tilegx_legacy_irq_mask,
286         .irq_unmask             = tilegx_legacy_irq_unmask,
287 
288         /* TBD: support set_affinity. */
289 };
290 
291 /*
292  * This is a wrapper function of the kernel level-trigger interrupt
293  * handler handle_level_irq() for PCI legacy interrupts. The TRIO
294  * is configured such that only INTx Assert interrupts are proxied
295  * to Linux which just calls handle_level_irq() after clearing the
296  * MAC INTx Assert status bit associated with this interrupt.
297  */
298 static void trio_handle_level_irq(struct irq_desc *desc)
299 {
300         struct pci_controller *controller = irq_desc_get_handler_data(desc);
301         gxio_trio_context_t *trio_context = controller->trio;
302         uint64_t intx = (uint64_t)irq_desc_get_chip_data(desc);
303         int mac = controller->mac;
304         unsigned int reg_offset;
305         uint64_t level_mask;
306 
307         handle_level_irq(desc);
308 
309         /*
310          * Clear the INTx Level status, otherwise future interrupts are
311          * not sent.
312          */
313         reg_offset = (TRIO_PCIE_INTFC_MAC_INT_STS <<
314                 TRIO_CFG_REGION_ADDR__REG_SHIFT) |
315                 (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_INTERFACE <<
316                 TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
317                 (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
318 
319         level_mask = TRIO_PCIE_INTFC_MAC_INT_STS__INT_LEVEL_MASK << intx;
320 
321         __gxio_mmio_write(trio_context->mmio_base_mac + reg_offset, level_mask);
322 }
323 
324 /*
325  * Create kernel irqs and set up the handlers for the legacy interrupts.
326  * Also some minimum initialization for the MSI support.
327  */
328 static int tile_init_irqs(struct pci_controller *controller)
329 {
330         int i;
331         int j;
332         int irq;
333         int result;
334 
335         cpumask_copy(&intr_cpus_map, cpu_online_mask);
336 
337 
338         for (i = 0; i < 4; i++) {
339                 gxio_trio_context_t *context = controller->trio;
340                 int cpu;
341 
342                 /* Ask the kernel to allocate an IRQ. */
343                 irq = irq_alloc_hwirq(-1);
344                 if (!irq) {
345                         pr_err("PCI: no free irq vectors, failed for %d\n", i);
346                         goto free_irqs;
347                 }
348                 controller->irq_intx_table[i] = irq;
349 
350                 /* Distribute the 4 IRQs to different tiles. */
351                 cpu = tile_irq_cpu(irq);
352 
353                 /* Configure the TRIO intr binding for this IRQ. */
354                 result = gxio_trio_config_legacy_intr(context, cpu_x(cpu),
355                                                       cpu_y(cpu), KERNEL_PL,
356                                                       irq, controller->mac, i);
357                 if (result < 0) {
358                         pr_err("PCI: MAC intx config failed for %d\n", i);
359 
360                         goto free_irqs;
361                 }
362 
363                 /* Register the IRQ handler with the kernel. */
364                 irq_set_chip_and_handler(irq, &tilegx_legacy_irq_chip,
365                                         trio_handle_level_irq);
366                 irq_set_chip_data(irq, (void *)(uint64_t)i);
367                 irq_set_handler_data(irq, controller);
368         }
369 
370         return 0;
371 
372 free_irqs:
373         for (j = 0; j < i; j++)
374                 irq_free_hwirq(controller->irq_intx_table[j]);
375 
376         return -1;
377 }
378 
379 /*
380  * Return 1 if the port is strapped to operate in RC mode.
381  */
382 static int
383 strapped_for_rc(gxio_trio_context_t *trio_context, int mac)
384 {
385         TRIO_PCIE_INTFC_PORT_CONFIG_t port_config;
386         unsigned int reg_offset;
387 
388         /* Check the port configuration. */
389         reg_offset =
390                 (TRIO_PCIE_INTFC_PORT_CONFIG <<
391                         TRIO_CFG_REGION_ADDR__REG_SHIFT) |
392                 (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_INTERFACE <<
393                         TRIO_CFG_REGION_ADDR__INTFC_SHIFT) |
394                 (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
395         port_config.word =
396                 __gxio_mmio_read(trio_context->mmio_base_mac + reg_offset);
397 
398         if (port_config.strap_state == AUTO_CONFIG_RC ||
399             port_config.strap_state == AUTO_CONFIG_RC_G1)
400                 return 1;
401         else
402                 return 0;
403 }
404 
405 /*
406  * Find valid controllers and fill in pci_controller structs for each
407  * of them.
408  *
409  * Return the number of controllers discovered.
410  */
411 int __init tile_pci_init(void)
412 {
413         int ctl_index = 0;
414         int i, j;
415 
416         if (!pci_probe) {
417                 pr_info("PCI: disabled by boot argument\n");
418                 return 0;
419         }
420 
421         pr_info("PCI: Searching for controllers...\n");
422 
423         if (num_trio_shims == 0 || sim_is_simulator())
424                 return 0;
425 
426         /*
427          * Now determine which PCIe ports are configured to operate in RC
428          * mode. There is a difference in the port configuration capability
429          * between the Gx36 and Gx72 devices.
430          *
431          * The Gx36 has configuration capability for each of the 3 PCIe
432          * interfaces (disable, auto endpoint, auto RC, etc.).
433          * On the Gx72, you can only select one of the 3 PCIe interfaces per
434          * TRIO to train automatically. Further, the allowable training modes
435          * are reduced to four options (auto endpoint, auto RC, stream x1,
436          * stream x4).
437          *
438          * For Gx36 ports, it must be allowed to be in RC mode by the
439          * Board Information Block, and the hardware strapping pins must be
440          * set to RC mode.
441          *
442          * For Gx72 ports, the port will operate in RC mode if either of the
443          * following is true:
444          * 1. It is allowed to be in RC mode by the Board Information Block,
445          *    and the BIB doesn't allow the EP mode.
446          * 2. It is allowed to be in either the RC or the EP mode by the BIB,
447          *    and the hardware strapping pin is set to RC mode.
448          */
449         for (i = 0; i < TILEGX_NUM_TRIO; i++) {
450                 gxio_trio_context_t *context = &trio_contexts[i];
451 
452                 if (context->fd < 0)
453                         continue;
454 
455                 for (j = 0; j < TILEGX_TRIO_PCIES; j++) {
456                         int is_rc = 0;
457 
458                         if (pcie_ports[i].is_gx72 &&
459                             pcie_ports[i].ports[j].allow_rc) {
460                                 if (!pcie_ports[i].ports[j].allow_ep ||
461                                     strapped_for_rc(context, j))
462                                         is_rc = 1;
463                         } else if (pcie_ports[i].ports[j].allow_rc &&
464                                    strapped_for_rc(context, j)) {
465                                 is_rc = 1;
466                         }
467                         if (is_rc) {
468                                 pcie_rc[i][j] = 1;
469                                 num_rc_controllers++;
470                         }
471                 }
472         }
473 
474         /* Return if no PCIe ports are configured to operate in RC mode. */
475         if (num_rc_controllers == 0)
476                 return 0;
477 
478         /* Set the TRIO pointer and MAC index for each PCIe RC port. */
479         for (i = 0; i < TILEGX_NUM_TRIO; i++) {
480                 for (j = 0; j < TILEGX_TRIO_PCIES; j++) {
481                         if (pcie_rc[i][j]) {
482                                 pci_controllers[ctl_index].trio =
483                                         &trio_contexts[i];
484                                 pci_controllers[ctl_index].mac = j;
485                                 pci_controllers[ctl_index].trio_index = i;
486                                 ctl_index++;
487                                 if (ctl_index == num_rc_controllers)
488                                         goto out;
489                         }
490                 }
491         }
492 
493 out:
494         /* Configure each PCIe RC port. */
495         for (i = 0; i < num_rc_controllers; i++) {
496 
497                 /* Configure the PCIe MAC to run in RC mode. */
498                 struct pci_controller *controller = &pci_controllers[i];
499 
500                 controller->index = i;
501                 controller->ops = &tile_cfg_ops;
502 
503                 controller->io_space.start = PCIBIOS_MIN_IO +
504                         (i * IO_SPACE_SIZE);
505                 controller->io_space.end = controller->io_space.start +
506                         IO_SPACE_SIZE - 1;
507                 BUG_ON(controller->io_space.end > IO_SPACE_LIMIT);
508                 controller->io_space.flags = IORESOURCE_IO;
509                 snprintf(controller->io_space_name,
510                          sizeof(controller->io_space_name),
511                          "PCI I/O domain %d", i);
512                 controller->io_space.name = controller->io_space_name;
513 
514                 /*
515                  * The PCI memory resource is located above the PA space.
516                  * For every host bridge, the BAR window or the MMIO aperture
517                  * is in range [3GB, 4GB - 1] of a 4GB space beyond the
518                  * PA space.
519                  */
520                 controller->mem_offset = TILE_PCI_MEM_START +
521                         (i * TILE_PCI_BAR_WINDOW_TOP);
522                 controller->mem_space.start = controller->mem_offset +
523                         TILE_PCI_BAR_WINDOW_TOP - TILE_PCI_BAR_WINDOW_SIZE;
524                 controller->mem_space.end = controller->mem_offset +
525                         TILE_PCI_BAR_WINDOW_TOP - 1;
526                 controller->mem_space.flags = IORESOURCE_MEM;
527                 snprintf(controller->mem_space_name,
528                          sizeof(controller->mem_space_name),
529                          "PCI mem domain %d", i);
530                 controller->mem_space.name = controller->mem_space_name;
531         }
532 
533         return num_rc_controllers;
534 }
535 
536 /*
537  * (pin - 1) converts from the PCI standard's [1:4] convention to
538  * a normal [0:3] range.
539  */
540 static int tile_map_irq(const struct pci_dev *dev, u8 device, u8 pin)
541 {
542         struct pci_controller *controller =
543                 (struct pci_controller *)dev->sysdata;
544         return controller->irq_intx_table[pin - 1];
545 }
546 
547 static void fixup_read_and_payload_sizes(struct pci_controller *controller)
548 {
549         gxio_trio_context_t *trio_context = controller->trio;
550         struct pci_bus *root_bus = controller->root_bus;
551         TRIO_PCIE_RC_DEVICE_CONTROL_t dev_control;
552         TRIO_PCIE_RC_DEVICE_CAP_t rc_dev_cap;
553         unsigned int reg_offset;
554         struct pci_bus *child;
555         int mac;
556         int err;
557 
558         mac = controller->mac;
559 
560         /* Set our max read request size to be 4KB. */
561         reg_offset =
562                 (TRIO_PCIE_RC_DEVICE_CONTROL <<
563                         TRIO_CFG_REGION_ADDR__REG_SHIFT) |
564                 (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_STANDARD <<
565                         TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
566                 (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
567 
568         dev_control.word = __gxio_mmio_read32(trio_context->mmio_base_mac +
569                                               reg_offset);
570         dev_control.max_read_req_sz = 5;
571         __gxio_mmio_write32(trio_context->mmio_base_mac + reg_offset,
572                             dev_control.word);
573 
574         /*
575          * Set the max payload size supported by this Gx PCIe MAC.
576          * Though Gx PCIe supports Max Payload Size of up to 1024 bytes,
577          * experiments have shown that setting MPS to 256 yields the
578          * best performance.
579          */
580         reg_offset =
581                 (TRIO_PCIE_RC_DEVICE_CAP <<
582                         TRIO_CFG_REGION_ADDR__REG_SHIFT) |
583                 (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_STANDARD <<
584                         TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
585                 (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
586 
587         rc_dev_cap.word = __gxio_mmio_read32(trio_context->mmio_base_mac +
588                                              reg_offset);
589         rc_dev_cap.mps_sup = 1;
590         __gxio_mmio_write32(trio_context->mmio_base_mac + reg_offset,
591                             rc_dev_cap.word);
592 
593         /* Configure PCI Express MPS setting. */
594         list_for_each_entry(child, &root_bus->children, node)
595                 pcie_bus_configure_settings(child);
596 
597         /*
598          * Set the mac_config register in trio based on the MPS/MRS of the link.
599          */
600         reg_offset =
601                 (TRIO_PCIE_RC_DEVICE_CONTROL <<
602                         TRIO_CFG_REGION_ADDR__REG_SHIFT) |
603                 (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_STANDARD <<
604                         TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
605                 (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
606 
607         dev_control.word = __gxio_mmio_read32(trio_context->mmio_base_mac +
608                                                 reg_offset);
609 
610         err = gxio_trio_set_mps_mrs(trio_context,
611                                     dev_control.max_payload_size,
612                                     dev_control.max_read_req_sz,
613                                     mac);
614         if (err < 0) {
615                 pr_err("PCI: PCIE_CONFIGURE_MAC_MPS_MRS failure, MAC %d on TRIO %d\n",
616                        mac, controller->trio_index);
617         }
618 }
619 
620 static int setup_pcie_rc_delay(char *str)
621 {
622         unsigned long delay = 0;
623         unsigned long trio_index;
624         unsigned long mac;
625 
626         if (str == NULL || !isdigit(*str))
627                 return -EINVAL;
628         trio_index = simple_strtoul(str, (char **)&str, 10);
629         if (trio_index >= TILEGX_NUM_TRIO)
630                 return -EINVAL;
631 
632         if (*str != ',')
633                 return -EINVAL;
634 
635         str++;
636         if (!isdigit(*str))
637                 return -EINVAL;
638         mac = simple_strtoul(str, (char **)&str, 10);
639         if (mac >= TILEGX_TRIO_PCIES)
640                 return -EINVAL;
641 
642         if (*str != '\0') {
643                 if (*str != ',')
644                         return -EINVAL;
645 
646                 str++;
647                 if (!isdigit(*str))
648                         return -EINVAL;
649                 delay = simple_strtoul(str, (char **)&str, 10);
650         }
651 
652         rc_delay[trio_index][mac] = delay ? : DEFAULT_RC_DELAY;
653         return 0;
654 }
655 early_param("pcie_rc_delay", setup_pcie_rc_delay);
656 
657 /* PCI initialization entry point, called by subsys_initcall. */
658 int __init pcibios_init(void)
659 {
660         resource_size_t offset;
661         LIST_HEAD(resources);
662         int next_busno;
663         struct pci_host_bridge *bridge;
664         int i;
665 
666         tile_pci_init();
667 
668         if (num_rc_controllers == 0)
669                 return 0;
670 
671         /*
672          * Delay a bit in case devices aren't ready.  Some devices are
673          * known to require at least 20ms here, but we use a more
674          * conservative value.
675          */
676         msleep(250);
677 
678         /* Scan all of the recorded PCI controllers.  */
679         for (next_busno = 0, i = 0; i < num_rc_controllers; i++) {
680                 struct pci_controller *controller = &pci_controllers[i];
681                 gxio_trio_context_t *trio_context = controller->trio;
682                 TRIO_PCIE_INTFC_PORT_STATUS_t port_status;
683                 TRIO_PCIE_INTFC_TX_FIFO_CTL_t tx_fifo_ctl;
684                 struct pci_bus *bus;
685                 unsigned int reg_offset;
686                 unsigned int class_code_revision;
687                 int trio_index;
688                 int mac;
689                 int ret;
690 
691                 if (trio_context->fd < 0)
692                         continue;
693 
694                 trio_index = controller->trio_index;
695                 mac = controller->mac;
696 
697                 /*
698                  * Check for PCIe link-up status to decide if we need
699                  * to force the link to come up.
700                  */
701                 reg_offset =
702                         (TRIO_PCIE_INTFC_PORT_STATUS <<
703                                 TRIO_CFG_REGION_ADDR__REG_SHIFT) |
704                         (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_INTERFACE <<
705                                 TRIO_CFG_REGION_ADDR__INTFC_SHIFT) |
706                         (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
707 
708                 port_status.word =
709                         __gxio_mmio_read(trio_context->mmio_base_mac +
710                                          reg_offset);
711                 if (!port_status.dl_up) {
712                         if (rc_delay[trio_index][mac]) {
713                                 pr_info("Delaying PCIe RC TRIO init %d sec on MAC %d on TRIO %d\n",
714                                         rc_delay[trio_index][mac], mac,
715                                         trio_index);
716                                 msleep(rc_delay[trio_index][mac] * 1000);
717                         }
718                         ret = gxio_trio_force_rc_link_up(trio_context, mac);
719                         if (ret < 0)
720                                 pr_err("PCI: PCIE_FORCE_LINK_UP failure, MAC %d on TRIO %d\n",
721                                        mac, trio_index);
722                 }
723 
724                 pr_info("PCI: Found PCI controller #%d on TRIO %d MAC %d\n",
725                         i, trio_index, controller->mac);
726 
727                 /* Delay the bus probe if needed. */
728                 if (rc_delay[trio_index][mac]) {
729                         pr_info("Delaying PCIe RC bus enumerating %d sec on MAC %d on TRIO %d\n",
730                                 rc_delay[trio_index][mac], mac, trio_index);
731                         msleep(rc_delay[trio_index][mac] * 1000);
732                 } else {
733                         /*
734                          * Wait a bit here because some EP devices
735                          * take longer to come up.
736                          */
737                         msleep(1000);
738                 }
739 
740                 /* Check for PCIe link-up status again. */
741                 port_status.word =
742                         __gxio_mmio_read(trio_context->mmio_base_mac +
743                                          reg_offset);
744                 if (!port_status.dl_up) {
745                         if (pcie_ports[trio_index].ports[mac].removable) {
746                                 pr_info("PCI: link is down, MAC %d on TRIO %d\n",
747                                         mac, trio_index);
748                                 pr_info("This is expected if no PCIe card is connected to this link\n");
749                         } else
750                                 pr_err("PCI: link is down, MAC %d on TRIO %d\n",
751                                        mac, trio_index);
752                         continue;
753                 }
754 
755                 /*
756                  * Ensure that the link can come out of L1 power down state.
757                  * Strictly speaking, this is needed only in the case of
758                  * heavy RC-initiated DMAs.
759                  */
760                 reg_offset =
761                         (TRIO_PCIE_INTFC_TX_FIFO_CTL <<
762                                 TRIO_CFG_REGION_ADDR__REG_SHIFT) |
763                         (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_INTERFACE <<
764                                 TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
765                         (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
766                 tx_fifo_ctl.word =
767                         __gxio_mmio_read(trio_context->mmio_base_mac +
768                                          reg_offset);
769                 tx_fifo_ctl.min_p_credits = 0;
770                 __gxio_mmio_write(trio_context->mmio_base_mac + reg_offset,
771                                   tx_fifo_ctl.word);
772 
773                 /*
774                  * Change the device ID so that Linux bus crawl doesn't confuse
775                  * the internal bridge with any Tilera endpoints.
776                  */
777                 reg_offset =
778                         (TRIO_PCIE_RC_DEVICE_ID_VEN_ID <<
779                                 TRIO_CFG_REGION_ADDR__REG_SHIFT) |
780                         (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_STANDARD <<
781                                 TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
782                         (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
783 
784                 __gxio_mmio_write32(trio_context->mmio_base_mac + reg_offset,
785                                     (TILERA_GX36_RC_DEV_ID <<
786                                     TRIO_PCIE_RC_DEVICE_ID_VEN_ID__DEV_ID_SHIFT) |
787                                     TILERA_VENDOR_ID);
788 
789                 /* Set the internal P2P bridge class code. */
790                 reg_offset =
791                         (TRIO_PCIE_RC_REVISION_ID <<
792                                 TRIO_CFG_REGION_ADDR__REG_SHIFT) |
793                         (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_STANDARD <<
794                                 TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
795                         (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
796 
797                 class_code_revision =
798                         __gxio_mmio_read32(trio_context->mmio_base_mac +
799                                            reg_offset);
800                 class_code_revision = (class_code_revision & 0xff) |
801                         (PCI_CLASS_BRIDGE_PCI << 16);
802 
803                 __gxio_mmio_write32(trio_context->mmio_base_mac +
804                                     reg_offset, class_code_revision);
805 
806 #ifdef USE_SHARED_PCIE_CONFIG_REGION
807 
808                 /* Map in the MMIO space for the PIO region. */
809                 offset = HV_TRIO_PIO_OFFSET(trio_context->pio_cfg_index) |
810                         (((unsigned long long)mac) <<
811                         TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR__MAC_SHIFT);
812 
813 #else
814 
815                 /* Alloc a PIO region for PCI config access per MAC. */
816                 ret = gxio_trio_alloc_pio_regions(trio_context, 1, 0, 0);
817                 if (ret < 0) {
818                         pr_err("PCI: PCI CFG PIO alloc failure for mac %d on TRIO %d, give up\n",
819                                mac, trio_index);
820 
821                         continue;
822                 }
823 
824                 trio_context->pio_cfg_index[mac] = ret;
825 
826                 /* For PIO CFG, the bus_address_hi parameter is 0. */
827                 ret = gxio_trio_init_pio_region_aux(trio_context,
828                         trio_context->pio_cfg_index[mac],
829                         mac, 0, HV_TRIO_PIO_FLAG_CONFIG_SPACE);
830                 if (ret < 0) {
831                         pr_err("PCI: PCI CFG PIO init failure for mac %d on TRIO %d, give up\n",
832                                mac, trio_index);
833 
834                         continue;
835                 }
836 
837                 offset = HV_TRIO_PIO_OFFSET(trio_context->pio_cfg_index[mac]) |
838                         (((unsigned long long)mac) <<
839                         TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR__MAC_SHIFT);
840 
841 #endif
842 
843                 /*
844                  * To save VMALLOC space, we take advantage of the fact that
845                  * bit 29 in the PIO CFG address format is reserved 0. With
846                  * TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR__MAC_SHIFT being 30,
847                  * this cuts VMALLOC space usage from 1GB to 512MB per mac.
848                  */
849                 trio_context->mmio_base_pio_cfg[mac] =
850                         iorpc_ioremap(trio_context->fd, offset, (1UL <<
851                         (TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR__MAC_SHIFT - 1)));
852                 if (trio_context->mmio_base_pio_cfg[mac] == NULL) {
853                         pr_err("PCI: PIO map failure for mac %d on TRIO %d\n",
854                                mac, trio_index);
855 
856                         continue;
857                 }
858 
859                 /* Initialize the PCIe interrupts. */
860                 if (tile_init_irqs(controller)) {
861                         pr_err("PCI: IRQs init failure for mac %d on TRIO %d\n",
862                                 mac, trio_index);
863 
864                         continue;
865                 }
866 
867                 /*
868                  * The PCI memory resource is located above the PA space.
869                  * The memory range for the PCI root bus should not overlap
870                  * with the physical RAM.
871                  */
872                 pci_add_resource_offset(&resources, &controller->mem_space,
873                                         controller->mem_offset);
874                 pci_add_resource(&resources, &controller->io_space);
875                 controller->first_busno = next_busno;
876 
877                 bridge = pci_alloc_host_bridge(0);
878                 if (!bridge)
879                         break;
880 
881                 list_splice_init(&resources, &bridge->windows);
882                 bridge->dev.parent = NULL;
883                 bridge->sysdata = controller;
884                 bridge->busnr = next_busno;
885                 bridge->ops = controller->ops;
886                 bridge->swizzle_irq = pci_common_swizzle;
887                 bridge->map_irq = tile_map_irq;
888 
889                 pci_scan_root_bus_bridge(bridge);
890                 bus = bridge->bus;
891                 controller->root_bus = bus;
892                 next_busno = bus->busn_res.end + 1;
893         }
894 
895         /*
896          * This comes from the generic Linux PCI driver.
897          *
898          * It allocates all of the resources (I/O memory, etc)
899          * associated with the devices read in above.
900          */
901         pci_assign_unassigned_resources();
902 
903         /* Record the I/O resources in the PCI controller structure. */
904         for (i = 0; i < num_rc_controllers; i++) {
905                 struct pci_controller *controller = &pci_controllers[i];
906                 gxio_trio_context_t *trio_context = controller->trio;
907                 struct pci_bus *root_bus = pci_controllers[i].root_bus;
908                 int ret;
909                 int j;
910 
911                 /*
912                  * Skip controllers that are not properly initialized or
913                  * have down links.
914                  */
915                 if (root_bus == NULL)
916                         continue;
917 
918                 /* Configure the max_payload_size values for this domain. */
919                 fixup_read_and_payload_sizes(controller);
920 
921                 /* Alloc a PIO region for PCI memory access for each RC port. */
922                 ret = gxio_trio_alloc_pio_regions(trio_context, 1, 0, 0);
923                 if (ret < 0) {
924                         pr_err("PCI: MEM PIO alloc failure on TRIO %d mac %d, give up\n",
925                                controller->trio_index, controller->mac);
926 
927                         continue;
928                 }
929 
930                 controller->pio_mem_index = ret;
931 
932                 /*
933                  * For PIO MEM, the bus_address_hi parameter is hard-coded 0
934                  * because we always assign 32-bit PCI bus BAR ranges.
935                  */
936                 ret = gxio_trio_init_pio_region_aux(trio_context,
937                                                     controller->pio_mem_index,
938                                                     controller->mac,
939                                                     0,
940                                                     0);
941                 if (ret < 0) {
942                         pr_err("PCI: MEM PIO init failure on TRIO %d mac %d, give up\n",
943                                controller->trio_index, controller->mac);
944 
945                         continue;
946                 }
947 
948 #ifdef CONFIG_TILE_PCI_IO
949                 /*
950                  * Alloc a PIO region for PCI I/O space access for each RC port.
951                  */
952                 ret = gxio_trio_alloc_pio_regions(trio_context, 1, 0, 0);
953                 if (ret < 0) {
954                         pr_err("PCI: I/O PIO alloc failure on TRIO %d mac %d, give up\n",
955                                controller->trio_index, controller->mac);
956 
957                         continue;
958                 }
959 
960                 controller->pio_io_index = ret;
961 
962                 /*
963                  * For PIO IO, the bus_address_hi parameter is hard-coded 0
964                  * because PCI I/O address space is 32-bit.
965                  */
966                 ret = gxio_trio_init_pio_region_aux(trio_context,
967                                                     controller->pio_io_index,
968                                                     controller->mac,
969                                                     0,
970                                                     HV_TRIO_PIO_FLAG_IO_SPACE);
971                 if (ret < 0) {
972                         pr_err("PCI: I/O PIO init failure on TRIO %d mac %d, give up\n",
973                                controller->trio_index, controller->mac);
974 
975                         continue;
976                 }
977 #endif
978 
979                 /*
980                  * Configure a Mem-Map region for each memory controller so
981                  * that Linux can map all of its PA space to the PCI bus.
982                  * Use the IOMMU to handle hash-for-home memory.
983                  */
984                 for_each_online_node(j) {
985                         unsigned long start_pfn = node_start_pfn[j];
986                         unsigned long end_pfn = node_end_pfn[j];
987                         unsigned long nr_pages = end_pfn - start_pfn;
988 
989                         ret = gxio_trio_alloc_memory_maps(trio_context, 1, 0,
990                                                           0);
991                         if (ret < 0) {
992                                 pr_err("PCI: Mem-Map alloc failure on TRIO %d mac %d for MC %d, give up\n",
993                                        controller->trio_index, controller->mac,
994                                        j);
995 
996                                 goto alloc_mem_map_failed;
997                         }
998 
999                         controller->mem_maps[j] = ret;
1000 
1001                         /*
1002                          * Initialize the Mem-Map and the I/O MMU so that all
1003                          * the physical memory can be accessed by the endpoint
1004                          * devices. The base bus address is set to the base CPA
1005                          * of this memory controller plus an offset (see pci.h).
1006                          * The region's base VA is set to the base CPA. The
1007                          * I/O MMU table essentially translates the CPA to
1008                          * the real PA. Implicitly, for node 0, we create
1009                          * a separate Mem-Map region that serves as the inbound
1010                          * window for legacy 32-bit devices. This is a direct
1011                          * map of the low 4GB CPA space.
1012                          */
1013                         ret = gxio_trio_init_memory_map_mmu_aux(trio_context,
1014                                 controller->mem_maps[j],
1015                                 start_pfn << PAGE_SHIFT,
1016                                 nr_pages << PAGE_SHIFT,
1017                                 trio_context->asid,
1018                                 controller->mac,
1019                                 (start_pfn << PAGE_SHIFT) +
1020                                 TILE_PCI_MEM_MAP_BASE_OFFSET,
1021                                 j,
1022                                 GXIO_TRIO_ORDER_MODE_UNORDERED);
1023                         if (ret < 0) {
1024                                 pr_err("PCI: Mem-Map init failure on TRIO %d mac %d for MC %d, give up\n",
1025                                        controller->trio_index, controller->mac,
1026                                        j);
1027 
1028                                 goto alloc_mem_map_failed;
1029                         }
1030                         continue;
1031 
1032 alloc_mem_map_failed:
1033                         break;
1034                 }
1035 
1036                 pci_bus_add_devices(root_bus);
1037         }
1038 
1039         return 0;
1040 }
1041 subsys_initcall(pcibios_init);
1042 
1043 /* Process any "pci=" kernel boot arguments. */
1044 char *__init pcibios_setup(char *str)
1045 {
1046         if (!strcmp(str, "off")) {
1047                 pci_probe = 0;
1048                 return NULL;
1049         }
1050         return str;
1051 }
1052 
1053 /*
1054  * Called for each device after PCI setup is done.
1055  * We initialize the PCI device capabilities conservatively, assuming that
1056  * all devices can only address the 32-bit DMA space. The exception here is
1057  * that the device dma_offset is set to the value that matches the 64-bit
1058  * capable devices. This is OK because dma_offset is not used by legacy
1059  * dma_ops, nor by the hybrid dma_ops's streaming DMAs, which are 64-bit ops.
1060  * This implementation matches the kernel design of setting PCI devices'
1061  * coherent_dma_mask to 0xffffffffull by default, allowing the device drivers
1062  * to skip calling pci_set_consistent_dma_mask(DMA_BIT_MASK(32)).
1063  */
1064 static void pcibios_fixup_final(struct pci_dev *pdev)
1065 {
1066         set_dma_ops(&pdev->dev, gx_legacy_pci_dma_map_ops);
1067         set_dma_offset(&pdev->dev, TILE_PCI_MEM_MAP_BASE_OFFSET);
1068         pdev->dev.archdata.max_direct_dma_addr =
1069                 TILE_PCI_MAX_DIRECT_DMA_ADDRESS;
1070         pdev->dev.coherent_dma_mask = TILE_PCI_MAX_DIRECT_DMA_ADDRESS;
1071 }
1072 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_final);
1073 
1074 /* Map a PCI MMIO bus address into VA space. */
1075 void __iomem *ioremap(resource_size_t phys_addr, unsigned long size)
1076 {
1077         struct pci_controller *controller = NULL;
1078         resource_size_t bar_start;
1079         resource_size_t bar_end;
1080         resource_size_t offset;
1081         resource_size_t start;
1082         resource_size_t end;
1083         int trio_fd;
1084         int i;
1085 
1086         start = phys_addr;
1087         end = phys_addr + size - 1;
1088 
1089         /*
1090          * By searching phys_addr in each controller's mem_space, we can
1091          * determine the controller that should accept the PCI memory access.
1092          */
1093         for (i = 0; i < num_rc_controllers; i++) {
1094                 /*
1095                  * Skip controllers that are not properly initialized or
1096                  * have down links.
1097                  */
1098                 if (pci_controllers[i].root_bus == NULL)
1099                         continue;
1100 
1101                 bar_start = pci_controllers[i].mem_space.start;
1102                 bar_end = pci_controllers[i].mem_space.end;
1103 
1104                 if ((start >= bar_start) && (end <= bar_end)) {
1105                         controller = &pci_controllers[i];
1106                         break;
1107                 }
1108         }
1109 
1110         if (controller == NULL)
1111                 return NULL;
1112 
1113         trio_fd = controller->trio->fd;
1114 
1115         /* Convert the resource start to the bus address offset. */
1116         start = phys_addr - controller->mem_offset;
1117 
1118         offset = HV_TRIO_PIO_OFFSET(controller->pio_mem_index) + start;
1119 
1120         /* We need to keep the PCI bus address's in-page offset in the VA. */
1121         return iorpc_ioremap(trio_fd, offset, size) +
1122                 (start & (PAGE_SIZE - 1));
1123 }
1124 EXPORT_SYMBOL(ioremap);
1125 
1126 #ifdef CONFIG_TILE_PCI_IO
1127 /* Map a PCI I/O address into VA space. */
1128 void __iomem *ioport_map(unsigned long port, unsigned int size)
1129 {
1130         struct pci_controller *controller = NULL;
1131         resource_size_t bar_start;
1132         resource_size_t bar_end;
1133         resource_size_t offset;
1134         resource_size_t start;
1135         resource_size_t end;
1136         int trio_fd;
1137         int i;
1138 
1139         start = port;
1140         end = port + size - 1;
1141 
1142         /*
1143          * By searching the port in each controller's io_space, we can
1144          * determine the controller that should accept the PCI I/O access.
1145          */
1146         for (i = 0; i < num_rc_controllers; i++) {
1147                 /*
1148                  * Skip controllers that are not properly initialized or
1149                  * have down links.
1150                  */
1151                 if (pci_controllers[i].root_bus == NULL)
1152                         continue;
1153 
1154                 bar_start = pci_controllers[i].io_space.start;
1155                 bar_end = pci_controllers[i].io_space.end;
1156 
1157                 if ((start >= bar_start) && (end <= bar_end)) {
1158                         controller = &pci_controllers[i];
1159                         break;
1160                 }
1161         }
1162 
1163         if (controller == NULL)
1164                 return NULL;
1165 
1166         trio_fd = controller->trio->fd;
1167 
1168         /* Convert the resource start to the bus address offset. */
1169         port -= controller->io_space.start;
1170 
1171         offset = HV_TRIO_PIO_OFFSET(controller->pio_io_index) + port;
1172 
1173         /* We need to keep the PCI bus address's in-page offset in the VA. */
1174         return iorpc_ioremap(trio_fd, offset, size) + (port & (PAGE_SIZE - 1));
1175 }
1176 EXPORT_SYMBOL(ioport_map);
1177 
1178 void ioport_unmap(void __iomem *addr)
1179 {
1180         iounmap(addr);
1181 }
1182 EXPORT_SYMBOL(ioport_unmap);
1183 #endif
1184 
1185 void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
1186 {
1187         iounmap(addr);
1188 }
1189 EXPORT_SYMBOL(pci_iounmap);
1190 
1191 /****************************************************************
1192  *
1193  * Tile PCI config space read/write routines
1194  *
1195  ****************************************************************/
1196 
1197 /*
1198  * These are the normal read and write ops
1199  * These are expanded with macros from  pci_bus_read_config_byte() etc.
1200  *
1201  * devfn is the combined PCI device & function.
1202  *
1203  * offset is in bytes, from the start of config space for the
1204  * specified bus & device.
1205  */
1206 static int tile_cfg_read(struct pci_bus *bus, unsigned int devfn, int offset,
1207                          int size, u32 *val)
1208 {
1209         struct pci_controller *controller = bus->sysdata;
1210         gxio_trio_context_t *trio_context = controller->trio;
1211         int busnum = bus->number & 0xff;
1212         int device = PCI_SLOT(devfn);
1213         int function = PCI_FUNC(devfn);
1214         int config_type = 1;
1215         TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR_t cfg_addr;
1216         void *mmio_addr;
1217 
1218         /*
1219          * Map all accesses to the local device on root bus into the
1220          * MMIO space of the MAC. Accesses to the downstream devices
1221          * go to the PIO space.
1222          */
1223         if (pci_is_root_bus(bus)) {
1224                 if (device == 0) {
1225                         /*
1226                          * This is the internal downstream P2P bridge,
1227                          * access directly.
1228                          */
1229                         unsigned int reg_offset;
1230 
1231                         reg_offset = ((offset & 0xFFF) <<
1232                                 TRIO_CFG_REGION_ADDR__REG_SHIFT) |
1233                                 (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_PROTECTED
1234                                 << TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
1235                                 (controller->mac <<
1236                                         TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
1237 
1238                         mmio_addr = trio_context->mmio_base_mac + reg_offset;
1239 
1240                         goto valid_device;
1241 
1242                 } else {
1243                         /*
1244                          * We fake an empty device for (device > 0),
1245                          * since there is only one device on bus 0.
1246                          */
1247                         goto invalid_device;
1248                 }
1249         }
1250 
1251         /*
1252          * Accesses to the directly attached device have to be
1253          * sent as type-0 configs.
1254          */
1255         if (busnum == (controller->first_busno + 1)) {
1256                 /*
1257                  * There is only one device off of our built-in P2P bridge.
1258                  */
1259                 if (device != 0)
1260                         goto invalid_device;
1261 
1262                 config_type = 0;
1263         }
1264 
1265         cfg_addr.word = 0;
1266         cfg_addr.reg_addr = (offset & 0xFFF);
1267         cfg_addr.fn = function;
1268         cfg_addr.dev = device;
1269         cfg_addr.bus = busnum;
1270         cfg_addr.type = config_type;
1271 
1272         /*
1273          * Note that we don't set the mac field in cfg_addr because the
1274          * mapping is per port.
1275          */
1276         mmio_addr = trio_context->mmio_base_pio_cfg[controller->mac] +
1277                 cfg_addr.word;
1278 
1279 valid_device:
1280 
1281         switch (size) {
1282         case 4:
1283                 *val = __gxio_mmio_read32(mmio_addr);
1284                 break;
1285 
1286         case 2:
1287                 *val = __gxio_mmio_read16(mmio_addr);
1288                 break;
1289 
1290         case 1:
1291                 *val = __gxio_mmio_read8(mmio_addr);
1292                 break;
1293 
1294         default:
1295                 return PCIBIOS_FUNC_NOT_SUPPORTED;
1296         }
1297 
1298         TRACE_CFG_RD(size, *val, busnum, device, function, offset);
1299 
1300         return 0;
1301 
1302 invalid_device:
1303 
1304         switch (size) {
1305         case 4:
1306                 *val = 0xFFFFFFFF;
1307                 break;
1308 
1309         case 2:
1310                 *val = 0xFFFF;
1311                 break;
1312 
1313         case 1:
1314                 *val = 0xFF;
1315                 break;
1316 
1317         default:
1318                 return PCIBIOS_FUNC_NOT_SUPPORTED;
1319         }
1320 
1321         return 0;
1322 }
1323 
1324 
1325 /*
1326  * See tile_cfg_read() for relevant comments.
1327  * Note that "val" is the value to write, not a pointer to that value.
1328  */
1329 static int tile_cfg_write(struct pci_bus *bus, unsigned int devfn, int offset,
1330                           int size, u32 val)
1331 {
1332         struct pci_controller *controller = bus->sysdata;
1333         gxio_trio_context_t *trio_context = controller->trio;
1334         int busnum = bus->number & 0xff;
1335         int device = PCI_SLOT(devfn);
1336         int function = PCI_FUNC(devfn);
1337         int config_type = 1;
1338         TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR_t cfg_addr;
1339         void *mmio_addr;
1340         u32 val_32 = (u32)val;
1341         u16 val_16 = (u16)val;
1342         u8 val_8 = (u8)val;
1343 
1344         /*
1345          * Map all accesses to the local device on root bus into the
1346          * MMIO space of the MAC. Accesses to the downstream devices
1347          * go to the PIO space.
1348          */
1349         if (pci_is_root_bus(bus)) {
1350                 if (device == 0) {
1351                         /*
1352                          * This is the internal downstream P2P bridge,
1353                          * access directly.
1354                          */
1355                         unsigned int reg_offset;
1356 
1357                         reg_offset = ((offset & 0xFFF) <<
1358                                 TRIO_CFG_REGION_ADDR__REG_SHIFT) |
1359                                 (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_PROTECTED
1360                                 << TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
1361                                 (controller->mac <<
1362                                         TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
1363 
1364                         mmio_addr = trio_context->mmio_base_mac + reg_offset;
1365 
1366                         goto valid_device;
1367 
1368                 } else {
1369                         /*
1370                          * We fake an empty device for (device > 0),
1371                          * since there is only one device on bus 0.
1372                          */
1373                         goto invalid_device;
1374                 }
1375         }
1376 
1377         /*
1378          * Accesses to the directly attached device have to be
1379          * sent as type-0 configs.
1380          */
1381         if (busnum == (controller->first_busno + 1)) {
1382                 /*
1383                  * There is only one device off of our built-in P2P bridge.
1384                  */
1385                 if (device != 0)
1386                         goto invalid_device;
1387 
1388                 config_type = 0;
1389         }
1390 
1391         cfg_addr.word = 0;
1392         cfg_addr.reg_addr = (offset & 0xFFF);
1393         cfg_addr.fn = function;
1394         cfg_addr.dev = device;
1395         cfg_addr.bus = busnum;
1396         cfg_addr.type = config_type;
1397 
1398         /*
1399          * Note that we don't set the mac field in cfg_addr because the
1400          * mapping is per port.
1401          */
1402         mmio_addr = trio_context->mmio_base_pio_cfg[controller->mac] +
1403                         cfg_addr.word;
1404 
1405 valid_device:
1406 
1407         switch (size) {
1408         case 4:
1409                 __gxio_mmio_write32(mmio_addr, val_32);
1410                 TRACE_CFG_WR(size, val_32, busnum, device, function, offset);
1411                 break;
1412 
1413         case 2:
1414                 __gxio_mmio_write16(mmio_addr, val_16);
1415                 TRACE_CFG_WR(size, val_16, busnum, device, function, offset);
1416                 break;
1417 
1418         case 1:
1419                 __gxio_mmio_write8(mmio_addr, val_8);
1420                 TRACE_CFG_WR(size, val_8, busnum, device, function, offset);
1421                 break;
1422 
1423         default:
1424                 return PCIBIOS_FUNC_NOT_SUPPORTED;
1425         }
1426 
1427 invalid_device:
1428 
1429         return 0;
1430 }
1431 
1432 
1433 static struct pci_ops tile_cfg_ops = {
1434         .read =         tile_cfg_read,
1435         .write =        tile_cfg_write,
1436 };
1437 
1438 
1439 /* MSI support starts here. */
1440 static unsigned int tilegx_msi_startup(struct irq_data *d)
1441 {
1442         if (irq_data_get_msi_desc(d))
1443                 pci_msi_unmask_irq(d);
1444 
1445         return 0;
1446 }
1447 
1448 static void tilegx_msi_ack(struct irq_data *d)
1449 {
1450         __insn_mtspr(SPR_IPI_EVENT_RESET_K, 1UL << d->irq);
1451 }
1452 
1453 static void tilegx_msi_mask(struct irq_data *d)
1454 {
1455         pci_msi_mask_irq(d);
1456         __insn_mtspr(SPR_IPI_MASK_SET_K, 1UL << d->irq);
1457 }
1458 
1459 static void tilegx_msi_unmask(struct irq_data *d)
1460 {
1461         __insn_mtspr(SPR_IPI_MASK_RESET_K, 1UL << d->irq);
1462         pci_msi_unmask_irq(d);
1463 }
1464 
1465 static struct irq_chip tilegx_msi_chip = {
1466         .name                   = "tilegx_msi",
1467         .irq_startup            = tilegx_msi_startup,
1468         .irq_ack                = tilegx_msi_ack,
1469         .irq_mask               = tilegx_msi_mask,
1470         .irq_unmask             = tilegx_msi_unmask,
1471 
1472         /* TBD: support set_affinity. */
1473 };
1474 
1475 int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
1476 {
1477         struct pci_controller *controller;
1478         gxio_trio_context_t *trio_context;
1479         struct msi_msg msg;
1480         int default_irq;
1481         uint64_t mem_map_base;
1482         uint64_t mem_map_limit;
1483         u64 msi_addr;
1484         int mem_map;
1485         int cpu;
1486         int irq;
1487         int ret;
1488 
1489         irq = irq_alloc_hwirq(-1);
1490         if (!irq)
1491                 return -ENOSPC;
1492 
1493         /*
1494          * Since we use a 64-bit Mem-Map to accept the MSI write, we fail
1495          * devices that are not capable of generating a 64-bit message address.
1496          * These devices will fall back to using the legacy interrupts.
1497          * Most PCIe endpoint devices do support 64-bit message addressing.
1498          */
1499         if (desc->msi_attrib.is_64 == 0) {
1500                 dev_info(&pdev->dev, "64-bit MSI message address not supported, falling back to legacy interrupts\n");
1501 
1502                 ret = -ENOMEM;
1503                 goto is_64_failure;
1504         }
1505 
1506         default_irq = desc->msi_attrib.default_irq;
1507         controller = irq_get_handler_data(default_irq);
1508 
1509         BUG_ON(!controller);
1510 
1511         trio_context = controller->trio;
1512 
1513         /*
1514          * Allocate a scatter-queue that will accept the MSI write and
1515          * trigger the TILE-side interrupts. We use the scatter-queue regions
1516          * before the mem map regions, because the latter are needed by more
1517          * applications.
1518          */
1519         mem_map = gxio_trio_alloc_scatter_queues(trio_context, 1, 0, 0);
1520         if (mem_map >= 0) {
1521                 TRIO_MAP_SQ_DOORBELL_FMT_t doorbell_template = {{
1522                         .pop = 0,
1523                         .doorbell = 1,
1524                 }};
1525 
1526                 mem_map += TRIO_NUM_MAP_MEM_REGIONS;
1527                 mem_map_base = MEM_MAP_INTR_REGIONS_BASE +
1528                         mem_map * MEM_MAP_INTR_REGION_SIZE;
1529                 mem_map_limit = mem_map_base + MEM_MAP_INTR_REGION_SIZE - 1;
1530 
1531                 msi_addr = mem_map_base + MEM_MAP_INTR_REGION_SIZE - 8;
1532                 msg.data = (unsigned int)doorbell_template.word;
1533         } else {
1534                 /* SQ regions are out, allocate from map mem regions. */
1535                 mem_map = gxio_trio_alloc_memory_maps(trio_context, 1, 0, 0);
1536                 if (mem_map < 0) {
1537                         dev_info(&pdev->dev, "%s Mem-Map alloc failure - failed to initialize MSI interrupts - falling back to legacy interrupts\n",
1538                                  desc->msi_attrib.is_msix ? "MSI-X" : "MSI");
1539                         ret = -ENOMEM;
1540                         goto msi_mem_map_alloc_failure;
1541                 }
1542 
1543                 mem_map_base = MEM_MAP_INTR_REGIONS_BASE +
1544                         mem_map * MEM_MAP_INTR_REGION_SIZE;
1545                 mem_map_limit = mem_map_base + MEM_MAP_INTR_REGION_SIZE - 1;
1546 
1547                 msi_addr = mem_map_base + TRIO_MAP_MEM_REG_INT3 -
1548                         TRIO_MAP_MEM_REG_INT0;
1549 
1550                 msg.data = mem_map;
1551         }
1552 
1553         /* We try to distribute different IRQs to different tiles. */
1554         cpu = tile_irq_cpu(irq);
1555 
1556         /*
1557          * Now call up to the HV to configure the MSI interrupt and
1558          * set up the IPI binding.
1559          */
1560         ret = gxio_trio_config_msi_intr(trio_context, cpu_x(cpu), cpu_y(cpu),
1561                                         KERNEL_PL, irq, controller->mac,
1562                                         mem_map, mem_map_base, mem_map_limit,
1563                                         trio_context->asid);
1564         if (ret < 0) {
1565                 dev_info(&pdev->dev, "HV MSI config failed\n");
1566 
1567                 goto hv_msi_config_failure;
1568         }
1569 
1570         irq_set_msi_desc(irq, desc);
1571 
1572         msg.address_hi = msi_addr >> 32;
1573         msg.address_lo = msi_addr & 0xffffffff;
1574 
1575         pci_write_msi_msg(irq, &msg);
1576         irq_set_chip_and_handler(irq, &tilegx_msi_chip, handle_level_irq);
1577         irq_set_handler_data(irq, controller);
1578 
1579         return 0;
1580 
1581 hv_msi_config_failure:
1582         /* Free mem-map */
1583 msi_mem_map_alloc_failure:
1584 is_64_failure:
1585         irq_free_hwirq(irq);
1586         return ret;
1587 }
1588 
1589 void arch_teardown_msi_irq(unsigned int irq)
1590 {
1591         irq_free_hwirq(irq);
1592 }
1593 

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