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TOMOYO Linux Cross Reference
Linux/arch/tile/kernel/pci_gx.c

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  1 /*
  2  * Copyright 2012 Tilera Corporation. All Rights Reserved.
  3  *
  4  *   This program is free software; you can redistribute it and/or
  5  *   modify it under the terms of the GNU General Public License
  6  *   as published by the Free Software Foundation, version 2.
  7  *
  8  *   This program is distributed in the hope that it will be useful, but
  9  *   WITHOUT ANY WARRANTY; without even the implied warranty of
 10  *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
 11  *   NON INFRINGEMENT.  See the GNU General Public License for
 12  *   more details.
 13  */
 14 
 15 #include <linux/kernel.h>
 16 #include <linux/mmzone.h>
 17 #include <linux/pci.h>
 18 #include <linux/delay.h>
 19 #include <linux/string.h>
 20 #include <linux/init.h>
 21 #include <linux/capability.h>
 22 #include <linux/sched.h>
 23 #include <linux/errno.h>
 24 #include <linux/irq.h>
 25 #include <linux/msi.h>
 26 #include <linux/io.h>
 27 #include <linux/uaccess.h>
 28 #include <linux/ctype.h>
 29 
 30 #include <asm/processor.h>
 31 #include <asm/sections.h>
 32 #include <asm/byteorder.h>
 33 
 34 #include <gxio/iorpc_globals.h>
 35 #include <gxio/kiorpc.h>
 36 #include <gxio/trio.h>
 37 #include <gxio/iorpc_trio.h>
 38 #include <hv/drv_trio_intf.h>
 39 
 40 #include <arch/sim.h>
 41 
 42 /*
 43  * This file containes the routines to search for PCI buses,
 44  * enumerate the buses, and configure any attached devices.
 45  */
 46 
 47 #define DEBUG_PCI_CFG   0
 48 
 49 #if DEBUG_PCI_CFG
 50 #define TRACE_CFG_WR(size, val, bus, dev, func, offset) \
 51         pr_info("CFG WR %d-byte VAL %#x to bus %d dev %d func %d addr %u\n", \
 52                 size, val, bus, dev, func, offset & 0xFFF);
 53 #define TRACE_CFG_RD(size, val, bus, dev, func, offset) \
 54         pr_info("CFG RD %d-byte VAL %#x from bus %d dev %d func %d addr %u\n", \
 55                 size, val, bus, dev, func, offset & 0xFFF);
 56 #else
 57 #define TRACE_CFG_WR(...)
 58 #define TRACE_CFG_RD(...)
 59 #endif
 60 
 61 static int pci_probe = 1;
 62 
 63 /* Information on the PCIe RC ports configuration. */
 64 static int pcie_rc[TILEGX_NUM_TRIO][TILEGX_TRIO_PCIES];
 65 
 66 /*
 67  * On some platforms with one or more Gx endpoint ports, we need to
 68  * delay the PCIe RC port probe for a few seconds to work around
 69  * a HW PCIe link-training bug. The exact delay is specified with
 70  * a kernel boot argument in the form of "pcie_rc_delay=T,P,S",
 71  * where T is the TRIO instance number, P is the port number and S is
 72  * the delay in seconds. If the delay is not provided, the value
 73  * will be DEFAULT_RC_DELAY.
 74  */
 75 static int rc_delay[TILEGX_NUM_TRIO][TILEGX_TRIO_PCIES];
 76 
 77 /* Default number of seconds that the PCIe RC port probe can be delayed. */
 78 #define DEFAULT_RC_DELAY        10
 79 
 80 /* Max number of seconds that the PCIe RC port probe can be delayed. */
 81 #define MAX_RC_DELAY            20
 82 
 83 /* Array of the PCIe ports configuration info obtained from the BIB. */
 84 struct pcie_port_property pcie_ports[TILEGX_NUM_TRIO][TILEGX_TRIO_PCIES];
 85 
 86 /* All drivers share the TRIO contexts defined here. */
 87 gxio_trio_context_t trio_contexts[TILEGX_NUM_TRIO];
 88 
 89 /* Pointer to an array of PCIe RC controllers. */
 90 struct pci_controller pci_controllers[TILEGX_NUM_TRIO * TILEGX_TRIO_PCIES];
 91 int num_rc_controllers;
 92 static int num_ep_controllers;
 93 
 94 static struct pci_ops tile_cfg_ops;
 95 
 96 /* Mask of CPUs that should receive PCIe interrupts. */
 97 static struct cpumask intr_cpus_map;
 98 
 99 /*
100  * We don't need to worry about the alignment of resources.
101  */
102 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
103                                 resource_size_t size, resource_size_t align)
104 {
105         return res->start;
106 }
107 EXPORT_SYMBOL(pcibios_align_resource);
108 
109 
110 /*
111  * Pick a CPU to receive and handle the PCIe interrupts, based on the IRQ #.
112  * For now, we simply send interrupts to non-dataplane CPUs.
113  * We may implement methods to allow user to specify the target CPUs,
114  * e.g. via boot arguments.
115  */
116 static int tile_irq_cpu(int irq)
117 {
118         unsigned int count;
119         int i = 0;
120         int cpu;
121 
122         count = cpumask_weight(&intr_cpus_map);
123         if (unlikely(count == 0)) {
124                 pr_warning("intr_cpus_map empty, interrupts will be"
125                            " delievered to dataplane tiles\n");
126                 return irq % (smp_height * smp_width);
127         }
128 
129         count = irq % count;
130         for_each_cpu(cpu, &intr_cpus_map) {
131                 if (i++ == count)
132                         break;
133         }
134         return cpu;
135 }
136 
137 /*
138  * Open a file descriptor to the TRIO shim.
139  */
140 static int tile_pcie_open(int trio_index)
141 {
142         gxio_trio_context_t *context = &trio_contexts[trio_index];
143         int ret;
144 
145         /*
146          * This opens a file descriptor to the TRIO shim.
147          */
148         ret = gxio_trio_init(context, trio_index);
149         if (ret < 0)
150                 return ret;
151 
152         /*
153          * Allocate an ASID for the kernel.
154          */
155         ret = gxio_trio_alloc_asids(context, 1, 0, 0);
156         if (ret < 0) {
157                 pr_err("PCI: ASID alloc failure on TRIO %d, give up\n",
158                         trio_index);
159                 goto asid_alloc_failure;
160         }
161 
162         context->asid = ret;
163 
164 #ifdef USE_SHARED_PCIE_CONFIG_REGION
165         /*
166          * Alloc a PIO region for config access, shared by all MACs per TRIO.
167          * This shouldn't fail since the kernel is supposed to the first
168          * client of the TRIO's PIO regions.
169          */
170         ret = gxio_trio_alloc_pio_regions(context, 1, 0, 0);
171         if (ret < 0) {
172                 pr_err("PCI: CFG PIO alloc failure on TRIO %d, give up\n",
173                         trio_index);
174                 goto pio_alloc_failure;
175         }
176 
177         context->pio_cfg_index = ret;
178 
179         /*
180          * For PIO CFG, the bus_address_hi parameter is 0. The mac parameter
181          * is also 0 because it is specified in PIO_REGION_SETUP_CFG_ADDR.
182          */
183         ret = gxio_trio_init_pio_region_aux(context, context->pio_cfg_index,
184                 0, 0, HV_TRIO_PIO_FLAG_CONFIG_SPACE);
185         if (ret < 0) {
186                 pr_err("PCI: CFG PIO init failure on TRIO %d, give up\n",
187                         trio_index);
188                 goto pio_alloc_failure;
189         }
190 #endif
191 
192         return ret;
193 
194 asid_alloc_failure:
195 #ifdef USE_SHARED_PCIE_CONFIG_REGION
196 pio_alloc_failure:
197 #endif
198         hv_dev_close(context->fd);
199 
200         return ret;
201 }
202 
203 static void
204 tilegx_legacy_irq_ack(struct irq_data *d)
205 {
206         __insn_mtspr(SPR_IPI_EVENT_RESET_K, 1UL << d->irq);
207 }
208 
209 static void
210 tilegx_legacy_irq_mask(struct irq_data *d)
211 {
212         __insn_mtspr(SPR_IPI_MASK_SET_K, 1UL << d->irq);
213 }
214 
215 static void
216 tilegx_legacy_irq_unmask(struct irq_data *d)
217 {
218         __insn_mtspr(SPR_IPI_MASK_RESET_K, 1UL << d->irq);
219 }
220 
221 static struct irq_chip tilegx_legacy_irq_chip = {
222         .name                   = "tilegx_legacy_irq",
223         .irq_ack                = tilegx_legacy_irq_ack,
224         .irq_mask               = tilegx_legacy_irq_mask,
225         .irq_unmask             = tilegx_legacy_irq_unmask,
226 
227         /* TBD: support set_affinity. */
228 };
229 
230 /*
231  * This is a wrapper function of the kernel level-trigger interrupt
232  * handler handle_level_irq() for PCI legacy interrupts. The TRIO
233  * is configured such that only INTx Assert interrupts are proxied
234  * to Linux which just calls handle_level_irq() after clearing the
235  * MAC INTx Assert status bit associated with this interrupt.
236  */
237 static void
238 trio_handle_level_irq(unsigned int irq, struct irq_desc *desc)
239 {
240         struct pci_controller *controller = irq_desc_get_handler_data(desc);
241         gxio_trio_context_t *trio_context = controller->trio;
242         uint64_t intx = (uint64_t)irq_desc_get_chip_data(desc);
243         int mac = controller->mac;
244         unsigned int reg_offset;
245         uint64_t level_mask;
246 
247         handle_level_irq(irq, desc);
248 
249         /*
250          * Clear the INTx Level status, otherwise future interrupts are
251          * not sent.
252          */
253         reg_offset = (TRIO_PCIE_INTFC_MAC_INT_STS <<
254                 TRIO_CFG_REGION_ADDR__REG_SHIFT) |
255                 (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_INTERFACE <<
256                 TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
257                 (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
258 
259         level_mask = TRIO_PCIE_INTFC_MAC_INT_STS__INT_LEVEL_MASK << intx;
260 
261         __gxio_mmio_write(trio_context->mmio_base_mac + reg_offset, level_mask);
262 }
263 
264 /*
265  * Create kernel irqs and set up the handlers for the legacy interrupts.
266  * Also some minimum initialization for the MSI support.
267  */
268 static int tile_init_irqs(struct pci_controller *controller)
269 {
270         int i;
271         int j;
272         int irq;
273         int result;
274 
275         cpumask_copy(&intr_cpus_map, cpu_online_mask);
276 
277 
278         for (i = 0; i < 4; i++) {
279                 gxio_trio_context_t *context = controller->trio;
280                 int cpu;
281 
282                 /* Ask the kernel to allocate an IRQ. */
283                 irq = create_irq();
284                 if (irq < 0) {
285                         pr_err("PCI: no free irq vectors, failed for %d\n", i);
286 
287                         goto free_irqs;
288                 }
289                 controller->irq_intx_table[i] = irq;
290 
291                 /* Distribute the 4 IRQs to different tiles. */
292                 cpu = tile_irq_cpu(irq);
293 
294                 /* Configure the TRIO intr binding for this IRQ. */
295                 result = gxio_trio_config_legacy_intr(context, cpu_x(cpu),
296                                                       cpu_y(cpu), KERNEL_PL,
297                                                       irq, controller->mac, i);
298                 if (result < 0) {
299                         pr_err("PCI: MAC intx config failed for %d\n", i);
300 
301                         goto free_irqs;
302                 }
303 
304                 /*
305                  * Register the IRQ handler with the kernel.
306                  */
307                 irq_set_chip_and_handler(irq, &tilegx_legacy_irq_chip,
308                                         trio_handle_level_irq);
309                 irq_set_chip_data(irq, (void *)(uint64_t)i);
310                 irq_set_handler_data(irq, controller);
311         }
312 
313         return 0;
314 
315 free_irqs:
316         for (j = 0; j < i; j++)
317                 destroy_irq(controller->irq_intx_table[j]);
318 
319         return -1;
320 }
321 
322 /*
323  * Find valid controllers and fill in pci_controller structs for each
324  * of them.
325  *
326  * Returns the number of controllers discovered.
327  */
328 int __init tile_pci_init(void)
329 {
330         int num_trio_shims = 0;
331         int ctl_index = 0;
332         int i, j;
333 
334         if (!pci_probe) {
335                 pr_info("PCI: disabled by boot argument\n");
336                 return 0;
337         }
338 
339         pr_info("PCI: Searching for controllers...\n");
340 
341         /*
342          * We loop over all the TRIO shims.
343          */
344         for (i = 0; i < TILEGX_NUM_TRIO; i++) {
345                 int ret;
346 
347                 ret = tile_pcie_open(i);
348                 if (ret < 0)
349                         continue;
350 
351                 num_trio_shims++;
352         }
353 
354         if (num_trio_shims == 0 || sim_is_simulator())
355                 return 0;
356 
357         /*
358          * Now determine which PCIe ports are configured to operate in RC mode.
359          * We look at the Board Information Block first and then see if there
360          * are any overriding configuration by the HW strapping pin.
361          */
362         for (i = 0; i < TILEGX_NUM_TRIO; i++) {
363                 gxio_trio_context_t *context = &trio_contexts[i];
364                 int ret;
365 
366                 if (context->fd < 0)
367                         continue;
368 
369                 ret = hv_dev_pread(context->fd, 0,
370                         (HV_VirtAddr)&pcie_ports[i][0],
371                         sizeof(struct pcie_port_property) * TILEGX_TRIO_PCIES,
372                         GXIO_TRIO_OP_GET_PORT_PROPERTY);
373                 if (ret < 0) {
374                         pr_err("PCI: PCIE_GET_PORT_PROPERTY failure, error %d,"
375                                 " on TRIO %d\n", ret, i);
376                         continue;
377                 }
378 
379                 for (j = 0; j < TILEGX_TRIO_PCIES; j++) {
380                         if (pcie_ports[i][j].allow_rc) {
381                                 pcie_rc[i][j] = 1;
382                                 num_rc_controllers++;
383                         }
384                         else if (pcie_ports[i][j].allow_ep) {
385                                 num_ep_controllers++;
386                         }
387                 }
388         }
389 
390         /*
391          * Return if no PCIe ports are configured to operate in RC mode.
392          */
393         if (num_rc_controllers == 0)
394                 return 0;
395 
396         /*
397          * Set the TRIO pointer and MAC index for each PCIe RC port.
398          */
399         for (i = 0; i < TILEGX_NUM_TRIO; i++) {
400                 for (j = 0; j < TILEGX_TRIO_PCIES; j++) {
401                         if (pcie_rc[i][j]) {
402                                 pci_controllers[ctl_index].trio =
403                                         &trio_contexts[i];
404                                 pci_controllers[ctl_index].mac = j;
405                                 pci_controllers[ctl_index].trio_index = i;
406                                 ctl_index++;
407                                 if (ctl_index == num_rc_controllers)
408                                         goto out;
409                         }
410                 }
411         }
412 
413 out:
414         /*
415          * Configure each PCIe RC port.
416          */
417         for (i = 0; i < num_rc_controllers; i++) {
418                 /*
419                  * Configure the PCIe MAC to run in RC mode.
420                  */
421 
422                 struct pci_controller *controller = &pci_controllers[i];
423 
424                 controller->index = i;
425                 controller->ops = &tile_cfg_ops;
426 
427                 /*
428                  * The PCI memory resource is located above the PA space.
429                  * For every host bridge, the BAR window or the MMIO aperture
430                  * is in range [3GB, 4GB - 1] of a 4GB space beyond the
431                  * PA space.
432                  */
433 
434                 controller->mem_offset = TILE_PCI_MEM_START +
435                         (i * TILE_PCI_BAR_WINDOW_TOP);
436                 controller->mem_space.start = controller->mem_offset +
437                         TILE_PCI_BAR_WINDOW_TOP - TILE_PCI_BAR_WINDOW_SIZE;
438                 controller->mem_space.end = controller->mem_offset +
439                         TILE_PCI_BAR_WINDOW_TOP - 1;
440                 controller->mem_space.flags = IORESOURCE_MEM;
441                 snprintf(controller->mem_space_name,
442                          sizeof(controller->mem_space_name),
443                          "PCI mem domain %d", i);
444                 controller->mem_space.name = controller->mem_space_name;
445         }
446 
447         return num_rc_controllers;
448 }
449 
450 /*
451  * (pin - 1) converts from the PCI standard's [1:4] convention to
452  * a normal [0:3] range.
453  */
454 static int tile_map_irq(const struct pci_dev *dev, u8 device, u8 pin)
455 {
456         struct pci_controller *controller =
457                 (struct pci_controller *)dev->sysdata;
458         return controller->irq_intx_table[pin - 1];
459 }
460 
461 
462 static void fixup_read_and_payload_sizes(struct pci_controller *controller)
463 {
464         gxio_trio_context_t *trio_context = controller->trio;
465         struct pci_bus *root_bus = controller->root_bus;
466         TRIO_PCIE_RC_DEVICE_CONTROL_t dev_control;
467         TRIO_PCIE_RC_DEVICE_CAP_t rc_dev_cap;
468         unsigned int reg_offset;
469         struct pci_bus *child;
470         int mac;
471         int err;
472 
473         mac = controller->mac;
474 
475         /*
476          * Set our max read request size to be 4KB.
477          */
478         reg_offset =
479                 (TRIO_PCIE_RC_DEVICE_CONTROL <<
480                         TRIO_CFG_REGION_ADDR__REG_SHIFT) |
481                 (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_STANDARD <<
482                         TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
483                 (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
484 
485         dev_control.word = __gxio_mmio_read32(trio_context->mmio_base_mac +
486                                                 reg_offset);
487         dev_control.max_read_req_sz = 5;
488         __gxio_mmio_write32(trio_context->mmio_base_mac + reg_offset,
489                                                 dev_control.word);
490 
491         /*
492          * Set the max payload size supported by this Gx PCIe MAC.
493          * Though Gx PCIe supports Max Payload Size of up to 1024 bytes,
494          * experiments have shown that setting MPS to 256 yields the
495          * best performance.
496          */
497         reg_offset =
498                 (TRIO_PCIE_RC_DEVICE_CAP <<
499                         TRIO_CFG_REGION_ADDR__REG_SHIFT) |
500                 (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_STANDARD <<
501                         TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
502                 (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
503 
504         rc_dev_cap.word = __gxio_mmio_read32(trio_context->mmio_base_mac +
505                                                 reg_offset);
506         rc_dev_cap.mps_sup = 1;
507         __gxio_mmio_write32(trio_context->mmio_base_mac + reg_offset,
508                                                 rc_dev_cap.word);
509 
510         /* Configure PCI Express MPS setting. */
511         list_for_each_entry(child, &root_bus->children, node) {
512                 struct pci_dev *self = child->self;
513                 if (!self)
514                         continue;
515 
516                 pcie_bus_configure_settings(child, self->pcie_mpss);
517         }
518 
519         /*
520          * Set the mac_config register in trio based on the MPS/MRS of the link.
521          */
522         reg_offset =
523                 (TRIO_PCIE_RC_DEVICE_CONTROL <<
524                         TRIO_CFG_REGION_ADDR__REG_SHIFT) |
525                 (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_STANDARD <<
526                         TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
527                 (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
528 
529         dev_control.word = __gxio_mmio_read32(trio_context->mmio_base_mac +
530                                                 reg_offset);
531 
532         err = gxio_trio_set_mps_mrs(trio_context,
533                                     dev_control.max_payload_size,
534                                     dev_control.max_read_req_sz,
535                                     mac);
536         if (err < 0) {
537                 pr_err("PCI: PCIE_CONFIGURE_MAC_MPS_MRS failure, "
538                         "MAC %d on TRIO %d\n",
539                         mac, controller->trio_index);
540         }
541 }
542 
543 static int setup_pcie_rc_delay(char *str)
544 {
545         unsigned long delay = 0;
546         unsigned long trio_index;
547         unsigned long mac;
548 
549         if (str == NULL || !isdigit(*str))
550                 return -EINVAL;
551         trio_index = simple_strtoul(str, (char **)&str, 10);
552         if (trio_index >= TILEGX_NUM_TRIO)
553                 return -EINVAL;
554 
555         if (*str != ',')
556                 return -EINVAL;
557 
558         str++;
559         if (!isdigit(*str))
560                 return -EINVAL;
561         mac = simple_strtoul(str, (char **)&str, 10);
562         if (mac >= TILEGX_TRIO_PCIES)
563                 return -EINVAL;
564 
565         if (*str != '\0') {
566                 if (*str != ',')
567                         return -EINVAL;
568 
569                 str++;
570                 if (!isdigit(*str))
571                         return -EINVAL;
572                 delay = simple_strtoul(str, (char **)&str, 10);
573                 if (delay > MAX_RC_DELAY)
574                         return -EINVAL;
575         }
576 
577         rc_delay[trio_index][mac] = delay ? : DEFAULT_RC_DELAY;
578         pr_info("Delaying PCIe RC link training for %u sec"
579                 " on MAC %lu on TRIO %lu\n", rc_delay[trio_index][mac],
580                 mac, trio_index);
581         return 0;
582 }
583 early_param("pcie_rc_delay", setup_pcie_rc_delay);
584 
585 /*
586  * PCI initialization entry point, called by subsys_initcall.
587  */
588 int __init pcibios_init(void)
589 {
590         resource_size_t offset;
591         LIST_HEAD(resources);
592         int next_busno;
593         int i;
594 
595         tile_pci_init();
596 
597         if (num_rc_controllers == 0 && num_ep_controllers == 0)
598                 return 0;
599 
600         /*
601          * We loop over all the TRIO shims and set up the MMIO mappings.
602          */
603         for (i = 0; i < TILEGX_NUM_TRIO; i++) {
604                 gxio_trio_context_t *context = &trio_contexts[i];
605 
606                 if (context->fd < 0)
607                         continue;
608 
609                 /*
610                  * Map in the MMIO space for the MAC.
611                  */
612                 offset = 0;
613                 context->mmio_base_mac =
614                         iorpc_ioremap(context->fd, offset,
615                                       HV_TRIO_CONFIG_IOREMAP_SIZE);
616                 if (context->mmio_base_mac == NULL) {
617                         pr_err("PCI: MAC map failure on TRIO %d\n", i);
618 
619                         hv_dev_close(context->fd);
620                         context->fd = -1;
621                         continue;
622                 }
623         }
624 
625         /*
626          * Delay a bit in case devices aren't ready.  Some devices are
627          * known to require at least 20ms here, but we use a more
628          * conservative value.
629          */
630         msleep(250);
631 
632         /* Scan all of the recorded PCI controllers.  */
633         for (next_busno = 0, i = 0; i < num_rc_controllers; i++) {
634                 struct pci_controller *controller = &pci_controllers[i];
635                 gxio_trio_context_t *trio_context = controller->trio;
636                 TRIO_PCIE_INTFC_PORT_CONFIG_t port_config;
637                 TRIO_PCIE_INTFC_PORT_STATUS_t port_status;
638                 TRIO_PCIE_INTFC_TX_FIFO_CTL_t tx_fifo_ctl;
639                 struct pci_bus *bus;
640                 unsigned int reg_offset;
641                 unsigned int class_code_revision;
642                 int trio_index;
643                 int mac;
644                 int ret;
645 
646                 if (trio_context->fd < 0)
647                         continue;
648 
649                 trio_index = controller->trio_index;
650                 mac = controller->mac;
651 
652                 /*
653                  * Check the port strap state which will override the BIB
654                  * setting.
655                  */
656 
657                 reg_offset =
658                         (TRIO_PCIE_INTFC_PORT_CONFIG <<
659                                 TRIO_CFG_REGION_ADDR__REG_SHIFT) |
660                         (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_INTERFACE <<
661                                 TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
662                         (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
663 
664                 port_config.word =
665                         __gxio_mmio_read(trio_context->mmio_base_mac +
666                                          reg_offset);
667 
668                 if ((port_config.strap_state !=
669                         TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_RC) &&
670                         (port_config.strap_state !=
671                         TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_RC_G1)) {
672                         /*
673                          * If this is really intended to be an EP port,
674                          * record it so that the endpoint driver will know about it.
675                          */
676                         if (port_config.strap_state ==
677                         TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_ENDPOINT ||
678                         port_config.strap_state ==
679                         TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_ENDPOINT_G1)
680                                 pcie_ports[trio_index][mac].allow_ep = 1;
681 
682                         continue;
683                 }
684 
685                 /*
686                  * Delay the RC link training if needed.
687                  */
688                 if (rc_delay[trio_index][mac])
689                         msleep(rc_delay[trio_index][mac] * 1000);
690 
691                 ret = gxio_trio_force_rc_link_up(trio_context, mac);
692                 if (ret < 0)
693                         pr_err("PCI: PCIE_FORCE_LINK_UP failure, "
694                                 "MAC %d on TRIO %d\n", mac, trio_index);
695 
696                 pr_info("PCI: Found PCI controller #%d on TRIO %d MAC %d\n", i,
697                         trio_index, controller->mac);
698 
699                 /*
700                  * Wait a bit here because some EP devices take longer
701                  * to come up.
702                  */
703                 msleep(1000);
704 
705                 /*
706                  * Check for PCIe link-up status.
707                  */
708 
709                 reg_offset =
710                         (TRIO_PCIE_INTFC_PORT_STATUS <<
711                                 TRIO_CFG_REGION_ADDR__REG_SHIFT) |
712                         (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_INTERFACE <<
713                                 TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
714                         (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
715 
716                 port_status.word =
717                         __gxio_mmio_read(trio_context->mmio_base_mac +
718                                          reg_offset);
719                 if (!port_status.dl_up) {
720                         pr_err("PCI: link is down, MAC %d on TRIO %d\n",
721                                 mac, trio_index);
722                         continue;
723                 }
724 
725                 /*
726                  * Ensure that the link can come out of L1 power down state.
727                  * Strictly speaking, this is needed only in the case of
728                  * heavy RC-initiated DMAs.
729                  */
730                 reg_offset =
731                         (TRIO_PCIE_INTFC_TX_FIFO_CTL <<
732                                 TRIO_CFG_REGION_ADDR__REG_SHIFT) |
733                         (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_INTERFACE <<
734                                 TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
735                         (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
736                 tx_fifo_ctl.word =
737                         __gxio_mmio_read(trio_context->mmio_base_mac +
738                                          reg_offset);
739                 tx_fifo_ctl.min_p_credits = 0;
740                 __gxio_mmio_write(trio_context->mmio_base_mac + reg_offset,
741                                   tx_fifo_ctl.word);
742 
743                 /*
744                  * Change the device ID so that Linux bus crawl doesn't confuse
745                  * the internal bridge with any Tilera endpoints.
746                  */
747 
748                 reg_offset =
749                         (TRIO_PCIE_RC_DEVICE_ID_VEN_ID <<
750                                 TRIO_CFG_REGION_ADDR__REG_SHIFT) |
751                         (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_STANDARD <<
752                                 TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
753                         (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
754 
755                 __gxio_mmio_write32(trio_context->mmio_base_mac + reg_offset,
756                                     (TILERA_GX36_RC_DEV_ID <<
757                                     TRIO_PCIE_RC_DEVICE_ID_VEN_ID__DEV_ID_SHIFT) |
758                                     TILERA_VENDOR_ID);
759 
760                 /*
761                  * Set the internal P2P bridge class code.
762                  */
763 
764                 reg_offset =
765                         (TRIO_PCIE_RC_REVISION_ID <<
766                                 TRIO_CFG_REGION_ADDR__REG_SHIFT) |
767                         (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_STANDARD <<
768                                 TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
769                         (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
770 
771                 class_code_revision =
772                         __gxio_mmio_read32(trio_context->mmio_base_mac +
773                                            reg_offset);
774                 class_code_revision = (class_code_revision & 0xff ) |
775                                         (PCI_CLASS_BRIDGE_PCI << 16);
776 
777                 __gxio_mmio_write32(trio_context->mmio_base_mac +
778                                     reg_offset, class_code_revision);
779 
780 #ifdef USE_SHARED_PCIE_CONFIG_REGION
781 
782                 /*
783                  * Map in the MMIO space for the PIO region.
784                  */
785                 offset = HV_TRIO_PIO_OFFSET(trio_context->pio_cfg_index) |
786                         (((unsigned long long)mac) <<
787                         TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR__MAC_SHIFT);
788 
789 #else
790 
791                 /*
792                  * Alloc a PIO region for PCI config access per MAC.
793                  */
794                 ret = gxio_trio_alloc_pio_regions(trio_context, 1, 0, 0);
795                 if (ret < 0) {
796                         pr_err("PCI: PCI CFG PIO alloc failure for mac %d "
797                                 "on TRIO %d, give up\n", mac, trio_index);
798 
799                         continue;
800                 }
801 
802                 trio_context->pio_cfg_index[mac] = ret;
803 
804                 /*
805                  * For PIO CFG, the bus_address_hi parameter is 0.
806                  */
807                 ret = gxio_trio_init_pio_region_aux(trio_context,
808                         trio_context->pio_cfg_index[mac],
809                         mac, 0, HV_TRIO_PIO_FLAG_CONFIG_SPACE);
810                 if (ret < 0) {
811                         pr_err("PCI: PCI CFG PIO init failure for mac %d "
812                                 "on TRIO %d, give up\n", mac, trio_index);
813 
814                         continue;
815                 }
816 
817                 offset = HV_TRIO_PIO_OFFSET(trio_context->pio_cfg_index[mac]) |
818                         (((unsigned long long)mac) <<
819                         TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR__MAC_SHIFT);
820 
821 #endif
822 
823                 trio_context->mmio_base_pio_cfg[mac] =
824                         iorpc_ioremap(trio_context->fd, offset,
825                         (1 << TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR__MAC_SHIFT));
826                 if (trio_context->mmio_base_pio_cfg[mac] == NULL) {
827                         pr_err("PCI: PIO map failure for mac %d on TRIO %d\n",
828                                 mac, trio_index);
829 
830                         continue;
831                 }
832 
833                 /*
834                  * Initialize the PCIe interrupts.
835                  */
836                 if (tile_init_irqs(controller)) {
837                         pr_err("PCI: IRQs init failure for mac %d on TRIO %d\n",
838                                 mac, trio_index);
839 
840                         continue;
841                 }
842 
843                 /*
844                  * The PCI memory resource is located above the PA space.
845                  * The memory range for the PCI root bus should not overlap
846                  * with the physical RAM
847                  */
848                 pci_add_resource_offset(&resources, &controller->mem_space,
849                                         controller->mem_offset);
850 
851                 controller->first_busno = next_busno;
852                 bus = pci_scan_root_bus(NULL, next_busno, controller->ops,
853                                         controller, &resources);
854                 controller->root_bus = bus;
855                 next_busno = bus->busn_res.end + 1;
856 
857         }
858 
859         /* Do machine dependent PCI interrupt routing */
860         pci_fixup_irqs(pci_common_swizzle, tile_map_irq);
861 
862         /*
863          * This comes from the generic Linux PCI driver.
864          *
865          * It allocates all of the resources (I/O memory, etc)
866          * associated with the devices read in above.
867          */
868 
869         pci_assign_unassigned_resources();
870 
871         /* Record the I/O resources in the PCI controller structure. */
872         for (i = 0; i < num_rc_controllers; i++) {
873                 struct pci_controller *controller = &pci_controllers[i];
874                 gxio_trio_context_t *trio_context = controller->trio;
875                 struct pci_bus *root_bus = pci_controllers[i].root_bus;
876                 struct pci_bus *next_bus;
877                 uint32_t bus_address_hi;
878                 struct pci_dev *dev;
879                 int ret;
880                 int j;
881 
882                 /*
883                  * Skip controllers that are not properly initialized or
884                  * have down links.
885                  */
886                 if (root_bus == NULL)
887                         continue;
888 
889                 /* Configure the max_payload_size values for this domain. */
890                 fixup_read_and_payload_sizes(controller);
891 
892                 list_for_each_entry(dev, &root_bus->devices, bus_list) {
893                         /* Find the PCI host controller, ie. the 1st bridge. */
894                         if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI &&
895                                 (PCI_SLOT(dev->devfn) == 0)) {
896                                 next_bus = dev->subordinate;
897                                 pci_controllers[i].mem_resources[0] =
898                                         *next_bus->resource[0];
899                                 pci_controllers[i].mem_resources[1] =
900                                          *next_bus->resource[1];
901                                 pci_controllers[i].mem_resources[2] =
902                                          *next_bus->resource[2];
903 
904                                 break;
905                         }
906                 }
907 
908                 if (pci_controllers[i].mem_resources[1].flags & IORESOURCE_MEM)
909                         bus_address_hi =
910                                 pci_controllers[i].mem_resources[1].start >> 32;
911                 else if (pci_controllers[i].mem_resources[2].flags & IORESOURCE_PREFETCH)
912                         bus_address_hi =
913                                 pci_controllers[i].mem_resources[2].start >> 32;
914                 else {
915                         /* This is unlikely. */
916                         pr_err("PCI: no memory resources on TRIO %d mac %d\n",
917                                 controller->trio_index, controller->mac);
918                         continue;
919                 }
920 
921                 /*
922                  * Alloc a PIO region for PCI memory access for each RC port.
923                  */
924                 ret = gxio_trio_alloc_pio_regions(trio_context, 1, 0, 0);
925                 if (ret < 0) {
926                         pr_err("PCI: MEM PIO alloc failure on TRIO %d mac %d, "
927                                 "give up\n", controller->trio_index,
928                                 controller->mac);
929 
930                         continue;
931                 }
932 
933                 controller->pio_mem_index = ret;
934 
935                 /*
936                  * For PIO MEM, the bus_address_hi parameter is hard-coded 0
937                  * because we always assign 32-bit PCI bus BAR ranges.
938                  */
939                 ret = gxio_trio_init_pio_region_aux(trio_context,
940                                                     controller->pio_mem_index,
941                                                     controller->mac,
942                                                     0,
943                                                     0);
944                 if (ret < 0) {
945                         pr_err("PCI: MEM PIO init failure on TRIO %d mac %d, "
946                                 "give up\n", controller->trio_index,
947                                 controller->mac);
948 
949                         continue;
950                 }
951 
952                 /*
953                  * Configure a Mem-Map region for each memory controller so
954                  * that Linux can map all of its PA space to the PCI bus.
955                  * Use the IOMMU to handle hash-for-home memory.
956                  */
957                 for_each_online_node(j) {
958                         unsigned long start_pfn = node_start_pfn[j];
959                         unsigned long end_pfn = node_end_pfn[j];
960                         unsigned long nr_pages = end_pfn - start_pfn;
961 
962                         ret = gxio_trio_alloc_memory_maps(trio_context, 1, 0,
963                                                           0);
964                         if (ret < 0) {
965                                 pr_err("PCI: Mem-Map alloc failure on TRIO %d "
966                                         "mac %d for MC %d, give up\n",
967                                         controller->trio_index,
968                                         controller->mac, j);
969 
970                                 goto alloc_mem_map_failed;
971                         }
972 
973                         controller->mem_maps[j] = ret;
974 
975                         /*
976                          * Initialize the Mem-Map and the I/O MMU so that all
977                          * the physical memory can be accessed by the endpoint
978                          * devices. The base bus address is set to the base CPA
979                          * of this memory controller plus an offset (see pci.h).
980                          * The region's base VA is set to the base CPA. The
981                          * I/O MMU table essentially translates the CPA to
982                          * the real PA. Implicitly, for node 0, we create
983                          * a separate Mem-Map region that serves as the inbound
984                          * window for legacy 32-bit devices. This is a direct
985                          * map of the low 4GB CPA space.
986                          */
987                         ret = gxio_trio_init_memory_map_mmu_aux(trio_context,
988                                 controller->mem_maps[j],
989                                 start_pfn << PAGE_SHIFT,
990                                 nr_pages << PAGE_SHIFT,
991                                 trio_context->asid,
992                                 controller->mac,
993                                 (start_pfn << PAGE_SHIFT) +
994                                 TILE_PCI_MEM_MAP_BASE_OFFSET,
995                                 j,
996                                 GXIO_TRIO_ORDER_MODE_UNORDERED);
997                         if (ret < 0) {
998                                 pr_err("PCI: Mem-Map init failure on TRIO %d "
999                                         "mac %d for MC %d, give up\n",
1000                                         controller->trio_index,
1001                                         controller->mac, j);
1002 
1003                                 goto alloc_mem_map_failed;
1004                         }
1005                         continue;
1006 
1007 alloc_mem_map_failed:
1008                         break;
1009                 }
1010 
1011         }
1012 
1013         return 0;
1014 }
1015 subsys_initcall(pcibios_init);
1016 
1017 /* Note: to be deleted after Linux 3.6 merge. */
1018 void pcibios_fixup_bus(struct pci_bus *bus)
1019 {
1020 }
1021 
1022 /*
1023  * This can be called from the generic PCI layer, but doesn't need to
1024  * do anything.
1025  */
1026 char *pcibios_setup(char *str)
1027 {
1028         if (!strcmp(str, "off")) {
1029                 pci_probe = 0;
1030                 return NULL;
1031         }
1032         return str;
1033 }
1034 
1035 /*
1036  * Enable memory address decoding, as appropriate, for the
1037  * device described by the 'dev' struct. The I/O decoding
1038  * is disabled, though the TILE-Gx supports I/O addressing.
1039  *
1040  * This is called from the generic PCI layer, and can be called
1041  * for bridges or endpoints.
1042  */
1043 int pcibios_enable_device(struct pci_dev *dev, int mask)
1044 {
1045         return pci_enable_resources(dev, mask);
1046 }
1047 
1048 /* Called for each device after PCI setup is done. */
1049 static void pcibios_fixup_final(struct pci_dev *pdev)
1050 {
1051         set_dma_ops(&pdev->dev, gx_pci_dma_map_ops);
1052         set_dma_offset(&pdev->dev, TILE_PCI_MEM_MAP_BASE_OFFSET);
1053         pdev->dev.archdata.max_direct_dma_addr =
1054                 TILE_PCI_MAX_DIRECT_DMA_ADDRESS;
1055 }
1056 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_final);
1057 
1058 /* Map a PCI MMIO bus address into VA space. */
1059 void __iomem *ioremap(resource_size_t phys_addr, unsigned long size)
1060 {
1061         struct pci_controller *controller = NULL;
1062         resource_size_t bar_start;
1063         resource_size_t bar_end;
1064         resource_size_t offset;
1065         resource_size_t start;
1066         resource_size_t end;
1067         int trio_fd;
1068         int i, j;
1069 
1070         start = phys_addr;
1071         end = phys_addr + size - 1;
1072 
1073         /*
1074          * In the following, each PCI controller's mem_resources[1]
1075          * represents its (non-prefetchable) PCI memory resource and
1076          * mem_resources[2] refers to its prefetchable PCI memory resource.
1077          * By searching phys_addr in each controller's mem_resources[], we can
1078          * determine the controller that should accept the PCI memory access.
1079          */
1080 
1081         for (i = 0; i < num_rc_controllers; i++) {
1082                 /*
1083                  * Skip controllers that are not properly initialized or
1084                  * have down links.
1085                  */
1086                 if (pci_controllers[i].root_bus == NULL)
1087                         continue;
1088 
1089                 for (j = 1; j < 3; j++) {
1090                         bar_start =
1091                                 pci_controllers[i].mem_resources[j].start;
1092                         bar_end =
1093                                 pci_controllers[i].mem_resources[j].end;
1094 
1095                         if ((start >= bar_start) && (end <= bar_end)) {
1096 
1097                                 controller = &pci_controllers[i];
1098 
1099                                 goto got_it;
1100                         }
1101                 }
1102         }
1103 
1104         if (controller == NULL)
1105                 return NULL;
1106 
1107 got_it:
1108         trio_fd = controller->trio->fd;
1109 
1110         /* Convert the resource start to the bus address offset. */
1111         start = phys_addr - controller->mem_offset;
1112 
1113         offset = HV_TRIO_PIO_OFFSET(controller->pio_mem_index) + start;
1114 
1115         /*
1116          * We need to keep the PCI bus address's in-page offset in the VA.
1117          */
1118         return iorpc_ioremap(trio_fd, offset, size) +
1119                 (phys_addr & (PAGE_SIZE - 1));
1120 }
1121 EXPORT_SYMBOL(ioremap);
1122 
1123 void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
1124 {
1125         iounmap(addr);
1126 }
1127 EXPORT_SYMBOL(pci_iounmap);
1128 
1129 /****************************************************************
1130  *
1131  * Tile PCI config space read/write routines
1132  *
1133  ****************************************************************/
1134 
1135 /*
1136  * These are the normal read and write ops
1137  * These are expanded with macros from  pci_bus_read_config_byte() etc.
1138  *
1139  * devfn is the combined PCI device & function.
1140  *
1141  * offset is in bytes, from the start of config space for the
1142  * specified bus & device.
1143  */
1144 
1145 static int tile_cfg_read(struct pci_bus *bus, unsigned int devfn, int offset,
1146                          int size, u32 *val)
1147 {
1148         struct pci_controller *controller = bus->sysdata;
1149         gxio_trio_context_t *trio_context = controller->trio;
1150         int busnum = bus->number & 0xff;
1151         int device = PCI_SLOT(devfn);
1152         int function = PCI_FUNC(devfn);
1153         int config_type = 1;
1154         TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR_t cfg_addr;
1155         void *mmio_addr;
1156 
1157         /*
1158          * Map all accesses to the local device on root bus into the
1159          * MMIO space of the MAC. Accesses to the downstream devices
1160          * go to the PIO space.
1161          */
1162         if (pci_is_root_bus(bus)) {
1163                 if (device == 0) {
1164                         /*
1165                          * This is the internal downstream P2P bridge,
1166                          * access directly.
1167                          */
1168                         unsigned int reg_offset;
1169 
1170                         reg_offset = ((offset & 0xFFF) <<
1171                                 TRIO_CFG_REGION_ADDR__REG_SHIFT) |
1172                                 (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_PROTECTED
1173                                 << TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
1174                                 (controller->mac <<
1175                                         TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
1176 
1177                         mmio_addr = trio_context->mmio_base_mac + reg_offset;
1178 
1179                         goto valid_device;
1180 
1181                 } else {
1182                         /*
1183                          * We fake an empty device for (device > 0),
1184                          * since there is only one device on bus 0.
1185                          */
1186                         goto invalid_device;
1187                 }
1188         }
1189 
1190         /*
1191          * Accesses to the directly attached device have to be
1192          * sent as type-0 configs.
1193          */
1194 
1195         if (busnum == (controller->first_busno + 1)) {
1196                 /*
1197                  * There is only one device off of our built-in P2P bridge.
1198                  */
1199                 if (device != 0)
1200                         goto invalid_device;
1201 
1202                 config_type = 0;
1203         }
1204 
1205         cfg_addr.word = 0;
1206         cfg_addr.reg_addr = (offset & 0xFFF);
1207         cfg_addr.fn = function;
1208         cfg_addr.dev = device;
1209         cfg_addr.bus = busnum;
1210         cfg_addr.type = config_type;
1211 
1212         /*
1213          * Note that we don't set the mac field in cfg_addr because the
1214          * mapping is per port.
1215          */
1216 
1217         mmio_addr = trio_context->mmio_base_pio_cfg[controller->mac] +
1218                         cfg_addr.word;
1219 
1220 valid_device:
1221 
1222         switch (size) {
1223         case 4:
1224                 *val = __gxio_mmio_read32(mmio_addr);
1225                 break;
1226 
1227         case 2:
1228                 *val = __gxio_mmio_read16(mmio_addr);
1229                 break;
1230 
1231         case 1:
1232                 *val = __gxio_mmio_read8(mmio_addr);
1233                 break;
1234 
1235         default:
1236                 return PCIBIOS_FUNC_NOT_SUPPORTED;
1237         }
1238 
1239         TRACE_CFG_RD(size, *val, busnum, device, function, offset);
1240 
1241         return 0;
1242 
1243 invalid_device:
1244 
1245         switch (size) {
1246         case 4:
1247                 *val = 0xFFFFFFFF;
1248                 break;
1249 
1250         case 2:
1251                 *val = 0xFFFF;
1252                 break;
1253 
1254         case 1:
1255                 *val = 0xFF;
1256                 break;
1257 
1258         default:
1259                 return PCIBIOS_FUNC_NOT_SUPPORTED;
1260         }
1261 
1262         return 0;
1263 }
1264 
1265 
1266 /*
1267  * See tile_cfg_read() for relevent comments.
1268  * Note that "val" is the value to write, not a pointer to that value.
1269  */
1270 static int tile_cfg_write(struct pci_bus *bus, unsigned int devfn, int offset,
1271                           int size, u32 val)
1272 {
1273         struct pci_controller *controller = bus->sysdata;
1274         gxio_trio_context_t *trio_context = controller->trio;
1275         int busnum = bus->number & 0xff;
1276         int device = PCI_SLOT(devfn);
1277         int function = PCI_FUNC(devfn);
1278         int config_type = 1;
1279         TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR_t cfg_addr;
1280         void *mmio_addr;
1281         u32 val_32 = (u32)val;
1282         u16 val_16 = (u16)val;
1283         u8 val_8 = (u8)val;
1284 
1285         /*
1286          * Map all accesses to the local device on root bus into the
1287          * MMIO space of the MAC. Accesses to the downstream devices
1288          * go to the PIO space.
1289          */
1290         if (pci_is_root_bus(bus)) {
1291                 if (device == 0) {
1292                         /*
1293                          * This is the internal downstream P2P bridge,
1294                          * access directly.
1295                          */
1296                         unsigned int reg_offset;
1297 
1298                         reg_offset = ((offset & 0xFFF) <<
1299                                 TRIO_CFG_REGION_ADDR__REG_SHIFT) |
1300                                 (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_PROTECTED
1301                                 << TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
1302                                 (controller->mac <<
1303                                         TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
1304 
1305                         mmio_addr = trio_context->mmio_base_mac + reg_offset;
1306 
1307                         goto valid_device;
1308 
1309                 } else {
1310                         /*
1311                          * We fake an empty device for (device > 0),
1312                          * since there is only one device on bus 0.
1313                          */
1314                         goto invalid_device;
1315                 }
1316         }
1317 
1318         /*
1319          * Accesses to the directly attached device have to be
1320          * sent as type-0 configs.
1321          */
1322 
1323         if (busnum == (controller->first_busno + 1)) {
1324                 /*
1325                  * There is only one device off of our built-in P2P bridge.
1326                  */
1327                 if (device != 0)
1328                         goto invalid_device;
1329 
1330                 config_type = 0;
1331         }
1332 
1333         cfg_addr.word = 0;
1334         cfg_addr.reg_addr = (offset & 0xFFF);
1335         cfg_addr.fn = function;
1336         cfg_addr.dev = device;
1337         cfg_addr.bus = busnum;
1338         cfg_addr.type = config_type;
1339 
1340         /*
1341          * Note that we don't set the mac field in cfg_addr because the
1342          * mapping is per port.
1343          */
1344 
1345         mmio_addr = trio_context->mmio_base_pio_cfg[controller->mac] +
1346                         cfg_addr.word;
1347 
1348 valid_device:
1349 
1350         switch (size) {
1351         case 4:
1352                 __gxio_mmio_write32(mmio_addr, val_32);
1353                 TRACE_CFG_WR(size, val_32, busnum, device, function, offset);
1354                 break;
1355 
1356         case 2:
1357                 __gxio_mmio_write16(mmio_addr, val_16);
1358                 TRACE_CFG_WR(size, val_16, busnum, device, function, offset);
1359                 break;
1360 
1361         case 1:
1362                 __gxio_mmio_write8(mmio_addr, val_8);
1363                 TRACE_CFG_WR(size, val_8, busnum, device, function, offset);
1364                 break;
1365 
1366         default:
1367                 return PCIBIOS_FUNC_NOT_SUPPORTED;
1368         }
1369 
1370 invalid_device:
1371 
1372         return 0;
1373 }
1374 
1375 
1376 static struct pci_ops tile_cfg_ops = {
1377         .read =         tile_cfg_read,
1378         .write =        tile_cfg_write,
1379 };
1380 
1381 
1382 /*
1383  * MSI support starts here.
1384  */
1385 static unsigned int
1386 tilegx_msi_startup(struct irq_data *d)
1387 {
1388         if (d->msi_desc)
1389                 unmask_msi_irq(d);
1390 
1391         return 0;
1392 }
1393 
1394 static void
1395 tilegx_msi_ack(struct irq_data *d)
1396 {
1397         __insn_mtspr(SPR_IPI_EVENT_RESET_K, 1UL << d->irq);
1398 }
1399 
1400 static void
1401 tilegx_msi_mask(struct irq_data *d)
1402 {
1403         mask_msi_irq(d);
1404         __insn_mtspr(SPR_IPI_MASK_SET_K, 1UL << d->irq);
1405 }
1406 
1407 static void
1408 tilegx_msi_unmask(struct irq_data *d)
1409 {
1410         __insn_mtspr(SPR_IPI_MASK_RESET_K, 1UL << d->irq);
1411         unmask_msi_irq(d);
1412 }
1413 
1414 static struct irq_chip tilegx_msi_chip = {
1415         .name                   = "tilegx_msi",
1416         .irq_startup            = tilegx_msi_startup,
1417         .irq_ack                = tilegx_msi_ack,
1418         .irq_mask               = tilegx_msi_mask,
1419         .irq_unmask             = tilegx_msi_unmask,
1420 
1421         /* TBD: support set_affinity. */
1422 };
1423 
1424 int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
1425 {
1426         struct pci_controller *controller;
1427         gxio_trio_context_t *trio_context;
1428         struct msi_msg msg;
1429         int default_irq;
1430         uint64_t mem_map_base;
1431         uint64_t mem_map_limit;
1432         u64 msi_addr;
1433         int mem_map;
1434         int cpu;
1435         int irq;
1436         int ret;
1437 
1438         irq = create_irq();
1439         if (irq < 0)
1440                 return irq;
1441 
1442         /*
1443          * Since we use a 64-bit Mem-Map to accept the MSI write, we fail
1444          * devices that are not capable of generating a 64-bit message address.
1445          * These devices will fall back to using the legacy interrupts.
1446          * Most PCIe endpoint devices do support 64-bit message addressing.
1447          */
1448         if (desc->msi_attrib.is_64 == 0) {
1449                 dev_printk(KERN_INFO, &pdev->dev,
1450                         "64-bit MSI message address not supported, "
1451                         "falling back to legacy interrupts.\n");
1452 
1453                 ret = -ENOMEM;
1454                 goto is_64_failure;
1455         }
1456 
1457         default_irq = desc->msi_attrib.default_irq;
1458         controller = irq_get_handler_data(default_irq);
1459 
1460         BUG_ON(!controller);
1461 
1462         trio_context = controller->trio;
1463 
1464         /*
1465          * Allocate the Mem-Map that will accept the MSI write and
1466          * trigger the TILE-side interrupts.
1467          */
1468         mem_map = gxio_trio_alloc_memory_maps(trio_context, 1, 0, 0);
1469         if (mem_map < 0) {
1470                 dev_printk(KERN_INFO, &pdev->dev,
1471                         "%s Mem-Map alloc failure. "
1472                         "Failed to initialize MSI interrupts. "
1473                         "Falling back to legacy interrupts.\n",
1474                         desc->msi_attrib.is_msix ? "MSI-X" : "MSI");
1475 
1476                 ret = -ENOMEM;
1477                 goto msi_mem_map_alloc_failure;
1478         }
1479 
1480         /* We try to distribute different IRQs to different tiles. */
1481         cpu = tile_irq_cpu(irq);
1482 
1483         /*
1484          * Now call up to the HV to configure the Mem-Map interrupt and
1485          * set up the IPI binding.
1486          */
1487         mem_map_base = MEM_MAP_INTR_REGIONS_BASE +
1488                 mem_map * MEM_MAP_INTR_REGION_SIZE;
1489         mem_map_limit = mem_map_base + MEM_MAP_INTR_REGION_SIZE - 1;
1490 
1491         ret = gxio_trio_config_msi_intr(trio_context, cpu_x(cpu), cpu_y(cpu),
1492                                         KERNEL_PL, irq, controller->mac,
1493                                         mem_map, mem_map_base, mem_map_limit,
1494                                         trio_context->asid);
1495         if (ret < 0) {
1496                 dev_printk(KERN_INFO, &pdev->dev, "HV MSI config failed.\n");
1497 
1498                 goto hv_msi_config_failure;
1499         }
1500 
1501         irq_set_msi_desc(irq, desc);
1502 
1503         msi_addr = mem_map_base + TRIO_MAP_MEM_REG_INT3 - TRIO_MAP_MEM_REG_INT0;
1504 
1505         msg.address_hi = msi_addr >> 32;
1506         msg.address_lo = msi_addr & 0xffffffff;
1507 
1508         msg.data = mem_map;
1509 
1510         write_msi_msg(irq, &msg);
1511         irq_set_chip_and_handler(irq, &tilegx_msi_chip, handle_level_irq);
1512         irq_set_handler_data(irq, controller);
1513 
1514         return 0;
1515 
1516 hv_msi_config_failure:
1517         /* Free mem-map */
1518 msi_mem_map_alloc_failure:
1519 is_64_failure:
1520         destroy_irq(irq);
1521         return ret;
1522 }
1523 
1524 void arch_teardown_msi_irq(unsigned int irq)
1525 {
1526         destroy_irq(irq);
1527 }
1528 

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