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TOMOYO Linux Cross Reference
Linux/arch/unicore32/include/mach/regs-pm.h

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  1 /* SPDX-License-Identifier: GPL-2.0 */
  2 /*
  3  * PKUNITY Power Manager (PM) Registers
  4  */
  5 /*
  6  * PM Control Reg PM_PMCR
  7  */
  8 #define PM_PMCR                 (PKUNITY_PM_BASE + 0x0000)
  9 /*
 10  * PM General Conf. Reg PM_PGCR
 11  */
 12 #define PM_PGCR                 (PKUNITY_PM_BASE + 0x0004)
 13 /*
 14  * PM PLL Conf. Reg PM_PPCR
 15  */
 16 #define PM_PPCR                 (PKUNITY_PM_BASE + 0x0008)
 17 /*
 18  * PM Wakeup Enable Reg PM_PWER
 19  */
 20 #define PM_PWER                 (PKUNITY_PM_BASE + 0x000C)
 21 /*
 22  * PM GPIO Sleep Status Reg PM_PGSR
 23  */
 24 #define PM_PGSR                 (PKUNITY_PM_BASE + 0x0010)
 25 /*
 26  * PM Clock Gate Reg PM_PCGR
 27  */
 28 #define PM_PCGR                 (PKUNITY_PM_BASE + 0x0014)
 29 /*
 30  * PM SYS PLL Conf. Reg PM_PLLSYSCFG
 31  */
 32 #define PM_PLLSYSCFG            (PKUNITY_PM_BASE + 0x0018)
 33 /*
 34  * PM DDR PLL Conf. Reg PM_PLLDDRCFG
 35  */
 36 #define PM_PLLDDRCFG            (PKUNITY_PM_BASE + 0x001C)
 37 /*
 38  * PM VGA PLL Conf. Reg PM_PLLVGACFG
 39  */
 40 #define PM_PLLVGACFG            (PKUNITY_PM_BASE + 0x0020)
 41 /*
 42  * PM Div Conf. Reg PM_DIVCFG
 43  */
 44 #define PM_DIVCFG               (PKUNITY_PM_BASE + 0x0024)
 45 /*
 46  * PM SYS PLL Status Reg PM_PLLSYSSTATUS
 47  */
 48 #define PM_PLLSYSSTATUS         (PKUNITY_PM_BASE + 0x0028)
 49 /*
 50  * PM DDR PLL Status Reg PM_PLLDDRSTATUS
 51  */
 52 #define PM_PLLDDRSTATUS         (PKUNITY_PM_BASE + 0x002C)
 53 /*
 54  * PM VGA PLL Status Reg PM_PLLVGASTATUS
 55  */
 56 #define PM_PLLVGASTATUS         (PKUNITY_PM_BASE + 0x0030)
 57 /*
 58  * PM Div Status Reg PM_DIVSTATUS
 59  */
 60 #define PM_DIVSTATUS            (PKUNITY_PM_BASE + 0x0034)
 61 /*
 62  * PM Software Reset Reg PM_SWRESET
 63  */
 64 #define PM_SWRESET              (PKUNITY_PM_BASE + 0x0038)
 65 /*
 66  * PM DDR2 PAD Start Reg PM_DDR2START
 67  */
 68 #define PM_DDR2START            (PKUNITY_PM_BASE + 0x003C)
 69 /*
 70  * PM DDR2 PAD Status Reg PM_DDR2CAL0
 71  */
 72 #define PM_DDR2CAL0             (PKUNITY_PM_BASE + 0x0040)
 73 /*
 74  * PM PLL DFC Done Reg PM_PLLDFCDONE
 75  */
 76 #define PM_PLLDFCDONE           (PKUNITY_PM_BASE + 0x0044)
 77 
 78 #define PM_PMCR_SFB             FIELD(1, 1, 0)
 79 #define PM_PMCR_IFB             FIELD(1, 1, 1)
 80 #define PM_PMCR_CFBSYS          FIELD(1, 1, 2)
 81 #define PM_PMCR_CFBDDR          FIELD(1, 1, 3)
 82 #define PM_PMCR_CFBVGA          FIELD(1, 1, 4)
 83 #define PM_PMCR_CFBDIVBCLK      FIELD(1, 1, 5)
 84 
 85 /*
 86  * GPIO 8~27 wake-up enable PM_PWER_GPIOHIGH
 87  */
 88 #define PM_PWER_GPIOHIGH        FIELD(1, 1, 8)
 89 /*
 90  * RTC alarm wake-up enable PM_PWER_RTC
 91  */
 92 #define PM_PWER_RTC             FIELD(1, 1, 31)
 93 
 94 #define PM_PCGR_BCLK64DDR       FIELD(1, 1, 0)
 95 #define PM_PCGR_BCLK64VGA       FIELD(1, 1, 1)
 96 #define PM_PCGR_BCLKDDR         FIELD(1, 1, 2)
 97 #define PM_PCGR_BCLKPCI         FIELD(1, 1, 4)
 98 #define PM_PCGR_BCLKDMAC        FIELD(1, 1, 5)
 99 #define PM_PCGR_BCLKUMAL        FIELD(1, 1, 6)
100 #define PM_PCGR_BCLKUSB         FIELD(1, 1, 7)
101 #define PM_PCGR_BCLKMME         FIELD(1, 1, 10)
102 #define PM_PCGR_BCLKNAND        FIELD(1, 1, 11)
103 #define PM_PCGR_BCLKH264E       FIELD(1, 1, 12)
104 #define PM_PCGR_BCLKVGA         FIELD(1, 1, 13)
105 #define PM_PCGR_BCLKH264D       FIELD(1, 1, 14)
106 #define PM_PCGR_VECLK           FIELD(1, 1, 15)
107 #define PM_PCGR_HECLK           FIELD(1, 1, 16)
108 #define PM_PCGR_HDCLK           FIELD(1, 1, 17)
109 #define PM_PCGR_NANDCLK         FIELD(1, 1, 18)
110 #define PM_PCGR_GECLK           FIELD(1, 1, 19)
111 #define PM_PCGR_VGACLK          FIELD(1, 1, 20)
112 #define PM_PCGR_PCICLK          FIELD(1, 1, 21)
113 #define PM_PCGR_SATACLK         FIELD(1, 1, 25)
114 
115 /*
116  * [23:20]PM_DIVCFG_VGACLK(v)
117  */
118 #define PM_DIVCFG_VGACLK_MASK   FMASK(4, 20)
119 #define PM_DIVCFG_VGACLK(v)     FIELD((v), 4, 20)
120 
121 #define PM_SWRESET_USB          FIELD(1, 1, 6)
122 #define PM_SWRESET_VGADIV       FIELD(1, 1, 26)
123 #define PM_SWRESET_GEDIV        FIELD(1, 1, 27)
124 
125 #define PM_PLLDFCDONE_SYSDFC    FIELD(1, 1, 0)
126 #define PM_PLLDFCDONE_DDRDFC    FIELD(1, 1, 1)
127 #define PM_PLLDFCDONE_VGADFC    FIELD(1, 1, 2)
128 

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