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Linux/arch/x86/events/amd/ibs.c

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  1 /*
  2  * Performance events - AMD IBS
  3  *
  4  *  Copyright (C) 2011 Advanced Micro Devices, Inc., Robert Richter
  5  *
  6  *  For licencing details see kernel-base/COPYING
  7  */
  8 
  9 #include <linux/perf_event.h>
 10 #include <linux/init.h>
 11 #include <linux/export.h>
 12 #include <linux/pci.h>
 13 #include <linux/ptrace.h>
 14 #include <linux/syscore_ops.h>
 15 #include <linux/sched/clock.h>
 16 
 17 #include <asm/apic.h>
 18 
 19 #include "../perf_event.h"
 20 
 21 static u32 ibs_caps;
 22 
 23 #if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD)
 24 
 25 #include <linux/kprobes.h>
 26 #include <linux/hardirq.h>
 27 
 28 #include <asm/nmi.h>
 29 
 30 #define IBS_FETCH_CONFIG_MASK   (IBS_FETCH_RAND_EN | IBS_FETCH_MAX_CNT)
 31 #define IBS_OP_CONFIG_MASK      IBS_OP_MAX_CNT
 32 
 33 
 34 /*
 35  * IBS states:
 36  *
 37  * ENABLED; tracks the pmu::add(), pmu::del() state, when set the counter is taken
 38  * and any further add()s must fail.
 39  *
 40  * STARTED/STOPPING/STOPPED; deal with pmu::start(), pmu::stop() state but are
 41  * complicated by the fact that the IBS hardware can send late NMIs (ie. after
 42  * we've cleared the EN bit).
 43  *
 44  * In order to consume these late NMIs we have the STOPPED state, any NMI that
 45  * happens after we've cleared the EN state will clear this bit and report the
 46  * NMI handled (this is fundamentally racy in the face or multiple NMI sources,
 47  * someone else can consume our BIT and our NMI will go unhandled).
 48  *
 49  * And since we cannot set/clear this separate bit together with the EN bit,
 50  * there are races; if we cleared STARTED early, an NMI could land in
 51  * between clearing STARTED and clearing the EN bit (in fact multiple NMIs
 52  * could happen if the period is small enough), and consume our STOPPED bit
 53  * and trigger streams of unhandled NMIs.
 54  *
 55  * If, however, we clear STARTED late, an NMI can hit between clearing the
 56  * EN bit and clearing STARTED, still see STARTED set and process the event.
 57  * If this event will have the VALID bit clear, we bail properly, but this
 58  * is not a given. With VALID set we can end up calling pmu::stop() again
 59  * (the throttle logic) and trigger the WARNs in there.
 60  *
 61  * So what we do is set STOPPING before clearing EN to avoid the pmu::stop()
 62  * nesting, and clear STARTED late, so that we have a well defined state over
 63  * the clearing of the EN bit.
 64  *
 65  * XXX: we could probably be using !atomic bitops for all this.
 66  */
 67 
 68 enum ibs_states {
 69         IBS_ENABLED     = 0,
 70         IBS_STARTED     = 1,
 71         IBS_STOPPING    = 2,
 72         IBS_STOPPED     = 3,
 73 
 74         IBS_MAX_STATES,
 75 };
 76 
 77 struct cpu_perf_ibs {
 78         struct perf_event       *event;
 79         unsigned long           state[BITS_TO_LONGS(IBS_MAX_STATES)];
 80 };
 81 
 82 struct perf_ibs {
 83         struct pmu                      pmu;
 84         unsigned int                    msr;
 85         u64                             config_mask;
 86         u64                             cnt_mask;
 87         u64                             enable_mask;
 88         u64                             valid_mask;
 89         u64                             max_period;
 90         unsigned long                   offset_mask[1];
 91         int                             offset_max;
 92         struct cpu_perf_ibs __percpu    *pcpu;
 93 
 94         struct attribute                **format_attrs;
 95         struct attribute_group          format_group;
 96         const struct attribute_group    *attr_groups[2];
 97 
 98         u64                             (*get_count)(u64 config);
 99 };
100 
101 struct perf_ibs_data {
102         u32             size;
103         union {
104                 u32     data[0];        /* data buffer starts here */
105                 u32     caps;
106         };
107         u64             regs[MSR_AMD64_IBS_REG_COUNT_MAX];
108 };
109 
110 static int
111 perf_event_set_period(struct hw_perf_event *hwc, u64 min, u64 max, u64 *hw_period)
112 {
113         s64 left = local64_read(&hwc->period_left);
114         s64 period = hwc->sample_period;
115         int overflow = 0;
116 
117         /*
118          * If we are way outside a reasonable range then just skip forward:
119          */
120         if (unlikely(left <= -period)) {
121                 left = period;
122                 local64_set(&hwc->period_left, left);
123                 hwc->last_period = period;
124                 overflow = 1;
125         }
126 
127         if (unlikely(left < (s64)min)) {
128                 left += period;
129                 local64_set(&hwc->period_left, left);
130                 hwc->last_period = period;
131                 overflow = 1;
132         }
133 
134         /*
135          * If the hw period that triggers the sw overflow is too short
136          * we might hit the irq handler. This biases the results.
137          * Thus we shorten the next-to-last period and set the last
138          * period to the max period.
139          */
140         if (left > max) {
141                 left -= max;
142                 if (left > max)
143                         left = max;
144                 else if (left < min)
145                         left = min;
146         }
147 
148         *hw_period = (u64)left;
149 
150         return overflow;
151 }
152 
153 static  int
154 perf_event_try_update(struct perf_event *event, u64 new_raw_count, int width)
155 {
156         struct hw_perf_event *hwc = &event->hw;
157         int shift = 64 - width;
158         u64 prev_raw_count;
159         u64 delta;
160 
161         /*
162          * Careful: an NMI might modify the previous event value.
163          *
164          * Our tactic to handle this is to first atomically read and
165          * exchange a new raw count - then add that new-prev delta
166          * count to the generic event atomically:
167          */
168         prev_raw_count = local64_read(&hwc->prev_count);
169         if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
170                                         new_raw_count) != prev_raw_count)
171                 return 0;
172 
173         /*
174          * Now we have the new raw value and have updated the prev
175          * timestamp already. We can now calculate the elapsed delta
176          * (event-)time and add that to the generic event.
177          *
178          * Careful, not all hw sign-extends above the physical width
179          * of the count.
180          */
181         delta = (new_raw_count << shift) - (prev_raw_count << shift);
182         delta >>= shift;
183 
184         local64_add(delta, &event->count);
185         local64_sub(delta, &hwc->period_left);
186 
187         return 1;
188 }
189 
190 static struct perf_ibs perf_ibs_fetch;
191 static struct perf_ibs perf_ibs_op;
192 
193 static struct perf_ibs *get_ibs_pmu(int type)
194 {
195         if (perf_ibs_fetch.pmu.type == type)
196                 return &perf_ibs_fetch;
197         if (perf_ibs_op.pmu.type == type)
198                 return &perf_ibs_op;
199         return NULL;
200 }
201 
202 /*
203  * Use IBS for precise event sampling:
204  *
205  *  perf record -a -e cpu-cycles:p ...    # use ibs op counting cycle count
206  *  perf record -a -e r076:p ...          # same as -e cpu-cycles:p
207  *  perf record -a -e r0C1:p ...          # use ibs op counting micro-ops
208  *
209  * IbsOpCntCtl (bit 19) of IBS Execution Control Register (IbsOpCtl,
210  * MSRC001_1033) is used to select either cycle or micro-ops counting
211  * mode.
212  *
213  * The rip of IBS samples has skid 0. Thus, IBS supports precise
214  * levels 1 and 2 and the PERF_EFLAGS_EXACT is set. In rare cases the
215  * rip is invalid when IBS was not able to record the rip correctly.
216  * We clear PERF_EFLAGS_EXACT and take the rip from pt_regs then.
217  *
218  */
219 static int perf_ibs_precise_event(struct perf_event *event, u64 *config)
220 {
221         switch (event->attr.precise_ip) {
222         case 0:
223                 return -ENOENT;
224         case 1:
225         case 2:
226                 break;
227         default:
228                 return -EOPNOTSUPP;
229         }
230 
231         switch (event->attr.type) {
232         case PERF_TYPE_HARDWARE:
233                 switch (event->attr.config) {
234                 case PERF_COUNT_HW_CPU_CYCLES:
235                         *config = 0;
236                         return 0;
237                 }
238                 break;
239         case PERF_TYPE_RAW:
240                 switch (event->attr.config) {
241                 case 0x0076:
242                         *config = 0;
243                         return 0;
244                 case 0x00C1:
245                         *config = IBS_OP_CNT_CTL;
246                         return 0;
247                 }
248                 break;
249         default:
250                 return -ENOENT;
251         }
252 
253         return -EOPNOTSUPP;
254 }
255 
256 static int perf_ibs_init(struct perf_event *event)
257 {
258         struct hw_perf_event *hwc = &event->hw;
259         struct perf_ibs *perf_ibs;
260         u64 max_cnt, config;
261         int ret;
262 
263         perf_ibs = get_ibs_pmu(event->attr.type);
264         if (perf_ibs) {
265                 config = event->attr.config;
266         } else {
267                 perf_ibs = &perf_ibs_op;
268                 ret = perf_ibs_precise_event(event, &config);
269                 if (ret)
270                         return ret;
271         }
272 
273         if (event->pmu != &perf_ibs->pmu)
274                 return -ENOENT;
275 
276         if (config & ~perf_ibs->config_mask)
277                 return -EINVAL;
278 
279         if (hwc->sample_period) {
280                 if (config & perf_ibs->cnt_mask)
281                         /* raw max_cnt may not be set */
282                         return -EINVAL;
283                 if (!event->attr.sample_freq && hwc->sample_period & 0x0f)
284                         /*
285                          * lower 4 bits can not be set in ibs max cnt,
286                          * but allowing it in case we adjust the
287                          * sample period to set a frequency.
288                          */
289                         return -EINVAL;
290                 hwc->sample_period &= ~0x0FULL;
291                 if (!hwc->sample_period)
292                         hwc->sample_period = 0x10;
293         } else {
294                 max_cnt = config & perf_ibs->cnt_mask;
295                 config &= ~perf_ibs->cnt_mask;
296                 event->attr.sample_period = max_cnt << 4;
297                 hwc->sample_period = event->attr.sample_period;
298         }
299 
300         if (!hwc->sample_period)
301                 return -EINVAL;
302 
303         /*
304          * If we modify hwc->sample_period, we also need to update
305          * hwc->last_period and hwc->period_left.
306          */
307         hwc->last_period = hwc->sample_period;
308         local64_set(&hwc->period_left, hwc->sample_period);
309 
310         hwc->config_base = perf_ibs->msr;
311         hwc->config = config;
312 
313         return 0;
314 }
315 
316 static int perf_ibs_set_period(struct perf_ibs *perf_ibs,
317                                struct hw_perf_event *hwc, u64 *period)
318 {
319         int overflow;
320 
321         /* ignore lower 4 bits in min count: */
322         overflow = perf_event_set_period(hwc, 1<<4, perf_ibs->max_period, period);
323         local64_set(&hwc->prev_count, 0);
324 
325         return overflow;
326 }
327 
328 static u64 get_ibs_fetch_count(u64 config)
329 {
330         return (config & IBS_FETCH_CNT) >> 12;
331 }
332 
333 static u64 get_ibs_op_count(u64 config)
334 {
335         u64 count = 0;
336 
337         if (config & IBS_OP_VAL)
338                 count += (config & IBS_OP_MAX_CNT) << 4; /* cnt rolled over */
339 
340         if (ibs_caps & IBS_CAPS_RDWROPCNT)
341                 count += (config & IBS_OP_CUR_CNT) >> 32;
342 
343         return count;
344 }
345 
346 static void
347 perf_ibs_event_update(struct perf_ibs *perf_ibs, struct perf_event *event,
348                       u64 *config)
349 {
350         u64 count = perf_ibs->get_count(*config);
351 
352         /*
353          * Set width to 64 since we do not overflow on max width but
354          * instead on max count. In perf_ibs_set_period() we clear
355          * prev count manually on overflow.
356          */
357         while (!perf_event_try_update(event, count, 64)) {
358                 rdmsrl(event->hw.config_base, *config);
359                 count = perf_ibs->get_count(*config);
360         }
361 }
362 
363 static inline void perf_ibs_enable_event(struct perf_ibs *perf_ibs,
364                                          struct hw_perf_event *hwc, u64 config)
365 {
366         wrmsrl(hwc->config_base, hwc->config | config | perf_ibs->enable_mask);
367 }
368 
369 /*
370  * Erratum #420 Instruction-Based Sampling Engine May Generate
371  * Interrupt that Cannot Be Cleared:
372  *
373  * Must clear counter mask first, then clear the enable bit. See
374  * Revision Guide for AMD Family 10h Processors, Publication #41322.
375  */
376 static inline void perf_ibs_disable_event(struct perf_ibs *perf_ibs,
377                                           struct hw_perf_event *hwc, u64 config)
378 {
379         config &= ~perf_ibs->cnt_mask;
380         wrmsrl(hwc->config_base, config);
381         config &= ~perf_ibs->enable_mask;
382         wrmsrl(hwc->config_base, config);
383 }
384 
385 /*
386  * We cannot restore the ibs pmu state, so we always needs to update
387  * the event while stopping it and then reset the state when starting
388  * again. Thus, ignoring PERF_EF_RELOAD and PERF_EF_UPDATE flags in
389  * perf_ibs_start()/perf_ibs_stop() and instead always do it.
390  */
391 static void perf_ibs_start(struct perf_event *event, int flags)
392 {
393         struct hw_perf_event *hwc = &event->hw;
394         struct perf_ibs *perf_ibs = container_of(event->pmu, struct perf_ibs, pmu);
395         struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
396         u64 period;
397 
398         if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED)))
399                 return;
400 
401         WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
402         hwc->state = 0;
403 
404         perf_ibs_set_period(perf_ibs, hwc, &period);
405         /*
406          * Set STARTED before enabling the hardware, such that a subsequent NMI
407          * must observe it.
408          */
409         set_bit(IBS_STARTED,    pcpu->state);
410         clear_bit(IBS_STOPPING, pcpu->state);
411         perf_ibs_enable_event(perf_ibs, hwc, period >> 4);
412 
413         perf_event_update_userpage(event);
414 }
415 
416 static void perf_ibs_stop(struct perf_event *event, int flags)
417 {
418         struct hw_perf_event *hwc = &event->hw;
419         struct perf_ibs *perf_ibs = container_of(event->pmu, struct perf_ibs, pmu);
420         struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
421         u64 config;
422         int stopping;
423 
424         if (test_and_set_bit(IBS_STOPPING, pcpu->state))
425                 return;
426 
427         stopping = test_bit(IBS_STARTED, pcpu->state);
428 
429         if (!stopping && (hwc->state & PERF_HES_UPTODATE))
430                 return;
431 
432         rdmsrl(hwc->config_base, config);
433 
434         if (stopping) {
435                 /*
436                  * Set STOPPED before disabling the hardware, such that it
437                  * must be visible to NMIs the moment we clear the EN bit,
438                  * at which point we can generate an !VALID sample which
439                  * we need to consume.
440                  */
441                 set_bit(IBS_STOPPED, pcpu->state);
442                 perf_ibs_disable_event(perf_ibs, hwc, config);
443                 /*
444                  * Clear STARTED after disabling the hardware; if it were
445                  * cleared before an NMI hitting after the clear but before
446                  * clearing the EN bit might think it a spurious NMI and not
447                  * handle it.
448                  *
449                  * Clearing it after, however, creates the problem of the NMI
450                  * handler seeing STARTED but not having a valid sample.
451                  */
452                 clear_bit(IBS_STARTED, pcpu->state);
453                 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
454                 hwc->state |= PERF_HES_STOPPED;
455         }
456 
457         if (hwc->state & PERF_HES_UPTODATE)
458                 return;
459 
460         /*
461          * Clear valid bit to not count rollovers on update, rollovers
462          * are only updated in the irq handler.
463          */
464         config &= ~perf_ibs->valid_mask;
465 
466         perf_ibs_event_update(perf_ibs, event, &config);
467         hwc->state |= PERF_HES_UPTODATE;
468 }
469 
470 static int perf_ibs_add(struct perf_event *event, int flags)
471 {
472         struct perf_ibs *perf_ibs = container_of(event->pmu, struct perf_ibs, pmu);
473         struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
474 
475         if (test_and_set_bit(IBS_ENABLED, pcpu->state))
476                 return -ENOSPC;
477 
478         event->hw.state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
479 
480         pcpu->event = event;
481 
482         if (flags & PERF_EF_START)
483                 perf_ibs_start(event, PERF_EF_RELOAD);
484 
485         return 0;
486 }
487 
488 static void perf_ibs_del(struct perf_event *event, int flags)
489 {
490         struct perf_ibs *perf_ibs = container_of(event->pmu, struct perf_ibs, pmu);
491         struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
492 
493         if (!test_and_clear_bit(IBS_ENABLED, pcpu->state))
494                 return;
495 
496         perf_ibs_stop(event, PERF_EF_UPDATE);
497 
498         pcpu->event = NULL;
499 
500         perf_event_update_userpage(event);
501 }
502 
503 static void perf_ibs_read(struct perf_event *event) { }
504 
505 PMU_FORMAT_ATTR(rand_en,        "config:57");
506 PMU_FORMAT_ATTR(cnt_ctl,        "config:19");
507 
508 static struct attribute *ibs_fetch_format_attrs[] = {
509         &format_attr_rand_en.attr,
510         NULL,
511 };
512 
513 static struct attribute *ibs_op_format_attrs[] = {
514         NULL,   /* &format_attr_cnt_ctl.attr if IBS_CAPS_OPCNT */
515         NULL,
516 };
517 
518 static struct perf_ibs perf_ibs_fetch = {
519         .pmu = {
520                 .task_ctx_nr    = perf_invalid_context,
521 
522                 .event_init     = perf_ibs_init,
523                 .add            = perf_ibs_add,
524                 .del            = perf_ibs_del,
525                 .start          = perf_ibs_start,
526                 .stop           = perf_ibs_stop,
527                 .read           = perf_ibs_read,
528                 .capabilities   = PERF_PMU_CAP_NO_EXCLUDE,
529         },
530         .msr                    = MSR_AMD64_IBSFETCHCTL,
531         .config_mask            = IBS_FETCH_CONFIG_MASK,
532         .cnt_mask               = IBS_FETCH_MAX_CNT,
533         .enable_mask            = IBS_FETCH_ENABLE,
534         .valid_mask             = IBS_FETCH_VAL,
535         .max_period             = IBS_FETCH_MAX_CNT << 4,
536         .offset_mask            = { MSR_AMD64_IBSFETCH_REG_MASK },
537         .offset_max             = MSR_AMD64_IBSFETCH_REG_COUNT,
538         .format_attrs           = ibs_fetch_format_attrs,
539 
540         .get_count              = get_ibs_fetch_count,
541 };
542 
543 static struct perf_ibs perf_ibs_op = {
544         .pmu = {
545                 .task_ctx_nr    = perf_invalid_context,
546 
547                 .event_init     = perf_ibs_init,
548                 .add            = perf_ibs_add,
549                 .del            = perf_ibs_del,
550                 .start          = perf_ibs_start,
551                 .stop           = perf_ibs_stop,
552                 .read           = perf_ibs_read,
553         },
554         .msr                    = MSR_AMD64_IBSOPCTL,
555         .config_mask            = IBS_OP_CONFIG_MASK,
556         .cnt_mask               = IBS_OP_MAX_CNT,
557         .enable_mask            = IBS_OP_ENABLE,
558         .valid_mask             = IBS_OP_VAL,
559         .max_period             = IBS_OP_MAX_CNT << 4,
560         .offset_mask            = { MSR_AMD64_IBSOP_REG_MASK },
561         .offset_max             = MSR_AMD64_IBSOP_REG_COUNT,
562         .format_attrs           = ibs_op_format_attrs,
563 
564         .get_count              = get_ibs_op_count,
565 };
566 
567 static int perf_ibs_handle_irq(struct perf_ibs *perf_ibs, struct pt_regs *iregs)
568 {
569         struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
570         struct perf_event *event = pcpu->event;
571         struct hw_perf_event *hwc;
572         struct perf_sample_data data;
573         struct perf_raw_record raw;
574         struct pt_regs regs;
575         struct perf_ibs_data ibs_data;
576         int offset, size, check_rip, offset_max, throttle = 0;
577         unsigned int msr;
578         u64 *buf, *config, period;
579 
580         if (!test_bit(IBS_STARTED, pcpu->state)) {
581 fail:
582                 /*
583                  * Catch spurious interrupts after stopping IBS: After
584                  * disabling IBS there could be still incoming NMIs
585                  * with samples that even have the valid bit cleared.
586                  * Mark all this NMIs as handled.
587                  */
588                 if (test_and_clear_bit(IBS_STOPPED, pcpu->state))
589                         return 1;
590 
591                 return 0;
592         }
593 
594         if (WARN_ON_ONCE(!event))
595                 goto fail;
596 
597         hwc = &event->hw;
598         msr = hwc->config_base;
599         buf = ibs_data.regs;
600         rdmsrl(msr, *buf);
601         if (!(*buf++ & perf_ibs->valid_mask))
602                 goto fail;
603 
604         config = &ibs_data.regs[0];
605         perf_ibs_event_update(perf_ibs, event, config);
606         perf_sample_data_init(&data, 0, hwc->last_period);
607         if (!perf_ibs_set_period(perf_ibs, hwc, &period))
608                 goto out;       /* no sw counter overflow */
609 
610         ibs_data.caps = ibs_caps;
611         size = 1;
612         offset = 1;
613         check_rip = (perf_ibs == &perf_ibs_op && (ibs_caps & IBS_CAPS_RIPINVALIDCHK));
614         if (event->attr.sample_type & PERF_SAMPLE_RAW)
615                 offset_max = perf_ibs->offset_max;
616         else if (check_rip)
617                 offset_max = 2;
618         else
619                 offset_max = 1;
620         do {
621                 rdmsrl(msr + offset, *buf++);
622                 size++;
623                 offset = find_next_bit(perf_ibs->offset_mask,
624                                        perf_ibs->offset_max,
625                                        offset + 1);
626         } while (offset < offset_max);
627         if (event->attr.sample_type & PERF_SAMPLE_RAW) {
628                 /*
629                  * Read IbsBrTarget and IbsOpData4 separately
630                  * depending on their availability.
631                  * Can't add to offset_max as they are staggered
632                  */
633                 if (ibs_caps & IBS_CAPS_BRNTRGT) {
634                         rdmsrl(MSR_AMD64_IBSBRTARGET, *buf++);
635                         size++;
636                 }
637                 if (ibs_caps & IBS_CAPS_OPDATA4) {
638                         rdmsrl(MSR_AMD64_IBSOPDATA4, *buf++);
639                         size++;
640                 }
641         }
642         ibs_data.size = sizeof(u64) * size;
643 
644         regs = *iregs;
645         if (check_rip && (ibs_data.regs[2] & IBS_RIP_INVALID)) {
646                 regs.flags &= ~PERF_EFLAGS_EXACT;
647         } else {
648                 set_linear_ip(&regs, ibs_data.regs[1]);
649                 regs.flags |= PERF_EFLAGS_EXACT;
650         }
651 
652         if (event->attr.sample_type & PERF_SAMPLE_RAW) {
653                 raw = (struct perf_raw_record){
654                         .frag = {
655                                 .size = sizeof(u32) + ibs_data.size,
656                                 .data = ibs_data.data,
657                         },
658                 };
659                 data.raw = &raw;
660         }
661 
662         throttle = perf_event_overflow(event, &data, &regs);
663 out:
664         if (throttle)
665                 perf_ibs_stop(event, 0);
666         else
667                 perf_ibs_enable_event(perf_ibs, hwc, period >> 4);
668 
669         perf_event_update_userpage(event);
670 
671         return 1;
672 }
673 
674 static int
675 perf_ibs_nmi_handler(unsigned int cmd, struct pt_regs *regs)
676 {
677         u64 stamp = sched_clock();
678         int handled = 0;
679 
680         handled += perf_ibs_handle_irq(&perf_ibs_fetch, regs);
681         handled += perf_ibs_handle_irq(&perf_ibs_op, regs);
682 
683         if (handled)
684                 inc_irq_stat(apic_perf_irqs);
685 
686         perf_sample_event_took(sched_clock() - stamp);
687 
688         return handled;
689 }
690 NOKPROBE_SYMBOL(perf_ibs_nmi_handler);
691 
692 static __init int perf_ibs_pmu_init(struct perf_ibs *perf_ibs, char *name)
693 {
694         struct cpu_perf_ibs __percpu *pcpu;
695         int ret;
696 
697         pcpu = alloc_percpu(struct cpu_perf_ibs);
698         if (!pcpu)
699                 return -ENOMEM;
700 
701         perf_ibs->pcpu = pcpu;
702 
703         /* register attributes */
704         if (perf_ibs->format_attrs[0]) {
705                 memset(&perf_ibs->format_group, 0, sizeof(perf_ibs->format_group));
706                 perf_ibs->format_group.name     = "format";
707                 perf_ibs->format_group.attrs    = perf_ibs->format_attrs;
708 
709                 memset(&perf_ibs->attr_groups, 0, sizeof(perf_ibs->attr_groups));
710                 perf_ibs->attr_groups[0]        = &perf_ibs->format_group;
711                 perf_ibs->pmu.attr_groups       = perf_ibs->attr_groups;
712         }
713 
714         ret = perf_pmu_register(&perf_ibs->pmu, name, -1);
715         if (ret) {
716                 perf_ibs->pcpu = NULL;
717                 free_percpu(pcpu);
718         }
719 
720         return ret;
721 }
722 
723 static __init void perf_event_ibs_init(void)
724 {
725         struct attribute **attr = ibs_op_format_attrs;
726 
727         perf_ibs_pmu_init(&perf_ibs_fetch, "ibs_fetch");
728 
729         if (ibs_caps & IBS_CAPS_OPCNT) {
730                 perf_ibs_op.config_mask |= IBS_OP_CNT_CTL;
731                 *attr++ = &format_attr_cnt_ctl.attr;
732         }
733         perf_ibs_pmu_init(&perf_ibs_op, "ibs_op");
734 
735         register_nmi_handler(NMI_LOCAL, perf_ibs_nmi_handler, 0, "perf_ibs");
736         pr_info("perf: AMD IBS detected (0x%08x)\n", ibs_caps);
737 }
738 
739 #else /* defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD) */
740 
741 static __init void perf_event_ibs_init(void) { }
742 
743 #endif
744 
745 /* IBS - apic initialization, for perf and oprofile */
746 
747 static __init u32 __get_ibs_caps(void)
748 {
749         u32 caps;
750         unsigned int max_level;
751 
752         if (!boot_cpu_has(X86_FEATURE_IBS))
753                 return 0;
754 
755         /* check IBS cpuid feature flags */
756         max_level = cpuid_eax(0x80000000);
757         if (max_level < IBS_CPUID_FEATURES)
758                 return IBS_CAPS_DEFAULT;
759 
760         caps = cpuid_eax(IBS_CPUID_FEATURES);
761         if (!(caps & IBS_CAPS_AVAIL))
762                 /* cpuid flags not valid */
763                 return IBS_CAPS_DEFAULT;
764 
765         return caps;
766 }
767 
768 u32 get_ibs_caps(void)
769 {
770         return ibs_caps;
771 }
772 
773 EXPORT_SYMBOL(get_ibs_caps);
774 
775 static inline int get_eilvt(int offset)
776 {
777         return !setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_NMI, 1);
778 }
779 
780 static inline int put_eilvt(int offset)
781 {
782         return !setup_APIC_eilvt(offset, 0, 0, 1);
783 }
784 
785 /*
786  * Check and reserve APIC extended interrupt LVT offset for IBS if available.
787  */
788 static inline int ibs_eilvt_valid(void)
789 {
790         int offset;
791         u64 val;
792         int valid = 0;
793 
794         preempt_disable();
795 
796         rdmsrl(MSR_AMD64_IBSCTL, val);
797         offset = val & IBSCTL_LVT_OFFSET_MASK;
798 
799         if (!(val & IBSCTL_LVT_OFFSET_VALID)) {
800                 pr_err(FW_BUG "cpu %d, invalid IBS interrupt offset %d (MSR%08X=0x%016llx)\n",
801                        smp_processor_id(), offset, MSR_AMD64_IBSCTL, val);
802                 goto out;
803         }
804 
805         if (!get_eilvt(offset)) {
806                 pr_err(FW_BUG "cpu %d, IBS interrupt offset %d not available (MSR%08X=0x%016llx)\n",
807                        smp_processor_id(), offset, MSR_AMD64_IBSCTL, val);
808                 goto out;
809         }
810 
811         valid = 1;
812 out:
813         preempt_enable();
814 
815         return valid;
816 }
817 
818 static int setup_ibs_ctl(int ibs_eilvt_off)
819 {
820         struct pci_dev *cpu_cfg;
821         int nodes;
822         u32 value = 0;
823 
824         nodes = 0;
825         cpu_cfg = NULL;
826         do {
827                 cpu_cfg = pci_get_device(PCI_VENDOR_ID_AMD,
828                                          PCI_DEVICE_ID_AMD_10H_NB_MISC,
829                                          cpu_cfg);
830                 if (!cpu_cfg)
831                         break;
832                 ++nodes;
833                 pci_write_config_dword(cpu_cfg, IBSCTL, ibs_eilvt_off
834                                        | IBSCTL_LVT_OFFSET_VALID);
835                 pci_read_config_dword(cpu_cfg, IBSCTL, &value);
836                 if (value != (ibs_eilvt_off | IBSCTL_LVT_OFFSET_VALID)) {
837                         pci_dev_put(cpu_cfg);
838                         pr_debug("Failed to setup IBS LVT offset, IBSCTL = 0x%08x\n",
839                                  value);
840                         return -EINVAL;
841                 }
842         } while (1);
843 
844         if (!nodes) {
845                 pr_debug("No CPU node configured for IBS\n");
846                 return -ENODEV;
847         }
848 
849         return 0;
850 }
851 
852 /*
853  * This runs only on the current cpu. We try to find an LVT offset and
854  * setup the local APIC. For this we must disable preemption. On
855  * success we initialize all nodes with this offset. This updates then
856  * the offset in the IBS_CTL per-node msr. The per-core APIC setup of
857  * the IBS interrupt vector is handled by perf_ibs_cpu_notifier that
858  * is using the new offset.
859  */
860 static void force_ibs_eilvt_setup(void)
861 {
862         int offset;
863         int ret;
864 
865         preempt_disable();
866         /* find the next free available EILVT entry, skip offset 0 */
867         for (offset = 1; offset < APIC_EILVT_NR_MAX; offset++) {
868                 if (get_eilvt(offset))
869                         break;
870         }
871         preempt_enable();
872 
873         if (offset == APIC_EILVT_NR_MAX) {
874                 pr_debug("No EILVT entry available\n");
875                 return;
876         }
877 
878         ret = setup_ibs_ctl(offset);
879         if (ret)
880                 goto out;
881 
882         if (!ibs_eilvt_valid())
883                 goto out;
884 
885         pr_info("LVT offset %d assigned\n", offset);
886 
887         return;
888 out:
889         preempt_disable();
890         put_eilvt(offset);
891         preempt_enable();
892         return;
893 }
894 
895 static void ibs_eilvt_setup(void)
896 {
897         /*
898          * Force LVT offset assignment for family 10h: The offsets are
899          * not assigned by the BIOS for this family, so the OS is
900          * responsible for doing it. If the OS assignment fails, fall
901          * back to BIOS settings and try to setup this.
902          */
903         if (boot_cpu_data.x86 == 0x10)
904                 force_ibs_eilvt_setup();
905 }
906 
907 static inline int get_ibs_lvt_offset(void)
908 {
909         u64 val;
910 
911         rdmsrl(MSR_AMD64_IBSCTL, val);
912         if (!(val & IBSCTL_LVT_OFFSET_VALID))
913                 return -EINVAL;
914 
915         return val & IBSCTL_LVT_OFFSET_MASK;
916 }
917 
918 static void setup_APIC_ibs(void)
919 {
920         int offset;
921 
922         offset = get_ibs_lvt_offset();
923         if (offset < 0)
924                 goto failed;
925 
926         if (!setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_NMI, 0))
927                 return;
928 failed:
929         pr_warn("perf: IBS APIC setup failed on cpu #%d\n",
930                 smp_processor_id());
931 }
932 
933 static void clear_APIC_ibs(void)
934 {
935         int offset;
936 
937         offset = get_ibs_lvt_offset();
938         if (offset >= 0)
939                 setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_FIX, 1);
940 }
941 
942 static int x86_pmu_amd_ibs_starting_cpu(unsigned int cpu)
943 {
944         setup_APIC_ibs();
945         return 0;
946 }
947 
948 #ifdef CONFIG_PM
949 
950 static int perf_ibs_suspend(void)
951 {
952         clear_APIC_ibs();
953         return 0;
954 }
955 
956 static void perf_ibs_resume(void)
957 {
958         ibs_eilvt_setup();
959         setup_APIC_ibs();
960 }
961 
962 static struct syscore_ops perf_ibs_syscore_ops = {
963         .resume         = perf_ibs_resume,
964         .suspend        = perf_ibs_suspend,
965 };
966 
967 static void perf_ibs_pm_init(void)
968 {
969         register_syscore_ops(&perf_ibs_syscore_ops);
970 }
971 
972 #else
973 
974 static inline void perf_ibs_pm_init(void) { }
975 
976 #endif
977 
978 static int x86_pmu_amd_ibs_dying_cpu(unsigned int cpu)
979 {
980         clear_APIC_ibs();
981         return 0;
982 }
983 
984 static __init int amd_ibs_init(void)
985 {
986         u32 caps;
987 
988         caps = __get_ibs_caps();
989         if (!caps)
990                 return -ENODEV; /* ibs not supported by the cpu */
991 
992         ibs_eilvt_setup();
993 
994         if (!ibs_eilvt_valid())
995                 return -EINVAL;
996 
997         perf_ibs_pm_init();
998 
999         ibs_caps = caps;
1000         /* make ibs_caps visible to other cpus: */
1001         smp_mb();
1002         /*
1003          * x86_pmu_amd_ibs_starting_cpu will be called from core on
1004          * all online cpus.
1005          */
1006         cpuhp_setup_state(CPUHP_AP_PERF_X86_AMD_IBS_STARTING,
1007                           "perf/x86/amd/ibs:starting",
1008                           x86_pmu_amd_ibs_starting_cpu,
1009                           x86_pmu_amd_ibs_dying_cpu);
1010 
1011         perf_event_ibs_init();
1012 
1013         return 0;
1014 }
1015 
1016 /* Since we need the pci subsystem to init ibs we can't do this earlier: */
1017 device_initcall(amd_ibs_init);
1018 

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