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TOMOYO Linux Cross Reference
Linux/arch/x86/events/intel/uncore.c

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  1 #include <linux/module.h>
  2 
  3 #include <asm/cpu_device_id.h>
  4 #include <asm/intel-family.h>
  5 #include "uncore.h"
  6 
  7 static struct intel_uncore_type *empty_uncore[] = { NULL, };
  8 struct intel_uncore_type **uncore_msr_uncores = empty_uncore;
  9 struct intel_uncore_type **uncore_pci_uncores = empty_uncore;
 10 
 11 static bool pcidrv_registered;
 12 struct pci_driver *uncore_pci_driver;
 13 /* pci bus to socket mapping */
 14 DEFINE_RAW_SPINLOCK(pci2phy_map_lock);
 15 struct list_head pci2phy_map_head = LIST_HEAD_INIT(pci2phy_map_head);
 16 struct pci_extra_dev *uncore_extra_pci_dev;
 17 static int max_packages;
 18 
 19 /* mask of cpus that collect uncore events */
 20 static cpumask_t uncore_cpu_mask;
 21 
 22 /* constraint for the fixed counter */
 23 static struct event_constraint uncore_constraint_fixed =
 24         EVENT_CONSTRAINT(~0ULL, 1 << UNCORE_PMC_IDX_FIXED, ~0ULL);
 25 struct event_constraint uncore_constraint_empty =
 26         EVENT_CONSTRAINT(0, 0, 0);
 27 
 28 MODULE_LICENSE("GPL");
 29 
 30 static int uncore_pcibus_to_physid(struct pci_bus *bus)
 31 {
 32         struct pci2phy_map *map;
 33         int phys_id = -1;
 34 
 35         raw_spin_lock(&pci2phy_map_lock);
 36         list_for_each_entry(map, &pci2phy_map_head, list) {
 37                 if (map->segment == pci_domain_nr(bus)) {
 38                         phys_id = map->pbus_to_physid[bus->number];
 39                         break;
 40                 }
 41         }
 42         raw_spin_unlock(&pci2phy_map_lock);
 43 
 44         return phys_id;
 45 }
 46 
 47 static void uncore_free_pcibus_map(void)
 48 {
 49         struct pci2phy_map *map, *tmp;
 50 
 51         list_for_each_entry_safe(map, tmp, &pci2phy_map_head, list) {
 52                 list_del(&map->list);
 53                 kfree(map);
 54         }
 55 }
 56 
 57 struct pci2phy_map *__find_pci2phy_map(int segment)
 58 {
 59         struct pci2phy_map *map, *alloc = NULL;
 60         int i;
 61 
 62         lockdep_assert_held(&pci2phy_map_lock);
 63 
 64 lookup:
 65         list_for_each_entry(map, &pci2phy_map_head, list) {
 66                 if (map->segment == segment)
 67                         goto end;
 68         }
 69 
 70         if (!alloc) {
 71                 raw_spin_unlock(&pci2phy_map_lock);
 72                 alloc = kmalloc(sizeof(struct pci2phy_map), GFP_KERNEL);
 73                 raw_spin_lock(&pci2phy_map_lock);
 74 
 75                 if (!alloc)
 76                         return NULL;
 77 
 78                 goto lookup;
 79         }
 80 
 81         map = alloc;
 82         alloc = NULL;
 83         map->segment = segment;
 84         for (i = 0; i < 256; i++)
 85                 map->pbus_to_physid[i] = -1;
 86         list_add_tail(&map->list, &pci2phy_map_head);
 87 
 88 end:
 89         kfree(alloc);
 90         return map;
 91 }
 92 
 93 ssize_t uncore_event_show(struct kobject *kobj,
 94                           struct kobj_attribute *attr, char *buf)
 95 {
 96         struct uncore_event_desc *event =
 97                 container_of(attr, struct uncore_event_desc, attr);
 98         return sprintf(buf, "%s", event->config);
 99 }
100 
101 struct intel_uncore_box *uncore_pmu_to_box(struct intel_uncore_pmu *pmu, int cpu)
102 {
103         unsigned int pkgid = topology_logical_package_id(cpu);
104 
105         /*
106          * The unsigned check also catches the '-1' return value for non
107          * existent mappings in the topology map.
108          */
109         return pkgid < max_packages ? pmu->boxes[pkgid] : NULL;
110 }
111 
112 u64 uncore_msr_read_counter(struct intel_uncore_box *box, struct perf_event *event)
113 {
114         u64 count;
115 
116         rdmsrl(event->hw.event_base, count);
117 
118         return count;
119 }
120 
121 /*
122  * generic get constraint function for shared match/mask registers.
123  */
124 struct event_constraint *
125 uncore_get_constraint(struct intel_uncore_box *box, struct perf_event *event)
126 {
127         struct intel_uncore_extra_reg *er;
128         struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
129         struct hw_perf_event_extra *reg2 = &event->hw.branch_reg;
130         unsigned long flags;
131         bool ok = false;
132 
133         /*
134          * reg->alloc can be set due to existing state, so for fake box we
135          * need to ignore this, otherwise we might fail to allocate proper
136          * fake state for this extra reg constraint.
137          */
138         if (reg1->idx == EXTRA_REG_NONE ||
139             (!uncore_box_is_fake(box) && reg1->alloc))
140                 return NULL;
141 
142         er = &box->shared_regs[reg1->idx];
143         raw_spin_lock_irqsave(&er->lock, flags);
144         if (!atomic_read(&er->ref) ||
145             (er->config1 == reg1->config && er->config2 == reg2->config)) {
146                 atomic_inc(&er->ref);
147                 er->config1 = reg1->config;
148                 er->config2 = reg2->config;
149                 ok = true;
150         }
151         raw_spin_unlock_irqrestore(&er->lock, flags);
152 
153         if (ok) {
154                 if (!uncore_box_is_fake(box))
155                         reg1->alloc = 1;
156                 return NULL;
157         }
158 
159         return &uncore_constraint_empty;
160 }
161 
162 void uncore_put_constraint(struct intel_uncore_box *box, struct perf_event *event)
163 {
164         struct intel_uncore_extra_reg *er;
165         struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
166 
167         /*
168          * Only put constraint if extra reg was actually allocated. Also
169          * takes care of event which do not use an extra shared reg.
170          *
171          * Also, if this is a fake box we shouldn't touch any event state
172          * (reg->alloc) and we don't care about leaving inconsistent box
173          * state either since it will be thrown out.
174          */
175         if (uncore_box_is_fake(box) || !reg1->alloc)
176                 return;
177 
178         er = &box->shared_regs[reg1->idx];
179         atomic_dec(&er->ref);
180         reg1->alloc = 0;
181 }
182 
183 u64 uncore_shared_reg_config(struct intel_uncore_box *box, int idx)
184 {
185         struct intel_uncore_extra_reg *er;
186         unsigned long flags;
187         u64 config;
188 
189         er = &box->shared_regs[idx];
190 
191         raw_spin_lock_irqsave(&er->lock, flags);
192         config = er->config;
193         raw_spin_unlock_irqrestore(&er->lock, flags);
194 
195         return config;
196 }
197 
198 static void uncore_assign_hw_event(struct intel_uncore_box *box,
199                                    struct perf_event *event, int idx)
200 {
201         struct hw_perf_event *hwc = &event->hw;
202 
203         hwc->idx = idx;
204         hwc->last_tag = ++box->tags[idx];
205 
206         if (uncore_pmc_fixed(hwc->idx)) {
207                 hwc->event_base = uncore_fixed_ctr(box);
208                 hwc->config_base = uncore_fixed_ctl(box);
209                 return;
210         }
211 
212         hwc->config_base = uncore_event_ctl(box, hwc->idx);
213         hwc->event_base  = uncore_perf_ctr(box, hwc->idx);
214 }
215 
216 void uncore_perf_event_update(struct intel_uncore_box *box, struct perf_event *event)
217 {
218         u64 prev_count, new_count, delta;
219         int shift;
220 
221         if (uncore_pmc_freerunning(event->hw.idx))
222                 shift = 64 - uncore_freerunning_bits(box, event);
223         else if (uncore_pmc_fixed(event->hw.idx))
224                 shift = 64 - uncore_fixed_ctr_bits(box);
225         else
226                 shift = 64 - uncore_perf_ctr_bits(box);
227 
228         /* the hrtimer might modify the previous event value */
229 again:
230         prev_count = local64_read(&event->hw.prev_count);
231         new_count = uncore_read_counter(box, event);
232         if (local64_xchg(&event->hw.prev_count, new_count) != prev_count)
233                 goto again;
234 
235         delta = (new_count << shift) - (prev_count << shift);
236         delta >>= shift;
237 
238         local64_add(delta, &event->count);
239 }
240 
241 /*
242  * The overflow interrupt is unavailable for SandyBridge-EP, is broken
243  * for SandyBridge. So we use hrtimer to periodically poll the counter
244  * to avoid overflow.
245  */
246 static enum hrtimer_restart uncore_pmu_hrtimer(struct hrtimer *hrtimer)
247 {
248         struct intel_uncore_box *box;
249         struct perf_event *event;
250         unsigned long flags;
251         int bit;
252 
253         box = container_of(hrtimer, struct intel_uncore_box, hrtimer);
254         if (!box->n_active || box->cpu != smp_processor_id())
255                 return HRTIMER_NORESTART;
256         /*
257          * disable local interrupt to prevent uncore_pmu_event_start/stop
258          * to interrupt the update process
259          */
260         local_irq_save(flags);
261 
262         /*
263          * handle boxes with an active event list as opposed to active
264          * counters
265          */
266         list_for_each_entry(event, &box->active_list, active_entry) {
267                 uncore_perf_event_update(box, event);
268         }
269 
270         for_each_set_bit(bit, box->active_mask, UNCORE_PMC_IDX_MAX)
271                 uncore_perf_event_update(box, box->events[bit]);
272 
273         local_irq_restore(flags);
274 
275         hrtimer_forward_now(hrtimer, ns_to_ktime(box->hrtimer_duration));
276         return HRTIMER_RESTART;
277 }
278 
279 void uncore_pmu_start_hrtimer(struct intel_uncore_box *box)
280 {
281         hrtimer_start(&box->hrtimer, ns_to_ktime(box->hrtimer_duration),
282                       HRTIMER_MODE_REL_PINNED);
283 }
284 
285 void uncore_pmu_cancel_hrtimer(struct intel_uncore_box *box)
286 {
287         hrtimer_cancel(&box->hrtimer);
288 }
289 
290 static void uncore_pmu_init_hrtimer(struct intel_uncore_box *box)
291 {
292         hrtimer_init(&box->hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
293         box->hrtimer.function = uncore_pmu_hrtimer;
294 }
295 
296 static struct intel_uncore_box *uncore_alloc_box(struct intel_uncore_type *type,
297                                                  int node)
298 {
299         int i, size, numshared = type->num_shared_regs ;
300         struct intel_uncore_box *box;
301 
302         size = sizeof(*box) + numshared * sizeof(struct intel_uncore_extra_reg);
303 
304         box = kzalloc_node(size, GFP_KERNEL, node);
305         if (!box)
306                 return NULL;
307 
308         for (i = 0; i < numshared; i++)
309                 raw_spin_lock_init(&box->shared_regs[i].lock);
310 
311         uncore_pmu_init_hrtimer(box);
312         box->cpu = -1;
313         box->pci_phys_id = -1;
314         box->pkgid = -1;
315 
316         /* set default hrtimer timeout */
317         box->hrtimer_duration = UNCORE_PMU_HRTIMER_INTERVAL;
318 
319         INIT_LIST_HEAD(&box->active_list);
320 
321         return box;
322 }
323 
324 /*
325  * Using uncore_pmu_event_init pmu event_init callback
326  * as a detection point for uncore events.
327  */
328 static int uncore_pmu_event_init(struct perf_event *event);
329 
330 static bool is_box_event(struct intel_uncore_box *box, struct perf_event *event)
331 {
332         return &box->pmu->pmu == event->pmu;
333 }
334 
335 static int
336 uncore_collect_events(struct intel_uncore_box *box, struct perf_event *leader,
337                       bool dogrp)
338 {
339         struct perf_event *event;
340         int n, max_count;
341 
342         max_count = box->pmu->type->num_counters;
343         if (box->pmu->type->fixed_ctl)
344                 max_count++;
345 
346         if (box->n_events >= max_count)
347                 return -EINVAL;
348 
349         n = box->n_events;
350 
351         if (is_box_event(box, leader)) {
352                 box->event_list[n] = leader;
353                 n++;
354         }
355 
356         if (!dogrp)
357                 return n;
358 
359         for_each_sibling_event(event, leader) {
360                 if (!is_box_event(box, event) ||
361                     event->state <= PERF_EVENT_STATE_OFF)
362                         continue;
363 
364                 if (n >= max_count)
365                         return -EINVAL;
366 
367                 box->event_list[n] = event;
368                 n++;
369         }
370         return n;
371 }
372 
373 static struct event_constraint *
374 uncore_get_event_constraint(struct intel_uncore_box *box, struct perf_event *event)
375 {
376         struct intel_uncore_type *type = box->pmu->type;
377         struct event_constraint *c;
378 
379         if (type->ops->get_constraint) {
380                 c = type->ops->get_constraint(box, event);
381                 if (c)
382                         return c;
383         }
384 
385         if (event->attr.config == UNCORE_FIXED_EVENT)
386                 return &uncore_constraint_fixed;
387 
388         if (type->constraints) {
389                 for_each_event_constraint(c, type->constraints) {
390                         if ((event->hw.config & c->cmask) == c->code)
391                                 return c;
392                 }
393         }
394 
395         return &type->unconstrainted;
396 }
397 
398 static void uncore_put_event_constraint(struct intel_uncore_box *box,
399                                         struct perf_event *event)
400 {
401         if (box->pmu->type->ops->put_constraint)
402                 box->pmu->type->ops->put_constraint(box, event);
403 }
404 
405 static int uncore_assign_events(struct intel_uncore_box *box, int assign[], int n)
406 {
407         unsigned long used_mask[BITS_TO_LONGS(UNCORE_PMC_IDX_MAX)];
408         struct event_constraint *c;
409         int i, wmin, wmax, ret = 0;
410         struct hw_perf_event *hwc;
411 
412         bitmap_zero(used_mask, UNCORE_PMC_IDX_MAX);
413 
414         for (i = 0, wmin = UNCORE_PMC_IDX_MAX, wmax = 0; i < n; i++) {
415                 c = uncore_get_event_constraint(box, box->event_list[i]);
416                 box->event_constraint[i] = c;
417                 wmin = min(wmin, c->weight);
418                 wmax = max(wmax, c->weight);
419         }
420 
421         /* fastpath, try to reuse previous register */
422         for (i = 0; i < n; i++) {
423                 hwc = &box->event_list[i]->hw;
424                 c = box->event_constraint[i];
425 
426                 /* never assigned */
427                 if (hwc->idx == -1)
428                         break;
429 
430                 /* constraint still honored */
431                 if (!test_bit(hwc->idx, c->idxmsk))
432                         break;
433 
434                 /* not already used */
435                 if (test_bit(hwc->idx, used_mask))
436                         break;
437 
438                 __set_bit(hwc->idx, used_mask);
439                 if (assign)
440                         assign[i] = hwc->idx;
441         }
442         /* slow path */
443         if (i != n)
444                 ret = perf_assign_events(box->event_constraint, n,
445                                          wmin, wmax, n, assign);
446 
447         if (!assign || ret) {
448                 for (i = 0; i < n; i++)
449                         uncore_put_event_constraint(box, box->event_list[i]);
450         }
451         return ret ? -EINVAL : 0;
452 }
453 
454 void uncore_pmu_event_start(struct perf_event *event, int flags)
455 {
456         struct intel_uncore_box *box = uncore_event_to_box(event);
457         int idx = event->hw.idx;
458 
459         if (WARN_ON_ONCE(idx == -1 || idx >= UNCORE_PMC_IDX_MAX))
460                 return;
461 
462         /*
463          * Free running counter is read-only and always active.
464          * Use the current counter value as start point.
465          * There is no overflow interrupt for free running counter.
466          * Use hrtimer to periodically poll the counter to avoid overflow.
467          */
468         if (uncore_pmc_freerunning(event->hw.idx)) {
469                 list_add_tail(&event->active_entry, &box->active_list);
470                 local64_set(&event->hw.prev_count,
471                             uncore_read_counter(box, event));
472                 if (box->n_active++ == 0)
473                         uncore_pmu_start_hrtimer(box);
474                 return;
475         }
476 
477         if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
478                 return;
479 
480         event->hw.state = 0;
481         box->events[idx] = event;
482         box->n_active++;
483         __set_bit(idx, box->active_mask);
484 
485         local64_set(&event->hw.prev_count, uncore_read_counter(box, event));
486         uncore_enable_event(box, event);
487 
488         if (box->n_active == 1) {
489                 uncore_enable_box(box);
490                 uncore_pmu_start_hrtimer(box);
491         }
492 }
493 
494 void uncore_pmu_event_stop(struct perf_event *event, int flags)
495 {
496         struct intel_uncore_box *box = uncore_event_to_box(event);
497         struct hw_perf_event *hwc = &event->hw;
498 
499         /* Cannot disable free running counter which is read-only */
500         if (uncore_pmc_freerunning(hwc->idx)) {
501                 list_del(&event->active_entry);
502                 if (--box->n_active == 0)
503                         uncore_pmu_cancel_hrtimer(box);
504                 uncore_perf_event_update(box, event);
505                 return;
506         }
507 
508         if (__test_and_clear_bit(hwc->idx, box->active_mask)) {
509                 uncore_disable_event(box, event);
510                 box->n_active--;
511                 box->events[hwc->idx] = NULL;
512                 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
513                 hwc->state |= PERF_HES_STOPPED;
514 
515                 if (box->n_active == 0) {
516                         uncore_disable_box(box);
517                         uncore_pmu_cancel_hrtimer(box);
518                 }
519         }
520 
521         if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
522                 /*
523                  * Drain the remaining delta count out of a event
524                  * that we are disabling:
525                  */
526                 uncore_perf_event_update(box, event);
527                 hwc->state |= PERF_HES_UPTODATE;
528         }
529 }
530 
531 int uncore_pmu_event_add(struct perf_event *event, int flags)
532 {
533         struct intel_uncore_box *box = uncore_event_to_box(event);
534         struct hw_perf_event *hwc = &event->hw;
535         int assign[UNCORE_PMC_IDX_MAX];
536         int i, n, ret;
537 
538         if (!box)
539                 return -ENODEV;
540 
541         /*
542          * The free funning counter is assigned in event_init().
543          * The free running counter event and free running counter
544          * are 1:1 mapped. It doesn't need to be tracked in event_list.
545          */
546         if (uncore_pmc_freerunning(hwc->idx)) {
547                 if (flags & PERF_EF_START)
548                         uncore_pmu_event_start(event, 0);
549                 return 0;
550         }
551 
552         ret = n = uncore_collect_events(box, event, false);
553         if (ret < 0)
554                 return ret;
555 
556         hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
557         if (!(flags & PERF_EF_START))
558                 hwc->state |= PERF_HES_ARCH;
559 
560         ret = uncore_assign_events(box, assign, n);
561         if (ret)
562                 return ret;
563 
564         /* save events moving to new counters */
565         for (i = 0; i < box->n_events; i++) {
566                 event = box->event_list[i];
567                 hwc = &event->hw;
568 
569                 if (hwc->idx == assign[i] &&
570                         hwc->last_tag == box->tags[assign[i]])
571                         continue;
572                 /*
573                  * Ensure we don't accidentally enable a stopped
574                  * counter simply because we rescheduled.
575                  */
576                 if (hwc->state & PERF_HES_STOPPED)
577                         hwc->state |= PERF_HES_ARCH;
578 
579                 uncore_pmu_event_stop(event, PERF_EF_UPDATE);
580         }
581 
582         /* reprogram moved events into new counters */
583         for (i = 0; i < n; i++) {
584                 event = box->event_list[i];
585                 hwc = &event->hw;
586 
587                 if (hwc->idx != assign[i] ||
588                         hwc->last_tag != box->tags[assign[i]])
589                         uncore_assign_hw_event(box, event, assign[i]);
590                 else if (i < box->n_events)
591                         continue;
592 
593                 if (hwc->state & PERF_HES_ARCH)
594                         continue;
595 
596                 uncore_pmu_event_start(event, 0);
597         }
598         box->n_events = n;
599 
600         return 0;
601 }
602 
603 void uncore_pmu_event_del(struct perf_event *event, int flags)
604 {
605         struct intel_uncore_box *box = uncore_event_to_box(event);
606         int i;
607 
608         uncore_pmu_event_stop(event, PERF_EF_UPDATE);
609 
610         /*
611          * The event for free running counter is not tracked by event_list.
612          * It doesn't need to force event->hw.idx = -1 to reassign the counter.
613          * Because the event and the free running counter are 1:1 mapped.
614          */
615         if (uncore_pmc_freerunning(event->hw.idx))
616                 return;
617 
618         for (i = 0; i < box->n_events; i++) {
619                 if (event == box->event_list[i]) {
620                         uncore_put_event_constraint(box, event);
621 
622                         for (++i; i < box->n_events; i++)
623                                 box->event_list[i - 1] = box->event_list[i];
624 
625                         --box->n_events;
626                         break;
627                 }
628         }
629 
630         event->hw.idx = -1;
631         event->hw.last_tag = ~0ULL;
632 }
633 
634 void uncore_pmu_event_read(struct perf_event *event)
635 {
636         struct intel_uncore_box *box = uncore_event_to_box(event);
637         uncore_perf_event_update(box, event);
638 }
639 
640 /*
641  * validation ensures the group can be loaded onto the
642  * PMU if it was the only group available.
643  */
644 static int uncore_validate_group(struct intel_uncore_pmu *pmu,
645                                 struct perf_event *event)
646 {
647         struct perf_event *leader = event->group_leader;
648         struct intel_uncore_box *fake_box;
649         int ret = -EINVAL, n;
650 
651         /* The free running counter is always active. */
652         if (uncore_pmc_freerunning(event->hw.idx))
653                 return 0;
654 
655         fake_box = uncore_alloc_box(pmu->type, NUMA_NO_NODE);
656         if (!fake_box)
657                 return -ENOMEM;
658 
659         fake_box->pmu = pmu;
660         /*
661          * the event is not yet connected with its
662          * siblings therefore we must first collect
663          * existing siblings, then add the new event
664          * before we can simulate the scheduling
665          */
666         n = uncore_collect_events(fake_box, leader, true);
667         if (n < 0)
668                 goto out;
669 
670         fake_box->n_events = n;
671         n = uncore_collect_events(fake_box, event, false);
672         if (n < 0)
673                 goto out;
674 
675         fake_box->n_events = n;
676 
677         ret = uncore_assign_events(fake_box, NULL, n);
678 out:
679         kfree(fake_box);
680         return ret;
681 }
682 
683 static int uncore_pmu_event_init(struct perf_event *event)
684 {
685         struct intel_uncore_pmu *pmu;
686         struct intel_uncore_box *box;
687         struct hw_perf_event *hwc = &event->hw;
688         int ret;
689 
690         if (event->attr.type != event->pmu->type)
691                 return -ENOENT;
692 
693         pmu = uncore_event_to_pmu(event);
694         /* no device found for this pmu */
695         if (pmu->func_id < 0)
696                 return -ENOENT;
697 
698         /*
699          * Uncore PMU does measure at all privilege level all the time.
700          * So it doesn't make sense to specify any exclude bits.
701          */
702         if (event->attr.exclude_user || event->attr.exclude_kernel ||
703                         event->attr.exclude_hv || event->attr.exclude_idle)
704                 return -EINVAL;
705 
706         /* Sampling not supported yet */
707         if (hwc->sample_period)
708                 return -EINVAL;
709 
710         /*
711          * Place all uncore events for a particular physical package
712          * onto a single cpu
713          */
714         if (event->cpu < 0)
715                 return -EINVAL;
716         box = uncore_pmu_to_box(pmu, event->cpu);
717         if (!box || box->cpu < 0)
718                 return -EINVAL;
719         event->cpu = box->cpu;
720         event->pmu_private = box;
721 
722         event->event_caps |= PERF_EV_CAP_READ_ACTIVE_PKG;
723 
724         event->hw.idx = -1;
725         event->hw.last_tag = ~0ULL;
726         event->hw.extra_reg.idx = EXTRA_REG_NONE;
727         event->hw.branch_reg.idx = EXTRA_REG_NONE;
728 
729         if (event->attr.config == UNCORE_FIXED_EVENT) {
730                 /* no fixed counter */
731                 if (!pmu->type->fixed_ctl)
732                         return -EINVAL;
733                 /*
734                  * if there is only one fixed counter, only the first pmu
735                  * can access the fixed counter
736                  */
737                 if (pmu->type->single_fixed && pmu->pmu_idx > 0)
738                         return -EINVAL;
739 
740                 /* fixed counters have event field hardcoded to zero */
741                 hwc->config = 0ULL;
742         } else if (is_freerunning_event(event)) {
743                 if (!check_valid_freerunning_event(box, event))
744                         return -EINVAL;
745                 event->hw.idx = UNCORE_PMC_IDX_FREERUNNING;
746                 /*
747                  * The free running counter event and free running counter
748                  * are always 1:1 mapped.
749                  * The free running counter is always active.
750                  * Assign the free running counter here.
751                  */
752                 event->hw.event_base = uncore_freerunning_counter(box, event);
753         } else {
754                 hwc->config = event->attr.config &
755                               (pmu->type->event_mask | ((u64)pmu->type->event_mask_ext << 32));
756                 if (pmu->type->ops->hw_config) {
757                         ret = pmu->type->ops->hw_config(box, event);
758                         if (ret)
759                                 return ret;
760                 }
761         }
762 
763         if (event->group_leader != event)
764                 ret = uncore_validate_group(pmu, event);
765         else
766                 ret = 0;
767 
768         return ret;
769 }
770 
771 static ssize_t uncore_get_attr_cpumask(struct device *dev,
772                                 struct device_attribute *attr, char *buf)
773 {
774         return cpumap_print_to_pagebuf(true, buf, &uncore_cpu_mask);
775 }
776 
777 static DEVICE_ATTR(cpumask, S_IRUGO, uncore_get_attr_cpumask, NULL);
778 
779 static struct attribute *uncore_pmu_attrs[] = {
780         &dev_attr_cpumask.attr,
781         NULL,
782 };
783 
784 static const struct attribute_group uncore_pmu_attr_group = {
785         .attrs = uncore_pmu_attrs,
786 };
787 
788 static int uncore_pmu_register(struct intel_uncore_pmu *pmu)
789 {
790         int ret;
791 
792         if (!pmu->type->pmu) {
793                 pmu->pmu = (struct pmu) {
794                         .attr_groups    = pmu->type->attr_groups,
795                         .task_ctx_nr    = perf_invalid_context,
796                         .event_init     = uncore_pmu_event_init,
797                         .add            = uncore_pmu_event_add,
798                         .del            = uncore_pmu_event_del,
799                         .start          = uncore_pmu_event_start,
800                         .stop           = uncore_pmu_event_stop,
801                         .read           = uncore_pmu_event_read,
802                         .module         = THIS_MODULE,
803                 };
804         } else {
805                 pmu->pmu = *pmu->type->pmu;
806                 pmu->pmu.attr_groups = pmu->type->attr_groups;
807         }
808 
809         if (pmu->type->num_boxes == 1) {
810                 if (strlen(pmu->type->name) > 0)
811                         sprintf(pmu->name, "uncore_%s", pmu->type->name);
812                 else
813                         sprintf(pmu->name, "uncore");
814         } else {
815                 sprintf(pmu->name, "uncore_%s_%d", pmu->type->name,
816                         pmu->pmu_idx);
817         }
818 
819         ret = perf_pmu_register(&pmu->pmu, pmu->name, -1);
820         if (!ret)
821                 pmu->registered = true;
822         return ret;
823 }
824 
825 static void uncore_pmu_unregister(struct intel_uncore_pmu *pmu)
826 {
827         if (!pmu->registered)
828                 return;
829         perf_pmu_unregister(&pmu->pmu);
830         pmu->registered = false;
831 }
832 
833 static void uncore_free_boxes(struct intel_uncore_pmu *pmu)
834 {
835         int pkg;
836 
837         for (pkg = 0; pkg < max_packages; pkg++)
838                 kfree(pmu->boxes[pkg]);
839         kfree(pmu->boxes);
840 }
841 
842 static void uncore_type_exit(struct intel_uncore_type *type)
843 {
844         struct intel_uncore_pmu *pmu = type->pmus;
845         int i;
846 
847         if (pmu) {
848                 for (i = 0; i < type->num_boxes; i++, pmu++) {
849                         uncore_pmu_unregister(pmu);
850                         uncore_free_boxes(pmu);
851                 }
852                 kfree(type->pmus);
853                 type->pmus = NULL;
854         }
855         kfree(type->events_group);
856         type->events_group = NULL;
857 }
858 
859 static void uncore_types_exit(struct intel_uncore_type **types)
860 {
861         for (; *types; types++)
862                 uncore_type_exit(*types);
863 }
864 
865 static int __init uncore_type_init(struct intel_uncore_type *type, bool setid)
866 {
867         struct intel_uncore_pmu *pmus;
868         size_t size;
869         int i, j;
870 
871         pmus = kcalloc(type->num_boxes, sizeof(*pmus), GFP_KERNEL);
872         if (!pmus)
873                 return -ENOMEM;
874 
875         size = max_packages * sizeof(struct intel_uncore_box *);
876 
877         for (i = 0; i < type->num_boxes; i++) {
878                 pmus[i].func_id = setid ? i : -1;
879                 pmus[i].pmu_idx = i;
880                 pmus[i].type    = type;
881                 pmus[i].boxes   = kzalloc(size, GFP_KERNEL);
882                 if (!pmus[i].boxes)
883                         goto err;
884         }
885 
886         type->pmus = pmus;
887         type->unconstrainted = (struct event_constraint)
888                 __EVENT_CONSTRAINT(0, (1ULL << type->num_counters) - 1,
889                                 0, type->num_counters, 0, 0);
890 
891         if (type->event_descs) {
892                 struct {
893                         struct attribute_group group;
894                         struct attribute *attrs[];
895                 } *attr_group;
896                 for (i = 0; type->event_descs[i].attr.attr.name; i++);
897 
898                 attr_group = kzalloc(struct_size(attr_group, attrs, i + 1),
899                                                                 GFP_KERNEL);
900                 if (!attr_group)
901                         goto err;
902 
903                 attr_group->group.name = "events";
904                 attr_group->group.attrs = attr_group->attrs;
905 
906                 for (j = 0; j < i; j++)
907                         attr_group->attrs[j] = &type->event_descs[j].attr.attr;
908 
909                 type->events_group = &attr_group->group;
910         }
911 
912         type->pmu_group = &uncore_pmu_attr_group;
913 
914         return 0;
915 
916 err:
917         for (i = 0; i < type->num_boxes; i++)
918                 kfree(pmus[i].boxes);
919         kfree(pmus);
920 
921         return -ENOMEM;
922 }
923 
924 static int __init
925 uncore_types_init(struct intel_uncore_type **types, bool setid)
926 {
927         int ret;
928 
929         for (; *types; types++) {
930                 ret = uncore_type_init(*types, setid);
931                 if (ret)
932                         return ret;
933         }
934         return 0;
935 }
936 
937 /*
938  * add a pci uncore device
939  */
940 static int uncore_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
941 {
942         struct intel_uncore_type *type;
943         struct intel_uncore_pmu *pmu = NULL;
944         struct intel_uncore_box *box;
945         int phys_id, pkg, ret;
946 
947         phys_id = uncore_pcibus_to_physid(pdev->bus);
948         if (phys_id < 0)
949                 return -ENODEV;
950 
951         pkg = topology_phys_to_logical_pkg(phys_id);
952         if (pkg < 0)
953                 return -EINVAL;
954 
955         if (UNCORE_PCI_DEV_TYPE(id->driver_data) == UNCORE_EXTRA_PCI_DEV) {
956                 int idx = UNCORE_PCI_DEV_IDX(id->driver_data);
957 
958                 uncore_extra_pci_dev[pkg].dev[idx] = pdev;
959                 pci_set_drvdata(pdev, NULL);
960                 return 0;
961         }
962 
963         type = uncore_pci_uncores[UNCORE_PCI_DEV_TYPE(id->driver_data)];
964 
965         /*
966          * Some platforms, e.g.  Knights Landing, use a common PCI device ID
967          * for multiple instances of an uncore PMU device type. We should check
968          * PCI slot and func to indicate the uncore box.
969          */
970         if (id->driver_data & ~0xffff) {
971                 struct pci_driver *pci_drv = pdev->driver;
972                 const struct pci_device_id *ids = pci_drv->id_table;
973                 unsigned int devfn;
974 
975                 while (ids && ids->vendor) {
976                         if ((ids->vendor == pdev->vendor) &&
977                             (ids->device == pdev->device)) {
978                                 devfn = PCI_DEVFN(UNCORE_PCI_DEV_DEV(ids->driver_data),
979                                                   UNCORE_PCI_DEV_FUNC(ids->driver_data));
980                                 if (devfn == pdev->devfn) {
981                                         pmu = &type->pmus[UNCORE_PCI_DEV_IDX(ids->driver_data)];
982                                         break;
983                                 }
984                         }
985                         ids++;
986                 }
987                 if (pmu == NULL)
988                         return -ENODEV;
989         } else {
990                 /*
991                  * for performance monitoring unit with multiple boxes,
992                  * each box has a different function id.
993                  */
994                 pmu = &type->pmus[UNCORE_PCI_DEV_IDX(id->driver_data)];
995         }
996 
997         if (WARN_ON_ONCE(pmu->boxes[pkg] != NULL))
998                 return -EINVAL;
999 
1000         box = uncore_alloc_box(type, NUMA_NO_NODE);
1001         if (!box)
1002                 return -ENOMEM;
1003 
1004         if (pmu->func_id < 0)
1005                 pmu->func_id = pdev->devfn;
1006         else
1007                 WARN_ON_ONCE(pmu->func_id != pdev->devfn);
1008 
1009         atomic_inc(&box->refcnt);
1010         box->pci_phys_id = phys_id;
1011         box->pkgid = pkg;
1012         box->pci_dev = pdev;
1013         box->pmu = pmu;
1014         uncore_box_init(box);
1015         pci_set_drvdata(pdev, box);
1016 
1017         pmu->boxes[pkg] = box;
1018         if (atomic_inc_return(&pmu->activeboxes) > 1)
1019                 return 0;
1020 
1021         /* First active box registers the pmu */
1022         ret = uncore_pmu_register(pmu);
1023         if (ret) {
1024                 pci_set_drvdata(pdev, NULL);
1025                 pmu->boxes[pkg] = NULL;
1026                 uncore_box_exit(box);
1027                 kfree(box);
1028         }
1029         return ret;
1030 }
1031 
1032 static void uncore_pci_remove(struct pci_dev *pdev)
1033 {
1034         struct intel_uncore_box *box;
1035         struct intel_uncore_pmu *pmu;
1036         int i, phys_id, pkg;
1037 
1038         phys_id = uncore_pcibus_to_physid(pdev->bus);
1039 
1040         box = pci_get_drvdata(pdev);
1041         if (!box) {
1042                 pkg = topology_phys_to_logical_pkg(phys_id);
1043                 for (i = 0; i < UNCORE_EXTRA_PCI_DEV_MAX; i++) {
1044                         if (uncore_extra_pci_dev[pkg].dev[i] == pdev) {
1045                                 uncore_extra_pci_dev[pkg].dev[i] = NULL;
1046                                 break;
1047                         }
1048                 }
1049                 WARN_ON_ONCE(i >= UNCORE_EXTRA_PCI_DEV_MAX);
1050                 return;
1051         }
1052 
1053         pmu = box->pmu;
1054         if (WARN_ON_ONCE(phys_id != box->pci_phys_id))
1055                 return;
1056 
1057         pci_set_drvdata(pdev, NULL);
1058         pmu->boxes[box->pkgid] = NULL;
1059         if (atomic_dec_return(&pmu->activeboxes) == 0)
1060                 uncore_pmu_unregister(pmu);
1061         uncore_box_exit(box);
1062         kfree(box);
1063 }
1064 
1065 static int __init uncore_pci_init(void)
1066 {
1067         size_t size;
1068         int ret;
1069 
1070         size = max_packages * sizeof(struct pci_extra_dev);
1071         uncore_extra_pci_dev = kzalloc(size, GFP_KERNEL);
1072         if (!uncore_extra_pci_dev) {
1073                 ret = -ENOMEM;
1074                 goto err;
1075         }
1076 
1077         ret = uncore_types_init(uncore_pci_uncores, false);
1078         if (ret)
1079                 goto errtype;
1080 
1081         uncore_pci_driver->probe = uncore_pci_probe;
1082         uncore_pci_driver->remove = uncore_pci_remove;
1083 
1084         ret = pci_register_driver(uncore_pci_driver);
1085         if (ret)
1086                 goto errtype;
1087 
1088         pcidrv_registered = true;
1089         return 0;
1090 
1091 errtype:
1092         uncore_types_exit(uncore_pci_uncores);
1093         kfree(uncore_extra_pci_dev);
1094         uncore_extra_pci_dev = NULL;
1095         uncore_free_pcibus_map();
1096 err:
1097         uncore_pci_uncores = empty_uncore;
1098         return ret;
1099 }
1100 
1101 static void uncore_pci_exit(void)
1102 {
1103         if (pcidrv_registered) {
1104                 pcidrv_registered = false;
1105                 pci_unregister_driver(uncore_pci_driver);
1106                 uncore_types_exit(uncore_pci_uncores);
1107                 kfree(uncore_extra_pci_dev);
1108                 uncore_free_pcibus_map();
1109         }
1110 }
1111 
1112 static void uncore_change_type_ctx(struct intel_uncore_type *type, int old_cpu,
1113                                    int new_cpu)
1114 {
1115         struct intel_uncore_pmu *pmu = type->pmus;
1116         struct intel_uncore_box *box;
1117         int i, pkg;
1118 
1119         pkg = topology_logical_package_id(old_cpu < 0 ? new_cpu : old_cpu);
1120         for (i = 0; i < type->num_boxes; i++, pmu++) {
1121                 box = pmu->boxes[pkg];
1122                 if (!box)
1123                         continue;
1124 
1125                 if (old_cpu < 0) {
1126                         WARN_ON_ONCE(box->cpu != -1);
1127                         box->cpu = new_cpu;
1128                         continue;
1129                 }
1130 
1131                 WARN_ON_ONCE(box->cpu != old_cpu);
1132                 box->cpu = -1;
1133                 if (new_cpu < 0)
1134                         continue;
1135 
1136                 uncore_pmu_cancel_hrtimer(box);
1137                 perf_pmu_migrate_context(&pmu->pmu, old_cpu, new_cpu);
1138                 box->cpu = new_cpu;
1139         }
1140 }
1141 
1142 static void uncore_change_context(struct intel_uncore_type **uncores,
1143                                   int old_cpu, int new_cpu)
1144 {
1145         for (; *uncores; uncores++)
1146                 uncore_change_type_ctx(*uncores, old_cpu, new_cpu);
1147 }
1148 
1149 static int uncore_event_cpu_offline(unsigned int cpu)
1150 {
1151         struct intel_uncore_type *type, **types = uncore_msr_uncores;
1152         struct intel_uncore_pmu *pmu;
1153         struct intel_uncore_box *box;
1154         int i, pkg, target;
1155 
1156         /* Check if exiting cpu is used for collecting uncore events */
1157         if (!cpumask_test_and_clear_cpu(cpu, &uncore_cpu_mask))
1158                 goto unref;
1159         /* Find a new cpu to collect uncore events */
1160         target = cpumask_any_but(topology_core_cpumask(cpu), cpu);
1161 
1162         /* Migrate uncore events to the new target */
1163         if (target < nr_cpu_ids)
1164                 cpumask_set_cpu(target, &uncore_cpu_mask);
1165         else
1166                 target = -1;
1167 
1168         uncore_change_context(uncore_msr_uncores, cpu, target);
1169         uncore_change_context(uncore_pci_uncores, cpu, target);
1170 
1171 unref:
1172         /* Clear the references */
1173         pkg = topology_logical_package_id(cpu);
1174         for (; *types; types++) {
1175                 type = *types;
1176                 pmu = type->pmus;
1177                 for (i = 0; i < type->num_boxes; i++, pmu++) {
1178                         box = pmu->boxes[pkg];
1179                         if (box && atomic_dec_return(&box->refcnt) == 0)
1180                                 uncore_box_exit(box);
1181                 }
1182         }
1183         return 0;
1184 }
1185 
1186 static int allocate_boxes(struct intel_uncore_type **types,
1187                          unsigned int pkg, unsigned int cpu)
1188 {
1189         struct intel_uncore_box *box, *tmp;
1190         struct intel_uncore_type *type;
1191         struct intel_uncore_pmu *pmu;
1192         LIST_HEAD(allocated);
1193         int i;
1194 
1195         /* Try to allocate all required boxes */
1196         for (; *types; types++) {
1197                 type = *types;
1198                 pmu = type->pmus;
1199                 for (i = 0; i < type->num_boxes; i++, pmu++) {
1200                         if (pmu->boxes[pkg])
1201                                 continue;
1202                         box = uncore_alloc_box(type, cpu_to_node(cpu));
1203                         if (!box)
1204                                 goto cleanup;
1205                         box->pmu = pmu;
1206                         box->pkgid = pkg;
1207                         list_add(&box->active_list, &allocated);
1208                 }
1209         }
1210         /* Install them in the pmus */
1211         list_for_each_entry_safe(box, tmp, &allocated, active_list) {
1212                 list_del_init(&box->active_list);
1213                 box->pmu->boxes[pkg] = box;
1214         }
1215         return 0;
1216 
1217 cleanup:
1218         list_for_each_entry_safe(box, tmp, &allocated, active_list) {
1219                 list_del_init(&box->active_list);
1220                 kfree(box);
1221         }
1222         return -ENOMEM;
1223 }
1224 
1225 static int uncore_event_cpu_online(unsigned int cpu)
1226 {
1227         struct intel_uncore_type *type, **types = uncore_msr_uncores;
1228         struct intel_uncore_pmu *pmu;
1229         struct intel_uncore_box *box;
1230         int i, ret, pkg, target;
1231 
1232         pkg = topology_logical_package_id(cpu);
1233         ret = allocate_boxes(types, pkg, cpu);
1234         if (ret)
1235                 return ret;
1236 
1237         for (; *types; types++) {
1238                 type = *types;
1239                 pmu = type->pmus;
1240                 for (i = 0; i < type->num_boxes; i++, pmu++) {
1241                         box = pmu->boxes[pkg];
1242                         if (box && atomic_inc_return(&box->refcnt) == 1)
1243                                 uncore_box_init(box);
1244                 }
1245         }
1246 
1247         /*
1248          * Check if there is an online cpu in the package
1249          * which collects uncore events already.
1250          */
1251         target = cpumask_any_and(&uncore_cpu_mask, topology_core_cpumask(cpu));
1252         if (target < nr_cpu_ids)
1253                 return 0;
1254 
1255         cpumask_set_cpu(cpu, &uncore_cpu_mask);
1256 
1257         uncore_change_context(uncore_msr_uncores, -1, cpu);
1258         uncore_change_context(uncore_pci_uncores, -1, cpu);
1259         return 0;
1260 }
1261 
1262 static int __init type_pmu_register(struct intel_uncore_type *type)
1263 {
1264         int i, ret;
1265 
1266         for (i = 0; i < type->num_boxes; i++) {
1267                 ret = uncore_pmu_register(&type->pmus[i]);
1268                 if (ret)
1269                         return ret;
1270         }
1271         return 0;
1272 }
1273 
1274 static int __init uncore_msr_pmus_register(void)
1275 {
1276         struct intel_uncore_type **types = uncore_msr_uncores;
1277         int ret;
1278 
1279         for (; *types; types++) {
1280                 ret = type_pmu_register(*types);
1281                 if (ret)
1282                         return ret;
1283         }
1284         return 0;
1285 }
1286 
1287 static int __init uncore_cpu_init(void)
1288 {
1289         int ret;
1290 
1291         ret = uncore_types_init(uncore_msr_uncores, true);
1292         if (ret)
1293                 goto err;
1294 
1295         ret = uncore_msr_pmus_register();
1296         if (ret)
1297                 goto err;
1298         return 0;
1299 err:
1300         uncore_types_exit(uncore_msr_uncores);
1301         uncore_msr_uncores = empty_uncore;
1302         return ret;
1303 }
1304 
1305 #define X86_UNCORE_MODEL_MATCH(model, init)     \
1306         { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)&init }
1307 
1308 struct intel_uncore_init_fun {
1309         void    (*cpu_init)(void);
1310         int     (*pci_init)(void);
1311 };
1312 
1313 static const struct intel_uncore_init_fun nhm_uncore_init __initconst = {
1314         .cpu_init = nhm_uncore_cpu_init,
1315 };
1316 
1317 static const struct intel_uncore_init_fun snb_uncore_init __initconst = {
1318         .cpu_init = snb_uncore_cpu_init,
1319         .pci_init = snb_uncore_pci_init,
1320 };
1321 
1322 static const struct intel_uncore_init_fun ivb_uncore_init __initconst = {
1323         .cpu_init = snb_uncore_cpu_init,
1324         .pci_init = ivb_uncore_pci_init,
1325 };
1326 
1327 static const struct intel_uncore_init_fun hsw_uncore_init __initconst = {
1328         .cpu_init = snb_uncore_cpu_init,
1329         .pci_init = hsw_uncore_pci_init,
1330 };
1331 
1332 static const struct intel_uncore_init_fun bdw_uncore_init __initconst = {
1333         .cpu_init = snb_uncore_cpu_init,
1334         .pci_init = bdw_uncore_pci_init,
1335 };
1336 
1337 static const struct intel_uncore_init_fun snbep_uncore_init __initconst = {
1338         .cpu_init = snbep_uncore_cpu_init,
1339         .pci_init = snbep_uncore_pci_init,
1340 };
1341 
1342 static const struct intel_uncore_init_fun nhmex_uncore_init __initconst = {
1343         .cpu_init = nhmex_uncore_cpu_init,
1344 };
1345 
1346 static const struct intel_uncore_init_fun ivbep_uncore_init __initconst = {
1347         .cpu_init = ivbep_uncore_cpu_init,
1348         .pci_init = ivbep_uncore_pci_init,
1349 };
1350 
1351 static const struct intel_uncore_init_fun hswep_uncore_init __initconst = {
1352         .cpu_init = hswep_uncore_cpu_init,
1353         .pci_init = hswep_uncore_pci_init,
1354 };
1355 
1356 static const struct intel_uncore_init_fun bdx_uncore_init __initconst = {
1357         .cpu_init = bdx_uncore_cpu_init,
1358         .pci_init = bdx_uncore_pci_init,
1359 };
1360 
1361 static const struct intel_uncore_init_fun knl_uncore_init __initconst = {
1362         .cpu_init = knl_uncore_cpu_init,
1363         .pci_init = knl_uncore_pci_init,
1364 };
1365 
1366 static const struct intel_uncore_init_fun skl_uncore_init __initconst = {
1367         .cpu_init = skl_uncore_cpu_init,
1368         .pci_init = skl_uncore_pci_init,
1369 };
1370 
1371 static const struct intel_uncore_init_fun skx_uncore_init __initconst = {
1372         .cpu_init = skx_uncore_cpu_init,
1373         .pci_init = skx_uncore_pci_init,
1374 };
1375 
1376 static const struct x86_cpu_id intel_uncore_match[] __initconst = {
1377         X86_UNCORE_MODEL_MATCH(INTEL_FAM6_NEHALEM_EP,     nhm_uncore_init),
1378         X86_UNCORE_MODEL_MATCH(INTEL_FAM6_NEHALEM,        nhm_uncore_init),
1379         X86_UNCORE_MODEL_MATCH(INTEL_FAM6_WESTMERE,       nhm_uncore_init),
1380         X86_UNCORE_MODEL_MATCH(INTEL_FAM6_WESTMERE_EP,    nhm_uncore_init),
1381         X86_UNCORE_MODEL_MATCH(INTEL_FAM6_SANDYBRIDGE,    snb_uncore_init),
1382         X86_UNCORE_MODEL_MATCH(INTEL_FAM6_IVYBRIDGE,      ivb_uncore_init),
1383         X86_UNCORE_MODEL_MATCH(INTEL_FAM6_HASWELL_CORE,   hsw_uncore_init),
1384         X86_UNCORE_MODEL_MATCH(INTEL_FAM6_HASWELL_ULT,    hsw_uncore_init),
1385         X86_UNCORE_MODEL_MATCH(INTEL_FAM6_HASWELL_GT3E,   hsw_uncore_init),
1386         X86_UNCORE_MODEL_MATCH(INTEL_FAM6_BROADWELL_CORE, bdw_uncore_init),
1387         X86_UNCORE_MODEL_MATCH(INTEL_FAM6_BROADWELL_GT3E, bdw_uncore_init),
1388         X86_UNCORE_MODEL_MATCH(INTEL_FAM6_SANDYBRIDGE_X,  snbep_uncore_init),
1389         X86_UNCORE_MODEL_MATCH(INTEL_FAM6_NEHALEM_EX,     nhmex_uncore_init),
1390         X86_UNCORE_MODEL_MATCH(INTEL_FAM6_WESTMERE_EX,    nhmex_uncore_init),
1391         X86_UNCORE_MODEL_MATCH(INTEL_FAM6_IVYBRIDGE_X,    ivbep_uncore_init),
1392         X86_UNCORE_MODEL_MATCH(INTEL_FAM6_HASWELL_X,      hswep_uncore_init),
1393         X86_UNCORE_MODEL_MATCH(INTEL_FAM6_BROADWELL_X,    bdx_uncore_init),
1394         X86_UNCORE_MODEL_MATCH(INTEL_FAM6_BROADWELL_XEON_D, bdx_uncore_init),
1395         X86_UNCORE_MODEL_MATCH(INTEL_FAM6_XEON_PHI_KNL,   knl_uncore_init),
1396         X86_UNCORE_MODEL_MATCH(INTEL_FAM6_XEON_PHI_KNM,   knl_uncore_init),
1397         X86_UNCORE_MODEL_MATCH(INTEL_FAM6_SKYLAKE_DESKTOP,skl_uncore_init),
1398         X86_UNCORE_MODEL_MATCH(INTEL_FAM6_SKYLAKE_MOBILE, skl_uncore_init),
1399         X86_UNCORE_MODEL_MATCH(INTEL_FAM6_SKYLAKE_X,      skx_uncore_init),
1400         X86_UNCORE_MODEL_MATCH(INTEL_FAM6_KABYLAKE_MOBILE, skl_uncore_init),
1401         X86_UNCORE_MODEL_MATCH(INTEL_FAM6_KABYLAKE_DESKTOP, skl_uncore_init),
1402         {},
1403 };
1404 
1405 MODULE_DEVICE_TABLE(x86cpu, intel_uncore_match);
1406 
1407 static int __init intel_uncore_init(void)
1408 {
1409         const struct x86_cpu_id *id;
1410         struct intel_uncore_init_fun *uncore_init;
1411         int pret = 0, cret = 0, ret;
1412 
1413         id = x86_match_cpu(intel_uncore_match);
1414         if (!id)
1415                 return -ENODEV;
1416 
1417         if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
1418                 return -ENODEV;
1419 
1420         max_packages = topology_max_packages();
1421 
1422         uncore_init = (struct intel_uncore_init_fun *)id->driver_data;
1423         if (uncore_init->pci_init) {
1424                 pret = uncore_init->pci_init();
1425                 if (!pret)
1426                         pret = uncore_pci_init();
1427         }
1428 
1429         if (uncore_init->cpu_init) {
1430                 uncore_init->cpu_init();
1431                 cret = uncore_cpu_init();
1432         }
1433 
1434         if (cret && pret)
1435                 return -ENODEV;
1436 
1437         /* Install hotplug callbacks to setup the targets for each package */
1438         ret = cpuhp_setup_state(CPUHP_AP_PERF_X86_UNCORE_ONLINE,
1439                                 "perf/x86/intel/uncore:online",
1440                                 uncore_event_cpu_online,
1441                                 uncore_event_cpu_offline);
1442         if (ret)
1443                 goto err;
1444         return 0;
1445 
1446 err:
1447         uncore_types_exit(uncore_msr_uncores);
1448         uncore_pci_exit();
1449         return ret;
1450 }
1451 module_init(intel_uncore_init);
1452 
1453 static void __exit intel_uncore_exit(void)
1454 {
1455         cpuhp_remove_state(CPUHP_AP_PERF_X86_UNCORE_ONLINE);
1456         uncore_types_exit(uncore_msr_uncores);
1457         uncore_pci_exit();
1458 }
1459 module_exit(intel_uncore_exit);
1460 

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