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Linux/arch/x86/include/asm/amd_nb.h

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  1 #ifndef _ASM_X86_AMD_NB_H
  2 #define _ASM_X86_AMD_NB_H
  3 
  4 #include <linux/ioport.h>
  5 #include <linux/pci.h>
  6 
  7 struct amd_nb_bus_dev_range {
  8         u8 bus;
  9         u8 dev_base;
 10         u8 dev_limit;
 11 };
 12 
 13 extern const struct pci_device_id amd_nb_misc_ids[];
 14 extern const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[];
 15 
 16 extern bool early_is_amd_nb(u32 value);
 17 extern struct resource *amd_get_mmconfig_range(struct resource *res);
 18 extern int amd_cache_northbridges(void);
 19 extern void amd_flush_garts(void);
 20 extern int amd_numa_init(void);
 21 extern int amd_get_subcaches(int);
 22 extern int amd_set_subcaches(int, unsigned long);
 23 
 24 extern int amd_smn_read(u16 node, u32 address, u32 *value);
 25 extern int amd_smn_write(u16 node, u32 address, u32 value);
 26 extern int amd_df_indirect_read(u16 node, u8 func, u16 reg, u8 instance_id, u32 *lo);
 27 
 28 struct amd_l3_cache {
 29         unsigned indices;
 30         u8       subcaches[4];
 31 };
 32 
 33 struct threshold_block {
 34         unsigned int     block;                 /* Number within bank */
 35         unsigned int     bank;                  /* MCA bank the block belongs to */
 36         unsigned int     cpu;                   /* CPU which controls MCA bank */
 37         u32              address;               /* MSR address for the block */
 38         u16              interrupt_enable;      /* Enable/Disable APIC interrupt */
 39         bool             interrupt_capable;     /* Bank can generate an interrupt. */
 40 
 41         u16              threshold_limit;       /*
 42                                                  * Value upon which threshold
 43                                                  * interrupt is generated.
 44                                                  */
 45 
 46         struct kobject   kobj;                  /* sysfs object */
 47         struct list_head miscj;                 /*
 48                                                  * List of threshold blocks
 49                                                  * within a bank.
 50                                                  */
 51 };
 52 
 53 struct threshold_bank {
 54         struct kobject          *kobj;
 55         struct threshold_block  *blocks;
 56 
 57         /* initialized to the number of CPUs on the node sharing this bank */
 58         atomic_t                cpus;
 59 };
 60 
 61 struct amd_northbridge {
 62         struct pci_dev *root;
 63         struct pci_dev *misc;
 64         struct pci_dev *link;
 65         struct amd_l3_cache l3_cache;
 66         struct threshold_bank *bank4;
 67 };
 68 
 69 struct amd_northbridge_info {
 70         u16 num;
 71         u64 flags;
 72         struct amd_northbridge *nb;
 73 };
 74 
 75 #define AMD_NB_GART                     BIT(0)
 76 #define AMD_NB_L3_INDEX_DISABLE         BIT(1)
 77 #define AMD_NB_L3_PARTITIONING          BIT(2)
 78 
 79 #ifdef CONFIG_AMD_NB
 80 
 81 u16 amd_nb_num(void);
 82 bool amd_nb_has_feature(unsigned int feature);
 83 struct amd_northbridge *node_to_amd_nb(int node);
 84 
 85 static inline u16 amd_pci_dev_to_node_id(struct pci_dev *pdev)
 86 {
 87         struct pci_dev *misc;
 88         int i;
 89 
 90         for (i = 0; i != amd_nb_num(); i++) {
 91                 misc = node_to_amd_nb(i)->misc;
 92 
 93                 if (pci_domain_nr(misc->bus) == pci_domain_nr(pdev->bus) &&
 94                     PCI_SLOT(misc->devfn) == PCI_SLOT(pdev->devfn))
 95                         return i;
 96         }
 97 
 98         WARN(1, "Unable to find AMD Northbridge id for %s\n", pci_name(pdev));
 99         return 0;
100 }
101 
102 static inline bool amd_gart_present(void)
103 {
104         /* GART present only on Fam15h, upto model 0fh */
105         if (boot_cpu_data.x86 == 0xf || boot_cpu_data.x86 == 0x10 ||
106             (boot_cpu_data.x86 == 0x15 && boot_cpu_data.x86_model < 0x10))
107                 return true;
108 
109         return false;
110 }
111 
112 #else
113 
114 #define amd_nb_num(x)           0
115 #define amd_nb_has_feature(x)   false
116 #define node_to_amd_nb(x)       NULL
117 #define amd_gart_present(x)     false
118 
119 #endif
120 
121 
122 #endif /* _ASM_X86_AMD_NB_H */
123 

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