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Linux/arch/x86/include/asm/apic.h

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  1 #ifndef _ASM_X86_APIC_H
  2 #define _ASM_X86_APIC_H
  3 
  4 #include <linux/cpumask.h>
  5 
  6 #include <asm/alternative.h>
  7 #include <asm/cpufeature.h>
  8 #include <asm/apicdef.h>
  9 #include <linux/atomic.h>
 10 #include <asm/fixmap.h>
 11 #include <asm/mpspec.h>
 12 #include <asm/msr.h>
 13 #include <asm/hardirq.h>
 14 
 15 #define ARCH_APICTIMER_STOPS_ON_C3      1
 16 
 17 /*
 18  * Debugging macros
 19  */
 20 #define APIC_QUIET   0
 21 #define APIC_VERBOSE 1
 22 #define APIC_DEBUG   2
 23 
 24 /* Macros for apic_extnmi which controls external NMI masking */
 25 #define APIC_EXTNMI_BSP         0 /* Default */
 26 #define APIC_EXTNMI_ALL         1
 27 #define APIC_EXTNMI_NONE        2
 28 
 29 /*
 30  * Define the default level of output to be very little
 31  * This can be turned up by using apic=verbose for more
 32  * information and apic=debug for _lots_ of information.
 33  * apic_verbosity is defined in apic.c
 34  */
 35 #define apic_printk(v, s, a...) do {       \
 36                 if ((v) <= apic_verbosity) \
 37                         printk(s, ##a);    \
 38         } while (0)
 39 
 40 
 41 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
 42 extern void generic_apic_probe(void);
 43 #else
 44 static inline void generic_apic_probe(void)
 45 {
 46 }
 47 #endif
 48 
 49 #ifdef CONFIG_X86_LOCAL_APIC
 50 
 51 extern unsigned int apic_verbosity;
 52 extern int local_apic_timer_c2_ok;
 53 
 54 extern int disable_apic;
 55 extern unsigned int lapic_timer_frequency;
 56 
 57 extern enum apic_intr_mode_id apic_intr_mode;
 58 enum apic_intr_mode_id {
 59         APIC_PIC,
 60         APIC_VIRTUAL_WIRE,
 61         APIC_VIRTUAL_WIRE_NO_CONFIG,
 62         APIC_SYMMETRIC_IO,
 63         APIC_SYMMETRIC_IO_NO_ROUTING
 64 };
 65 
 66 #ifdef CONFIG_SMP
 67 extern void __inquire_remote_apic(int apicid);
 68 #else /* CONFIG_SMP */
 69 static inline void __inquire_remote_apic(int apicid)
 70 {
 71 }
 72 #endif /* CONFIG_SMP */
 73 
 74 static inline void default_inquire_remote_apic(int apicid)
 75 {
 76         if (apic_verbosity >= APIC_DEBUG)
 77                 __inquire_remote_apic(apicid);
 78 }
 79 
 80 /*
 81  * With 82489DX we can't rely on apic feature bit
 82  * retrieved via cpuid but still have to deal with
 83  * such an apic chip so we assume that SMP configuration
 84  * is found from MP table (64bit case uses ACPI mostly
 85  * which set smp presence flag as well so we are safe
 86  * to use this helper too).
 87  */
 88 static inline bool apic_from_smp_config(void)
 89 {
 90         return smp_found_config && !disable_apic;
 91 }
 92 
 93 /*
 94  * Basic functions accessing APICs.
 95  */
 96 #ifdef CONFIG_PARAVIRT
 97 #include <asm/paravirt.h>
 98 #endif
 99 
100 extern int setup_profiling_timer(unsigned int);
101 
102 static inline void native_apic_mem_write(u32 reg, u32 v)
103 {
104         volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);
105 
106         alternative_io("movl %0, %P1", "xchgl %0, %P1", X86_BUG_11AP,
107                        ASM_OUTPUT2("=r" (v), "=m" (*addr)),
108                        ASM_OUTPUT2("" (v), "m" (*addr)));
109 }
110 
111 static inline u32 native_apic_mem_read(u32 reg)
112 {
113         return *((volatile u32 *)(APIC_BASE + reg));
114 }
115 
116 extern void native_apic_wait_icr_idle(void);
117 extern u32 native_safe_apic_wait_icr_idle(void);
118 extern void native_apic_icr_write(u32 low, u32 id);
119 extern u64 native_apic_icr_read(void);
120 
121 static inline bool apic_is_x2apic_enabled(void)
122 {
123         u64 msr;
124 
125         if (rdmsrl_safe(MSR_IA32_APICBASE, &msr))
126                 return false;
127         return msr & X2APIC_ENABLE;
128 }
129 
130 extern void enable_IR_x2apic(void);
131 
132 extern int get_physical_broadcast(void);
133 
134 extern int lapic_get_maxlvt(void);
135 extern void clear_local_APIC(void);
136 extern void disconnect_bsp_APIC(int virt_wire_setup);
137 extern void disable_local_APIC(void);
138 extern void lapic_shutdown(void);
139 extern void sync_Arb_IDs(void);
140 extern void init_bsp_APIC(void);
141 extern void apic_intr_mode_init(void);
142 extern void init_apic_mappings(void);
143 void register_lapic_address(unsigned long address);
144 extern void setup_boot_APIC_clock(void);
145 extern void setup_secondary_APIC_clock(void);
146 extern void lapic_update_tsc_freq(void);
147 
148 #ifdef CONFIG_X86_64
149 static inline int apic_force_enable(unsigned long addr)
150 {
151         return -1;
152 }
153 #else
154 extern int apic_force_enable(unsigned long addr);
155 #endif
156 
157 extern void apic_bsp_setup(bool upmode);
158 extern void apic_ap_setup(void);
159 
160 /*
161  * On 32bit this is mach-xxx local
162  */
163 #ifdef CONFIG_X86_64
164 extern int apic_is_clustered_box(void);
165 #else
166 static inline int apic_is_clustered_box(void)
167 {
168         return 0;
169 }
170 #endif
171 
172 extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask);
173 extern void lapic_assign_system_vectors(void);
174 extern void lapic_assign_legacy_vector(unsigned int isairq, bool replace);
175 extern void lapic_online(void);
176 extern void lapic_offline(void);
177 
178 #else /* !CONFIG_X86_LOCAL_APIC */
179 static inline void lapic_shutdown(void) { }
180 #define local_apic_timer_c2_ok          1
181 static inline void init_apic_mappings(void) { }
182 static inline void disable_local_APIC(void) { }
183 # define setup_boot_APIC_clock x86_init_noop
184 # define setup_secondary_APIC_clock x86_init_noop
185 static inline void lapic_update_tsc_freq(void) { }
186 static inline void init_bsp_APIC(void) { }
187 static inline void apic_intr_mode_init(void) { }
188 static inline void lapic_assign_system_vectors(void) { }
189 static inline void lapic_assign_legacy_vector(unsigned int i, bool r) { }
190 #endif /* !CONFIG_X86_LOCAL_APIC */
191 
192 #ifdef CONFIG_X86_X2APIC
193 /*
194  * Make previous memory operations globally visible before
195  * sending the IPI through x2apic wrmsr. We need a serializing instruction or
196  * mfence for this.
197  */
198 static inline void x2apic_wrmsr_fence(void)
199 {
200         asm volatile("mfence" : : : "memory");
201 }
202 
203 static inline void native_apic_msr_write(u32 reg, u32 v)
204 {
205         if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
206             reg == APIC_LVR)
207                 return;
208 
209         wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
210 }
211 
212 static inline void native_apic_msr_eoi_write(u32 reg, u32 v)
213 {
214         __wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0);
215 }
216 
217 static inline u32 native_apic_msr_read(u32 reg)
218 {
219         u64 msr;
220 
221         if (reg == APIC_DFR)
222                 return -1;
223 
224         rdmsrl(APIC_BASE_MSR + (reg >> 4), msr);
225         return (u32)msr;
226 }
227 
228 static inline void native_x2apic_wait_icr_idle(void)
229 {
230         /* no need to wait for icr idle in x2apic */
231         return;
232 }
233 
234 static inline u32 native_safe_x2apic_wait_icr_idle(void)
235 {
236         /* no need to wait for icr idle in x2apic */
237         return 0;
238 }
239 
240 static inline void native_x2apic_icr_write(u32 low, u32 id)
241 {
242         wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
243 }
244 
245 static inline u64 native_x2apic_icr_read(void)
246 {
247         unsigned long val;
248 
249         rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
250         return val;
251 }
252 
253 extern int x2apic_mode;
254 extern int x2apic_phys;
255 extern void __init check_x2apic(void);
256 extern void x2apic_setup(void);
257 static inline int x2apic_enabled(void)
258 {
259         return boot_cpu_has(X86_FEATURE_X2APIC) && apic_is_x2apic_enabled();
260 }
261 
262 #define x2apic_supported()      (boot_cpu_has(X86_FEATURE_X2APIC))
263 #else /* !CONFIG_X86_X2APIC */
264 static inline void check_x2apic(void) { }
265 static inline void x2apic_setup(void) { }
266 static inline int x2apic_enabled(void) { return 0; }
267 
268 #define x2apic_mode             (0)
269 #define x2apic_supported()      (0)
270 #endif /* !CONFIG_X86_X2APIC */
271 
272 struct irq_data;
273 
274 /*
275  * Copyright 2004 James Cleverdon, IBM.
276  * Subject to the GNU Public License, v.2
277  *
278  * Generic APIC sub-arch data struct.
279  *
280  * Hacked for x86-64 by James Cleverdon from i386 architecture code by
281  * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
282  * James Cleverdon.
283  */
284 struct apic {
285         /* Hotpath functions first */
286         void    (*eoi_write)(u32 reg, u32 v);
287         void    (*native_eoi_write)(u32 reg, u32 v);
288         void    (*write)(u32 reg, u32 v);
289         u32     (*read)(u32 reg);
290 
291         /* IPI related functions */
292         void    (*wait_icr_idle)(void);
293         u32     (*safe_wait_icr_idle)(void);
294 
295         void    (*send_IPI)(int cpu, int vector);
296         void    (*send_IPI_mask)(const struct cpumask *mask, int vector);
297         void    (*send_IPI_mask_allbutself)(const struct cpumask *msk, int vec);
298         void    (*send_IPI_allbutself)(int vector);
299         void    (*send_IPI_all)(int vector);
300         void    (*send_IPI_self)(int vector);
301 
302         /* dest_logical is used by the IPI functions */
303         u32     dest_logical;
304         u32     disable_esr;
305         u32     irq_delivery_mode;
306         u32     irq_dest_mode;
307 
308         u32     (*calc_dest_apicid)(unsigned int cpu);
309 
310         /* ICR related functions */
311         u64     (*icr_read)(void);
312         void    (*icr_write)(u32 low, u32 high);
313 
314         /* Probe, setup and smpboot functions */
315         int     (*probe)(void);
316         int     (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
317         int     (*apic_id_valid)(u32 apicid);
318         int     (*apic_id_registered)(void);
319 
320         bool    (*check_apicid_used)(physid_mask_t *map, int apicid);
321         void    (*init_apic_ldr)(void);
322         void    (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap);
323         void    (*setup_apic_routing)(void);
324         int     (*cpu_present_to_apicid)(int mps_cpu);
325         void    (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap);
326         int     (*check_phys_apicid_present)(int phys_apicid);
327         int     (*phys_pkg_id)(int cpuid_apic, int index_msb);
328 
329         u32     (*get_apic_id)(unsigned long x);
330         u32     (*set_apic_id)(unsigned int id);
331 
332         /* wakeup_secondary_cpu */
333         int     (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip);
334 
335         void    (*inquire_remote_apic)(int apicid);
336 
337 #ifdef CONFIG_X86_32
338         /*
339          * Called very early during boot from get_smp_config().  It should
340          * return the logical apicid.  x86_[bios]_cpu_to_apicid is
341          * initialized before this function is called.
342          *
343          * If logical apicid can't be determined that early, the function
344          * may return BAD_APICID.  Logical apicid will be configured after
345          * init_apic_ldr() while bringing up CPUs.  Note that NUMA affinity
346          * won't be applied properly during early boot in this case.
347          */
348         int (*x86_32_early_logical_apicid)(int cpu);
349 #endif
350         char    *name;
351 };
352 
353 /*
354  * Pointer to the local APIC driver in use on this system (there's
355  * always just one such driver in use - the kernel decides via an
356  * early probing process which one it picks - and then sticks to it):
357  */
358 extern struct apic *apic;
359 
360 /*
361  * APIC drivers are probed based on how they are listed in the .apicdrivers
362  * section. So the order is important and enforced by the ordering
363  * of different apic driver files in the Makefile.
364  *
365  * For the files having two apic drivers, we use apic_drivers()
366  * to enforce the order with in them.
367  */
368 #define apic_driver(sym)                                        \
369         static const struct apic *__apicdrivers_##sym __used            \
370         __aligned(sizeof(struct apic *))                        \
371         __section(.apicdrivers) = { &sym }
372 
373 #define apic_drivers(sym1, sym2)                                        \
374         static struct apic *__apicdrivers_##sym1##sym2[2] __used        \
375         __aligned(sizeof(struct apic *))                                \
376         __section(.apicdrivers) = { &sym1, &sym2 }
377 
378 extern struct apic *__apicdrivers[], *__apicdrivers_end[];
379 
380 /*
381  * APIC functionality to boot other CPUs - only used on SMP:
382  */
383 #ifdef CONFIG_SMP
384 extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip);
385 extern int lapic_can_unplug_cpu(void);
386 #endif
387 
388 #ifdef CONFIG_X86_LOCAL_APIC
389 
390 static inline u32 apic_read(u32 reg)
391 {
392         return apic->read(reg);
393 }
394 
395 static inline void apic_write(u32 reg, u32 val)
396 {
397         apic->write(reg, val);
398 }
399 
400 static inline void apic_eoi(void)
401 {
402         apic->eoi_write(APIC_EOI, APIC_EOI_ACK);
403 }
404 
405 static inline u64 apic_icr_read(void)
406 {
407         return apic->icr_read();
408 }
409 
410 static inline void apic_icr_write(u32 low, u32 high)
411 {
412         apic->icr_write(low, high);
413 }
414 
415 static inline void apic_wait_icr_idle(void)
416 {
417         apic->wait_icr_idle();
418 }
419 
420 static inline u32 safe_apic_wait_icr_idle(void)
421 {
422         return apic->safe_wait_icr_idle();
423 }
424 
425 extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v));
426 
427 #else /* CONFIG_X86_LOCAL_APIC */
428 
429 static inline u32 apic_read(u32 reg) { return 0; }
430 static inline void apic_write(u32 reg, u32 val) { }
431 static inline void apic_eoi(void) { }
432 static inline u64 apic_icr_read(void) { return 0; }
433 static inline void apic_icr_write(u32 low, u32 high) { }
434 static inline void apic_wait_icr_idle(void) { }
435 static inline u32 safe_apic_wait_icr_idle(void) { return 0; }
436 static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {}
437 
438 #endif /* CONFIG_X86_LOCAL_APIC */
439 
440 extern void apic_ack_irq(struct irq_data *data);
441 
442 static inline void ack_APIC_irq(void)
443 {
444         /*
445          * ack_APIC_irq() actually gets compiled as a single instruction
446          * ... yummie.
447          */
448         apic_eoi();
449 }
450 
451 static inline unsigned default_get_apic_id(unsigned long x)
452 {
453         unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
454 
455         if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID))
456                 return (x >> 24) & 0xFF;
457         else
458                 return (x >> 24) & 0x0F;
459 }
460 
461 /*
462  * Warm reset vector position:
463  */
464 #define TRAMPOLINE_PHYS_LOW             0x467
465 #define TRAMPOLINE_PHYS_HIGH            0x469
466 
467 #ifdef CONFIG_X86_64
468 extern void apic_send_IPI_self(int vector);
469 
470 DECLARE_PER_CPU(int, x2apic_extra_bits);
471 #endif
472 
473 extern void generic_bigsmp_probe(void);
474 
475 #ifdef CONFIG_X86_LOCAL_APIC
476 
477 #include <asm/smp.h>
478 
479 #define APIC_DFR_VALUE  (APIC_DFR_FLAT)
480 
481 DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid);
482 
483 extern struct apic apic_noop;
484 
485 static inline unsigned int read_apic_id(void)
486 {
487         unsigned int reg = apic_read(APIC_ID);
488 
489         return apic->get_apic_id(reg);
490 }
491 
492 extern int default_apic_id_valid(u32 apicid);
493 extern int default_acpi_madt_oem_check(char *, char *);
494 extern void default_setup_apic_routing(void);
495 
496 extern u32 apic_default_calc_apicid(unsigned int cpu);
497 extern u32 apic_flat_calc_apicid(unsigned int cpu);
498 
499 extern bool default_check_apicid_used(physid_mask_t *map, int apicid);
500 extern void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap);
501 extern int default_cpu_present_to_apicid(int mps_cpu);
502 extern int default_check_phys_apicid_present(int phys_apicid);
503 
504 #endif /* CONFIG_X86_LOCAL_APIC */
505 
506 #ifdef CONFIG_SMP
507 bool apic_id_is_primary_thread(unsigned int id);
508 #else
509 static inline bool apic_id_is_primary_thread(unsigned int id) { return false; }
510 #endif
511 
512 extern void irq_enter(void);
513 extern void irq_exit(void);
514 
515 static inline void entering_irq(void)
516 {
517         irq_enter();
518         kvm_set_cpu_l1tf_flush_l1d();
519 }
520 
521 static inline void entering_ack_irq(void)
522 {
523         entering_irq();
524         ack_APIC_irq();
525 }
526 
527 static inline void ipi_entering_ack_irq(void)
528 {
529         irq_enter();
530         ack_APIC_irq();
531         kvm_set_cpu_l1tf_flush_l1d();
532 }
533 
534 static inline void exiting_irq(void)
535 {
536         irq_exit();
537 }
538 
539 static inline void exiting_ack_irq(void)
540 {
541         ack_APIC_irq();
542         irq_exit();
543 }
544 
545 extern void ioapic_zap_locks(void);
546 
547 #endif /* _ASM_X86_APIC_H */
548 

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