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Linux/arch/x86/include/asm/mce.h

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  1 /* SPDX-License-Identifier: GPL-2.0 */
  2 #ifndef _ASM_X86_MCE_H
  3 #define _ASM_X86_MCE_H
  4 
  5 #include <uapi/asm/mce.h>
  6 
  7 /*
  8  * Machine Check support for x86
  9  */
 10 
 11 /* MCG_CAP register defines */
 12 #define MCG_BANKCNT_MASK        0xff         /* Number of Banks */
 13 #define MCG_CTL_P               BIT_ULL(8)   /* MCG_CTL register available */
 14 #define MCG_EXT_P               BIT_ULL(9)   /* Extended registers available */
 15 #define MCG_CMCI_P              BIT_ULL(10)  /* CMCI supported */
 16 #define MCG_EXT_CNT_MASK        0xff0000     /* Number of Extended registers */
 17 #define MCG_EXT_CNT_SHIFT       16
 18 #define MCG_EXT_CNT(c)          (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
 19 #define MCG_SER_P               BIT_ULL(24)  /* MCA recovery/new status bits */
 20 #define MCG_ELOG_P              BIT_ULL(26)  /* Extended error log supported */
 21 #define MCG_LMCE_P              BIT_ULL(27)  /* Local machine check supported */
 22 
 23 /* MCG_STATUS register defines */
 24 #define MCG_STATUS_RIPV         BIT_ULL(0)   /* restart ip valid */
 25 #define MCG_STATUS_EIPV         BIT_ULL(1)   /* ip points to correct instruction */
 26 #define MCG_STATUS_MCIP         BIT_ULL(2)   /* machine check in progress */
 27 #define MCG_STATUS_LMCES        BIT_ULL(3)   /* LMCE signaled */
 28 
 29 /* MCG_EXT_CTL register defines */
 30 #define MCG_EXT_CTL_LMCE_EN     BIT_ULL(0) /* Enable LMCE */
 31 
 32 /* MCi_STATUS register defines */
 33 #define MCI_STATUS_VAL          BIT_ULL(63)  /* valid error */
 34 #define MCI_STATUS_OVER         BIT_ULL(62)  /* previous errors lost */
 35 #define MCI_STATUS_UC           BIT_ULL(61)  /* uncorrected error */
 36 #define MCI_STATUS_EN           BIT_ULL(60)  /* error enabled */
 37 #define MCI_STATUS_MISCV        BIT_ULL(59)  /* misc error reg. valid */
 38 #define MCI_STATUS_ADDRV        BIT_ULL(58)  /* addr reg. valid */
 39 #define MCI_STATUS_PCC          BIT_ULL(57)  /* processor context corrupt */
 40 #define MCI_STATUS_S            BIT_ULL(56)  /* Signaled machine check */
 41 #define MCI_STATUS_AR           BIT_ULL(55)  /* Action required */
 42 #define MCI_STATUS_CEC_SHIFT    38           /* Corrected Error Count */
 43 #define MCI_STATUS_CEC_MASK     GENMASK_ULL(52,38)
 44 #define MCI_STATUS_CEC(c)       (((c) & MCI_STATUS_CEC_MASK) >> MCI_STATUS_CEC_SHIFT)
 45 
 46 /* AMD-specific bits */
 47 #define MCI_STATUS_TCC          BIT_ULL(55)  /* Task context corrupt */
 48 #define MCI_STATUS_SYNDV        BIT_ULL(53)  /* synd reg. valid */
 49 #define MCI_STATUS_DEFERRED     BIT_ULL(44)  /* uncorrected error, deferred exception */
 50 #define MCI_STATUS_POISON       BIT_ULL(43)  /* access poisonous data */
 51 
 52 /*
 53  * McaX field if set indicates a given bank supports MCA extensions:
 54  *  - Deferred error interrupt type is specifiable by bank.
 55  *  - MCx_MISC0[BlkPtr] field indicates presence of extended MISC registers,
 56  *    But should not be used to determine MSR numbers.
 57  *  - TCC bit is present in MCx_STATUS.
 58  */
 59 #define MCI_CONFIG_MCAX         0x1
 60 #define MCI_IPID_MCATYPE        0xFFFF0000
 61 #define MCI_IPID_HWID           0xFFF
 62 
 63 /*
 64  * Note that the full MCACOD field of IA32_MCi_STATUS MSR is
 65  * bits 15:0.  But bit 12 is the 'F' bit, defined for corrected
 66  * errors to indicate that errors are being filtered by hardware.
 67  * We should mask out bit 12 when looking for specific signatures
 68  * of uncorrected errors - so the F bit is deliberately skipped
 69  * in this #define.
 70  */
 71 #define MCACOD            0xefff     /* MCA Error Code */
 72 
 73 /* Architecturally defined codes from SDM Vol. 3B Chapter 15 */
 74 #define MCACOD_SCRUB    0x00C0  /* 0xC0-0xCF Memory Scrubbing */
 75 #define MCACOD_SCRUBMSK 0xeff0  /* Skip bit 12 ('F' bit) */
 76 #define MCACOD_L3WB     0x017A  /* L3 Explicit Writeback */
 77 #define MCACOD_DATA     0x0134  /* Data Load */
 78 #define MCACOD_INSTR    0x0150  /* Instruction Fetch */
 79 
 80 /* MCi_MISC register defines */
 81 #define MCI_MISC_ADDR_LSB(m)    ((m) & 0x3f)
 82 #define MCI_MISC_ADDR_MODE(m)   (((m) >> 6) & 7)
 83 #define  MCI_MISC_ADDR_SEGOFF   0       /* segment offset */
 84 #define  MCI_MISC_ADDR_LINEAR   1       /* linear address */
 85 #define  MCI_MISC_ADDR_PHYS     2       /* physical address */
 86 #define  MCI_MISC_ADDR_MEM      3       /* memory address */
 87 #define  MCI_MISC_ADDR_GENERIC  7       /* generic */
 88 
 89 /* CTL2 register defines */
 90 #define MCI_CTL2_CMCI_EN                BIT_ULL(30)
 91 #define MCI_CTL2_CMCI_THRESHOLD_MASK    0x7fffULL
 92 
 93 #define MCJ_CTX_MASK            3
 94 #define MCJ_CTX(flags)          ((flags) & MCJ_CTX_MASK)
 95 #define MCJ_CTX_RANDOM          0    /* inject context: random */
 96 #define MCJ_CTX_PROCESS         0x1  /* inject context: process */
 97 #define MCJ_CTX_IRQ             0x2  /* inject context: IRQ */
 98 #define MCJ_NMI_BROADCAST       0x4  /* do NMI broadcasting */
 99 #define MCJ_EXCEPTION           0x8  /* raise as exception */
100 #define MCJ_IRQ_BROADCAST       0x10 /* do IRQ broadcasting */
101 
102 #define MCE_OVERFLOW 0          /* bit 0 in flags means overflow */
103 
104 #define MCE_LOG_LEN 32
105 #define MCE_LOG_SIGNATURE       "MACHINECHECK"
106 
107 /* AMD Scalable MCA */
108 #define MSR_AMD64_SMCA_MC0_CTL          0xc0002000
109 #define MSR_AMD64_SMCA_MC0_STATUS       0xc0002001
110 #define MSR_AMD64_SMCA_MC0_ADDR         0xc0002002
111 #define MSR_AMD64_SMCA_MC0_MISC0        0xc0002003
112 #define MSR_AMD64_SMCA_MC0_CONFIG       0xc0002004
113 #define MSR_AMD64_SMCA_MC0_IPID         0xc0002005
114 #define MSR_AMD64_SMCA_MC0_SYND         0xc0002006
115 #define MSR_AMD64_SMCA_MC0_DESTAT       0xc0002008
116 #define MSR_AMD64_SMCA_MC0_DEADDR       0xc0002009
117 #define MSR_AMD64_SMCA_MC0_MISC1        0xc000200a
118 #define MSR_AMD64_SMCA_MCx_CTL(x)       (MSR_AMD64_SMCA_MC0_CTL + 0x10*(x))
119 #define MSR_AMD64_SMCA_MCx_STATUS(x)    (MSR_AMD64_SMCA_MC0_STATUS + 0x10*(x))
120 #define MSR_AMD64_SMCA_MCx_ADDR(x)      (MSR_AMD64_SMCA_MC0_ADDR + 0x10*(x))
121 #define MSR_AMD64_SMCA_MCx_MISC(x)      (MSR_AMD64_SMCA_MC0_MISC0 + 0x10*(x))
122 #define MSR_AMD64_SMCA_MCx_CONFIG(x)    (MSR_AMD64_SMCA_MC0_CONFIG + 0x10*(x))
123 #define MSR_AMD64_SMCA_MCx_IPID(x)      (MSR_AMD64_SMCA_MC0_IPID + 0x10*(x))
124 #define MSR_AMD64_SMCA_MCx_SYND(x)      (MSR_AMD64_SMCA_MC0_SYND + 0x10*(x))
125 #define MSR_AMD64_SMCA_MCx_DESTAT(x)    (MSR_AMD64_SMCA_MC0_DESTAT + 0x10*(x))
126 #define MSR_AMD64_SMCA_MCx_DEADDR(x)    (MSR_AMD64_SMCA_MC0_DEADDR + 0x10*(x))
127 #define MSR_AMD64_SMCA_MCx_MISCy(x, y)  ((MSR_AMD64_SMCA_MC0_MISC1 + y) + (0x10*(x)))
128 
129 /*
130  * This structure contains all data related to the MCE log.  Also
131  * carries a signature to make it easier to find from external
132  * debugging tools.  Each entry is only valid when its finished flag
133  * is set.
134  */
135 struct mce_log_buffer {
136         char signature[12]; /* "MACHINECHECK" */
137         unsigned len;       /* = MCE_LOG_LEN */
138         unsigned next;
139         unsigned flags;
140         unsigned recordlen;     /* length of struct mce */
141         struct mce entry[MCE_LOG_LEN];
142 };
143 
144 enum mce_notifier_prios {
145         MCE_PRIO_FIRST          = INT_MAX,
146         MCE_PRIO_SRAO           = INT_MAX - 1,
147         MCE_PRIO_EXTLOG         = INT_MAX - 2,
148         MCE_PRIO_NFIT           = INT_MAX - 3,
149         MCE_PRIO_EDAC           = INT_MAX - 4,
150         MCE_PRIO_MCELOG         = 1,
151         MCE_PRIO_LOWEST         = 0,
152 };
153 
154 struct notifier_block;
155 extern void mce_register_decode_chain(struct notifier_block *nb);
156 extern void mce_unregister_decode_chain(struct notifier_block *nb);
157 
158 #include <linux/percpu.h>
159 #include <linux/atomic.h>
160 
161 extern int mce_p5_enabled;
162 
163 #ifdef CONFIG_X86_MCE
164 int mcheck_init(void);
165 void mcheck_cpu_init(struct cpuinfo_x86 *c);
166 void mcheck_cpu_clear(struct cpuinfo_x86 *c);
167 void mcheck_vendor_init_severity(void);
168 #else
169 static inline int mcheck_init(void) { return 0; }
170 static inline void mcheck_cpu_init(struct cpuinfo_x86 *c) {}
171 static inline void mcheck_cpu_clear(struct cpuinfo_x86 *c) {}
172 static inline void mcheck_vendor_init_severity(void) {}
173 #endif
174 
175 #ifdef CONFIG_X86_ANCIENT_MCE
176 void intel_p5_mcheck_init(struct cpuinfo_x86 *c);
177 void winchip_mcheck_init(struct cpuinfo_x86 *c);
178 static inline void enable_p5_mce(void) { mce_p5_enabled = 1; }
179 #else
180 static inline void intel_p5_mcheck_init(struct cpuinfo_x86 *c) {}
181 static inline void winchip_mcheck_init(struct cpuinfo_x86 *c) {}
182 static inline void enable_p5_mce(void) {}
183 #endif
184 
185 void mce_setup(struct mce *m);
186 void mce_log(struct mce *m);
187 DECLARE_PER_CPU(struct device *, mce_device);
188 
189 /*
190  * Maximum banks number.
191  * This is the limit of the current register layout on
192  * Intel CPUs.
193  */
194 #define MAX_NR_BANKS 32
195 
196 #ifdef CONFIG_X86_MCE_INTEL
197 void mce_intel_feature_init(struct cpuinfo_x86 *c);
198 void mce_intel_feature_clear(struct cpuinfo_x86 *c);
199 void cmci_clear(void);
200 void cmci_reenable(void);
201 void cmci_rediscover(void);
202 void cmci_recheck(void);
203 #else
204 static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { }
205 static inline void mce_intel_feature_clear(struct cpuinfo_x86 *c) { }
206 static inline void cmci_clear(void) {}
207 static inline void cmci_reenable(void) {}
208 static inline void cmci_rediscover(void) {}
209 static inline void cmci_recheck(void) {}
210 #endif
211 
212 int mce_available(struct cpuinfo_x86 *c);
213 bool mce_is_memory_error(struct mce *m);
214 bool mce_is_correctable(struct mce *m);
215 int mce_usable_address(struct mce *m);
216 
217 DECLARE_PER_CPU(unsigned, mce_exception_count);
218 DECLARE_PER_CPU(unsigned, mce_poll_count);
219 
220 typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS);
221 DECLARE_PER_CPU(mce_banks_t, mce_poll_banks);
222 
223 enum mcp_flags {
224         MCP_TIMESTAMP   = BIT(0),       /* log time stamp */
225         MCP_UC          = BIT(1),       /* log uncorrected errors */
226         MCP_DONTLOG     = BIT(2),       /* only clear, don't log */
227 };
228 bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b);
229 
230 int mce_notify_irq(void);
231 
232 DECLARE_PER_CPU(struct mce, injectm);
233 
234 /* Disable CMCI/polling for MCA bank claimed by firmware */
235 extern void mce_disable_bank(int bank);
236 
237 /*
238  * Exception handler
239  */
240 
241 /* Call the installed machine check handler for this CPU setup. */
242 extern void (*machine_check_vector)(struct pt_regs *, long error_code);
243 void do_machine_check(struct pt_regs *, long);
244 
245 /*
246  * Threshold handler
247  */
248 extern void (*mce_threshold_vector)(void);
249 
250 /* Deferred error interrupt handler */
251 extern void (*deferred_error_int_vector)(void);
252 
253 /*
254  * Thermal handler
255  */
256 
257 void intel_init_thermal(struct cpuinfo_x86 *c);
258 
259 /* Interrupt Handler for core thermal thresholds */
260 extern int (*platform_thermal_notify)(__u64 msr_val);
261 
262 /* Interrupt Handler for package thermal thresholds */
263 extern int (*platform_thermal_package_notify)(__u64 msr_val);
264 
265 /* Callback support of rate control, return true, if
266  * callback has rate control */
267 extern bool (*platform_thermal_package_rate_control)(void);
268 
269 #ifdef CONFIG_X86_THERMAL_VECTOR
270 extern void mcheck_intel_therm_init(void);
271 #else
272 static inline void mcheck_intel_therm_init(void) { }
273 #endif
274 
275 /*
276  * Used by APEI to report memory error via /dev/mcelog
277  */
278 
279 struct cper_sec_mem_err;
280 extern void apei_mce_report_mem_error(int corrected,
281                                       struct cper_sec_mem_err *mem_err);
282 
283 /*
284  * Enumerate new IP types and HWID values in AMD processors which support
285  * Scalable MCA.
286  */
287 #ifdef CONFIG_X86_MCE_AMD
288 
289 /* These may be used by multiple smca_hwid_mcatypes */
290 enum smca_bank_types {
291         SMCA_LS = 0,    /* Load Store */
292         SMCA_IF,        /* Instruction Fetch */
293         SMCA_L2_CACHE,  /* L2 Cache */
294         SMCA_DE,        /* Decoder Unit */
295         SMCA_RESERVED,  /* Reserved */
296         SMCA_EX,        /* Execution Unit */
297         SMCA_FP,        /* Floating Point */
298         SMCA_L3_CACHE,  /* L3 Cache */
299         SMCA_CS,        /* Coherent Slave */
300         SMCA_PIE,       /* Power, Interrupts, etc. */
301         SMCA_UMC,       /* Unified Memory Controller */
302         SMCA_PB,        /* Parameter Block */
303         SMCA_PSP,       /* Platform Security Processor */
304         SMCA_SMU,       /* System Management Unit */
305         N_SMCA_BANK_TYPES
306 };
307 
308 #define HWID_MCATYPE(hwid, mcatype) (((hwid) << 16) | (mcatype))
309 
310 struct smca_hwid {
311         unsigned int bank_type; /* Use with smca_bank_types for easy indexing. */
312         u32 hwid_mcatype;       /* (hwid,mcatype) tuple */
313         u32 xec_bitmap;         /* Bitmap of valid ExtErrorCodes; current max is 21. */
314         u8 count;               /* Number of instances. */
315 };
316 
317 struct smca_bank {
318         struct smca_hwid *hwid;
319         u32 id;                 /* Value of MCA_IPID[InstanceId]. */
320         u8 sysfs_id;            /* Value used for sysfs name. */
321 };
322 
323 extern struct smca_bank smca_banks[MAX_NR_BANKS];
324 
325 extern const char *smca_get_long_name(enum smca_bank_types t);
326 extern bool amd_mce_is_memory_error(struct mce *m);
327 
328 extern int mce_threshold_create_device(unsigned int cpu);
329 extern int mce_threshold_remove_device(unsigned int cpu);
330 
331 void mce_amd_feature_init(struct cpuinfo_x86 *c);
332 int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr);
333 
334 #else
335 
336 static inline int mce_threshold_create_device(unsigned int cpu)         { return 0; };
337 static inline int mce_threshold_remove_device(unsigned int cpu)         { return 0; };
338 static inline bool amd_mce_is_memory_error(struct mce *m)               { return false; };
339 static inline void mce_amd_feature_init(struct cpuinfo_x86 *c)          { }
340 static inline int
341 umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr)  { return -EINVAL; };
342 #endif
343 
344 static inline void mce_hygon_feature_init(struct cpuinfo_x86 *c)        { return mce_amd_feature_init(c); }
345 
346 #endif /* _ASM_X86_MCE_H */
347 

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