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Linux/arch/x86/include/asm/msr.h

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  1 /* SPDX-License-Identifier: GPL-2.0 */
  2 #ifndef _ASM_X86_MSR_H
  3 #define _ASM_X86_MSR_H
  4 
  5 #include "msr-index.h"
  6 
  7 #ifndef __ASSEMBLY__
  8 
  9 #include <asm/asm.h>
 10 #include <asm/errno.h>
 11 #include <asm/cpumask.h>
 12 #include <uapi/asm/msr.h>
 13 
 14 struct msr {
 15         union {
 16                 struct {
 17                         u32 l;
 18                         u32 h;
 19                 };
 20                 u64 q;
 21         };
 22 };
 23 
 24 struct msr_info {
 25         u32 msr_no;
 26         struct msr reg;
 27         struct msr *msrs;
 28         int err;
 29 };
 30 
 31 struct msr_regs_info {
 32         u32 *regs;
 33         int err;
 34 };
 35 
 36 struct saved_msr {
 37         bool valid;
 38         struct msr_info info;
 39 };
 40 
 41 struct saved_msrs {
 42         unsigned int num;
 43         struct saved_msr *array;
 44 };
 45 
 46 /*
 47  * both i386 and x86_64 returns 64-bit value in edx:eax, but gcc's "A"
 48  * constraint has different meanings. For i386, "A" means exactly
 49  * edx:eax, while for x86_64 it doesn't mean rdx:rax or edx:eax. Instead,
 50  * it means rax *or* rdx.
 51  */
 52 #ifdef CONFIG_X86_64
 53 /* Using 64-bit values saves one instruction clearing the high half of low */
 54 #define DECLARE_ARGS(val, low, high)    unsigned long low, high
 55 #define EAX_EDX_VAL(val, low, high)     ((low) | (high) << 32)
 56 #define EAX_EDX_RET(val, low, high)     "=a" (low), "=d" (high)
 57 #else
 58 #define DECLARE_ARGS(val, low, high)    unsigned long long val
 59 #define EAX_EDX_VAL(val, low, high)     (val)
 60 #define EAX_EDX_RET(val, low, high)     "=A" (val)
 61 #endif
 62 
 63 #ifdef CONFIG_TRACEPOINTS
 64 /*
 65  * Be very careful with includes. This header is prone to include loops.
 66  */
 67 #include <asm/atomic.h>
 68 #include <linux/tracepoint-defs.h>
 69 
 70 extern struct tracepoint __tracepoint_read_msr;
 71 extern struct tracepoint __tracepoint_write_msr;
 72 extern struct tracepoint __tracepoint_rdpmc;
 73 #define msr_tracepoint_active(t) static_key_false(&(t).key)
 74 extern void do_trace_write_msr(unsigned int msr, u64 val, int failed);
 75 extern void do_trace_read_msr(unsigned int msr, u64 val, int failed);
 76 extern void do_trace_rdpmc(unsigned int msr, u64 val, int failed);
 77 #else
 78 #define msr_tracepoint_active(t) false
 79 static inline void do_trace_write_msr(unsigned int msr, u64 val, int failed) {}
 80 static inline void do_trace_read_msr(unsigned int msr, u64 val, int failed) {}
 81 static inline void do_trace_rdpmc(unsigned int msr, u64 val, int failed) {}
 82 #endif
 83 
 84 /*
 85  * __rdmsr() and __wrmsr() are the two primitives which are the bare minimum MSR
 86  * accessors and should not have any tracing or other functionality piggybacking
 87  * on them - those are *purely* for accessing MSRs and nothing more. So don't even
 88  * think of extending them - you will be slapped with a stinking trout or a frozen
 89  * shark will reach you, wherever you are! You've been warned.
 90  */
 91 static inline unsigned long long notrace __rdmsr(unsigned int msr)
 92 {
 93         DECLARE_ARGS(val, low, high);
 94 
 95         asm volatile("1: rdmsr\n"
 96                      "2:\n"
 97                      _ASM_EXTABLE_HANDLE(1b, 2b, ex_handler_rdmsr_unsafe)
 98                      : EAX_EDX_RET(val, low, high) : "c" (msr));
 99 
100         return EAX_EDX_VAL(val, low, high);
101 }
102 
103 static inline void notrace __wrmsr(unsigned int msr, u32 low, u32 high)
104 {
105         asm volatile("1: wrmsr\n"
106                      "2:\n"
107                      _ASM_EXTABLE_HANDLE(1b, 2b, ex_handler_wrmsr_unsafe)
108                      : : "c" (msr), "a"(low), "d" (high) : "memory");
109 }
110 
111 #define native_rdmsr(msr, val1, val2)                   \
112 do {                                                    \
113         u64 __val = __rdmsr((msr));                     \
114         (void)((val1) = (u32)__val);                    \
115         (void)((val2) = (u32)(__val >> 32));            \
116 } while (0)
117 
118 #define native_wrmsr(msr, low, high)                    \
119         __wrmsr(msr, low, high)
120 
121 #define native_wrmsrl(msr, val)                         \
122         __wrmsr((msr), (u32)((u64)(val)),               \
123                        (u32)((u64)(val) >> 32))
124 
125 static inline unsigned long long native_read_msr(unsigned int msr)
126 {
127         unsigned long long val;
128 
129         val = __rdmsr(msr);
130 
131         if (msr_tracepoint_active(__tracepoint_read_msr))
132                 do_trace_read_msr(msr, val, 0);
133 
134         return val;
135 }
136 
137 static inline unsigned long long native_read_msr_safe(unsigned int msr,
138                                                       int *err)
139 {
140         DECLARE_ARGS(val, low, high);
141 
142         asm volatile("2: rdmsr ; xor %[err],%[err]\n"
143                      "1:\n\t"
144                      ".section .fixup,\"ax\"\n\t"
145                      "3: mov %[fault],%[err]\n\t"
146                      "xorl %%eax, %%eax\n\t"
147                      "xorl %%edx, %%edx\n\t"
148                      "jmp 1b\n\t"
149                      ".previous\n\t"
150                      _ASM_EXTABLE(2b, 3b)
151                      : [err] "=r" (*err), EAX_EDX_RET(val, low, high)
152                      : "c" (msr), [fault] "i" (-EIO));
153         if (msr_tracepoint_active(__tracepoint_read_msr))
154                 do_trace_read_msr(msr, EAX_EDX_VAL(val, low, high), *err);
155         return EAX_EDX_VAL(val, low, high);
156 }
157 
158 /* Can be uninlined because referenced by paravirt */
159 static inline void notrace
160 native_write_msr(unsigned int msr, u32 low, u32 high)
161 {
162         __wrmsr(msr, low, high);
163 
164         if (msr_tracepoint_active(__tracepoint_write_msr))
165                 do_trace_write_msr(msr, ((u64)high << 32 | low), 0);
166 }
167 
168 /* Can be uninlined because referenced by paravirt */
169 static inline int notrace
170 native_write_msr_safe(unsigned int msr, u32 low, u32 high)
171 {
172         int err;
173 
174         asm volatile("2: wrmsr ; xor %[err],%[err]\n"
175                      "1:\n\t"
176                      ".section .fixup,\"ax\"\n\t"
177                      "3:  mov %[fault],%[err] ; jmp 1b\n\t"
178                      ".previous\n\t"
179                      _ASM_EXTABLE(2b, 3b)
180                      : [err] "=a" (err)
181                      : "c" (msr), "" (low), "d" (high),
182                        [fault] "i" (-EIO)
183                      : "memory");
184         if (msr_tracepoint_active(__tracepoint_write_msr))
185                 do_trace_write_msr(msr, ((u64)high << 32 | low), err);
186         return err;
187 }
188 
189 extern int rdmsr_safe_regs(u32 regs[8]);
190 extern int wrmsr_safe_regs(u32 regs[8]);
191 
192 /**
193  * rdtsc() - returns the current TSC without ordering constraints
194  *
195  * rdtsc() returns the result of RDTSC as a 64-bit integer.  The
196  * only ordering constraint it supplies is the ordering implied by
197  * "asm volatile": it will put the RDTSC in the place you expect.  The
198  * CPU can and will speculatively execute that RDTSC, though, so the
199  * results can be non-monotonic if compared on different CPUs.
200  */
201 static __always_inline unsigned long long rdtsc(void)
202 {
203         DECLARE_ARGS(val, low, high);
204 
205         asm volatile("rdtsc" : EAX_EDX_RET(val, low, high));
206 
207         return EAX_EDX_VAL(val, low, high);
208 }
209 
210 /**
211  * rdtsc_ordered() - read the current TSC in program order
212  *
213  * rdtsc_ordered() returns the result of RDTSC as a 64-bit integer.
214  * It is ordered like a load to a global in-memory counter.  It should
215  * be impossible to observe non-monotonic rdtsc_unordered() behavior
216  * across multiple CPUs as long as the TSC is synced.
217  */
218 static __always_inline unsigned long long rdtsc_ordered(void)
219 {
220         /*
221          * The RDTSC instruction is not ordered relative to memory
222          * access.  The Intel SDM and the AMD APM are both vague on this
223          * point, but empirically an RDTSC instruction can be
224          * speculatively executed before prior loads.  An RDTSC
225          * immediately after an appropriate barrier appears to be
226          * ordered as a normal load, that is, it provides the same
227          * ordering guarantees as reading from a global memory location
228          * that some other imaginary CPU is updating continuously with a
229          * time stamp.
230          */
231         barrier_nospec();
232         return rdtsc();
233 }
234 
235 static inline unsigned long long native_read_pmc(int counter)
236 {
237         DECLARE_ARGS(val, low, high);
238 
239         asm volatile("rdpmc" : EAX_EDX_RET(val, low, high) : "c" (counter));
240         if (msr_tracepoint_active(__tracepoint_rdpmc))
241                 do_trace_rdpmc(counter, EAX_EDX_VAL(val, low, high), 0);
242         return EAX_EDX_VAL(val, low, high);
243 }
244 
245 #ifdef CONFIG_PARAVIRT_XXL
246 #include <asm/paravirt.h>
247 #else
248 #include <linux/errno.h>
249 /*
250  * Access to machine-specific registers (available on 586 and better only)
251  * Note: the rd* operations modify the parameters directly (without using
252  * pointer indirection), this allows gcc to optimize better
253  */
254 
255 #define rdmsr(msr, low, high)                                   \
256 do {                                                            \
257         u64 __val = native_read_msr((msr));                     \
258         (void)((low) = (u32)__val);                             \
259         (void)((high) = (u32)(__val >> 32));                    \
260 } while (0)
261 
262 static inline void wrmsr(unsigned int msr, u32 low, u32 high)
263 {
264         native_write_msr(msr, low, high);
265 }
266 
267 #define rdmsrl(msr, val)                        \
268         ((val) = native_read_msr((msr)))
269 
270 static inline void wrmsrl(unsigned int msr, u64 val)
271 {
272         native_write_msr(msr, (u32)(val & 0xffffffffULL), (u32)(val >> 32));
273 }
274 
275 /* wrmsr with exception handling */
276 static inline int wrmsr_safe(unsigned int msr, u32 low, u32 high)
277 {
278         return native_write_msr_safe(msr, low, high);
279 }
280 
281 /* rdmsr with exception handling */
282 #define rdmsr_safe(msr, low, high)                              \
283 ({                                                              \
284         int __err;                                              \
285         u64 __val = native_read_msr_safe((msr), &__err);        \
286         (*low) = (u32)__val;                                    \
287         (*high) = (u32)(__val >> 32);                           \
288         __err;                                                  \
289 })
290 
291 static inline int rdmsrl_safe(unsigned int msr, unsigned long long *p)
292 {
293         int err;
294 
295         *p = native_read_msr_safe(msr, &err);
296         return err;
297 }
298 
299 #define rdpmc(counter, low, high)                       \
300 do {                                                    \
301         u64 _l = native_read_pmc((counter));            \
302         (low)  = (u32)_l;                               \
303         (high) = (u32)(_l >> 32);                       \
304 } while (0)
305 
306 #define rdpmcl(counter, val) ((val) = native_read_pmc(counter))
307 
308 #endif  /* !CONFIG_PARAVIRT_XXL */
309 
310 /*
311  * 64-bit version of wrmsr_safe():
312  */
313 static inline int wrmsrl_safe(u32 msr, u64 val)
314 {
315         return wrmsr_safe(msr, (u32)val,  (u32)(val >> 32));
316 }
317 
318 #define write_tsc(low, high) wrmsr(MSR_IA32_TSC, (low), (high))
319 
320 #define write_rdtscp_aux(val) wrmsr(MSR_TSC_AUX, (val), 0)
321 
322 struct msr *msrs_alloc(void);
323 void msrs_free(struct msr *msrs);
324 int msr_set_bit(u32 msr, u8 bit);
325 int msr_clear_bit(u32 msr, u8 bit);
326 
327 #ifdef CONFIG_SMP
328 int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
329 int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
330 int rdmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 *q);
331 int wrmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 q);
332 void rdmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs);
333 void wrmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs);
334 int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
335 int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
336 int rdmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q);
337 int wrmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q);
338 int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]);
339 int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]);
340 #else  /*  CONFIG_SMP  */
341 static inline int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h)
342 {
343         rdmsr(msr_no, *l, *h);
344         return 0;
345 }
346 static inline int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
347 {
348         wrmsr(msr_no, l, h);
349         return 0;
350 }
351 static inline int rdmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 *q)
352 {
353         rdmsrl(msr_no, *q);
354         return 0;
355 }
356 static inline int wrmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 q)
357 {
358         wrmsrl(msr_no, q);
359         return 0;
360 }
361 static inline void rdmsr_on_cpus(const struct cpumask *m, u32 msr_no,
362                                 struct msr *msrs)
363 {
364         rdmsr_on_cpu(0, msr_no, &(msrs[0].l), &(msrs[0].h));
365 }
366 static inline void wrmsr_on_cpus(const struct cpumask *m, u32 msr_no,
367                                 struct msr *msrs)
368 {
369         wrmsr_on_cpu(0, msr_no, msrs[0].l, msrs[0].h);
370 }
371 static inline int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no,
372                                     u32 *l, u32 *h)
373 {
374         return rdmsr_safe(msr_no, l, h);
375 }
376 static inline int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
377 {
378         return wrmsr_safe(msr_no, l, h);
379 }
380 static inline int rdmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q)
381 {
382         return rdmsrl_safe(msr_no, q);
383 }
384 static inline int wrmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q)
385 {
386         return wrmsrl_safe(msr_no, q);
387 }
388 static inline int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8])
389 {
390         return rdmsr_safe_regs(regs);
391 }
392 static inline int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8])
393 {
394         return wrmsr_safe_regs(regs);
395 }
396 #endif  /* CONFIG_SMP */
397 #endif /* __ASSEMBLY__ */
398 #endif /* _ASM_X86_MSR_H */
399 

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