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Linux/arch/x86/kernel/acpi/cstate.c

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  1 // SPDX-License-Identifier: GPL-2.0-only
  2 /*
  3  * Copyright (C) 2005 Intel Corporation
  4  *      Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
  5  *      - Added _PDC for SMP C-states on Intel CPUs
  6  */
  7 
  8 #include <linux/kernel.h>
  9 #include <linux/export.h>
 10 #include <linux/init.h>
 11 #include <linux/acpi.h>
 12 #include <linux/cpu.h>
 13 #include <linux/sched.h>
 14 
 15 #include <acpi/processor.h>
 16 #include <asm/mwait.h>
 17 #include <asm/special_insns.h>
 18 
 19 /*
 20  * Initialize bm_flags based on the CPU cache properties
 21  * On SMP it depends on cache configuration
 22  * - When cache is not shared among all CPUs, we flush cache
 23  *   before entering C3.
 24  * - When cache is shared among all CPUs, we use bm_check
 25  *   mechanism as in UP case
 26  *
 27  * This routine is called only after all the CPUs are online
 28  */
 29 void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags,
 30                                         unsigned int cpu)
 31 {
 32         struct cpuinfo_x86 *c = &cpu_data(cpu);
 33 
 34         flags->bm_check = 0;
 35         if (num_online_cpus() == 1)
 36                 flags->bm_check = 1;
 37         else if (c->x86_vendor == X86_VENDOR_INTEL) {
 38                 /*
 39                  * Today all MP CPUs that support C3 share cache.
 40                  * And caches should not be flushed by software while
 41                  * entering C3 type state.
 42                  */
 43                 flags->bm_check = 1;
 44         }
 45 
 46         /*
 47          * On all recent Intel platforms, ARB_DISABLE is a nop.
 48          * So, set bm_control to zero to indicate that ARB_DISABLE
 49          * is not required while entering C3 type state on
 50          * P4, Core and beyond CPUs
 51          */
 52         if (c->x86_vendor == X86_VENDOR_INTEL &&
 53             (c->x86 > 0xf || (c->x86 == 6 && c->x86_model >= 0x0f)))
 54                         flags->bm_control = 0;
 55         /*
 56          * For all recent Centaur CPUs, the ucode will make sure that each
 57          * core can keep cache coherence with each other while entering C3
 58          * type state. So, set bm_check to 1 to indicate that the kernel
 59          * doesn't need to execute a cache flush operation (WBINVD) when
 60          * entering C3 type state.
 61          */
 62         if (c->x86_vendor == X86_VENDOR_CENTAUR) {
 63                 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model == 0x0f &&
 64                     c->x86_stepping >= 0x0e))
 65                         flags->bm_check = 1;
 66         }
 67 
 68         if (c->x86_vendor == X86_VENDOR_ZHAOXIN) {
 69                 /*
 70                  * All Zhaoxin CPUs that support C3 share cache.
 71                  * And caches should not be flushed by software while
 72                  * entering C3 type state.
 73                  */
 74                 flags->bm_check = 1;
 75                 /*
 76                  * On all recent Zhaoxin platforms, ARB_DISABLE is a nop.
 77                  * So, set bm_control to zero to indicate that ARB_DISABLE
 78                  * is not required while entering C3 type state.
 79                  */
 80                 flags->bm_control = 0;
 81         }
 82 }
 83 EXPORT_SYMBOL(acpi_processor_power_init_bm_check);
 84 
 85 /* The code below handles cstate entry with monitor-mwait pair on Intel*/
 86 
 87 struct cstate_entry {
 88         struct {
 89                 unsigned int eax;
 90                 unsigned int ecx;
 91         } states[ACPI_PROCESSOR_MAX_POWER];
 92 };
 93 static struct cstate_entry __percpu *cpu_cstate_entry;  /* per CPU ptr */
 94 
 95 static short mwait_supported[ACPI_PROCESSOR_MAX_POWER];
 96 
 97 #define NATIVE_CSTATE_BEYOND_HALT       (2)
 98 
 99 static long acpi_processor_ffh_cstate_probe_cpu(void *_cx)
100 {
101         struct acpi_processor_cx *cx = _cx;
102         long retval;
103         unsigned int eax, ebx, ecx, edx;
104         unsigned int edx_part;
105         unsigned int cstate_type; /* C-state type and not ACPI C-state type */
106         unsigned int num_cstate_subtype;
107 
108         cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &edx);
109 
110         /* Check whether this particular cx_type (in CST) is supported or not */
111         cstate_type = ((cx->address >> MWAIT_SUBSTATE_SIZE) &
112                         MWAIT_CSTATE_MASK) + 1;
113         edx_part = edx >> (cstate_type * MWAIT_SUBSTATE_SIZE);
114         num_cstate_subtype = edx_part & MWAIT_SUBSTATE_MASK;
115 
116         retval = 0;
117         /* If the HW does not support any sub-states in this C-state */
118         if (num_cstate_subtype == 0) {
119                 pr_warn(FW_BUG "ACPI MWAIT C-state 0x%x not supported by HW (0x%x)\n",
120                                 cx->address, edx_part);
121                 retval = -1;
122                 goto out;
123         }
124 
125         /* mwait ecx extensions INTERRUPT_BREAK should be supported for C2/C3 */
126         if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) ||
127             !(ecx & CPUID5_ECX_INTERRUPT_BREAK)) {
128                 retval = -1;
129                 goto out;
130         }
131 
132         if (!mwait_supported[cstate_type]) {
133                 mwait_supported[cstate_type] = 1;
134                 printk(KERN_DEBUG
135                         "Monitor-Mwait will be used to enter C-%d state\n",
136                         cx->type);
137         }
138         snprintf(cx->desc,
139                         ACPI_CX_DESC_LEN, "ACPI FFH MWAIT 0x%x",
140                         cx->address);
141 out:
142         return retval;
143 }
144 
145 int acpi_processor_ffh_cstate_probe(unsigned int cpu,
146                 struct acpi_processor_cx *cx, struct acpi_power_register *reg)
147 {
148         struct cstate_entry *percpu_entry;
149         struct cpuinfo_x86 *c = &cpu_data(cpu);
150         long retval;
151 
152         if (!cpu_cstate_entry || c->cpuid_level < CPUID_MWAIT_LEAF)
153                 return -1;
154 
155         if (reg->bit_offset != NATIVE_CSTATE_BEYOND_HALT)
156                 return -1;
157 
158         percpu_entry = per_cpu_ptr(cpu_cstate_entry, cpu);
159         percpu_entry->states[cx->index].eax = 0;
160         percpu_entry->states[cx->index].ecx = 0;
161 
162         /* Make sure we are running on right CPU */
163 
164         retval = work_on_cpu(cpu, acpi_processor_ffh_cstate_probe_cpu, cx);
165         if (retval == 0) {
166                 /* Use the hint in CST */
167                 percpu_entry->states[cx->index].eax = cx->address;
168                 percpu_entry->states[cx->index].ecx = MWAIT_ECX_INTERRUPT_BREAK;
169         }
170 
171         /*
172          * For _CST FFH on Intel, if GAS.access_size bit 1 is cleared,
173          * then we should skip checking BM_STS for this C-state.
174          * ref: "Intel Processor Vendor-Specific ACPI Interface Specification"
175          */
176         if ((c->x86_vendor == X86_VENDOR_INTEL) && !(reg->access_size & 0x2))
177                 cx->bm_sts_skip = 1;
178 
179         return retval;
180 }
181 EXPORT_SYMBOL_GPL(acpi_processor_ffh_cstate_probe);
182 
183 void __cpuidle acpi_processor_ffh_cstate_enter(struct acpi_processor_cx *cx)
184 {
185         unsigned int cpu = smp_processor_id();
186         struct cstate_entry *percpu_entry;
187 
188         percpu_entry = per_cpu_ptr(cpu_cstate_entry, cpu);
189         mwait_idle_with_hints(percpu_entry->states[cx->index].eax,
190                               percpu_entry->states[cx->index].ecx);
191 }
192 EXPORT_SYMBOL_GPL(acpi_processor_ffh_cstate_enter);
193 
194 static int __init ffh_cstate_init(void)
195 {
196         struct cpuinfo_x86 *c = &boot_cpu_data;
197 
198         if (c->x86_vendor != X86_VENDOR_INTEL &&
199             c->x86_vendor != X86_VENDOR_AMD)
200                 return -1;
201 
202         cpu_cstate_entry = alloc_percpu(struct cstate_entry);
203         return 0;
204 }
205 
206 static void __exit ffh_cstate_exit(void)
207 {
208         free_percpu(cpu_cstate_entry);
209         cpu_cstate_entry = NULL;
210 }
211 
212 arch_initcall(ffh_cstate_init);
213 __exitcall(ffh_cstate_exit);
214 

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