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TOMOYO Linux Cross Reference
Linux/arch/x86/kernel/aperture_64.c

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  1 // SPDX-License-Identifier: GPL-2.0
  2 /*
  3  * Firmware replacement code.
  4  *
  5  * Work around broken BIOSes that don't set an aperture, only set the
  6  * aperture in the AGP bridge, or set too small aperture.
  7  *
  8  * If all fails map the aperture over some low memory.  This is cheaper than
  9  * doing bounce buffering. The memory is lost. This is done at early boot
 10  * because only the bootmem allocator can allocate 32+MB.
 11  *
 12  * Copyright 2002 Andi Kleen, SuSE Labs.
 13  */
 14 #define pr_fmt(fmt) "AGP: " fmt
 15 
 16 #include <linux/kernel.h>
 17 #include <linux/types.h>
 18 #include <linux/init.h>
 19 #include <linux/memblock.h>
 20 #include <linux/mmzone.h>
 21 #include <linux/pci_ids.h>
 22 #include <linux/pci.h>
 23 #include <linux/bitops.h>
 24 #include <linux/suspend.h>
 25 #include <asm/e820/api.h>
 26 #include <asm/io.h>
 27 #include <asm/iommu.h>
 28 #include <asm/gart.h>
 29 #include <asm/pci-direct.h>
 30 #include <asm/dma.h>
 31 #include <asm/amd_nb.h>
 32 #include <asm/x86_init.h>
 33 #include <linux/crash_dump.h>
 34 
 35 /*
 36  * Using 512M as goal, in case kexec will load kernel_big
 37  * that will do the on-position decompress, and could overlap with
 38  * with the gart aperture that is used.
 39  * Sequence:
 40  * kernel_small
 41  * ==> kexec (with kdump trigger path or gart still enabled)
 42  * ==> kernel_small (gart area become e820_reserved)
 43  * ==> kexec (with kdump trigger path or gart still enabled)
 44  * ==> kerne_big (uncompressed size will be big than 64M or 128M)
 45  * So don't use 512M below as gart iommu, leave the space for kernel
 46  * code for safe.
 47  */
 48 #define GART_MIN_ADDR   (512ULL << 20)
 49 #define GART_MAX_ADDR   (1ULL   << 32)
 50 
 51 int gart_iommu_aperture;
 52 int gart_iommu_aperture_disabled __initdata;
 53 int gart_iommu_aperture_allowed __initdata;
 54 
 55 int fallback_aper_order __initdata = 1; /* 64MB */
 56 int fallback_aper_force __initdata;
 57 
 58 int fix_aperture __initdata = 1;
 59 
 60 #ifdef CONFIG_PROC_VMCORE
 61 /*
 62  * If the first kernel maps the aperture over e820 RAM, the kdump kernel will
 63  * use the same range because it will remain configured in the northbridge.
 64  * Trying to dump this area via /proc/vmcore may crash the machine, so exclude
 65  * it from vmcore.
 66  */
 67 static unsigned long aperture_pfn_start, aperture_page_count;
 68 
 69 static int gart_oldmem_pfn_is_ram(unsigned long pfn)
 70 {
 71         return likely((pfn < aperture_pfn_start) ||
 72                       (pfn >= aperture_pfn_start + aperture_page_count));
 73 }
 74 
 75 static void exclude_from_vmcore(u64 aper_base, u32 aper_order)
 76 {
 77         aperture_pfn_start = aper_base >> PAGE_SHIFT;
 78         aperture_page_count = (32 * 1024 * 1024) << aper_order >> PAGE_SHIFT;
 79         WARN_ON(register_oldmem_pfn_is_ram(&gart_oldmem_pfn_is_ram));
 80 }
 81 #else
 82 static void exclude_from_vmcore(u64 aper_base, u32 aper_order)
 83 {
 84 }
 85 #endif
 86 
 87 /* This code runs before the PCI subsystem is initialized, so just
 88    access the northbridge directly. */
 89 
 90 static u32 __init allocate_aperture(void)
 91 {
 92         u32 aper_size;
 93         unsigned long addr;
 94 
 95         /* aper_size should <= 1G */
 96         if (fallback_aper_order > 5)
 97                 fallback_aper_order = 5;
 98         aper_size = (32 * 1024 * 1024) << fallback_aper_order;
 99 
100         /*
101          * Aperture has to be naturally aligned. This means a 2GB aperture
102          * won't have much chance of finding a place in the lower 4GB of
103          * memory. Unfortunately we cannot move it up because that would
104          * make the IOMMU useless.
105          */
106         addr = memblock_find_in_range(GART_MIN_ADDR, GART_MAX_ADDR,
107                                       aper_size, aper_size);
108         if (!addr) {
109                 pr_err("Cannot allocate aperture memory hole [mem %#010lx-%#010lx] (%uKB)\n",
110                        addr, addr + aper_size - 1, aper_size >> 10);
111                 return 0;
112         }
113         memblock_reserve(addr, aper_size);
114         pr_info("Mapping aperture over RAM [mem %#010lx-%#010lx] (%uKB)\n",
115                 addr, addr + aper_size - 1, aper_size >> 10);
116         register_nosave_region(addr >> PAGE_SHIFT,
117                                (addr+aper_size) >> PAGE_SHIFT);
118 
119         return (u32)addr;
120 }
121 
122 
123 /* Find a PCI capability */
124 static u32 __init find_cap(int bus, int slot, int func, int cap)
125 {
126         int bytes;
127         u8 pos;
128 
129         if (!(read_pci_config_16(bus, slot, func, PCI_STATUS) &
130                                                 PCI_STATUS_CAP_LIST))
131                 return 0;
132 
133         pos = read_pci_config_byte(bus, slot, func, PCI_CAPABILITY_LIST);
134         for (bytes = 0; bytes < 48 && pos >= 0x40; bytes++) {
135                 u8 id;
136 
137                 pos &= ~3;
138                 id = read_pci_config_byte(bus, slot, func, pos+PCI_CAP_LIST_ID);
139                 if (id == 0xff)
140                         break;
141                 if (id == cap)
142                         return pos;
143                 pos = read_pci_config_byte(bus, slot, func,
144                                                 pos+PCI_CAP_LIST_NEXT);
145         }
146         return 0;
147 }
148 
149 /* Read a standard AGPv3 bridge header */
150 static u32 __init read_agp(int bus, int slot, int func, int cap, u32 *order)
151 {
152         u32 apsize;
153         u32 apsizereg;
154         int nbits;
155         u32 aper_low, aper_hi;
156         u64 aper;
157         u32 old_order;
158 
159         pr_info("pci 0000:%02x:%02x:%02x: AGP bridge\n", bus, slot, func);
160         apsizereg = read_pci_config_16(bus, slot, func, cap + 0x14);
161         if (apsizereg == 0xffffffff) {
162                 pr_err("pci 0000:%02x:%02x.%d: APSIZE unreadable\n",
163                        bus, slot, func);
164                 return 0;
165         }
166 
167         /* old_order could be the value from NB gart setting */
168         old_order = *order;
169 
170         apsize = apsizereg & 0xfff;
171         /* Some BIOS use weird encodings not in the AGPv3 table. */
172         if (apsize & 0xff)
173                 apsize |= 0xf00;
174         nbits = hweight16(apsize);
175         *order = 7 - nbits;
176         if ((int)*order < 0) /* < 32MB */
177                 *order = 0;
178 
179         aper_low = read_pci_config(bus, slot, func, 0x10);
180         aper_hi = read_pci_config(bus, slot, func, 0x14);
181         aper = (aper_low & ~((1<<22)-1)) | ((u64)aper_hi << 32);
182 
183         /*
184          * On some sick chips, APSIZE is 0. It means it wants 4G
185          * so let double check that order, and lets trust AMD NB settings:
186          */
187         pr_info("pci 0000:%02x:%02x.%d: AGP aperture [bus addr %#010Lx-%#010Lx] (old size %uMB)\n",
188                 bus, slot, func, aper, aper + (32ULL << (old_order + 20)) - 1,
189                 32 << old_order);
190         if (aper + (32ULL<<(20 + *order)) > 0x100000000ULL) {
191                 pr_info("pci 0000:%02x:%02x.%d: AGP aperture size %uMB (APSIZE %#x) is not right, using settings from NB\n",
192                         bus, slot, func, 32 << *order, apsizereg);
193                 *order = old_order;
194         }
195 
196         pr_info("pci 0000:%02x:%02x.%d: AGP aperture [bus addr %#010Lx-%#010Lx] (%uMB, APSIZE %#x)\n",
197                 bus, slot, func, aper, aper + (32ULL << (*order + 20)) - 1,
198                 32 << *order, apsizereg);
199 
200         if (!aperture_valid(aper, (32*1024*1024) << *order, 32<<20))
201                 return 0;
202         return (u32)aper;
203 }
204 
205 /*
206  * Look for an AGP bridge. Windows only expects the aperture in the
207  * AGP bridge and some BIOS forget to initialize the Northbridge too.
208  * Work around this here.
209  *
210  * Do an PCI bus scan by hand because we're running before the PCI
211  * subsystem.
212  *
213  * All AMD AGP bridges are AGPv3 compliant, so we can do this scan
214  * generically. It's probably overkill to always scan all slots because
215  * the AGP bridges should be always an own bus on the HT hierarchy,
216  * but do it here for future safety.
217  */
218 static u32 __init search_agp_bridge(u32 *order, int *valid_agp)
219 {
220         int bus, slot, func;
221 
222         /* Poor man's PCI discovery */
223         for (bus = 0; bus < 256; bus++) {
224                 for (slot = 0; slot < 32; slot++) {
225                         for (func = 0; func < 8; func++) {
226                                 u32 class, cap;
227                                 u8 type;
228                                 class = read_pci_config(bus, slot, func,
229                                                         PCI_CLASS_REVISION);
230                                 if (class == 0xffffffff)
231                                         break;
232 
233                                 switch (class >> 16) {
234                                 case PCI_CLASS_BRIDGE_HOST:
235                                 case PCI_CLASS_BRIDGE_OTHER: /* needed? */
236                                         /* AGP bridge? */
237                                         cap = find_cap(bus, slot, func,
238                                                         PCI_CAP_ID_AGP);
239                                         if (!cap)
240                                                 break;
241                                         *valid_agp = 1;
242                                         return read_agp(bus, slot, func, cap,
243                                                         order);
244                                 }
245 
246                                 /* No multi-function device? */
247                                 type = read_pci_config_byte(bus, slot, func,
248                                                                PCI_HEADER_TYPE);
249                                 if (!(type & 0x80))
250                                         break;
251                         }
252                 }
253         }
254         pr_info("No AGP bridge found\n");
255 
256         return 0;
257 }
258 
259 static bool gart_fix_e820 __initdata = true;
260 
261 static int __init parse_gart_mem(char *p)
262 {
263         return kstrtobool(p, &gart_fix_e820);
264 }
265 early_param("gart_fix_e820", parse_gart_mem);
266 
267 /*
268  * With kexec/kdump, if the first kernel doesn't shut down the GART and the
269  * second kernel allocates a different GART region, there might be two
270  * overlapping GART regions present:
271  *
272  * - the first still used by the GART initialized in the first kernel.
273  * - (sub-)set of it used as normal RAM by the second kernel.
274  *
275  * which leads to memory corruptions and a kernel panic eventually.
276  *
277  * This can also happen if the BIOS has forgotten to mark the GART region
278  * as reserved.
279  *
280  * Try to update the e820 map to mark that new region as reserved.
281  */
282 void __init early_gart_iommu_check(void)
283 {
284         u32 agp_aper_order = 0;
285         int i, fix, slot, valid_agp = 0;
286         u32 ctl;
287         u32 aper_size = 0, aper_order = 0, last_aper_order = 0;
288         u64 aper_base = 0, last_aper_base = 0;
289         int aper_enabled = 0, last_aper_enabled = 0, last_valid = 0;
290 
291         if (!amd_gart_present())
292                 return;
293 
294         if (!early_pci_allowed())
295                 return;
296 
297         /* This is mostly duplicate of iommu_hole_init */
298         search_agp_bridge(&agp_aper_order, &valid_agp);
299 
300         fix = 0;
301         for (i = 0; amd_nb_bus_dev_ranges[i].dev_limit; i++) {
302                 int bus;
303                 int dev_base, dev_limit;
304 
305                 bus = amd_nb_bus_dev_ranges[i].bus;
306                 dev_base = amd_nb_bus_dev_ranges[i].dev_base;
307                 dev_limit = amd_nb_bus_dev_ranges[i].dev_limit;
308 
309                 for (slot = dev_base; slot < dev_limit; slot++) {
310                         if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00)))
311                                 continue;
312 
313                         ctl = read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL);
314                         aper_enabled = ctl & GARTEN;
315                         aper_order = (ctl >> 1) & 7;
316                         aper_size = (32 * 1024 * 1024) << aper_order;
317                         aper_base = read_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE) & 0x7fff;
318                         aper_base <<= 25;
319 
320                         if (last_valid) {
321                                 if ((aper_order != last_aper_order) ||
322                                     (aper_base != last_aper_base) ||
323                                     (aper_enabled != last_aper_enabled)) {
324                                         fix = 1;
325                                         break;
326                                 }
327                         }
328 
329                         last_aper_order = aper_order;
330                         last_aper_base = aper_base;
331                         last_aper_enabled = aper_enabled;
332                         last_valid = 1;
333                 }
334         }
335 
336         if (!fix && !aper_enabled)
337                 return;
338 
339         if (!aper_base || !aper_size || aper_base + aper_size > 0x100000000UL)
340                 fix = 1;
341 
342         if (gart_fix_e820 && !fix && aper_enabled) {
343                 if (e820__mapped_any(aper_base, aper_base + aper_size,
344                                     E820_TYPE_RAM)) {
345                         /* reserve it, so we can reuse it in second kernel */
346                         pr_info("e820: reserve [mem %#010Lx-%#010Lx] for GART\n",
347                                 aper_base, aper_base + aper_size - 1);
348                         e820__range_add(aper_base, aper_size, E820_TYPE_RESERVED);
349                         e820__update_table_print();
350                 }
351         }
352 
353         if (valid_agp)
354                 return;
355 
356         /* disable them all at first */
357         for (i = 0; i < amd_nb_bus_dev_ranges[i].dev_limit; i++) {
358                 int bus;
359                 int dev_base, dev_limit;
360 
361                 bus = amd_nb_bus_dev_ranges[i].bus;
362                 dev_base = amd_nb_bus_dev_ranges[i].dev_base;
363                 dev_limit = amd_nb_bus_dev_ranges[i].dev_limit;
364 
365                 for (slot = dev_base; slot < dev_limit; slot++) {
366                         if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00)))
367                                 continue;
368 
369                         ctl = read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL);
370                         ctl &= ~GARTEN;
371                         write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl);
372                 }
373         }
374 
375 }
376 
377 static int __initdata printed_gart_size_msg;
378 
379 int __init gart_iommu_hole_init(void)
380 {
381         u32 agp_aper_base = 0, agp_aper_order = 0;
382         u32 aper_size, aper_alloc = 0, aper_order = 0, last_aper_order = 0;
383         u64 aper_base, last_aper_base = 0;
384         int fix, slot, valid_agp = 0;
385         int i, node;
386 
387         if (!amd_gart_present())
388                 return -ENODEV;
389 
390         if (gart_iommu_aperture_disabled || !fix_aperture ||
391             !early_pci_allowed())
392                 return -ENODEV;
393 
394         pr_info("Checking aperture...\n");
395 
396         if (!fallback_aper_force)
397                 agp_aper_base = search_agp_bridge(&agp_aper_order, &valid_agp);
398 
399         fix = 0;
400         node = 0;
401         for (i = 0; i < amd_nb_bus_dev_ranges[i].dev_limit; i++) {
402                 int bus;
403                 int dev_base, dev_limit;
404                 u32 ctl;
405 
406                 bus = amd_nb_bus_dev_ranges[i].bus;
407                 dev_base = amd_nb_bus_dev_ranges[i].dev_base;
408                 dev_limit = amd_nb_bus_dev_ranges[i].dev_limit;
409 
410                 for (slot = dev_base; slot < dev_limit; slot++) {
411                         if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00)))
412                                 continue;
413 
414                         iommu_detected = 1;
415                         gart_iommu_aperture = 1;
416                         x86_init.iommu.iommu_init = gart_iommu_init;
417 
418                         ctl = read_pci_config(bus, slot, 3,
419                                               AMD64_GARTAPERTURECTL);
420 
421                         /*
422                          * Before we do anything else disable the GART. It may
423                          * still be enabled if we boot into a crash-kernel here.
424                          * Reconfiguring the GART while it is enabled could have
425                          * unknown side-effects.
426                          */
427                         ctl &= ~GARTEN;
428                         write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl);
429 
430                         aper_order = (ctl >> 1) & 7;
431                         aper_size = (32 * 1024 * 1024) << aper_order;
432                         aper_base = read_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE) & 0x7fff;
433                         aper_base <<= 25;
434 
435                         pr_info("Node %d: aperture [bus addr %#010Lx-%#010Lx] (%uMB)\n",
436                                 node, aper_base, aper_base + aper_size - 1,
437                                 aper_size >> 20);
438                         node++;
439 
440                         if (!aperture_valid(aper_base, aper_size, 64<<20)) {
441                                 if (valid_agp && agp_aper_base &&
442                                     agp_aper_base == aper_base &&
443                                     agp_aper_order == aper_order) {
444                                         /* the same between two setting from NB and agp */
445                                         if (!no_iommu &&
446                                             max_pfn > MAX_DMA32_PFN &&
447                                             !printed_gart_size_msg) {
448                                                 pr_err("you are using iommu with agp, but GART size is less than 64MB\n");
449                                                 pr_err("please increase GART size in your BIOS setup\n");
450                                                 pr_err("if BIOS doesn't have that option, contact your HW vendor!\n");
451                                                 printed_gart_size_msg = 1;
452                                         }
453                                 } else {
454                                         fix = 1;
455                                         goto out;
456                                 }
457                         }
458 
459                         if ((last_aper_order && aper_order != last_aper_order) ||
460                             (last_aper_base && aper_base != last_aper_base)) {
461                                 fix = 1;
462                                 goto out;
463                         }
464                         last_aper_order = aper_order;
465                         last_aper_base = aper_base;
466                 }
467         }
468 
469 out:
470         if (!fix && !fallback_aper_force) {
471                 if (last_aper_base) {
472                         /*
473                          * If this is the kdump kernel, the first kernel
474                          * may have allocated the range over its e820 RAM
475                          * and fixed up the northbridge
476                          */
477                         exclude_from_vmcore(last_aper_base, last_aper_order);
478 
479                         return 1;
480                 }
481                 return 0;
482         }
483 
484         if (!fallback_aper_force) {
485                 aper_alloc = agp_aper_base;
486                 aper_order = agp_aper_order;
487         }
488 
489         if (aper_alloc) {
490                 /* Got the aperture from the AGP bridge */
491         } else if ((!no_iommu && max_pfn > MAX_DMA32_PFN) ||
492                    force_iommu ||
493                    valid_agp ||
494                    fallback_aper_force) {
495                 pr_info("Your BIOS doesn't leave an aperture memory hole\n");
496                 pr_info("Please enable the IOMMU option in the BIOS setup\n");
497                 pr_info("This costs you %dMB of RAM\n",
498                         32 << fallback_aper_order);
499 
500                 aper_order = fallback_aper_order;
501                 aper_alloc = allocate_aperture();
502                 if (!aper_alloc) {
503                         /*
504                          * Could disable AGP and IOMMU here, but it's
505                          * probably not worth it. But the later users
506                          * cannot deal with bad apertures and turning
507                          * on the aperture over memory causes very
508                          * strange problems, so it's better to panic
509                          * early.
510                          */
511                         panic("Not enough memory for aperture");
512                 }
513         } else {
514                 return 0;
515         }
516 
517         /*
518          * If this is the kdump kernel _and_ the first kernel did not
519          * configure the aperture in the northbridge, this range may
520          * overlap with the first kernel's memory. We can't access the
521          * range through vmcore even though it should be part of the dump.
522          */
523         exclude_from_vmcore(aper_alloc, aper_order);
524 
525         /* Fix up the north bridges */
526         for (i = 0; i < amd_nb_bus_dev_ranges[i].dev_limit; i++) {
527                 int bus, dev_base, dev_limit;
528 
529                 /*
530                  * Don't enable translation yet but enable GART IO and CPU
531                  * accesses and set DISTLBWALKPRB since GART table memory is UC.
532                  */
533                 u32 ctl = aper_order << 1;
534 
535                 bus = amd_nb_bus_dev_ranges[i].bus;
536                 dev_base = amd_nb_bus_dev_ranges[i].dev_base;
537                 dev_limit = amd_nb_bus_dev_ranges[i].dev_limit;
538                 for (slot = dev_base; slot < dev_limit; slot++) {
539                         if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00)))
540                                 continue;
541 
542                         write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl);
543                         write_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE, aper_alloc >> 25);
544                 }
545         }
546 
547         set_up_gart_resume(aper_order, aper_alloc);
548 
549         return 1;
550 }
551 

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