~ [ source navigation ] ~ [ diff markup ] ~ [ identifier search ] ~

TOMOYO Linux Cross Reference
Linux/arch/x86/kernel/apic/apic.c

Version: ~ [ linux-5.9.1 ] ~ [ linux-5.8.16 ] ~ [ linux-5.7.19 ] ~ [ linux-5.6.19 ] ~ [ linux-5.5.19 ] ~ [ linux-5.4.72 ] ~ [ linux-5.3.18 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.152 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.202 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.240 ] ~ [ linux-4.8.17 ] ~ [ linux-4.7.10 ] ~ [ linux-4.6.7 ] ~ [ linux-4.5.7 ] ~ [ linux-4.4.240 ] ~ [ linux-4.3.6 ] ~ [ linux-4.2.8 ] ~ [ linux-4.1.52 ] ~ [ linux-4.0.9 ] ~ [ linux-3.19.8 ] ~ [ linux-3.18.140 ] ~ [ linux-3.17.8 ] ~ [ linux-3.16.85 ] ~ [ linux-3.15.10 ] ~ [ linux-3.14.79 ] ~ [ linux-3.13.11 ] ~ [ linux-3.12.74 ] ~ [ linux-3.11.10 ] ~ [ linux-3.10.108 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.5 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 /*
  2  *      Local APIC handling, local APIC timers
  3  *
  4  *      (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
  5  *
  6  *      Fixes
  7  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  8  *                                      thanks to Eric Gilmore
  9  *                                      and Rolf G. Tews
 10  *                                      for testing these extensively.
 11  *      Maciej W. Rozycki       :       Various updates and fixes.
 12  *      Mikael Pettersson       :       Power Management for UP-APIC.
 13  *      Pavel Machek and
 14  *      Mikael Pettersson       :       PM converted to driver model.
 15  */
 16 
 17 #include <linux/perf_event.h>
 18 #include <linux/kernel_stat.h>
 19 #include <linux/mc146818rtc.h>
 20 #include <linux/acpi_pmtmr.h>
 21 #include <linux/clockchips.h>
 22 #include <linux/interrupt.h>
 23 #include <linux/bootmem.h>
 24 #include <linux/ftrace.h>
 25 #include <linux/ioport.h>
 26 #include <linux/module.h>
 27 #include <linux/syscore_ops.h>
 28 #include <linux/delay.h>
 29 #include <linux/timex.h>
 30 #include <linux/i8253.h>
 31 #include <linux/dmar.h>
 32 #include <linux/init.h>
 33 #include <linux/cpu.h>
 34 #include <linux/dmi.h>
 35 #include <linux/smp.h>
 36 #include <linux/mm.h>
 37 
 38 #include <asm/irq_remapping.h>
 39 #include <asm/perf_event.h>
 40 #include <asm/x86_init.h>
 41 #include <asm/pgalloc.h>
 42 #include <linux/atomic.h>
 43 #include <asm/mpspec.h>
 44 #include <asm/i8259.h>
 45 #include <asm/proto.h>
 46 #include <asm/apic.h>
 47 #include <asm/io_apic.h>
 48 #include <asm/desc.h>
 49 #include <asm/hpet.h>
 50 #include <asm/idle.h>
 51 #include <asm/mtrr.h>
 52 #include <asm/time.h>
 53 #include <asm/smp.h>
 54 #include <asm/mce.h>
 55 #include <asm/tsc.h>
 56 #include <asm/hypervisor.h>
 57 
 58 unsigned int num_processors;
 59 
 60 unsigned disabled_cpus __cpuinitdata;
 61 
 62 /* Processor that is doing the boot up */
 63 unsigned int boot_cpu_physical_apicid = -1U;
 64 
 65 /*
 66  * The highest APIC ID seen during enumeration.
 67  */
 68 unsigned int max_physical_apicid;
 69 
 70 /*
 71  * Bitmask of physically existing CPUs:
 72  */
 73 physid_mask_t phys_cpu_present_map;
 74 
 75 /*
 76  * Map cpu index to physical APIC ID
 77  */
 78 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID);
 79 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID);
 80 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid);
 81 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
 82 
 83 #ifdef CONFIG_X86_32
 84 
 85 /*
 86  * On x86_32, the mapping between cpu and logical apicid may vary
 87  * depending on apic in use.  The following early percpu variable is
 88  * used for the mapping.  This is where the behaviors of x86_64 and 32
 89  * actually diverge.  Let's keep it ugly for now.
 90  */
 91 DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID);
 92 
 93 /* Local APIC was disabled by the BIOS and enabled by the kernel */
 94 static int enabled_via_apicbase;
 95 
 96 /*
 97  * Handle interrupt mode configuration register (IMCR).
 98  * This register controls whether the interrupt signals
 99  * that reach the BSP come from the master PIC or from the
100  * local APIC. Before entering Symmetric I/O Mode, either
101  * the BIOS or the operating system must switch out of
102  * PIC Mode by changing the IMCR.
103  */
104 static inline void imcr_pic_to_apic(void)
105 {
106         /* select IMCR register */
107         outb(0x70, 0x22);
108         /* NMI and 8259 INTR go through APIC */
109         outb(0x01, 0x23);
110 }
111 
112 static inline void imcr_apic_to_pic(void)
113 {
114         /* select IMCR register */
115         outb(0x70, 0x22);
116         /* NMI and 8259 INTR go directly to BSP */
117         outb(0x00, 0x23);
118 }
119 #endif
120 
121 /*
122  * Knob to control our willingness to enable the local APIC.
123  *
124  * +1=force-enable
125  */
126 static int force_enable_local_apic __initdata;
127 /*
128  * APIC command line parameters
129  */
130 static int __init parse_lapic(char *arg)
131 {
132         if (config_enabled(CONFIG_X86_32) && !arg)
133                 force_enable_local_apic = 1;
134         else if (arg && !strncmp(arg, "notscdeadline", 13))
135                 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
136         return 0;
137 }
138 early_param("lapic", parse_lapic);
139 
140 #ifdef CONFIG_X86_64
141 static int apic_calibrate_pmtmr __initdata;
142 static __init int setup_apicpmtimer(char *s)
143 {
144         apic_calibrate_pmtmr = 1;
145         notsc_setup(NULL);
146         return 0;
147 }
148 __setup("apicpmtimer", setup_apicpmtimer);
149 #endif
150 
151 int x2apic_mode;
152 #ifdef CONFIG_X86_X2APIC
153 /* x2apic enabled before OS handover */
154 int x2apic_preenabled;
155 static int x2apic_disabled;
156 static int nox2apic;
157 static __init int setup_nox2apic(char *str)
158 {
159         if (x2apic_enabled()) {
160                 int apicid = native_apic_msr_read(APIC_ID);
161 
162                 if (apicid >= 255) {
163                         pr_warning("Apicid: %08x, cannot enforce nox2apic\n",
164                                    apicid);
165                         return 0;
166                 }
167 
168                 pr_warning("x2apic already enabled. will disable it\n");
169         } else
170                 setup_clear_cpu_cap(X86_FEATURE_X2APIC);
171 
172         nox2apic = 1;
173 
174         return 0;
175 }
176 early_param("nox2apic", setup_nox2apic);
177 #endif
178 
179 unsigned long mp_lapic_addr;
180 int disable_apic;
181 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
182 static int disable_apic_timer __initdata;
183 /* Local APIC timer works in C2 */
184 int local_apic_timer_c2_ok;
185 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
186 
187 int first_system_vector = 0xfe;
188 
189 /*
190  * Debug level, exported for io_apic.c
191  */
192 unsigned int apic_verbosity;
193 
194 int pic_mode;
195 
196 /* Have we found an MP table */
197 int smp_found_config;
198 
199 static struct resource lapic_resource = {
200         .name = "Local APIC",
201         .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
202 };
203 
204 unsigned int lapic_timer_frequency = 0;
205 
206 static void apic_pm_activate(void);
207 
208 static unsigned long apic_phys;
209 
210 /*
211  * Get the LAPIC version
212  */
213 static inline int lapic_get_version(void)
214 {
215         return GET_APIC_VERSION(apic_read(APIC_LVR));
216 }
217 
218 /*
219  * Check, if the APIC is integrated or a separate chip
220  */
221 static inline int lapic_is_integrated(void)
222 {
223 #ifdef CONFIG_X86_64
224         return 1;
225 #else
226         return APIC_INTEGRATED(lapic_get_version());
227 #endif
228 }
229 
230 /*
231  * Check, whether this is a modern or a first generation APIC
232  */
233 static int modern_apic(void)
234 {
235         /* AMD systems use old APIC versions, so check the CPU */
236         if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
237             boot_cpu_data.x86 >= 0xf)
238                 return 1;
239         return lapic_get_version() >= 0x14;
240 }
241 
242 /*
243  * right after this call apic become NOOP driven
244  * so apic->write/read doesn't do anything
245  */
246 static void __init apic_disable(void)
247 {
248         pr_info("APIC: switched to apic NOOP\n");
249         apic = &apic_noop;
250 }
251 
252 void native_apic_wait_icr_idle(void)
253 {
254         while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
255                 cpu_relax();
256 }
257 
258 u32 native_safe_apic_wait_icr_idle(void)
259 {
260         u32 send_status;
261         int timeout;
262 
263         timeout = 0;
264         do {
265                 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
266                 if (!send_status)
267                         break;
268                 inc_irq_stat(icr_read_retry_count);
269                 udelay(100);
270         } while (timeout++ < 1000);
271 
272         return send_status;
273 }
274 
275 void native_apic_icr_write(u32 low, u32 id)
276 {
277         apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
278         apic_write(APIC_ICR, low);
279 }
280 
281 u64 native_apic_icr_read(void)
282 {
283         u32 icr1, icr2;
284 
285         icr2 = apic_read(APIC_ICR2);
286         icr1 = apic_read(APIC_ICR);
287 
288         return icr1 | ((u64)icr2 << 32);
289 }
290 
291 #ifdef CONFIG_X86_32
292 /**
293  * get_physical_broadcast - Get number of physical broadcast IDs
294  */
295 int get_physical_broadcast(void)
296 {
297         return modern_apic() ? 0xff : 0xf;
298 }
299 #endif
300 
301 /**
302  * lapic_get_maxlvt - get the maximum number of local vector table entries
303  */
304 int lapic_get_maxlvt(void)
305 {
306         unsigned int v;
307 
308         v = apic_read(APIC_LVR);
309         /*
310          * - we always have APIC integrated on 64bit mode
311          * - 82489DXs do not report # of LVT entries
312          */
313         return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
314 }
315 
316 /*
317  * Local APIC timer
318  */
319 
320 /* Clock divisor */
321 #define APIC_DIVISOR 16
322 #define TSC_DIVISOR  32
323 
324 /*
325  * This function sets up the local APIC timer, with a timeout of
326  * 'clocks' APIC bus clock. During calibration we actually call
327  * this function twice on the boot CPU, once with a bogus timeout
328  * value, second time for real. The other (noncalibrating) CPUs
329  * call this function only once, with the real, calibrated value.
330  *
331  * We do reads before writes even if unnecessary, to get around the
332  * P5 APIC double write bug.
333  */
334 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
335 {
336         unsigned int lvtt_value, tmp_value;
337 
338         lvtt_value = LOCAL_TIMER_VECTOR;
339         if (!oneshot)
340                 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
341         else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
342                 lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE;
343 
344         if (!lapic_is_integrated())
345                 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
346 
347         if (!irqen)
348                 lvtt_value |= APIC_LVT_MASKED;
349 
350         apic_write(APIC_LVTT, lvtt_value);
351 
352         if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) {
353                 /*
354                  * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode,
355                  * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized.
356                  * According to Intel, MFENCE can do the serialization here.
357                  */
358                 asm volatile("mfence" : : : "memory");
359 
360                 printk_once(KERN_DEBUG "TSC deadline timer enabled\n");
361                 return;
362         }
363 
364         /*
365          * Divide PICLK by 16
366          */
367         tmp_value = apic_read(APIC_TDCR);
368         apic_write(APIC_TDCR,
369                 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
370                 APIC_TDR_DIV_16);
371 
372         if (!oneshot)
373                 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
374 }
375 
376 /*
377  * Setup extended LVT, AMD specific
378  *
379  * Software should use the LVT offsets the BIOS provides.  The offsets
380  * are determined by the subsystems using it like those for MCE
381  * threshold or IBS.  On K8 only offset 0 (APIC500) and MCE interrupts
382  * are supported. Beginning with family 10h at least 4 offsets are
383  * available.
384  *
385  * Since the offsets must be consistent for all cores, we keep track
386  * of the LVT offsets in software and reserve the offset for the same
387  * vector also to be used on other cores. An offset is freed by
388  * setting the entry to APIC_EILVT_MASKED.
389  *
390  * If the BIOS is right, there should be no conflicts. Otherwise a
391  * "[Firmware Bug]: ..." error message is generated. However, if
392  * software does not properly determines the offsets, it is not
393  * necessarily a BIOS bug.
394  */
395 
396 static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX];
397 
398 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new)
399 {
400         return (old & APIC_EILVT_MASKED)
401                 || (new == APIC_EILVT_MASKED)
402                 || ((new & ~APIC_EILVT_MASKED) == old);
403 }
404 
405 static unsigned int reserve_eilvt_offset(int offset, unsigned int new)
406 {
407         unsigned int rsvd, vector;
408 
409         if (offset >= APIC_EILVT_NR_MAX)
410                 return ~0;
411 
412         rsvd = atomic_read(&eilvt_offsets[offset]);
413         do {
414                 vector = rsvd & ~APIC_EILVT_MASKED;     /* 0: unassigned */
415                 if (vector && !eilvt_entry_is_changeable(vector, new))
416                         /* may not change if vectors are different */
417                         return rsvd;
418                 rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new);
419         } while (rsvd != new);
420 
421         rsvd &= ~APIC_EILVT_MASKED;
422         if (rsvd && rsvd != vector)
423                 pr_info("LVT offset %d assigned for vector 0x%02x\n",
424                         offset, rsvd);
425 
426         return new;
427 }
428 
429 /*
430  * If mask=1, the LVT entry does not generate interrupts while mask=0
431  * enables the vector. See also the BKDGs. Must be called with
432  * preemption disabled.
433  */
434 
435 int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask)
436 {
437         unsigned long reg = APIC_EILVTn(offset);
438         unsigned int new, old, reserved;
439 
440         new = (mask << 16) | (msg_type << 8) | vector;
441         old = apic_read(reg);
442         reserved = reserve_eilvt_offset(offset, new);
443 
444         if (reserved != new) {
445                 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
446                        "vector 0x%x, but the register is already in use for "
447                        "vector 0x%x on another cpu\n",
448                        smp_processor_id(), reg, offset, new, reserved);
449                 return -EINVAL;
450         }
451 
452         if (!eilvt_entry_is_changeable(old, new)) {
453                 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
454                        "vector 0x%x, but the register is already in use for "
455                        "vector 0x%x on this cpu\n",
456                        smp_processor_id(), reg, offset, new, old);
457                 return -EBUSY;
458         }
459 
460         apic_write(reg, new);
461 
462         return 0;
463 }
464 EXPORT_SYMBOL_GPL(setup_APIC_eilvt);
465 
466 /*
467  * Program the next event, relative to now
468  */
469 static int lapic_next_event(unsigned long delta,
470                             struct clock_event_device *evt)
471 {
472         apic_write(APIC_TMICT, delta);
473         return 0;
474 }
475 
476 static int lapic_next_deadline(unsigned long delta,
477                                struct clock_event_device *evt)
478 {
479         u64 tsc;
480 
481         rdtscll(tsc);
482         wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR));
483         return 0;
484 }
485 
486 /*
487  * Setup the lapic timer in periodic or oneshot mode
488  */
489 static void lapic_timer_setup(enum clock_event_mode mode,
490                               struct clock_event_device *evt)
491 {
492         unsigned long flags;
493         unsigned int v;
494 
495         /* Lapic used as dummy for broadcast ? */
496         if (evt->features & CLOCK_EVT_FEAT_DUMMY)
497                 return;
498 
499         local_irq_save(flags);
500 
501         switch (mode) {
502         case CLOCK_EVT_MODE_PERIODIC:
503         case CLOCK_EVT_MODE_ONESHOT:
504                 __setup_APIC_LVTT(lapic_timer_frequency,
505                                   mode != CLOCK_EVT_MODE_PERIODIC, 1);
506                 break;
507         case CLOCK_EVT_MODE_UNUSED:
508         case CLOCK_EVT_MODE_SHUTDOWN:
509                 v = apic_read(APIC_LVTT);
510                 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
511                 apic_write(APIC_LVTT, v);
512                 apic_write(APIC_TMICT, 0);
513                 break;
514         case CLOCK_EVT_MODE_RESUME:
515                 /* Nothing to do here */
516                 break;
517         }
518 
519         local_irq_restore(flags);
520 }
521 
522 /*
523  * Local APIC timer broadcast function
524  */
525 static void lapic_timer_broadcast(const struct cpumask *mask)
526 {
527 #ifdef CONFIG_SMP
528         apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
529 #endif
530 }
531 
532 
533 /*
534  * The local apic timer can be used for any function which is CPU local.
535  */
536 static struct clock_event_device lapic_clockevent = {
537         .name           = "lapic",
538         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
539                         | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
540         .shift          = 32,
541         .set_mode       = lapic_timer_setup,
542         .set_next_event = lapic_next_event,
543         .broadcast      = lapic_timer_broadcast,
544         .rating         = 100,
545         .irq            = -1,
546 };
547 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
548 
549 /*
550  * Setup the local APIC timer for this CPU. Copy the initialized values
551  * of the boot CPU and register the clock event in the framework.
552  */
553 static void __cpuinit setup_APIC_timer(void)
554 {
555         struct clock_event_device *levt = &__get_cpu_var(lapic_events);
556 
557         if (this_cpu_has(X86_FEATURE_ARAT)) {
558                 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP;
559                 /* Make LAPIC timer preferrable over percpu HPET */
560                 lapic_clockevent.rating = 150;
561         }
562 
563         memcpy(levt, &lapic_clockevent, sizeof(*levt));
564         levt->cpumask = cpumask_of(smp_processor_id());
565 
566         if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) {
567                 levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC |
568                                     CLOCK_EVT_FEAT_DUMMY);
569                 levt->set_next_event = lapic_next_deadline;
570                 clockevents_config_and_register(levt,
571                                                 (tsc_khz / TSC_DIVISOR) * 1000,
572                                                 0xF, ~0UL);
573         } else
574                 clockevents_register_device(levt);
575 }
576 
577 /*
578  * In this functions we calibrate APIC bus clocks to the external timer.
579  *
580  * We want to do the calibration only once since we want to have local timer
581  * irqs syncron. CPUs connected by the same APIC bus have the very same bus
582  * frequency.
583  *
584  * This was previously done by reading the PIT/HPET and waiting for a wrap
585  * around to find out, that a tick has elapsed. I have a box, where the PIT
586  * readout is broken, so it never gets out of the wait loop again. This was
587  * also reported by others.
588  *
589  * Monitoring the jiffies value is inaccurate and the clockevents
590  * infrastructure allows us to do a simple substitution of the interrupt
591  * handler.
592  *
593  * The calibration routine also uses the pm_timer when possible, as the PIT
594  * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
595  * back to normal later in the boot process).
596  */
597 
598 #define LAPIC_CAL_LOOPS         (HZ/10)
599 
600 static __initdata int lapic_cal_loops = -1;
601 static __initdata long lapic_cal_t1, lapic_cal_t2;
602 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
603 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
604 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
605 
606 /*
607  * Temporary interrupt handler.
608  */
609 static void __init lapic_cal_handler(struct clock_event_device *dev)
610 {
611         unsigned long long tsc = 0;
612         long tapic = apic_read(APIC_TMCCT);
613         unsigned long pm = acpi_pm_read_early();
614 
615         if (cpu_has_tsc)
616                 rdtscll(tsc);
617 
618         switch (lapic_cal_loops++) {
619         case 0:
620                 lapic_cal_t1 = tapic;
621                 lapic_cal_tsc1 = tsc;
622                 lapic_cal_pm1 = pm;
623                 lapic_cal_j1 = jiffies;
624                 break;
625 
626         case LAPIC_CAL_LOOPS:
627                 lapic_cal_t2 = tapic;
628                 lapic_cal_tsc2 = tsc;
629                 if (pm < lapic_cal_pm1)
630                         pm += ACPI_PM_OVRRUN;
631                 lapic_cal_pm2 = pm;
632                 lapic_cal_j2 = jiffies;
633                 break;
634         }
635 }
636 
637 static int __init
638 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc)
639 {
640         const long pm_100ms = PMTMR_TICKS_PER_SEC / 10;
641         const long pm_thresh = pm_100ms / 100;
642         unsigned long mult;
643         u64 res;
644 
645 #ifndef CONFIG_X86_PM_TIMER
646         return -1;
647 #endif
648 
649         apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm);
650 
651         /* Check, if the PM timer is available */
652         if (!deltapm)
653                 return -1;
654 
655         mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
656 
657         if (deltapm > (pm_100ms - pm_thresh) &&
658             deltapm < (pm_100ms + pm_thresh)) {
659                 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n");
660                 return 0;
661         }
662 
663         res = (((u64)deltapm) *  mult) >> 22;
664         do_div(res, 1000000);
665         pr_warning("APIC calibration not consistent "
666                    "with PM-Timer: %ldms instead of 100ms\n",(long)res);
667 
668         /* Correct the lapic counter value */
669         res = (((u64)(*delta)) * pm_100ms);
670         do_div(res, deltapm);
671         pr_info("APIC delta adjusted to PM-Timer: "
672                 "%lu (%ld)\n", (unsigned long)res, *delta);
673         *delta = (long)res;
674 
675         /* Correct the tsc counter value */
676         if (cpu_has_tsc) {
677                 res = (((u64)(*deltatsc)) * pm_100ms);
678                 do_div(res, deltapm);
679                 apic_printk(APIC_VERBOSE, "TSC delta adjusted to "
680                                           "PM-Timer: %lu (%ld)\n",
681                                         (unsigned long)res, *deltatsc);
682                 *deltatsc = (long)res;
683         }
684 
685         return 0;
686 }
687 
688 static int __init calibrate_APIC_clock(void)
689 {
690         struct clock_event_device *levt = &__get_cpu_var(lapic_events);
691         void (*real_handler)(struct clock_event_device *dev);
692         unsigned long deltaj;
693         long delta, deltatsc;
694         int pm_referenced = 0;
695 
696         /**
697          * check if lapic timer has already been calibrated by platform
698          * specific routine, such as tsc calibration code. if so, we just fill
699          * in the clockevent structure and return.
700          */
701 
702         if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) {
703                 return 0;
704         } else if (lapic_timer_frequency) {
705                 apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n",
706                                 lapic_timer_frequency);
707                 lapic_clockevent.mult = div_sc(lapic_timer_frequency/APIC_DIVISOR,
708                                         TICK_NSEC, lapic_clockevent.shift);
709                 lapic_clockevent.max_delta_ns =
710                         clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
711                 lapic_clockevent.min_delta_ns =
712                         clockevent_delta2ns(0xF, &lapic_clockevent);
713                 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
714                 return 0;
715         }
716 
717         apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
718                     "calibrating APIC timer ...\n");
719 
720         local_irq_disable();
721 
722         /* Replace the global interrupt handler */
723         real_handler = global_clock_event->event_handler;
724         global_clock_event->event_handler = lapic_cal_handler;
725 
726         /*
727          * Setup the APIC counter to maximum. There is no way the lapic
728          * can underflow in the 100ms detection time frame
729          */
730         __setup_APIC_LVTT(0xffffffff, 0, 0);
731 
732         /* Let the interrupts run */
733         local_irq_enable();
734 
735         while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
736                 cpu_relax();
737 
738         local_irq_disable();
739 
740         /* Restore the real event handler */
741         global_clock_event->event_handler = real_handler;
742 
743         /* Build delta t1-t2 as apic timer counts down */
744         delta = lapic_cal_t1 - lapic_cal_t2;
745         apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
746 
747         deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
748 
749         /* we trust the PM based calibration if possible */
750         pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,
751                                         &delta, &deltatsc);
752 
753         /* Calculate the scaled math multiplication factor */
754         lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
755                                        lapic_clockevent.shift);
756         lapic_clockevent.max_delta_ns =
757                 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent);
758         lapic_clockevent.min_delta_ns =
759                 clockevent_delta2ns(0xF, &lapic_clockevent);
760 
761         lapic_timer_frequency = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
762 
763         apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
764         apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult);
765         apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
766                     lapic_timer_frequency);
767 
768         if (cpu_has_tsc) {
769                 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
770                             "%ld.%04ld MHz.\n",
771                             (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ),
772                             (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ));
773         }
774 
775         apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
776                     "%u.%04u MHz.\n",
777                     lapic_timer_frequency / (1000000 / HZ),
778                     lapic_timer_frequency % (1000000 / HZ));
779 
780         /*
781          * Do a sanity check on the APIC calibration result
782          */
783         if (lapic_timer_frequency < (1000000 / HZ)) {
784                 local_irq_enable();
785                 pr_warning("APIC frequency too slow, disabling apic timer\n");
786                 return -1;
787         }
788 
789         levt->features &= ~CLOCK_EVT_FEAT_DUMMY;
790 
791         /*
792          * PM timer calibration failed or not turned on
793          * so lets try APIC timer based calibration
794          */
795         if (!pm_referenced) {
796                 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
797 
798                 /*
799                  * Setup the apic timer manually
800                  */
801                 levt->event_handler = lapic_cal_handler;
802                 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt);
803                 lapic_cal_loops = -1;
804 
805                 /* Let the interrupts run */
806                 local_irq_enable();
807 
808                 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
809                         cpu_relax();
810 
811                 /* Stop the lapic timer */
812                 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt);
813 
814                 /* Jiffies delta */
815                 deltaj = lapic_cal_j2 - lapic_cal_j1;
816                 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
817 
818                 /* Check, if the jiffies result is consistent */
819                 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
820                         apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
821                 else
822                         levt->features |= CLOCK_EVT_FEAT_DUMMY;
823         } else
824                 local_irq_enable();
825 
826         if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
827                 pr_warning("APIC timer disabled due to verification failure\n");
828                         return -1;
829         }
830 
831         return 0;
832 }
833 
834 /*
835  * Setup the boot APIC
836  *
837  * Calibrate and verify the result.
838  */
839 void __init setup_boot_APIC_clock(void)
840 {
841         /*
842          * The local apic timer can be disabled via the kernel
843          * commandline or from the CPU detection code. Register the lapic
844          * timer as a dummy clock event source on SMP systems, so the
845          * broadcast mechanism is used. On UP systems simply ignore it.
846          */
847         if (disable_apic_timer) {
848                 pr_info("Disabling APIC timer\n");
849                 /* No broadcast on UP ! */
850                 if (num_possible_cpus() > 1) {
851                         lapic_clockevent.mult = 1;
852                         setup_APIC_timer();
853                 }
854                 return;
855         }
856 
857         if (calibrate_APIC_clock()) {
858                 /* No broadcast on UP ! */
859                 if (num_possible_cpus() > 1)
860                         setup_APIC_timer();
861                 return;
862         }
863 
864         /*
865          * If nmi_watchdog is set to IO_APIC, we need the
866          * PIT/HPET going.  Otherwise register lapic as a dummy
867          * device.
868          */
869         lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
870 
871         /* Setup the lapic or request the broadcast */
872         setup_APIC_timer();
873 }
874 
875 void __cpuinit setup_secondary_APIC_clock(void)
876 {
877         setup_APIC_timer();
878 }
879 
880 /*
881  * The guts of the apic timer interrupt
882  */
883 static void local_apic_timer_interrupt(void)
884 {
885         int cpu = smp_processor_id();
886         struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
887 
888         /*
889          * Normally we should not be here till LAPIC has been initialized but
890          * in some cases like kdump, its possible that there is a pending LAPIC
891          * timer interrupt from previous kernel's context and is delivered in
892          * new kernel the moment interrupts are enabled.
893          *
894          * Interrupts are enabled early and LAPIC is setup much later, hence
895          * its possible that when we get here evt->event_handler is NULL.
896          * Check for event_handler being NULL and discard the interrupt as
897          * spurious.
898          */
899         if (!evt->event_handler) {
900                 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu);
901                 /* Switch it off */
902                 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
903                 return;
904         }
905 
906         /*
907          * the NMI deadlock-detector uses this.
908          */
909         inc_irq_stat(apic_timer_irqs);
910 
911         evt->event_handler(evt);
912 }
913 
914 /*
915  * Local APIC timer interrupt. This is the most natural way for doing
916  * local interrupts, but local timer interrupts can be emulated by
917  * broadcast interrupts too. [in case the hw doesn't support APIC timers]
918  *
919  * [ if a single-CPU system runs an SMP kernel then we call the local
920  *   interrupt as well. Thus we cannot inline the local irq ... ]
921  */
922 void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs)
923 {
924         struct pt_regs *old_regs = set_irq_regs(regs);
925 
926         /*
927          * NOTE! We'd better ACK the irq immediately,
928          * because timer handling can be slow.
929          */
930         ack_APIC_irq();
931         /*
932          * update_process_times() expects us to have done irq_enter().
933          * Besides, if we don't timer interrupts ignore the global
934          * interrupt lock, which is the WrongThing (tm) to do.
935          */
936         irq_enter();
937         exit_idle();
938         local_apic_timer_interrupt();
939         irq_exit();
940 
941         set_irq_regs(old_regs);
942 }
943 
944 int setup_profiling_timer(unsigned int multiplier)
945 {
946         return -EINVAL;
947 }
948 
949 /*
950  * Local APIC start and shutdown
951  */
952 
953 /**
954  * clear_local_APIC - shutdown the local APIC
955  *
956  * This is called, when a CPU is disabled and before rebooting, so the state of
957  * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
958  * leftovers during boot.
959  */
960 void clear_local_APIC(void)
961 {
962         int maxlvt;
963         u32 v;
964 
965         /* APIC hasn't been mapped yet */
966         if (!x2apic_mode && !apic_phys)
967                 return;
968 
969         maxlvt = lapic_get_maxlvt();
970         /*
971          * Masking an LVT entry can trigger a local APIC error
972          * if the vector is zero. Mask LVTERR first to prevent this.
973          */
974         if (maxlvt >= 3) {
975                 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
976                 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
977         }
978         /*
979          * Careful: we have to set masks only first to deassert
980          * any level-triggered sources.
981          */
982         v = apic_read(APIC_LVTT);
983         apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
984         v = apic_read(APIC_LVT0);
985         apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
986         v = apic_read(APIC_LVT1);
987         apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
988         if (maxlvt >= 4) {
989                 v = apic_read(APIC_LVTPC);
990                 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
991         }
992 
993         /* lets not touch this if we didn't frob it */
994 #ifdef CONFIG_X86_THERMAL_VECTOR
995         if (maxlvt >= 5) {
996                 v = apic_read(APIC_LVTTHMR);
997                 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
998         }
999 #endif
1000 #ifdef CONFIG_X86_MCE_INTEL
1001         if (maxlvt >= 6) {
1002                 v = apic_read(APIC_LVTCMCI);
1003                 if (!(v & APIC_LVT_MASKED))
1004                         apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED);
1005         }
1006 #endif
1007 
1008         /*
1009          * Clean APIC state for other OSs:
1010          */
1011         apic_write(APIC_LVTT, APIC_LVT_MASKED);
1012         apic_write(APIC_LVT0, APIC_LVT_MASKED);
1013         apic_write(APIC_LVT1, APIC_LVT_MASKED);
1014         if (maxlvt >= 3)
1015                 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
1016         if (maxlvt >= 4)
1017                 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
1018 
1019         /* Integrated APIC (!82489DX) ? */
1020         if (lapic_is_integrated()) {
1021                 if (maxlvt > 3)
1022                         /* Clear ESR due to Pentium errata 3AP and 11AP */
1023                         apic_write(APIC_ESR, 0);
1024                 apic_read(APIC_ESR);
1025         }
1026 }
1027 
1028 /**
1029  * disable_local_APIC - clear and disable the local APIC
1030  */
1031 void disable_local_APIC(void)
1032 {
1033         unsigned int value;
1034 
1035         /* APIC hasn't been mapped yet */
1036         if (!x2apic_mode && !apic_phys)
1037                 return;
1038 
1039         clear_local_APIC();
1040 
1041         /*
1042          * Disable APIC (implies clearing of registers
1043          * for 82489DX!).
1044          */
1045         value = apic_read(APIC_SPIV);
1046         value &= ~APIC_SPIV_APIC_ENABLED;
1047         apic_write(APIC_SPIV, value);
1048 
1049 #ifdef CONFIG_X86_32
1050         /*
1051          * When LAPIC was disabled by the BIOS and enabled by the kernel,
1052          * restore the disabled state.
1053          */
1054         if (enabled_via_apicbase) {
1055                 unsigned int l, h;
1056 
1057                 rdmsr(MSR_IA32_APICBASE, l, h);
1058                 l &= ~MSR_IA32_APICBASE_ENABLE;
1059                 wrmsr(MSR_IA32_APICBASE, l, h);
1060         }
1061 #endif
1062 }
1063 
1064 /*
1065  * If Linux enabled the LAPIC against the BIOS default disable it down before
1066  * re-entering the BIOS on shutdown.  Otherwise the BIOS may get confused and
1067  * not power-off.  Additionally clear all LVT entries before disable_local_APIC
1068  * for the case where Linux didn't enable the LAPIC.
1069  */
1070 void lapic_shutdown(void)
1071 {
1072         unsigned long flags;
1073 
1074         if (!cpu_has_apic && !apic_from_smp_config())
1075                 return;
1076 
1077         local_irq_save(flags);
1078 
1079 #ifdef CONFIG_X86_32
1080         if (!enabled_via_apicbase)
1081                 clear_local_APIC();
1082         else
1083 #endif
1084                 disable_local_APIC();
1085 
1086 
1087         local_irq_restore(flags);
1088 }
1089 
1090 /*
1091  * This is to verify that we're looking at a real local APIC.
1092  * Check these against your board if the CPUs aren't getting
1093  * started for no apparent reason.
1094  */
1095 int __init verify_local_APIC(void)
1096 {
1097         unsigned int reg0, reg1;
1098 
1099         /*
1100          * The version register is read-only in a real APIC.
1101          */
1102         reg0 = apic_read(APIC_LVR);
1103         apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
1104         apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
1105         reg1 = apic_read(APIC_LVR);
1106         apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
1107 
1108         /*
1109          * The two version reads above should print the same
1110          * numbers.  If the second one is different, then we
1111          * poke at a non-APIC.
1112          */
1113         if (reg1 != reg0)
1114                 return 0;
1115 
1116         /*
1117          * Check if the version looks reasonably.
1118          */
1119         reg1 = GET_APIC_VERSION(reg0);
1120         if (reg1 == 0x00 || reg1 == 0xff)
1121                 return 0;
1122         reg1 = lapic_get_maxlvt();
1123         if (reg1 < 0x02 || reg1 == 0xff)
1124                 return 0;
1125 
1126         /*
1127          * The ID register is read/write in a real APIC.
1128          */
1129         reg0 = apic_read(APIC_ID);
1130         apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
1131         apic_write(APIC_ID, reg0 ^ apic->apic_id_mask);
1132         reg1 = apic_read(APIC_ID);
1133         apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
1134         apic_write(APIC_ID, reg0);
1135         if (reg1 != (reg0 ^ apic->apic_id_mask))
1136                 return 0;
1137 
1138         /*
1139          * The next two are just to see if we have sane values.
1140          * They're only really relevant if we're in Virtual Wire
1141          * compatibility mode, but most boxes are anymore.
1142          */
1143         reg0 = apic_read(APIC_LVT0);
1144         apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
1145         reg1 = apic_read(APIC_LVT1);
1146         apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
1147 
1148         return 1;
1149 }
1150 
1151 /**
1152  * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1153  */
1154 void __init sync_Arb_IDs(void)
1155 {
1156         /*
1157          * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1158          * needed on AMD.
1159          */
1160         if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1161                 return;
1162 
1163         /*
1164          * Wait for idle.
1165          */
1166         apic_wait_icr_idle();
1167 
1168         apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
1169         apic_write(APIC_ICR, APIC_DEST_ALLINC |
1170                         APIC_INT_LEVELTRIG | APIC_DM_INIT);
1171 }
1172 
1173 /*
1174  * An initial setup of the virtual wire mode.
1175  */
1176 void __init init_bsp_APIC(void)
1177 {
1178         unsigned int value;
1179 
1180         /*
1181          * Don't do the setup now if we have a SMP BIOS as the
1182          * through-I/O-APIC virtual wire mode might be active.
1183          */
1184         if (smp_found_config || !cpu_has_apic)
1185                 return;
1186 
1187         /*
1188          * Do not trust the local APIC being empty at bootup.
1189          */
1190         clear_local_APIC();
1191 
1192         /*
1193          * Enable APIC.
1194          */
1195         value = apic_read(APIC_SPIV);
1196         value &= ~APIC_VECTOR_MASK;
1197         value |= APIC_SPIV_APIC_ENABLED;
1198 
1199 #ifdef CONFIG_X86_32
1200         /* This bit is reserved on P4/Xeon and should be cleared */
1201         if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
1202             (boot_cpu_data.x86 == 15))
1203                 value &= ~APIC_SPIV_FOCUS_DISABLED;
1204         else
1205 #endif
1206                 value |= APIC_SPIV_FOCUS_DISABLED;
1207         value |= SPURIOUS_APIC_VECTOR;
1208         apic_write(APIC_SPIV, value);
1209 
1210         /*
1211          * Set up the virtual wire mode.
1212          */
1213         apic_write(APIC_LVT0, APIC_DM_EXTINT);
1214         value = APIC_DM_NMI;
1215         if (!lapic_is_integrated())             /* 82489DX */
1216                 value |= APIC_LVT_LEVEL_TRIGGER;
1217         apic_write(APIC_LVT1, value);
1218 }
1219 
1220 static void __cpuinit lapic_setup_esr(void)
1221 {
1222         unsigned int oldvalue, value, maxlvt;
1223 
1224         if (!lapic_is_integrated()) {
1225                 pr_info("No ESR for 82489DX.\n");
1226                 return;
1227         }
1228 
1229         if (apic->disable_esr) {
1230                 /*
1231                  * Something untraceable is creating bad interrupts on
1232                  * secondary quads ... for the moment, just leave the
1233                  * ESR disabled - we can't do anything useful with the
1234                  * errors anyway - mbligh
1235                  */
1236                 pr_info("Leaving ESR disabled.\n");
1237                 return;
1238         }
1239 
1240         maxlvt = lapic_get_maxlvt();
1241         if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
1242                 apic_write(APIC_ESR, 0);
1243         oldvalue = apic_read(APIC_ESR);
1244 
1245         /* enables sending errors */
1246         value = ERROR_APIC_VECTOR;
1247         apic_write(APIC_LVTERR, value);
1248 
1249         /*
1250          * spec says clear errors after enabling vector.
1251          */
1252         if (maxlvt > 3)
1253                 apic_write(APIC_ESR, 0);
1254         value = apic_read(APIC_ESR);
1255         if (value != oldvalue)
1256                 apic_printk(APIC_VERBOSE, "ESR value before enabling "
1257                         "vector: 0x%08x  after: 0x%08x\n",
1258                         oldvalue, value);
1259 }
1260 
1261 /**
1262  * setup_local_APIC - setup the local APIC
1263  *
1264  * Used to setup local APIC while initializing BSP or bringin up APs.
1265  * Always called with preemption disabled.
1266  */
1267 void __cpuinit setup_local_APIC(void)
1268 {
1269         int cpu = smp_processor_id();
1270         unsigned int value, queued;
1271         int i, j, acked = 0;
1272         unsigned long long tsc = 0, ntsc;
1273         long long max_loops = cpu_khz ? cpu_khz : 1000000;
1274 
1275         if (cpu_has_tsc)
1276                 rdtscll(tsc);
1277 
1278         if (disable_apic) {
1279                 disable_ioapic_support();
1280                 return;
1281         }
1282 
1283 #ifdef CONFIG_X86_32
1284         /* Pound the ESR really hard over the head with a big hammer - mbligh */
1285         if (lapic_is_integrated() && apic->disable_esr) {
1286                 apic_write(APIC_ESR, 0);
1287                 apic_write(APIC_ESR, 0);
1288                 apic_write(APIC_ESR, 0);
1289                 apic_write(APIC_ESR, 0);
1290         }
1291 #endif
1292         perf_events_lapic_init();
1293 
1294         /*
1295          * Double-check whether this APIC is really registered.
1296          * This is meaningless in clustered apic mode, so we skip it.
1297          */
1298         BUG_ON(!apic->apic_id_registered());
1299 
1300         /*
1301          * Intel recommends to set DFR, LDR and TPR before enabling
1302          * an APIC.  See e.g. "AP-388 82489DX User's Manual" (Intel
1303          * document number 292116).  So here it goes...
1304          */
1305         apic->init_apic_ldr();
1306 
1307 #ifdef CONFIG_X86_32
1308         /*
1309          * APIC LDR is initialized.  If logical_apicid mapping was
1310          * initialized during get_smp_config(), make sure it matches the
1311          * actual value.
1312          */
1313         i = early_per_cpu(x86_cpu_to_logical_apicid, cpu);
1314         WARN_ON(i != BAD_APICID && i != logical_smp_processor_id());
1315         /* always use the value from LDR */
1316         early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
1317                 logical_smp_processor_id();
1318 
1319         /*
1320          * Some NUMA implementations (NUMAQ) don't initialize apicid to
1321          * node mapping during NUMA init.  Now that logical apicid is
1322          * guaranteed to be known, give it another chance.  This is already
1323          * a bit too late - percpu allocation has already happened without
1324          * proper NUMA affinity.
1325          */
1326         if (apic->x86_32_numa_cpu_node)
1327                 set_apicid_to_node(early_per_cpu(x86_cpu_to_apicid, cpu),
1328                                    apic->x86_32_numa_cpu_node(cpu));
1329 #endif
1330 
1331         /*
1332          * Set Task Priority to 'accept all'. We never change this
1333          * later on.
1334          */
1335         value = apic_read(APIC_TASKPRI);
1336         value &= ~APIC_TPRI_MASK;
1337         apic_write(APIC_TASKPRI, value);
1338 
1339         /*
1340          * After a crash, we no longer service the interrupts and a pending
1341          * interrupt from previous kernel might still have ISR bit set.
1342          *
1343          * Most probably by now CPU has serviced that pending interrupt and
1344          * it might not have done the ack_APIC_irq() because it thought,
1345          * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1346          * does not clear the ISR bit and cpu thinks it has already serivced
1347          * the interrupt. Hence a vector might get locked. It was noticed
1348          * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1349          */
1350         do {
1351                 queued = 0;
1352                 for (i = APIC_ISR_NR - 1; i >= 0; i--)
1353                         queued |= apic_read(APIC_IRR + i*0x10);
1354 
1355                 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
1356                         value = apic_read(APIC_ISR + i*0x10);
1357                         for (j = 31; j >= 0; j--) {
1358                                 if (value & (1<<j)) {
1359                                         ack_APIC_irq();
1360                                         acked++;
1361                                 }
1362                         }
1363                 }
1364                 if (acked > 256) {
1365                         printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n",
1366                                acked);
1367                         break;
1368                 }
1369                 if (queued) {
1370                         if (cpu_has_tsc && cpu_khz) {
1371                                 rdtscll(ntsc);
1372                                 max_loops = (cpu_khz << 10) - (ntsc - tsc);
1373                         } else
1374                                 max_loops--;
1375                 }
1376         } while (queued && max_loops > 0);
1377         WARN_ON(max_loops <= 0);
1378 
1379         /*
1380          * Now that we are all set up, enable the APIC
1381          */
1382         value = apic_read(APIC_SPIV);
1383         value &= ~APIC_VECTOR_MASK;
1384         /*
1385          * Enable APIC
1386          */
1387         value |= APIC_SPIV_APIC_ENABLED;
1388 
1389 #ifdef CONFIG_X86_32
1390         /*
1391          * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1392          * certain networking cards. If high frequency interrupts are
1393          * happening on a particular IOAPIC pin, plus the IOAPIC routing
1394          * entry is masked/unmasked at a high rate as well then sooner or
1395          * later IOAPIC line gets 'stuck', no more interrupts are received
1396          * from the device. If focus CPU is disabled then the hang goes
1397          * away, oh well :-(
1398          *
1399          * [ This bug can be reproduced easily with a level-triggered
1400          *   PCI Ne2000 networking cards and PII/PIII processors, dual
1401          *   BX chipset. ]
1402          */
1403         /*
1404          * Actually disabling the focus CPU check just makes the hang less
1405          * frequent as it makes the interrupt distributon model be more
1406          * like LRU than MRU (the short-term load is more even across CPUs).
1407          * See also the comment in end_level_ioapic_irq().  --macro
1408          */
1409 
1410         /*
1411          * - enable focus processor (bit==0)
1412          * - 64bit mode always use processor focus
1413          *   so no need to set it
1414          */
1415         value &= ~APIC_SPIV_FOCUS_DISABLED;
1416 #endif
1417 
1418         /*
1419          * Set spurious IRQ vector
1420          */
1421         value |= SPURIOUS_APIC_VECTOR;
1422         apic_write(APIC_SPIV, value);
1423 
1424         /*
1425          * Set up LVT0, LVT1:
1426          *
1427          * set up through-local-APIC on the BP's LINT0. This is not
1428          * strictly necessary in pure symmetric-IO mode, but sometimes
1429          * we delegate interrupts to the 8259A.
1430          */
1431         /*
1432          * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1433          */
1434         value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1435         if (!cpu && (pic_mode || !value)) {
1436                 value = APIC_DM_EXTINT;
1437                 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu);
1438         } else {
1439                 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1440                 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu);
1441         }
1442         apic_write(APIC_LVT0, value);
1443 
1444         /*
1445          * only the BP should see the LINT1 NMI signal, obviously.
1446          */
1447         if (!cpu)
1448                 value = APIC_DM_NMI;
1449         else
1450                 value = APIC_DM_NMI | APIC_LVT_MASKED;
1451         if (!lapic_is_integrated())             /* 82489DX */
1452                 value |= APIC_LVT_LEVEL_TRIGGER;
1453         apic_write(APIC_LVT1, value);
1454 
1455 #ifdef CONFIG_X86_MCE_INTEL
1456         /* Recheck CMCI information after local APIC is up on CPU #0 */
1457         if (!cpu)
1458                 cmci_recheck();
1459 #endif
1460 }
1461 
1462 void __cpuinit end_local_APIC_setup(void)
1463 {
1464         lapic_setup_esr();
1465 
1466 #ifdef CONFIG_X86_32
1467         {
1468                 unsigned int value;
1469                 /* Disable the local apic timer */
1470                 value = apic_read(APIC_LVTT);
1471                 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1472                 apic_write(APIC_LVTT, value);
1473         }
1474 #endif
1475 
1476         apic_pm_activate();
1477 }
1478 
1479 void __init bsp_end_local_APIC_setup(void)
1480 {
1481         end_local_APIC_setup();
1482 
1483         /*
1484          * Now that local APIC setup is completed for BP, configure the fault
1485          * handling for interrupt remapping.
1486          */
1487         irq_remap_enable_fault_handling();
1488 
1489 }
1490 
1491 #ifdef CONFIG_X86_X2APIC
1492 /*
1493  * Need to disable xapic and x2apic at the same time and then enable xapic mode
1494  */
1495 static inline void __disable_x2apic(u64 msr)
1496 {
1497         wrmsrl(MSR_IA32_APICBASE,
1498                msr & ~(X2APIC_ENABLE | XAPIC_ENABLE));
1499         wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE);
1500 }
1501 
1502 static __init void disable_x2apic(void)
1503 {
1504         u64 msr;
1505 
1506         if (!cpu_has_x2apic)
1507                 return;
1508 
1509         rdmsrl(MSR_IA32_APICBASE, msr);
1510         if (msr & X2APIC_ENABLE) {
1511                 u32 x2apic_id = read_apic_id();
1512 
1513                 if (x2apic_id >= 255)
1514                         panic("Cannot disable x2apic, id: %08x\n", x2apic_id);
1515 
1516                 pr_info("Disabling x2apic\n");
1517                 __disable_x2apic(msr);
1518 
1519                 if (nox2apic) {
1520                         clear_cpu_cap(&cpu_data(0), X86_FEATURE_X2APIC);
1521                         setup_clear_cpu_cap(X86_FEATURE_X2APIC);
1522                 }
1523 
1524                 x2apic_disabled = 1;
1525                 x2apic_mode = 0;
1526 
1527                 register_lapic_address(mp_lapic_addr);
1528         }
1529 }
1530 
1531 void check_x2apic(void)
1532 {
1533         if (x2apic_enabled()) {
1534                 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n");
1535                 x2apic_preenabled = x2apic_mode = 1;
1536         }
1537 }
1538 
1539 void enable_x2apic(void)
1540 {
1541         u64 msr;
1542 
1543         rdmsrl(MSR_IA32_APICBASE, msr);
1544         if (x2apic_disabled) {
1545                 __disable_x2apic(msr);
1546                 return;
1547         }
1548 
1549         if (!x2apic_mode)
1550                 return;
1551 
1552         if (!(msr & X2APIC_ENABLE)) {
1553                 printk_once(KERN_INFO "Enabling x2apic\n");
1554                 wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE);
1555         }
1556 }
1557 #endif /* CONFIG_X86_X2APIC */
1558 
1559 int __init enable_IR(void)
1560 {
1561 #ifdef CONFIG_IRQ_REMAP
1562         if (!irq_remapping_supported()) {
1563                 pr_debug("intr-remapping not supported\n");
1564                 return -1;
1565         }
1566 
1567         if (!x2apic_preenabled && skip_ioapic_setup) {
1568                 pr_info("Skipped enabling intr-remap because of skipping "
1569                         "io-apic setup\n");
1570                 return -1;
1571         }
1572 
1573         return irq_remapping_enable();
1574 #endif
1575         return -1;
1576 }
1577 
1578 void __init enable_IR_x2apic(void)
1579 {
1580         unsigned long flags;
1581         int ret, x2apic_enabled = 0;
1582         int hardware_init_ret;
1583 
1584 #ifdef CONFIG_X86_IO_APIC
1585         if (skip_ioapic_setup)
1586                 return;
1587 #endif
1588 
1589         /* Make sure irq_remap_ops are initialized */
1590         setup_irq_remapping_ops();
1591 
1592         hardware_init_ret = irq_remapping_prepare();
1593         if (hardware_init_ret && !x2apic_supported())
1594                 return;
1595 
1596         ret = save_ioapic_entries();
1597         if (ret) {
1598                 pr_info("Saving IO-APIC state failed: %d\n", ret);
1599                 return;
1600         }
1601 
1602         local_irq_save(flags);
1603         legacy_pic->mask_all();
1604         mask_ioapic_entries();
1605 
1606         if (x2apic_preenabled && nox2apic)
1607                 disable_x2apic();
1608 
1609         if (hardware_init_ret)
1610                 ret = -1;
1611         else
1612                 ret = enable_IR();
1613 
1614         if (!x2apic_supported())
1615                 goto skip_x2apic;
1616 
1617         if (ret < 0) {
1618                 /* IR is required if there is APIC ID > 255 even when running
1619                  * under KVM
1620                  */
1621                 if (max_physical_apicid > 255 ||
1622                     !hypervisor_x2apic_available()) {
1623                         if (x2apic_preenabled)
1624                                 disable_x2apic();
1625                         goto skip_x2apic;
1626                 }
1627                 /*
1628                  * without IR all CPUs can be addressed by IOAPIC/MSI
1629                  * only in physical mode
1630                  */
1631                 x2apic_force_phys();
1632         }
1633 
1634         if (ret == IRQ_REMAP_XAPIC_MODE) {
1635                 pr_info("x2apic not enabled, IRQ remapping is in xapic mode\n");
1636                 goto skip_x2apic;
1637         }
1638 
1639         x2apic_enabled = 1;
1640 
1641         if (x2apic_supported() && !x2apic_mode) {
1642                 x2apic_mode = 1;
1643                 enable_x2apic();
1644                 pr_info("Enabled x2apic\n");
1645         }
1646 
1647 skip_x2apic:
1648         if (ret < 0) /* IR enabling failed */
1649                 restore_ioapic_entries();
1650         legacy_pic->restore_mask();
1651         local_irq_restore(flags);
1652 }
1653 
1654 #ifdef CONFIG_X86_64
1655 /*
1656  * Detect and enable local APICs on non-SMP boards.
1657  * Original code written by Keir Fraser.
1658  * On AMD64 we trust the BIOS - if it says no APIC it is likely
1659  * not correctly set up (usually the APIC timer won't work etc.)
1660  */
1661 static int __init detect_init_APIC(void)
1662 {
1663         if (!cpu_has_apic) {
1664                 pr_info("No local APIC present\n");
1665                 return -1;
1666         }
1667 
1668         mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1669         return 0;
1670 }
1671 #else
1672 
1673 static int __init apic_verify(void)
1674 {
1675         u32 features, h, l;
1676 
1677         /*
1678          * The APIC feature bit should now be enabled
1679          * in `cpuid'
1680          */
1681         features = cpuid_edx(1);
1682         if (!(features & (1 << X86_FEATURE_APIC))) {
1683                 pr_warning("Could not enable APIC!\n");
1684                 return -1;
1685         }
1686         set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1687         mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1688 
1689         /* The BIOS may have set up the APIC at some other address */
1690         if (boot_cpu_data.x86 >= 6) {
1691                 rdmsr(MSR_IA32_APICBASE, l, h);
1692                 if (l & MSR_IA32_APICBASE_ENABLE)
1693                         mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1694         }
1695 
1696         pr_info("Found and enabled local APIC!\n");
1697         return 0;
1698 }
1699 
1700 int __init apic_force_enable(unsigned long addr)
1701 {
1702         u32 h, l;
1703 
1704         if (disable_apic)
1705                 return -1;
1706 
1707         /*
1708          * Some BIOSes disable the local APIC in the APIC_BASE
1709          * MSR. This can only be done in software for Intel P6 or later
1710          * and AMD K7 (Model > 1) or later.
1711          */
1712         if (boot_cpu_data.x86 >= 6) {
1713                 rdmsr(MSR_IA32_APICBASE, l, h);
1714                 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
1715                         pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1716                         l &= ~MSR_IA32_APICBASE_BASE;
1717                         l |= MSR_IA32_APICBASE_ENABLE | addr;
1718                         wrmsr(MSR_IA32_APICBASE, l, h);
1719                         enabled_via_apicbase = 1;
1720                 }
1721         }
1722         return apic_verify();
1723 }
1724 
1725 /*
1726  * Detect and initialize APIC
1727  */
1728 static int __init detect_init_APIC(void)
1729 {
1730         /* Disabled by kernel option? */
1731         if (disable_apic)
1732                 return -1;
1733 
1734         switch (boot_cpu_data.x86_vendor) {
1735         case X86_VENDOR_AMD:
1736                 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1737                     (boot_cpu_data.x86 >= 15))
1738                         break;
1739                 goto no_apic;
1740         case X86_VENDOR_INTEL:
1741                 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
1742                     (boot_cpu_data.x86 == 5 && cpu_has_apic))
1743                         break;
1744                 goto no_apic;
1745         default:
1746                 goto no_apic;
1747         }
1748 
1749         if (!cpu_has_apic) {
1750                 /*
1751                  * Over-ride BIOS and try to enable the local APIC only if
1752                  * "lapic" specified.
1753                  */
1754                 if (!force_enable_local_apic) {
1755                         pr_info("Local APIC disabled by BIOS -- "
1756                                 "you can enable it with \"lapic\"\n");
1757                         return -1;
1758                 }
1759                 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE))
1760                         return -1;
1761         } else {
1762                 if (apic_verify())
1763                         return -1;
1764         }
1765 
1766         apic_pm_activate();
1767 
1768         return 0;
1769 
1770 no_apic:
1771         pr_info("No local APIC present or hardware disabled\n");
1772         return -1;
1773 }
1774 #endif
1775 
1776 /**
1777  * init_apic_mappings - initialize APIC mappings
1778  */
1779 void __init init_apic_mappings(void)
1780 {
1781         unsigned int new_apicid;
1782 
1783         if (x2apic_mode) {
1784                 boot_cpu_physical_apicid = read_apic_id();
1785                 return;
1786         }
1787 
1788         /* If no local APIC can be found return early */
1789         if (!smp_found_config && detect_init_APIC()) {
1790                 /* lets NOP'ify apic operations */
1791                 pr_info("APIC: disable apic facility\n");
1792                 apic_disable();
1793         } else {
1794                 apic_phys = mp_lapic_addr;
1795 
1796                 /*
1797                  * acpi lapic path already maps that address in
1798                  * acpi_register_lapic_address()
1799                  */
1800                 if (!acpi_lapic && !smp_found_config)
1801                         register_lapic_address(apic_phys);
1802         }
1803 
1804         /*
1805          * Fetch the APIC ID of the BSP in case we have a
1806          * default configuration (or the MP table is broken).
1807          */
1808         new_apicid = read_apic_id();
1809         if (boot_cpu_physical_apicid != new_apicid) {
1810                 boot_cpu_physical_apicid = new_apicid;
1811                 /*
1812                  * yeah -- we lie about apic_version
1813                  * in case if apic was disabled via boot option
1814                  * but it's not a problem for SMP compiled kernel
1815                  * since smp_sanity_check is prepared for such a case
1816                  * and disable smp mode
1817                  */
1818                 apic_version[new_apicid] =
1819                          GET_APIC_VERSION(apic_read(APIC_LVR));
1820         }
1821 }
1822 
1823 void __init register_lapic_address(unsigned long address)
1824 {
1825         mp_lapic_addr = address;
1826 
1827         if (!x2apic_mode) {
1828                 set_fixmap_nocache(FIX_APIC_BASE, address);
1829                 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
1830                             APIC_BASE, mp_lapic_addr);
1831         }
1832         if (boot_cpu_physical_apicid == -1U) {
1833                 boot_cpu_physical_apicid  = read_apic_id();
1834                 apic_version[boot_cpu_physical_apicid] =
1835                          GET_APIC_VERSION(apic_read(APIC_LVR));
1836         }
1837 }
1838 
1839 /*
1840  * This initializes the IO-APIC and APIC hardware if this is
1841  * a UP kernel.
1842  */
1843 int apic_version[MAX_LOCAL_APIC];
1844 
1845 int __init APIC_init_uniprocessor(void)
1846 {
1847         if (disable_apic) {
1848                 pr_info("Apic disabled\n");
1849                 return -1;
1850         }
1851 #ifdef CONFIG_X86_64
1852         if (!cpu_has_apic) {
1853                 disable_apic = 1;
1854                 pr_info("Apic disabled by BIOS\n");
1855                 return -1;
1856         }
1857 #else
1858         if (!smp_found_config && !cpu_has_apic)
1859                 return -1;
1860 
1861         /*
1862          * Complain if the BIOS pretends there is one.
1863          */
1864         if (!cpu_has_apic &&
1865             APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
1866                 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
1867                         boot_cpu_physical_apicid);
1868                 return -1;
1869         }
1870 #endif
1871 
1872         default_setup_apic_routing();
1873 
1874         verify_local_APIC();
1875         connect_bsp_APIC();
1876 
1877 #ifdef CONFIG_X86_64
1878         apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid));
1879 #else
1880         /*
1881          * Hack: In case of kdump, after a crash, kernel might be booting
1882          * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1883          * might be zero if read from MP tables. Get it from LAPIC.
1884          */
1885 # ifdef CONFIG_CRASH_DUMP
1886         boot_cpu_physical_apicid = read_apic_id();
1887 # endif
1888 #endif
1889         physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1890         setup_local_APIC();
1891 
1892 #ifdef CONFIG_X86_IO_APIC
1893         /*
1894          * Now enable IO-APICs, actually call clear_IO_APIC
1895          * We need clear_IO_APIC before enabling error vector
1896          */
1897         if (!skip_ioapic_setup && nr_ioapics)
1898                 enable_IO_APIC();
1899 #endif
1900 
1901         bsp_end_local_APIC_setup();
1902 
1903 #ifdef CONFIG_X86_IO_APIC
1904         if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
1905                 setup_IO_APIC();
1906         else {
1907                 nr_ioapics = 0;
1908         }
1909 #endif
1910 
1911         x86_init.timers.setup_percpu_clockev();
1912         return 0;
1913 }
1914 
1915 /*
1916  * Local APIC interrupts
1917  */
1918 
1919 /*
1920  * This interrupt should _never_ happen with our APIC/SMP architecture
1921  */
1922 void smp_spurious_interrupt(struct pt_regs *regs)
1923 {
1924         u32 v;
1925 
1926         irq_enter();
1927         exit_idle();
1928         /*
1929          * Check if this really is a spurious interrupt and ACK it
1930          * if it is a vectored one.  Just in case...
1931          * Spurious interrupts should not be ACKed.
1932          */
1933         v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
1934         if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
1935                 ack_APIC_irq();
1936 
1937         inc_irq_stat(irq_spurious_count);
1938 
1939         /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1940         pr_info("spurious APIC interrupt on CPU#%d, "
1941                 "should never happen.\n", smp_processor_id());
1942         irq_exit();
1943 }
1944 
1945 /*
1946  * This interrupt should never happen with our APIC/SMP architecture
1947  */
1948 void smp_error_interrupt(struct pt_regs *regs)
1949 {
1950         u32 v0, v1;
1951         u32 i = 0;
1952         static const char * const error_interrupt_reason[] = {
1953                 "Send CS error",                /* APIC Error Bit 0 */
1954                 "Receive CS error",             /* APIC Error Bit 1 */
1955                 "Send accept error",            /* APIC Error Bit 2 */
1956                 "Receive accept error",         /* APIC Error Bit 3 */
1957                 "Redirectable IPI",             /* APIC Error Bit 4 */
1958                 "Send illegal vector",          /* APIC Error Bit 5 */
1959                 "Received illegal vector",      /* APIC Error Bit 6 */
1960                 "Illegal register address",     /* APIC Error Bit 7 */
1961         };
1962 
1963         irq_enter();
1964         exit_idle();
1965         /* First tickle the hardware, only then report what went on. -- REW */
1966         v0 = apic_read(APIC_ESR);
1967         apic_write(APIC_ESR, 0);
1968         v1 = apic_read(APIC_ESR);
1969         ack_APIC_irq();
1970         atomic_inc(&irq_err_count);
1971 
1972         apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x(%02x)",
1973                     smp_processor_id(), v0 , v1);
1974 
1975         v1 = v1 & 0xff;
1976         while (v1) {
1977                 if (v1 & 0x1)
1978                         apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]);
1979                 i++;
1980                 v1 >>= 1;
1981         }
1982 
1983         apic_printk(APIC_DEBUG, KERN_CONT "\n");
1984 
1985         irq_exit();
1986 }
1987 
1988 /**
1989  * connect_bsp_APIC - attach the APIC to the interrupt system
1990  */
1991 void __init connect_bsp_APIC(void)
1992 {
1993 #ifdef CONFIG_X86_32
1994         if (pic_mode) {
1995                 /*
1996                  * Do not trust the local APIC being empty at bootup.
1997                  */
1998                 clear_local_APIC();
1999                 /*
2000                  * PIC mode, enable APIC mode in the IMCR, i.e.  connect BSP's
2001                  * local APIC to INT and NMI lines.
2002                  */
2003                 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
2004                                 "enabling APIC mode.\n");
2005                 imcr_pic_to_apic();
2006         }
2007 #endif
2008         if (apic->enable_apic_mode)
2009                 apic->enable_apic_mode();
2010 }
2011 
2012 /**
2013  * disconnect_bsp_APIC - detach the APIC from the interrupt system
2014  * @virt_wire_setup:    indicates, whether virtual wire mode is selected
2015  *
2016  * Virtual wire mode is necessary to deliver legacy interrupts even when the
2017  * APIC is disabled.
2018  */
2019 void disconnect_bsp_APIC(int virt_wire_setup)
2020 {
2021         unsigned int value;
2022 
2023 #ifdef CONFIG_X86_32
2024         if (pic_mode) {
2025                 /*
2026                  * Put the board back into PIC mode (has an effect only on
2027                  * certain older boards).  Note that APIC interrupts, including
2028                  * IPIs, won't work beyond this point!  The only exception are
2029                  * INIT IPIs.
2030                  */
2031                 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
2032                                 "entering PIC mode.\n");
2033                 imcr_apic_to_pic();
2034                 return;
2035         }
2036 #endif
2037 
2038         /* Go back to Virtual Wire compatibility mode */
2039 
2040         /* For the spurious interrupt use vector F, and enable it */
2041         value = apic_read(APIC_SPIV);
2042         value &= ~APIC_VECTOR_MASK;
2043         value |= APIC_SPIV_APIC_ENABLED;
2044         value |= 0xf;
2045         apic_write(APIC_SPIV, value);
2046 
2047         if (!virt_wire_setup) {
2048                 /*
2049                  * For LVT0 make it edge triggered, active high,
2050                  * external and enabled
2051                  */
2052                 value = apic_read(APIC_LVT0);
2053                 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
2054                         APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
2055                         APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
2056                 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
2057                 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
2058                 apic_write(APIC_LVT0, value);
2059         } else {
2060                 /* Disable LVT0 */
2061                 apic_write(APIC_LVT0, APIC_LVT_MASKED);
2062         }
2063 
2064         /*
2065          * For LVT1 make it edge triggered, active high,
2066          * nmi and enabled
2067          */
2068         value = apic_read(APIC_LVT1);
2069         value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
2070                         APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
2071                         APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
2072         value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
2073         value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
2074         apic_write(APIC_LVT1, value);
2075 }
2076 
2077 void __cpuinit generic_processor_info(int apicid, int version)
2078 {
2079         int cpu, max = nr_cpu_ids;
2080         bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid,
2081                                 phys_cpu_present_map);
2082 
2083         /*
2084          * If boot cpu has not been detected yet, then only allow upto
2085          * nr_cpu_ids - 1 processors and keep one slot free for boot cpu
2086          */
2087         if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 &&
2088             apicid != boot_cpu_physical_apicid) {
2089                 int thiscpu = max + disabled_cpus - 1;
2090 
2091                 pr_warning(
2092                         "ACPI: NR_CPUS/possible_cpus limit of %i almost"
2093                         " reached. Keeping one slot for boot cpu."
2094                         "  Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
2095 
2096                 disabled_cpus++;
2097                 return;
2098         }
2099 
2100         if (num_processors >= nr_cpu_ids) {
2101                 int thiscpu = max + disabled_cpus;
2102 
2103                 pr_warning(
2104                         "ACPI: NR_CPUS/possible_cpus limit of %i reached."
2105                         "  Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
2106 
2107                 disabled_cpus++;
2108                 return;
2109         }
2110 
2111         num_processors++;
2112         if (apicid == boot_cpu_physical_apicid) {
2113                 /*
2114                  * x86_bios_cpu_apicid is required to have processors listed
2115                  * in same order as logical cpu numbers. Hence the first
2116                  * entry is BSP, and so on.
2117                  * boot_cpu_init() already hold bit 0 in cpu_present_mask
2118                  * for BSP.
2119                  */
2120                 cpu = 0;
2121         } else
2122                 cpu = cpumask_next_zero(-1, cpu_present_mask);
2123 
2124         /*
2125          * Validate version
2126          */
2127         if (version == 0x0) {
2128                 pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n",
2129                            cpu, apicid);
2130                 version = 0x10;
2131         }
2132         apic_version[apicid] = version;
2133 
2134         if (version != apic_version[boot_cpu_physical_apicid]) {
2135                 pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n",
2136                         apic_version[boot_cpu_physical_apicid], cpu, version);
2137         }
2138 
2139         physid_set(apicid, phys_cpu_present_map);
2140         if (apicid > max_physical_apicid)
2141                 max_physical_apicid = apicid;
2142 
2143 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
2144         early_per_cpu(x86_cpu_to_apicid, cpu) = apicid;
2145         early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
2146 #endif
2147 #ifdef CONFIG_X86_32
2148         early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
2149                 apic->x86_32_early_logical_apicid(cpu);
2150 #endif
2151         set_cpu_possible(cpu, true);
2152         set_cpu_present(cpu, true);
2153 }
2154 
2155 int hard_smp_processor_id(void)
2156 {
2157         return read_apic_id();
2158 }
2159 
2160 void default_init_apic_ldr(void)
2161 {
2162         unsigned long val;
2163 
2164         apic_write(APIC_DFR, APIC_DFR_VALUE);
2165         val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
2166         val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
2167         apic_write(APIC_LDR, val);
2168 }
2169 
2170 int default_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
2171                                    const struct cpumask *andmask,
2172                                    unsigned int *apicid)
2173 {
2174         unsigned int cpu;
2175 
2176         for_each_cpu_and(cpu, cpumask, andmask) {
2177                 if (cpumask_test_cpu(cpu, cpu_online_mask))
2178                         break;
2179         }
2180 
2181         if (likely(cpu < nr_cpu_ids)) {
2182                 *apicid = per_cpu(x86_cpu_to_apicid, cpu);
2183                 return 0;
2184         }
2185 
2186         return -EINVAL;
2187 }
2188 
2189 /*
2190  * Override the generic EOI implementation with an optimized version.
2191  * Only called during early boot when only one CPU is active and with
2192  * interrupts disabled, so we know this does not race with actual APIC driver
2193  * use.
2194  */
2195 void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v))
2196 {
2197         struct apic **drv;
2198 
2199         for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) {
2200                 /* Should happen once for each apic */
2201                 WARN_ON((*drv)->eoi_write == eoi_write);
2202                 (*drv)->eoi_write = eoi_write;
2203         }
2204 }
2205 
2206 /*
2207  * Power management
2208  */
2209 #ifdef CONFIG_PM
2210 
2211 static struct {
2212         /*
2213          * 'active' is true if the local APIC was enabled by us and
2214          * not the BIOS; this signifies that we are also responsible
2215          * for disabling it before entering apm/acpi suspend
2216          */
2217         int active;
2218         /* r/w apic fields */
2219         unsigned int apic_id;
2220         unsigned int apic_taskpri;
2221         unsigned int apic_ldr;
2222         unsigned int apic_dfr;
2223         unsigned int apic_spiv;
2224         unsigned int apic_lvtt;
2225         unsigned int apic_lvtpc;
2226         unsigned int apic_lvt0;
2227         unsigned int apic_lvt1;
2228         unsigned int apic_lvterr;
2229         unsigned int apic_tmict;
2230         unsigned int apic_tdcr;
2231         unsigned int apic_thmr;
2232 } apic_pm_state;
2233 
2234 static int lapic_suspend(void)
2235 {
2236         unsigned long flags;
2237         int maxlvt;
2238 
2239         if (!apic_pm_state.active)
2240                 return 0;
2241 
2242         maxlvt = lapic_get_maxlvt();
2243 
2244         apic_pm_state.apic_id = apic_read(APIC_ID);
2245         apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
2246         apic_pm_state.apic_ldr = apic_read(APIC_LDR);
2247         apic_pm_state.apic_dfr = apic_read(APIC_DFR);
2248         apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
2249         apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
2250         if (maxlvt >= 4)
2251                 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
2252         apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
2253         apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
2254         apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
2255         apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
2256         apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
2257 #ifdef CONFIG_X86_THERMAL_VECTOR
2258         if (maxlvt >= 5)
2259                 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
2260 #endif
2261 
2262         local_irq_save(flags);
2263         disable_local_APIC();
2264 
2265         irq_remapping_disable();
2266 
2267         local_irq_restore(flags);
2268         return 0;
2269 }
2270 
2271 static void lapic_resume(void)
2272 {
2273         unsigned int l, h;
2274         unsigned long flags;
2275         int maxlvt;
2276 
2277         if (!apic_pm_state.active)
2278                 return;
2279 
2280         local_irq_save(flags);
2281 
2282         /*
2283          * IO-APIC and PIC have their own resume routines.
2284          * We just mask them here to make sure the interrupt
2285          * subsystem is completely quiet while we enable x2apic
2286          * and interrupt-remapping.
2287          */
2288         mask_ioapic_entries();
2289         legacy_pic->mask_all();
2290 
2291         if (x2apic_mode)
2292                 enable_x2apic();
2293         else {
2294                 /*
2295                  * Make sure the APICBASE points to the right address
2296                  *
2297                  * FIXME! This will be wrong if we ever support suspend on
2298                  * SMP! We'll need to do this as part of the CPU restore!
2299                  */
2300                 if (boot_cpu_data.x86 >= 6) {
2301                         rdmsr(MSR_IA32_APICBASE, l, h);
2302                         l &= ~MSR_IA32_APICBASE_BASE;
2303                         l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
2304                         wrmsr(MSR_IA32_APICBASE, l, h);
2305                 }
2306         }
2307 
2308         maxlvt = lapic_get_maxlvt();
2309         apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
2310         apic_write(APIC_ID, apic_pm_state.apic_id);
2311         apic_write(APIC_DFR, apic_pm_state.apic_dfr);
2312         apic_write(APIC_LDR, apic_pm_state.apic_ldr);
2313         apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
2314         apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
2315         apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
2316         apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
2317 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
2318         if (maxlvt >= 5)
2319                 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
2320 #endif
2321         if (maxlvt >= 4)
2322                 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
2323         apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
2324         apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
2325         apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
2326         apic_write(APIC_ESR, 0);
2327         apic_read(APIC_ESR);
2328         apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
2329         apic_write(APIC_ESR, 0);
2330         apic_read(APIC_ESR);
2331 
2332         irq_remapping_reenable(x2apic_mode);
2333 
2334         local_irq_restore(flags);
2335 }
2336 
2337 /*
2338  * This device has no shutdown method - fully functioning local APICs
2339  * are needed on every CPU up until machine_halt/restart/poweroff.
2340  */
2341 
2342 static struct syscore_ops lapic_syscore_ops = {
2343         .resume         = lapic_resume,
2344         .suspend        = lapic_suspend,
2345 };
2346 
2347 static void __cpuinit apic_pm_activate(void)
2348 {
2349         apic_pm_state.active = 1;
2350 }
2351 
2352 static int __init init_lapic_sysfs(void)
2353 {
2354         /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2355         if (cpu_has_apic)
2356                 register_syscore_ops(&lapic_syscore_ops);
2357 
2358         return 0;
2359 }
2360 
2361 /* local apic needs to resume before other devices access its registers. */
2362 core_initcall(init_lapic_sysfs);
2363 
2364 #else   /* CONFIG_PM */
2365 
2366 static void apic_pm_activate(void) { }
2367 
2368 #endif  /* CONFIG_PM */
2369 
2370 #ifdef CONFIG_X86_64
2371 
2372 static int __cpuinit apic_cluster_num(void)
2373 {
2374         int i, clusters, zeros;
2375         unsigned id;
2376         u16 *bios_cpu_apicid;
2377         DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);
2378 
2379         bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
2380         bitmap_zero(clustermap, NUM_APIC_CLUSTERS);
2381 
2382         for (i = 0; i < nr_cpu_ids; i++) {
2383                 /* are we being called early in kernel startup? */
2384                 if (bios_cpu_apicid) {
2385                         id = bios_cpu_apicid[i];
2386                 } else if (i < nr_cpu_ids) {
2387                         if (cpu_present(i))
2388                                 id = per_cpu(x86_bios_cpu_apicid, i);
2389                         else
2390                                 continue;
2391                 } else
2392                         break;
2393 
2394                 if (id != BAD_APICID)
2395                         __set_bit(APIC_CLUSTERID(id), clustermap);
2396         }
2397 
2398         /* Problem:  Partially populated chassis may not have CPUs in some of
2399          * the APIC clusters they have been allocated.  Only present CPUs have
2400          * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
2401          * Since clusters are allocated sequentially, count zeros only if
2402          * they are bounded by ones.
2403          */
2404         clusters = 0;
2405         zeros = 0;
2406         for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
2407                 if (test_bit(i, clustermap)) {
2408                         clusters += 1 + zeros;
2409                         zeros = 0;
2410                 } else
2411                         ++zeros;
2412         }
2413 
2414         return clusters;
2415 }
2416 
2417 static int __cpuinitdata multi_checked;
2418 static int __cpuinitdata multi;
2419 
2420 static int __cpuinit set_multi(const struct dmi_system_id *d)
2421 {
2422         if (multi)
2423                 return 0;
2424         pr_info("APIC: %s detected, Multi Chassis\n", d->ident);
2425         multi = 1;
2426         return 0;
2427 }
2428 
2429 static const __cpuinitconst struct dmi_system_id multi_dmi_table[] = {
2430         {
2431                 .callback = set_multi,
2432                 .ident = "IBM System Summit2",
2433                 .matches = {
2434                         DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
2435                         DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"),
2436                 },
2437         },
2438         {}
2439 };
2440 
2441 static void __cpuinit dmi_check_multi(void)
2442 {
2443         if (multi_checked)
2444                 return;
2445 
2446         dmi_check_system(multi_dmi_table);
2447         multi_checked = 1;
2448 }
2449 
2450 /*
2451  * apic_is_clustered_box() -- Check if we can expect good TSC
2452  *
2453  * Thus far, the major user of this is IBM's Summit2 series:
2454  * Clustered boxes may have unsynced TSC problems if they are
2455  * multi-chassis.
2456  * Use DMI to check them
2457  */
2458 __cpuinit int apic_is_clustered_box(void)
2459 {
2460         dmi_check_multi();
2461         if (multi)
2462                 return 1;
2463 
2464         if (!is_vsmp_box())
2465                 return 0;
2466 
2467         /*
2468          * ScaleMP vSMPowered boxes have one cluster per board and TSCs are
2469          * not guaranteed to be synced between boards
2470          */
2471         if (apic_cluster_num() > 1)
2472                 return 1;
2473 
2474         return 0;
2475 }
2476 #endif
2477 
2478 /*
2479  * APIC command line parameters
2480  */
2481 static int __init setup_disableapic(char *arg)
2482 {
2483         disable_apic = 1;
2484         setup_clear_cpu_cap(X86_FEATURE_APIC);
2485         return 0;
2486 }
2487 early_param("disableapic", setup_disableapic);
2488 
2489 /* same as disableapic, for compatibility */
2490 static int __init setup_nolapic(char *arg)
2491 {
2492         return setup_disableapic(arg);
2493 }
2494 early_param("nolapic", setup_nolapic);
2495 
2496 static int __init parse_lapic_timer_c2_ok(char *arg)
2497 {
2498         local_apic_timer_c2_ok = 1;
2499         return 0;
2500 }
2501 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
2502 
2503 static int __init parse_disable_apic_timer(char *arg)
2504 {
2505         disable_apic_timer = 1;
2506         return 0;
2507 }
2508 early_param("noapictimer", parse_disable_apic_timer);
2509 
2510 static int __init parse_nolapic_timer(char *arg)
2511 {
2512         disable_apic_timer = 1;
2513         return 0;
2514 }
2515 early_param("nolapic_timer", parse_nolapic_timer);
2516 
2517 static int __init apic_set_verbosity(char *arg)
2518 {
2519         if (!arg)  {
2520 #ifdef CONFIG_X86_64
2521                 skip_ioapic_setup = 0;
2522                 return 0;
2523 #endif
2524                 return -EINVAL;
2525         }
2526 
2527         if (strcmp("debug", arg) == 0)
2528                 apic_verbosity = APIC_DEBUG;
2529         else if (strcmp("verbose", arg) == 0)
2530                 apic_verbosity = APIC_VERBOSE;
2531         else {
2532                 pr_warning("APIC Verbosity level %s not recognised"
2533                         " use apic=verbose or apic=debug\n", arg);
2534                 return -EINVAL;
2535         }
2536 
2537         return 0;
2538 }
2539 early_param("apic", apic_set_verbosity);
2540 
2541 static int __init lapic_insert_resource(void)
2542 {
2543         if (!apic_phys)
2544                 return -1;
2545 
2546         /* Put local APIC into the resource map. */
2547         lapic_resource.start = apic_phys;
2548         lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
2549         insert_resource(&iomem_resource, &lapic_resource);
2550 
2551         return 0;
2552 }
2553 
2554 /*
2555  * need call insert after e820_reserve_resources()
2556  * that is using request_resource
2557  */
2558 late_initcall(lapic_insert_resource);
2559 

~ [ source navigation ] ~ [ diff markup ] ~ [ identifier search ] ~

kernel.org | git.kernel.org | LWN.net | Project Home | Wiki (Japanese) | Wiki (English) | SVN repository | Mail admin

Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.

osdn.jp