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TOMOYO Linux Cross Reference
Linux/arch/x86/kernel/apic/apic.c

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  1 /*
  2  *      Local APIC handling, local APIC timers
  3  *
  4  *      (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
  5  *
  6  *      Fixes
  7  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  8  *                                      thanks to Eric Gilmore
  9  *                                      and Rolf G. Tews
 10  *                                      for testing these extensively.
 11  *      Maciej W. Rozycki       :       Various updates and fixes.
 12  *      Mikael Pettersson       :       Power Management for UP-APIC.
 13  *      Pavel Machek and
 14  *      Mikael Pettersson       :       PM converted to driver model.
 15  */
 16 
 17 #include <linux/perf_event.h>
 18 #include <linux/kernel_stat.h>
 19 #include <linux/mc146818rtc.h>
 20 #include <linux/acpi_pmtmr.h>
 21 #include <linux/clockchips.h>
 22 #include <linux/interrupt.h>
 23 #include <linux/bootmem.h>
 24 #include <linux/ftrace.h>
 25 #include <linux/ioport.h>
 26 #include <linux/module.h>
 27 #include <linux/syscore_ops.h>
 28 #include <linux/delay.h>
 29 #include <linux/timex.h>
 30 #include <linux/i8253.h>
 31 #include <linux/dmar.h>
 32 #include <linux/init.h>
 33 #include <linux/cpu.h>
 34 #include <linux/dmi.h>
 35 #include <linux/smp.h>
 36 #include <linux/mm.h>
 37 
 38 #include <asm/perf_event.h>
 39 #include <asm/x86_init.h>
 40 #include <asm/pgalloc.h>
 41 #include <linux/atomic.h>
 42 #include <asm/mpspec.h>
 43 #include <asm/i8259.h>
 44 #include <asm/proto.h>
 45 #include <asm/apic.h>
 46 #include <asm/io_apic.h>
 47 #include <asm/desc.h>
 48 #include <asm/hpet.h>
 49 #include <asm/idle.h>
 50 #include <asm/mtrr.h>
 51 #include <asm/time.h>
 52 #include <asm/smp.h>
 53 #include <asm/mce.h>
 54 #include <asm/tsc.h>
 55 #include <asm/hypervisor.h>
 56 
 57 unsigned int num_processors;
 58 
 59 unsigned disabled_cpus __cpuinitdata;
 60 
 61 /* Processor that is doing the boot up */
 62 unsigned int boot_cpu_physical_apicid = -1U;
 63 
 64 /*
 65  * The highest APIC ID seen during enumeration.
 66  */
 67 unsigned int max_physical_apicid;
 68 
 69 /*
 70  * Bitmask of physically existing CPUs:
 71  */
 72 physid_mask_t phys_cpu_present_map;
 73 
 74 /*
 75  * Map cpu index to physical APIC ID
 76  */
 77 DEFINE_EARLY_PER_CPU(u16, x86_cpu_to_apicid, BAD_APICID);
 78 DEFINE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid, BAD_APICID);
 79 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid);
 80 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
 81 
 82 #ifdef CONFIG_X86_32
 83 
 84 /*
 85  * On x86_32, the mapping between cpu and logical apicid may vary
 86  * depending on apic in use.  The following early percpu variable is
 87  * used for the mapping.  This is where the behaviors of x86_64 and 32
 88  * actually diverge.  Let's keep it ugly for now.
 89  */
 90 DEFINE_EARLY_PER_CPU(int, x86_cpu_to_logical_apicid, BAD_APICID);
 91 
 92 /*
 93  * Knob to control our willingness to enable the local APIC.
 94  *
 95  * +1=force-enable
 96  */
 97 static int force_enable_local_apic __initdata;
 98 /*
 99  * APIC command line parameters
100  */
101 static int __init parse_lapic(char *arg)
102 {
103         force_enable_local_apic = 1;
104         return 0;
105 }
106 early_param("lapic", parse_lapic);
107 /* Local APIC was disabled by the BIOS and enabled by the kernel */
108 static int enabled_via_apicbase;
109 
110 /*
111  * Handle interrupt mode configuration register (IMCR).
112  * This register controls whether the interrupt signals
113  * that reach the BSP come from the master PIC or from the
114  * local APIC. Before entering Symmetric I/O Mode, either
115  * the BIOS or the operating system must switch out of
116  * PIC Mode by changing the IMCR.
117  */
118 static inline void imcr_pic_to_apic(void)
119 {
120         /* select IMCR register */
121         outb(0x70, 0x22);
122         /* NMI and 8259 INTR go through APIC */
123         outb(0x01, 0x23);
124 }
125 
126 static inline void imcr_apic_to_pic(void)
127 {
128         /* select IMCR register */
129         outb(0x70, 0x22);
130         /* NMI and 8259 INTR go directly to BSP */
131         outb(0x00, 0x23);
132 }
133 #endif
134 
135 #ifdef CONFIG_X86_64
136 static int apic_calibrate_pmtmr __initdata;
137 static __init int setup_apicpmtimer(char *s)
138 {
139         apic_calibrate_pmtmr = 1;
140         notsc_setup(NULL);
141         return 0;
142 }
143 __setup("apicpmtimer", setup_apicpmtimer);
144 #endif
145 
146 int x2apic_mode;
147 #ifdef CONFIG_X86_X2APIC
148 /* x2apic enabled before OS handover */
149 static int x2apic_preenabled;
150 static __init int setup_nox2apic(char *str)
151 {
152         if (x2apic_enabled()) {
153                 pr_warning("Bios already enabled x2apic, "
154                            "can't enforce nox2apic");
155                 return 0;
156         }
157 
158         setup_clear_cpu_cap(X86_FEATURE_X2APIC);
159         return 0;
160 }
161 early_param("nox2apic", setup_nox2apic);
162 #endif
163 
164 unsigned long mp_lapic_addr;
165 int disable_apic;
166 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
167 static int disable_apic_timer __initdata;
168 /* Local APIC timer works in C2 */
169 int local_apic_timer_c2_ok;
170 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
171 
172 int first_system_vector = 0xfe;
173 
174 /*
175  * Debug level, exported for io_apic.c
176  */
177 unsigned int apic_verbosity;
178 
179 int pic_mode;
180 
181 /* Have we found an MP table */
182 int smp_found_config;
183 
184 static struct resource lapic_resource = {
185         .name = "Local APIC",
186         .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
187 };
188 
189 unsigned int lapic_timer_frequency = 0;
190 
191 static void apic_pm_activate(void);
192 
193 static unsigned long apic_phys;
194 
195 /*
196  * Get the LAPIC version
197  */
198 static inline int lapic_get_version(void)
199 {
200         return GET_APIC_VERSION(apic_read(APIC_LVR));
201 }
202 
203 /*
204  * Check, if the APIC is integrated or a separate chip
205  */
206 static inline int lapic_is_integrated(void)
207 {
208 #ifdef CONFIG_X86_64
209         return 1;
210 #else
211         return APIC_INTEGRATED(lapic_get_version());
212 #endif
213 }
214 
215 /*
216  * Check, whether this is a modern or a first generation APIC
217  */
218 static int modern_apic(void)
219 {
220         /* AMD systems use old APIC versions, so check the CPU */
221         if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
222             boot_cpu_data.x86 >= 0xf)
223                 return 1;
224         return lapic_get_version() >= 0x14;
225 }
226 
227 /*
228  * right after this call apic become NOOP driven
229  * so apic->write/read doesn't do anything
230  */
231 static void __init apic_disable(void)
232 {
233         pr_info("APIC: switched to apic NOOP\n");
234         apic = &apic_noop;
235 }
236 
237 void native_apic_wait_icr_idle(void)
238 {
239         while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
240                 cpu_relax();
241 }
242 
243 u32 native_safe_apic_wait_icr_idle(void)
244 {
245         u32 send_status;
246         int timeout;
247 
248         timeout = 0;
249         do {
250                 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
251                 if (!send_status)
252                         break;
253                 udelay(100);
254         } while (timeout++ < 1000);
255 
256         return send_status;
257 }
258 
259 void native_apic_icr_write(u32 low, u32 id)
260 {
261         apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
262         apic_write(APIC_ICR, low);
263 }
264 
265 u64 native_apic_icr_read(void)
266 {
267         u32 icr1, icr2;
268 
269         icr2 = apic_read(APIC_ICR2);
270         icr1 = apic_read(APIC_ICR);
271 
272         return icr1 | ((u64)icr2 << 32);
273 }
274 
275 #ifdef CONFIG_X86_32
276 /**
277  * get_physical_broadcast - Get number of physical broadcast IDs
278  */
279 int get_physical_broadcast(void)
280 {
281         return modern_apic() ? 0xff : 0xf;
282 }
283 #endif
284 
285 /**
286  * lapic_get_maxlvt - get the maximum number of local vector table entries
287  */
288 int lapic_get_maxlvt(void)
289 {
290         unsigned int v;
291 
292         v = apic_read(APIC_LVR);
293         /*
294          * - we always have APIC integrated on 64bit mode
295          * - 82489DXs do not report # of LVT entries
296          */
297         return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
298 }
299 
300 /*
301  * Local APIC timer
302  */
303 
304 /* Clock divisor */
305 #define APIC_DIVISOR 16
306 
307 /*
308  * This function sets up the local APIC timer, with a timeout of
309  * 'clocks' APIC bus clock. During calibration we actually call
310  * this function twice on the boot CPU, once with a bogus timeout
311  * value, second time for real. The other (noncalibrating) CPUs
312  * call this function only once, with the real, calibrated value.
313  *
314  * We do reads before writes even if unnecessary, to get around the
315  * P5 APIC double write bug.
316  */
317 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
318 {
319         unsigned int lvtt_value, tmp_value;
320 
321         lvtt_value = LOCAL_TIMER_VECTOR;
322         if (!oneshot)
323                 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
324         if (!lapic_is_integrated())
325                 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
326 
327         if (!irqen)
328                 lvtt_value |= APIC_LVT_MASKED;
329 
330         apic_write(APIC_LVTT, lvtt_value);
331 
332         /*
333          * Divide PICLK by 16
334          */
335         tmp_value = apic_read(APIC_TDCR);
336         apic_write(APIC_TDCR,
337                 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
338                 APIC_TDR_DIV_16);
339 
340         if (!oneshot)
341                 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
342 }
343 
344 /*
345  * Setup extended LVT, AMD specific
346  *
347  * Software should use the LVT offsets the BIOS provides.  The offsets
348  * are determined by the subsystems using it like those for MCE
349  * threshold or IBS.  On K8 only offset 0 (APIC500) and MCE interrupts
350  * are supported. Beginning with family 10h at least 4 offsets are
351  * available.
352  *
353  * Since the offsets must be consistent for all cores, we keep track
354  * of the LVT offsets in software and reserve the offset for the same
355  * vector also to be used on other cores. An offset is freed by
356  * setting the entry to APIC_EILVT_MASKED.
357  *
358  * If the BIOS is right, there should be no conflicts. Otherwise a
359  * "[Firmware Bug]: ..." error message is generated. However, if
360  * software does not properly determines the offsets, it is not
361  * necessarily a BIOS bug.
362  */
363 
364 static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX];
365 
366 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new)
367 {
368         return (old & APIC_EILVT_MASKED)
369                 || (new == APIC_EILVT_MASKED)
370                 || ((new & ~APIC_EILVT_MASKED) == old);
371 }
372 
373 static unsigned int reserve_eilvt_offset(int offset, unsigned int new)
374 {
375         unsigned int rsvd;                      /* 0: uninitialized */
376 
377         if (offset >= APIC_EILVT_NR_MAX)
378                 return ~0;
379 
380         rsvd = atomic_read(&eilvt_offsets[offset]) & ~APIC_EILVT_MASKED;
381         do {
382                 if (rsvd &&
383                     !eilvt_entry_is_changeable(rsvd, new))
384                         /* may not change if vectors are different */
385                         return rsvd;
386                 rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new);
387         } while (rsvd != new);
388 
389         return new;
390 }
391 
392 /*
393  * If mask=1, the LVT entry does not generate interrupts while mask=0
394  * enables the vector. See also the BKDGs. Must be called with
395  * preemption disabled.
396  */
397 
398 int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask)
399 {
400         unsigned long reg = APIC_EILVTn(offset);
401         unsigned int new, old, reserved;
402 
403         new = (mask << 16) | (msg_type << 8) | vector;
404         old = apic_read(reg);
405         reserved = reserve_eilvt_offset(offset, new);
406 
407         if (reserved != new) {
408                 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
409                        "vector 0x%x, but the register is already in use for "
410                        "vector 0x%x on another cpu\n",
411                        smp_processor_id(), reg, offset, new, reserved);
412                 return -EINVAL;
413         }
414 
415         if (!eilvt_entry_is_changeable(old, new)) {
416                 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
417                        "vector 0x%x, but the register is already in use for "
418                        "vector 0x%x on this cpu\n",
419                        smp_processor_id(), reg, offset, new, old);
420                 return -EBUSY;
421         }
422 
423         apic_write(reg, new);
424 
425         return 0;
426 }
427 EXPORT_SYMBOL_GPL(setup_APIC_eilvt);
428 
429 /*
430  * Program the next event, relative to now
431  */
432 static int lapic_next_event(unsigned long delta,
433                             struct clock_event_device *evt)
434 {
435         apic_write(APIC_TMICT, delta);
436         return 0;
437 }
438 
439 /*
440  * Setup the lapic timer in periodic or oneshot mode
441  */
442 static void lapic_timer_setup(enum clock_event_mode mode,
443                               struct clock_event_device *evt)
444 {
445         unsigned long flags;
446         unsigned int v;
447 
448         /* Lapic used as dummy for broadcast ? */
449         if (evt->features & CLOCK_EVT_FEAT_DUMMY)
450                 return;
451 
452         local_irq_save(flags);
453 
454         switch (mode) {
455         case CLOCK_EVT_MODE_PERIODIC:
456         case CLOCK_EVT_MODE_ONESHOT:
457                 __setup_APIC_LVTT(lapic_timer_frequency,
458                                   mode != CLOCK_EVT_MODE_PERIODIC, 1);
459                 break;
460         case CLOCK_EVT_MODE_UNUSED:
461         case CLOCK_EVT_MODE_SHUTDOWN:
462                 v = apic_read(APIC_LVTT);
463                 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
464                 apic_write(APIC_LVTT, v);
465                 apic_write(APIC_TMICT, 0);
466                 break;
467         case CLOCK_EVT_MODE_RESUME:
468                 /* Nothing to do here */
469                 break;
470         }
471 
472         local_irq_restore(flags);
473 }
474 
475 /*
476  * Local APIC timer broadcast function
477  */
478 static void lapic_timer_broadcast(const struct cpumask *mask)
479 {
480 #ifdef CONFIG_SMP
481         apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
482 #endif
483 }
484 
485 
486 /*
487  * The local apic timer can be used for any function which is CPU local.
488  */
489 static struct clock_event_device lapic_clockevent = {
490         .name           = "lapic",
491         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
492                         | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
493         .shift          = 32,
494         .set_mode       = lapic_timer_setup,
495         .set_next_event = lapic_next_event,
496         .broadcast      = lapic_timer_broadcast,
497         .rating         = 100,
498         .irq            = -1,
499 };
500 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
501 
502 /*
503  * Setup the local APIC timer for this CPU. Copy the initialized values
504  * of the boot CPU and register the clock event in the framework.
505  */
506 static void __cpuinit setup_APIC_timer(void)
507 {
508         struct clock_event_device *levt = &__get_cpu_var(lapic_events);
509 
510         if (this_cpu_has(X86_FEATURE_ARAT)) {
511                 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP;
512                 /* Make LAPIC timer preferrable over percpu HPET */
513                 lapic_clockevent.rating = 150;
514         }
515 
516         memcpy(levt, &lapic_clockevent, sizeof(*levt));
517         levt->cpumask = cpumask_of(smp_processor_id());
518 
519         clockevents_register_device(levt);
520 }
521 
522 /*
523  * In this functions we calibrate APIC bus clocks to the external timer.
524  *
525  * We want to do the calibration only once since we want to have local timer
526  * irqs syncron. CPUs connected by the same APIC bus have the very same bus
527  * frequency.
528  *
529  * This was previously done by reading the PIT/HPET and waiting for a wrap
530  * around to find out, that a tick has elapsed. I have a box, where the PIT
531  * readout is broken, so it never gets out of the wait loop again. This was
532  * also reported by others.
533  *
534  * Monitoring the jiffies value is inaccurate and the clockevents
535  * infrastructure allows us to do a simple substitution of the interrupt
536  * handler.
537  *
538  * The calibration routine also uses the pm_timer when possible, as the PIT
539  * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
540  * back to normal later in the boot process).
541  */
542 
543 #define LAPIC_CAL_LOOPS         (HZ/10)
544 
545 static __initdata int lapic_cal_loops = -1;
546 static __initdata long lapic_cal_t1, lapic_cal_t2;
547 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
548 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
549 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
550 
551 /*
552  * Temporary interrupt handler.
553  */
554 static void __init lapic_cal_handler(struct clock_event_device *dev)
555 {
556         unsigned long long tsc = 0;
557         long tapic = apic_read(APIC_TMCCT);
558         unsigned long pm = acpi_pm_read_early();
559 
560         if (cpu_has_tsc)
561                 rdtscll(tsc);
562 
563         switch (lapic_cal_loops++) {
564         case 0:
565                 lapic_cal_t1 = tapic;
566                 lapic_cal_tsc1 = tsc;
567                 lapic_cal_pm1 = pm;
568                 lapic_cal_j1 = jiffies;
569                 break;
570 
571         case LAPIC_CAL_LOOPS:
572                 lapic_cal_t2 = tapic;
573                 lapic_cal_tsc2 = tsc;
574                 if (pm < lapic_cal_pm1)
575                         pm += ACPI_PM_OVRRUN;
576                 lapic_cal_pm2 = pm;
577                 lapic_cal_j2 = jiffies;
578                 break;
579         }
580 }
581 
582 static int __init
583 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc)
584 {
585         const long pm_100ms = PMTMR_TICKS_PER_SEC / 10;
586         const long pm_thresh = pm_100ms / 100;
587         unsigned long mult;
588         u64 res;
589 
590 #ifndef CONFIG_X86_PM_TIMER
591         return -1;
592 #endif
593 
594         apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm);
595 
596         /* Check, if the PM timer is available */
597         if (!deltapm)
598                 return -1;
599 
600         mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
601 
602         if (deltapm > (pm_100ms - pm_thresh) &&
603             deltapm < (pm_100ms + pm_thresh)) {
604                 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n");
605                 return 0;
606         }
607 
608         res = (((u64)deltapm) *  mult) >> 22;
609         do_div(res, 1000000);
610         pr_warning("APIC calibration not consistent "
611                    "with PM-Timer: %ldms instead of 100ms\n",(long)res);
612 
613         /* Correct the lapic counter value */
614         res = (((u64)(*delta)) * pm_100ms);
615         do_div(res, deltapm);
616         pr_info("APIC delta adjusted to PM-Timer: "
617                 "%lu (%ld)\n", (unsigned long)res, *delta);
618         *delta = (long)res;
619 
620         /* Correct the tsc counter value */
621         if (cpu_has_tsc) {
622                 res = (((u64)(*deltatsc)) * pm_100ms);
623                 do_div(res, deltapm);
624                 apic_printk(APIC_VERBOSE, "TSC delta adjusted to "
625                                           "PM-Timer: %lu (%ld)\n",
626                                         (unsigned long)res, *deltatsc);
627                 *deltatsc = (long)res;
628         }
629 
630         return 0;
631 }
632 
633 static int __init calibrate_APIC_clock(void)
634 {
635         struct clock_event_device *levt = &__get_cpu_var(lapic_events);
636         void (*real_handler)(struct clock_event_device *dev);
637         unsigned long deltaj;
638         long delta, deltatsc;
639         int pm_referenced = 0;
640 
641         /**
642          * check if lapic timer has already been calibrated by platform
643          * specific routine, such as tsc calibration code. if so, we just fill
644          * in the clockevent structure and return.
645          */
646 
647         if (lapic_timer_frequency) {
648                 apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n",
649                                 lapic_timer_frequency);
650                 lapic_clockevent.mult = div_sc(lapic_timer_frequency/APIC_DIVISOR,
651                                         TICK_NSEC, lapic_clockevent.shift);
652                 lapic_clockevent.max_delta_ns =
653                         clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
654                 lapic_clockevent.min_delta_ns =
655                         clockevent_delta2ns(0xF, &lapic_clockevent);
656                 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
657                 return 0;
658         }
659 
660         local_irq_disable();
661 
662         /* Replace the global interrupt handler */
663         real_handler = global_clock_event->event_handler;
664         global_clock_event->event_handler = lapic_cal_handler;
665 
666         /*
667          * Setup the APIC counter to maximum. There is no way the lapic
668          * can underflow in the 100ms detection time frame
669          */
670         __setup_APIC_LVTT(0xffffffff, 0, 0);
671 
672         /* Let the interrupts run */
673         local_irq_enable();
674 
675         while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
676                 cpu_relax();
677 
678         local_irq_disable();
679 
680         /* Restore the real event handler */
681         global_clock_event->event_handler = real_handler;
682 
683         /* Build delta t1-t2 as apic timer counts down */
684         delta = lapic_cal_t1 - lapic_cal_t2;
685         apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
686 
687         deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
688 
689         /* we trust the PM based calibration if possible */
690         pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,
691                                         &delta, &deltatsc);
692 
693         /* Calculate the scaled math multiplication factor */
694         lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
695                                        lapic_clockevent.shift);
696         lapic_clockevent.max_delta_ns =
697                 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent);
698         lapic_clockevent.min_delta_ns =
699                 clockevent_delta2ns(0xF, &lapic_clockevent);
700 
701         lapic_timer_frequency = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
702 
703         apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
704         apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult);
705         apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
706                     lapic_timer_frequency);
707 
708         if (cpu_has_tsc) {
709                 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
710                             "%ld.%04ld MHz.\n",
711                             (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ),
712                             (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ));
713         }
714 
715         apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
716                     "%u.%04u MHz.\n",
717                     lapic_timer_frequency / (1000000 / HZ),
718                     lapic_timer_frequency % (1000000 / HZ));
719 
720         /*
721          * Do a sanity check on the APIC calibration result
722          */
723         if (lapic_timer_frequency < (1000000 / HZ)) {
724                 local_irq_enable();
725                 pr_warning("APIC frequency too slow, disabling apic timer\n");
726                 return -1;
727         }
728 
729         levt->features &= ~CLOCK_EVT_FEAT_DUMMY;
730 
731         /*
732          * PM timer calibration failed or not turned on
733          * so lets try APIC timer based calibration
734          */
735         if (!pm_referenced) {
736                 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
737 
738                 /*
739                  * Setup the apic timer manually
740                  */
741                 levt->event_handler = lapic_cal_handler;
742                 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt);
743                 lapic_cal_loops = -1;
744 
745                 /* Let the interrupts run */
746                 local_irq_enable();
747 
748                 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
749                         cpu_relax();
750 
751                 /* Stop the lapic timer */
752                 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt);
753 
754                 /* Jiffies delta */
755                 deltaj = lapic_cal_j2 - lapic_cal_j1;
756                 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
757 
758                 /* Check, if the jiffies result is consistent */
759                 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
760                         apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
761                 else
762                         levt->features |= CLOCK_EVT_FEAT_DUMMY;
763         } else
764                 local_irq_enable();
765 
766         if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
767                 pr_warning("APIC timer disabled due to verification failure\n");
768                         return -1;
769         }
770 
771         return 0;
772 }
773 
774 /*
775  * Setup the boot APIC
776  *
777  * Calibrate and verify the result.
778  */
779 void __init setup_boot_APIC_clock(void)
780 {
781         /*
782          * The local apic timer can be disabled via the kernel
783          * commandline or from the CPU detection code. Register the lapic
784          * timer as a dummy clock event source on SMP systems, so the
785          * broadcast mechanism is used. On UP systems simply ignore it.
786          */
787         if (disable_apic_timer) {
788                 pr_info("Disabling APIC timer\n");
789                 /* No broadcast on UP ! */
790                 if (num_possible_cpus() > 1) {
791                         lapic_clockevent.mult = 1;
792                         setup_APIC_timer();
793                 }
794                 return;
795         }
796 
797         apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
798                     "calibrating APIC timer ...\n");
799 
800         if (calibrate_APIC_clock()) {
801                 /* No broadcast on UP ! */
802                 if (num_possible_cpus() > 1)
803                         setup_APIC_timer();
804                 return;
805         }
806 
807         /*
808          * If nmi_watchdog is set to IO_APIC, we need the
809          * PIT/HPET going.  Otherwise register lapic as a dummy
810          * device.
811          */
812         lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
813 
814         /* Setup the lapic or request the broadcast */
815         setup_APIC_timer();
816 }
817 
818 void __cpuinit setup_secondary_APIC_clock(void)
819 {
820         setup_APIC_timer();
821 }
822 
823 /*
824  * The guts of the apic timer interrupt
825  */
826 static void local_apic_timer_interrupt(void)
827 {
828         int cpu = smp_processor_id();
829         struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
830 
831         /*
832          * Normally we should not be here till LAPIC has been initialized but
833          * in some cases like kdump, its possible that there is a pending LAPIC
834          * timer interrupt from previous kernel's context and is delivered in
835          * new kernel the moment interrupts are enabled.
836          *
837          * Interrupts are enabled early and LAPIC is setup much later, hence
838          * its possible that when we get here evt->event_handler is NULL.
839          * Check for event_handler being NULL and discard the interrupt as
840          * spurious.
841          */
842         if (!evt->event_handler) {
843                 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu);
844                 /* Switch it off */
845                 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
846                 return;
847         }
848 
849         /*
850          * the NMI deadlock-detector uses this.
851          */
852         inc_irq_stat(apic_timer_irqs);
853 
854         evt->event_handler(evt);
855 }
856 
857 /*
858  * Local APIC timer interrupt. This is the most natural way for doing
859  * local interrupts, but local timer interrupts can be emulated by
860  * broadcast interrupts too. [in case the hw doesn't support APIC timers]
861  *
862  * [ if a single-CPU system runs an SMP kernel then we call the local
863  *   interrupt as well. Thus we cannot inline the local irq ... ]
864  */
865 void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs)
866 {
867         struct pt_regs *old_regs = set_irq_regs(regs);
868 
869         /*
870          * NOTE! We'd better ACK the irq immediately,
871          * because timer handling can be slow.
872          */
873         ack_APIC_irq();
874         /*
875          * update_process_times() expects us to have done irq_enter().
876          * Besides, if we don't timer interrupts ignore the global
877          * interrupt lock, which is the WrongThing (tm) to do.
878          */
879         exit_idle();
880         irq_enter();
881         local_apic_timer_interrupt();
882         irq_exit();
883 
884         set_irq_regs(old_regs);
885 }
886 
887 int setup_profiling_timer(unsigned int multiplier)
888 {
889         return -EINVAL;
890 }
891 
892 /*
893  * Local APIC start and shutdown
894  */
895 
896 /**
897  * clear_local_APIC - shutdown the local APIC
898  *
899  * This is called, when a CPU is disabled and before rebooting, so the state of
900  * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
901  * leftovers during boot.
902  */
903 void clear_local_APIC(void)
904 {
905         int maxlvt;
906         u32 v;
907 
908         /* APIC hasn't been mapped yet */
909         if (!x2apic_mode && !apic_phys)
910                 return;
911 
912         maxlvt = lapic_get_maxlvt();
913         /*
914          * Masking an LVT entry can trigger a local APIC error
915          * if the vector is zero. Mask LVTERR first to prevent this.
916          */
917         if (maxlvt >= 3) {
918                 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
919                 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
920         }
921         /*
922          * Careful: we have to set masks only first to deassert
923          * any level-triggered sources.
924          */
925         v = apic_read(APIC_LVTT);
926         apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
927         v = apic_read(APIC_LVT0);
928         apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
929         v = apic_read(APIC_LVT1);
930         apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
931         if (maxlvt >= 4) {
932                 v = apic_read(APIC_LVTPC);
933                 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
934         }
935 
936         /* lets not touch this if we didn't frob it */
937 #ifdef CONFIG_X86_THERMAL_VECTOR
938         if (maxlvt >= 5) {
939                 v = apic_read(APIC_LVTTHMR);
940                 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
941         }
942 #endif
943 #ifdef CONFIG_X86_MCE_INTEL
944         if (maxlvt >= 6) {
945                 v = apic_read(APIC_LVTCMCI);
946                 if (!(v & APIC_LVT_MASKED))
947                         apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED);
948         }
949 #endif
950 
951         /*
952          * Clean APIC state for other OSs:
953          */
954         apic_write(APIC_LVTT, APIC_LVT_MASKED);
955         apic_write(APIC_LVT0, APIC_LVT_MASKED);
956         apic_write(APIC_LVT1, APIC_LVT_MASKED);
957         if (maxlvt >= 3)
958                 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
959         if (maxlvt >= 4)
960                 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
961 
962         /* Integrated APIC (!82489DX) ? */
963         if (lapic_is_integrated()) {
964                 if (maxlvt > 3)
965                         /* Clear ESR due to Pentium errata 3AP and 11AP */
966                         apic_write(APIC_ESR, 0);
967                 apic_read(APIC_ESR);
968         }
969 }
970 
971 /**
972  * disable_local_APIC - clear and disable the local APIC
973  */
974 void disable_local_APIC(void)
975 {
976         unsigned int value;
977 
978         /* APIC hasn't been mapped yet */
979         if (!x2apic_mode && !apic_phys)
980                 return;
981 
982         clear_local_APIC();
983 
984         /*
985          * Disable APIC (implies clearing of registers
986          * for 82489DX!).
987          */
988         value = apic_read(APIC_SPIV);
989         value &= ~APIC_SPIV_APIC_ENABLED;
990         apic_write(APIC_SPIV, value);
991 
992 #ifdef CONFIG_X86_32
993         /*
994          * When LAPIC was disabled by the BIOS and enabled by the kernel,
995          * restore the disabled state.
996          */
997         if (enabled_via_apicbase) {
998                 unsigned int l, h;
999 
1000                 rdmsr(MSR_IA32_APICBASE, l, h);
1001                 l &= ~MSR_IA32_APICBASE_ENABLE;
1002                 wrmsr(MSR_IA32_APICBASE, l, h);
1003         }
1004 #endif
1005 }
1006 
1007 /*
1008  * If Linux enabled the LAPIC against the BIOS default disable it down before
1009  * re-entering the BIOS on shutdown.  Otherwise the BIOS may get confused and
1010  * not power-off.  Additionally clear all LVT entries before disable_local_APIC
1011  * for the case where Linux didn't enable the LAPIC.
1012  */
1013 void lapic_shutdown(void)
1014 {
1015         unsigned long flags;
1016 
1017         if (!cpu_has_apic && !apic_from_smp_config())
1018                 return;
1019 
1020         local_irq_save(flags);
1021 
1022 #ifdef CONFIG_X86_32
1023         if (!enabled_via_apicbase)
1024                 clear_local_APIC();
1025         else
1026 #endif
1027                 disable_local_APIC();
1028 
1029 
1030         local_irq_restore(flags);
1031 }
1032 
1033 /*
1034  * This is to verify that we're looking at a real local APIC.
1035  * Check these against your board if the CPUs aren't getting
1036  * started for no apparent reason.
1037  */
1038 int __init verify_local_APIC(void)
1039 {
1040         unsigned int reg0, reg1;
1041 
1042         /*
1043          * The version register is read-only in a real APIC.
1044          */
1045         reg0 = apic_read(APIC_LVR);
1046         apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
1047         apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
1048         reg1 = apic_read(APIC_LVR);
1049         apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
1050 
1051         /*
1052          * The two version reads above should print the same
1053          * numbers.  If the second one is different, then we
1054          * poke at a non-APIC.
1055          */
1056         if (reg1 != reg0)
1057                 return 0;
1058 
1059         /*
1060          * Check if the version looks reasonably.
1061          */
1062         reg1 = GET_APIC_VERSION(reg0);
1063         if (reg1 == 0x00 || reg1 == 0xff)
1064                 return 0;
1065         reg1 = lapic_get_maxlvt();
1066         if (reg1 < 0x02 || reg1 == 0xff)
1067                 return 0;
1068 
1069         /*
1070          * The ID register is read/write in a real APIC.
1071          */
1072         reg0 = apic_read(APIC_ID);
1073         apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
1074         apic_write(APIC_ID, reg0 ^ apic->apic_id_mask);
1075         reg1 = apic_read(APIC_ID);
1076         apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
1077         apic_write(APIC_ID, reg0);
1078         if (reg1 != (reg0 ^ apic->apic_id_mask))
1079                 return 0;
1080 
1081         /*
1082          * The next two are just to see if we have sane values.
1083          * They're only really relevant if we're in Virtual Wire
1084          * compatibility mode, but most boxes are anymore.
1085          */
1086         reg0 = apic_read(APIC_LVT0);
1087         apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
1088         reg1 = apic_read(APIC_LVT1);
1089         apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
1090 
1091         return 1;
1092 }
1093 
1094 /**
1095  * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1096  */
1097 void __init sync_Arb_IDs(void)
1098 {
1099         /*
1100          * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1101          * needed on AMD.
1102          */
1103         if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1104                 return;
1105 
1106         /*
1107          * Wait for idle.
1108          */
1109         apic_wait_icr_idle();
1110 
1111         apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
1112         apic_write(APIC_ICR, APIC_DEST_ALLINC |
1113                         APIC_INT_LEVELTRIG | APIC_DM_INIT);
1114 }
1115 
1116 /*
1117  * An initial setup of the virtual wire mode.
1118  */
1119 void __init init_bsp_APIC(void)
1120 {
1121         unsigned int value;
1122 
1123         /*
1124          * Don't do the setup now if we have a SMP BIOS as the
1125          * through-I/O-APIC virtual wire mode might be active.
1126          */
1127         if (smp_found_config || !cpu_has_apic)
1128                 return;
1129 
1130         /*
1131          * Do not trust the local APIC being empty at bootup.
1132          */
1133         clear_local_APIC();
1134 
1135         /*
1136          * Enable APIC.
1137          */
1138         value = apic_read(APIC_SPIV);
1139         value &= ~APIC_VECTOR_MASK;
1140         value |= APIC_SPIV_APIC_ENABLED;
1141 
1142 #ifdef CONFIG_X86_32
1143         /* This bit is reserved on P4/Xeon and should be cleared */
1144         if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
1145             (boot_cpu_data.x86 == 15))
1146                 value &= ~APIC_SPIV_FOCUS_DISABLED;
1147         else
1148 #endif
1149                 value |= APIC_SPIV_FOCUS_DISABLED;
1150         value |= SPURIOUS_APIC_VECTOR;
1151         apic_write(APIC_SPIV, value);
1152 
1153         /*
1154          * Set up the virtual wire mode.
1155          */
1156         apic_write(APIC_LVT0, APIC_DM_EXTINT);
1157         value = APIC_DM_NMI;
1158         if (!lapic_is_integrated())             /* 82489DX */
1159                 value |= APIC_LVT_LEVEL_TRIGGER;
1160         apic_write(APIC_LVT1, value);
1161 }
1162 
1163 static void __cpuinit lapic_setup_esr(void)
1164 {
1165         unsigned int oldvalue, value, maxlvt;
1166 
1167         if (!lapic_is_integrated()) {
1168                 pr_info("No ESR for 82489DX.\n");
1169                 return;
1170         }
1171 
1172         if (apic->disable_esr) {
1173                 /*
1174                  * Something untraceable is creating bad interrupts on
1175                  * secondary quads ... for the moment, just leave the
1176                  * ESR disabled - we can't do anything useful with the
1177                  * errors anyway - mbligh
1178                  */
1179                 pr_info("Leaving ESR disabled.\n");
1180                 return;
1181         }
1182 
1183         maxlvt = lapic_get_maxlvt();
1184         if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
1185                 apic_write(APIC_ESR, 0);
1186         oldvalue = apic_read(APIC_ESR);
1187 
1188         /* enables sending errors */
1189         value = ERROR_APIC_VECTOR;
1190         apic_write(APIC_LVTERR, value);
1191 
1192         /*
1193          * spec says clear errors after enabling vector.
1194          */
1195         if (maxlvt > 3)
1196                 apic_write(APIC_ESR, 0);
1197         value = apic_read(APIC_ESR);
1198         if (value != oldvalue)
1199                 apic_printk(APIC_VERBOSE, "ESR value before enabling "
1200                         "vector: 0x%08x  after: 0x%08x\n",
1201                         oldvalue, value);
1202 }
1203 
1204 /**
1205  * setup_local_APIC - setup the local APIC
1206  *
1207  * Used to setup local APIC while initializing BSP or bringin up APs.
1208  * Always called with preemption disabled.
1209  */
1210 void __cpuinit setup_local_APIC(void)
1211 {
1212         int cpu = smp_processor_id();
1213         unsigned int value, queued;
1214         int i, j, acked = 0;
1215         unsigned long long tsc = 0, ntsc;
1216         long long max_loops = cpu_khz ? cpu_khz : 1000000;
1217 
1218         if (cpu_has_tsc)
1219                 rdtscll(tsc);
1220 
1221         if (disable_apic) {
1222                 disable_ioapic_support();
1223                 return;
1224         }
1225 
1226 #ifdef CONFIG_X86_32
1227         /* Pound the ESR really hard over the head with a big hammer - mbligh */
1228         if (lapic_is_integrated() && apic->disable_esr) {
1229                 apic_write(APIC_ESR, 0);
1230                 apic_write(APIC_ESR, 0);
1231                 apic_write(APIC_ESR, 0);
1232                 apic_write(APIC_ESR, 0);
1233         }
1234 #endif
1235         perf_events_lapic_init();
1236 
1237         /*
1238          * Double-check whether this APIC is really registered.
1239          * This is meaningless in clustered apic mode, so we skip it.
1240          */
1241         BUG_ON(!apic->apic_id_registered());
1242 
1243         /*
1244          * Intel recommends to set DFR, LDR and TPR before enabling
1245          * an APIC.  See e.g. "AP-388 82489DX User's Manual" (Intel
1246          * document number 292116).  So here it goes...
1247          */
1248         apic->init_apic_ldr();
1249 
1250 #ifdef CONFIG_X86_32
1251         /*
1252          * APIC LDR is initialized.  If logical_apicid mapping was
1253          * initialized during get_smp_config(), make sure it matches the
1254          * actual value.
1255          */
1256         i = early_per_cpu(x86_cpu_to_logical_apicid, cpu);
1257         WARN_ON(i != BAD_APICID && i != logical_smp_processor_id());
1258         /* always use the value from LDR */
1259         early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
1260                 logical_smp_processor_id();
1261 
1262         /*
1263          * Some NUMA implementations (NUMAQ) don't initialize apicid to
1264          * node mapping during NUMA init.  Now that logical apicid is
1265          * guaranteed to be known, give it another chance.  This is already
1266          * a bit too late - percpu allocation has already happened without
1267          * proper NUMA affinity.
1268          */
1269         if (apic->x86_32_numa_cpu_node)
1270                 set_apicid_to_node(early_per_cpu(x86_cpu_to_apicid, cpu),
1271                                    apic->x86_32_numa_cpu_node(cpu));
1272 #endif
1273 
1274         /*
1275          * Set Task Priority to 'accept all'. We never change this
1276          * later on.
1277          */
1278         value = apic_read(APIC_TASKPRI);
1279         value &= ~APIC_TPRI_MASK;
1280         apic_write(APIC_TASKPRI, value);
1281 
1282         /*
1283          * After a crash, we no longer service the interrupts and a pending
1284          * interrupt from previous kernel might still have ISR bit set.
1285          *
1286          * Most probably by now CPU has serviced that pending interrupt and
1287          * it might not have done the ack_APIC_irq() because it thought,
1288          * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1289          * does not clear the ISR bit and cpu thinks it has already serivced
1290          * the interrupt. Hence a vector might get locked. It was noticed
1291          * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1292          */
1293         do {
1294                 queued = 0;
1295                 for (i = APIC_ISR_NR - 1; i >= 0; i--)
1296                         queued |= apic_read(APIC_IRR + i*0x10);
1297 
1298                 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
1299                         value = apic_read(APIC_ISR + i*0x10);
1300                         for (j = 31; j >= 0; j--) {
1301                                 if (value & (1<<j)) {
1302                                         ack_APIC_irq();
1303                                         acked++;
1304                                 }
1305                         }
1306                 }
1307                 if (acked > 256) {
1308                         printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n",
1309                                acked);
1310                         break;
1311                 }
1312                 if (queued) {
1313                         if (cpu_has_tsc && cpu_khz) {
1314                                 rdtscll(ntsc);
1315                                 max_loops = (cpu_khz << 10) - (ntsc - tsc);
1316                         } else
1317                                 max_loops--;
1318                 }
1319         } while (queued && max_loops > 0);
1320         WARN_ON(max_loops <= 0);
1321 
1322         /*
1323          * Now that we are all set up, enable the APIC
1324          */
1325         value = apic_read(APIC_SPIV);
1326         value &= ~APIC_VECTOR_MASK;
1327         /*
1328          * Enable APIC
1329          */
1330         value |= APIC_SPIV_APIC_ENABLED;
1331 
1332 #ifdef CONFIG_X86_32
1333         /*
1334          * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1335          * certain networking cards. If high frequency interrupts are
1336          * happening on a particular IOAPIC pin, plus the IOAPIC routing
1337          * entry is masked/unmasked at a high rate as well then sooner or
1338          * later IOAPIC line gets 'stuck', no more interrupts are received
1339          * from the device. If focus CPU is disabled then the hang goes
1340          * away, oh well :-(
1341          *
1342          * [ This bug can be reproduced easily with a level-triggered
1343          *   PCI Ne2000 networking cards and PII/PIII processors, dual
1344          *   BX chipset. ]
1345          */
1346         /*
1347          * Actually disabling the focus CPU check just makes the hang less
1348          * frequent as it makes the interrupt distributon model be more
1349          * like LRU than MRU (the short-term load is more even across CPUs).
1350          * See also the comment in end_level_ioapic_irq().  --macro
1351          */
1352 
1353         /*
1354          * - enable focus processor (bit==0)
1355          * - 64bit mode always use processor focus
1356          *   so no need to set it
1357          */
1358         value &= ~APIC_SPIV_FOCUS_DISABLED;
1359 #endif
1360 
1361         /*
1362          * Set spurious IRQ vector
1363          */
1364         value |= SPURIOUS_APIC_VECTOR;
1365         apic_write(APIC_SPIV, value);
1366 
1367         /*
1368          * Set up LVT0, LVT1:
1369          *
1370          * set up through-local-APIC on the BP's LINT0. This is not
1371          * strictly necessary in pure symmetric-IO mode, but sometimes
1372          * we delegate interrupts to the 8259A.
1373          */
1374         /*
1375          * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1376          */
1377         value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1378         if (!cpu && (pic_mode || !value)) {
1379                 value = APIC_DM_EXTINT;
1380                 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu);
1381         } else {
1382                 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1383                 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu);
1384         }
1385         apic_write(APIC_LVT0, value);
1386 
1387         /*
1388          * only the BP should see the LINT1 NMI signal, obviously.
1389          */
1390         if (!cpu)
1391                 value = APIC_DM_NMI;
1392         else
1393                 value = APIC_DM_NMI | APIC_LVT_MASKED;
1394         if (!lapic_is_integrated())             /* 82489DX */
1395                 value |= APIC_LVT_LEVEL_TRIGGER;
1396         apic_write(APIC_LVT1, value);
1397 
1398 #ifdef CONFIG_X86_MCE_INTEL
1399         /* Recheck CMCI information after local APIC is up on CPU #0 */
1400         if (!cpu)
1401                 cmci_recheck();
1402 #endif
1403 }
1404 
1405 void __cpuinit end_local_APIC_setup(void)
1406 {
1407         lapic_setup_esr();
1408 
1409 #ifdef CONFIG_X86_32
1410         {
1411                 unsigned int value;
1412                 /* Disable the local apic timer */
1413                 value = apic_read(APIC_LVTT);
1414                 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1415                 apic_write(APIC_LVTT, value);
1416         }
1417 #endif
1418 
1419         apic_pm_activate();
1420 }
1421 
1422 void __init bsp_end_local_APIC_setup(void)
1423 {
1424         end_local_APIC_setup();
1425 
1426         /*
1427          * Now that local APIC setup is completed for BP, configure the fault
1428          * handling for interrupt remapping.
1429          */
1430         if (intr_remapping_enabled)
1431                 enable_drhd_fault_handling();
1432 
1433 }
1434 
1435 #ifdef CONFIG_X86_X2APIC
1436 void check_x2apic(void)
1437 {
1438         if (x2apic_enabled()) {
1439                 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n");
1440                 x2apic_preenabled = x2apic_mode = 1;
1441         }
1442 }
1443 
1444 void enable_x2apic(void)
1445 {
1446         int msr, msr2;
1447 
1448         if (!x2apic_mode)
1449                 return;
1450 
1451         rdmsr(MSR_IA32_APICBASE, msr, msr2);
1452         if (!(msr & X2APIC_ENABLE)) {
1453                 printk_once(KERN_INFO "Enabling x2apic\n");
1454                 wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, msr2);
1455         }
1456 }
1457 #endif /* CONFIG_X86_X2APIC */
1458 
1459 int __init enable_IR(void)
1460 {
1461 #ifdef CONFIG_IRQ_REMAP
1462         if (!intr_remapping_supported()) {
1463                 pr_debug("intr-remapping not supported\n");
1464                 return -1;
1465         }
1466 
1467         if (!x2apic_preenabled && skip_ioapic_setup) {
1468                 pr_info("Skipped enabling intr-remap because of skipping "
1469                         "io-apic setup\n");
1470                 return -1;
1471         }
1472 
1473         return enable_intr_remapping();
1474 #endif
1475         return -1;
1476 }
1477 
1478 void __init enable_IR_x2apic(void)
1479 {
1480         unsigned long flags;
1481         int ret, x2apic_enabled = 0;
1482         int dmar_table_init_ret;
1483 
1484         if (skip_ioapic_setup)
1485                 return;
1486 
1487         dmar_table_init_ret = dmar_table_init();
1488         if (dmar_table_init_ret && !x2apic_supported())
1489                 return;
1490 
1491         ret = save_ioapic_entries();
1492         if (ret) {
1493                 pr_info("Saving IO-APIC state failed: %d\n", ret);
1494                 goto out;
1495         }
1496 
1497         local_irq_save(flags);
1498         legacy_pic->mask_all();
1499         mask_ioapic_entries();
1500 
1501         if (dmar_table_init_ret)
1502                 ret = -1;
1503         else
1504                 ret = enable_IR();
1505 
1506         if (ret < 0) {
1507                 /* IR is required if there is APIC ID > 255 even when running
1508                  * under KVM
1509                  */
1510                 if (max_physical_apicid > 255 ||
1511                     !hypervisor_x2apic_available())
1512                         goto nox2apic;
1513                 /*
1514                  * without IR all CPUs can be addressed by IOAPIC/MSI
1515                  * only in physical mode
1516                  */
1517                 x2apic_force_phys();
1518         }
1519 
1520         if (ret == IRQ_REMAP_XAPIC_MODE)
1521                 goto nox2apic;
1522 
1523         x2apic_enabled = 1;
1524 
1525         if (x2apic_supported() && !x2apic_mode) {
1526                 x2apic_mode = 1;
1527                 enable_x2apic();
1528                 pr_info("Enabled x2apic\n");
1529         }
1530 
1531 nox2apic:
1532         if (ret < 0) /* IR enabling failed */
1533                 restore_ioapic_entries();
1534         legacy_pic->restore_mask();
1535         local_irq_restore(flags);
1536 
1537 out:
1538         if (x2apic_enabled || !x2apic_supported())
1539                 return;
1540 
1541         if (x2apic_preenabled)
1542                 panic("x2apic: enabled by BIOS but kernel init failed.");
1543         else if (ret == IRQ_REMAP_XAPIC_MODE)
1544                 pr_info("x2apic not enabled, IRQ remapping is in xapic mode\n");
1545         else if (ret < 0)
1546                 pr_info("x2apic not enabled, IRQ remapping init failed\n");
1547 }
1548 
1549 #ifdef CONFIG_X86_64
1550 /*
1551  * Detect and enable local APICs on non-SMP boards.
1552  * Original code written by Keir Fraser.
1553  * On AMD64 we trust the BIOS - if it says no APIC it is likely
1554  * not correctly set up (usually the APIC timer won't work etc.)
1555  */
1556 static int __init detect_init_APIC(void)
1557 {
1558         if (!cpu_has_apic) {
1559                 pr_info("No local APIC present\n");
1560                 return -1;
1561         }
1562 
1563         mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1564         return 0;
1565 }
1566 #else
1567 
1568 static int __init apic_verify(void)
1569 {
1570         u32 features, h, l;
1571 
1572         /*
1573          * The APIC feature bit should now be enabled
1574          * in `cpuid'
1575          */
1576         features = cpuid_edx(1);
1577         if (!(features & (1 << X86_FEATURE_APIC))) {
1578                 pr_warning("Could not enable APIC!\n");
1579                 return -1;
1580         }
1581         set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1582         mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1583 
1584         /* The BIOS may have set up the APIC at some other address */
1585         if (boot_cpu_data.x86 >= 6) {
1586                 rdmsr(MSR_IA32_APICBASE, l, h);
1587                 if (l & MSR_IA32_APICBASE_ENABLE)
1588                         mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1589         }
1590 
1591         pr_info("Found and enabled local APIC!\n");
1592         return 0;
1593 }
1594 
1595 int __init apic_force_enable(unsigned long addr)
1596 {
1597         u32 h, l;
1598 
1599         if (disable_apic)
1600                 return -1;
1601 
1602         /*
1603          * Some BIOSes disable the local APIC in the APIC_BASE
1604          * MSR. This can only be done in software for Intel P6 or later
1605          * and AMD K7 (Model > 1) or later.
1606          */
1607         if (boot_cpu_data.x86 >= 6) {
1608                 rdmsr(MSR_IA32_APICBASE, l, h);
1609                 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
1610                         pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1611                         l &= ~MSR_IA32_APICBASE_BASE;
1612                         l |= MSR_IA32_APICBASE_ENABLE | addr;
1613                         wrmsr(MSR_IA32_APICBASE, l, h);
1614                         enabled_via_apicbase = 1;
1615                 }
1616         }
1617         return apic_verify();
1618 }
1619 
1620 /*
1621  * Detect and initialize APIC
1622  */
1623 static int __init detect_init_APIC(void)
1624 {
1625         /* Disabled by kernel option? */
1626         if (disable_apic)
1627                 return -1;
1628 
1629         switch (boot_cpu_data.x86_vendor) {
1630         case X86_VENDOR_AMD:
1631                 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1632                     (boot_cpu_data.x86 >= 15))
1633                         break;
1634                 goto no_apic;
1635         case X86_VENDOR_INTEL:
1636                 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
1637                     (boot_cpu_data.x86 == 5 && cpu_has_apic))
1638                         break;
1639                 goto no_apic;
1640         default:
1641                 goto no_apic;
1642         }
1643 
1644         if (!cpu_has_apic) {
1645                 /*
1646                  * Over-ride BIOS and try to enable the local APIC only if
1647                  * "lapic" specified.
1648                  */
1649                 if (!force_enable_local_apic) {
1650                         pr_info("Local APIC disabled by BIOS -- "
1651                                 "you can enable it with \"lapic\"\n");
1652                         return -1;
1653                 }
1654                 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE))
1655                         return -1;
1656         } else {
1657                 if (apic_verify())
1658                         return -1;
1659         }
1660 
1661         apic_pm_activate();
1662 
1663         return 0;
1664 
1665 no_apic:
1666         pr_info("No local APIC present or hardware disabled\n");
1667         return -1;
1668 }
1669 #endif
1670 
1671 /**
1672  * init_apic_mappings - initialize APIC mappings
1673  */
1674 void __init init_apic_mappings(void)
1675 {
1676         unsigned int new_apicid;
1677 
1678         if (x2apic_mode) {
1679                 boot_cpu_physical_apicid = read_apic_id();
1680                 return;
1681         }
1682 
1683         /* If no local APIC can be found return early */
1684         if (!smp_found_config && detect_init_APIC()) {
1685                 /* lets NOP'ify apic operations */
1686                 pr_info("APIC: disable apic facility\n");
1687                 apic_disable();
1688         } else {
1689                 apic_phys = mp_lapic_addr;
1690 
1691                 /*
1692                  * acpi lapic path already maps that address in
1693                  * acpi_register_lapic_address()
1694                  */
1695                 if (!acpi_lapic && !smp_found_config)
1696                         register_lapic_address(apic_phys);
1697         }
1698 
1699         /*
1700          * Fetch the APIC ID of the BSP in case we have a
1701          * default configuration (or the MP table is broken).
1702          */
1703         new_apicid = read_apic_id();
1704         if (boot_cpu_physical_apicid != new_apicid) {
1705                 boot_cpu_physical_apicid = new_apicid;
1706                 /*
1707                  * yeah -- we lie about apic_version
1708                  * in case if apic was disabled via boot option
1709                  * but it's not a problem for SMP compiled kernel
1710                  * since smp_sanity_check is prepared for such a case
1711                  * and disable smp mode
1712                  */
1713                 apic_version[new_apicid] =
1714                          GET_APIC_VERSION(apic_read(APIC_LVR));
1715         }
1716 }
1717 
1718 void __init register_lapic_address(unsigned long address)
1719 {
1720         mp_lapic_addr = address;
1721 
1722         if (!x2apic_mode) {
1723                 set_fixmap_nocache(FIX_APIC_BASE, address);
1724                 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
1725                             APIC_BASE, mp_lapic_addr);
1726         }
1727         if (boot_cpu_physical_apicid == -1U) {
1728                 boot_cpu_physical_apicid  = read_apic_id();
1729                 apic_version[boot_cpu_physical_apicid] =
1730                          GET_APIC_VERSION(apic_read(APIC_LVR));
1731         }
1732 }
1733 
1734 /*
1735  * This initializes the IO-APIC and APIC hardware if this is
1736  * a UP kernel.
1737  */
1738 int apic_version[MAX_LOCAL_APIC];
1739 
1740 int __init APIC_init_uniprocessor(void)
1741 {
1742         if (disable_apic) {
1743                 pr_info("Apic disabled\n");
1744                 return -1;
1745         }
1746 #ifdef CONFIG_X86_64
1747         if (!cpu_has_apic) {
1748                 disable_apic = 1;
1749                 pr_info("Apic disabled by BIOS\n");
1750                 return -1;
1751         }
1752 #else
1753         if (!smp_found_config && !cpu_has_apic)
1754                 return -1;
1755 
1756         /*
1757          * Complain if the BIOS pretends there is one.
1758          */
1759         if (!cpu_has_apic &&
1760             APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
1761                 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
1762                         boot_cpu_physical_apicid);
1763                 return -1;
1764         }
1765 #endif
1766 
1767         default_setup_apic_routing();
1768 
1769         verify_local_APIC();
1770         connect_bsp_APIC();
1771 
1772 #ifdef CONFIG_X86_64
1773         apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid));
1774 #else
1775         /*
1776          * Hack: In case of kdump, after a crash, kernel might be booting
1777          * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1778          * might be zero if read from MP tables. Get it from LAPIC.
1779          */
1780 # ifdef CONFIG_CRASH_DUMP
1781         boot_cpu_physical_apicid = read_apic_id();
1782 # endif
1783 #endif
1784         physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1785         setup_local_APIC();
1786 
1787 #ifdef CONFIG_X86_IO_APIC
1788         /*
1789          * Now enable IO-APICs, actually call clear_IO_APIC
1790          * We need clear_IO_APIC before enabling error vector
1791          */
1792         if (!skip_ioapic_setup && nr_ioapics)
1793                 enable_IO_APIC();
1794 #endif
1795 
1796         bsp_end_local_APIC_setup();
1797 
1798 #ifdef CONFIG_X86_IO_APIC
1799         if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
1800                 setup_IO_APIC();
1801         else {
1802                 nr_ioapics = 0;
1803         }
1804 #endif
1805 
1806         x86_init.timers.setup_percpu_clockev();
1807         return 0;
1808 }
1809 
1810 /*
1811  * Local APIC interrupts
1812  */
1813 
1814 /*
1815  * This interrupt should _never_ happen with our APIC/SMP architecture
1816  */
1817 void smp_spurious_interrupt(struct pt_regs *regs)
1818 {
1819         u32 v;
1820 
1821         exit_idle();
1822         irq_enter();
1823         /*
1824          * Check if this really is a spurious interrupt and ACK it
1825          * if it is a vectored one.  Just in case...
1826          * Spurious interrupts should not be ACKed.
1827          */
1828         v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
1829         if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
1830                 ack_APIC_irq();
1831 
1832         inc_irq_stat(irq_spurious_count);
1833 
1834         /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1835         pr_info("spurious APIC interrupt on CPU#%d, "
1836                 "should never happen.\n", smp_processor_id());
1837         irq_exit();
1838 }
1839 
1840 /*
1841  * This interrupt should never happen with our APIC/SMP architecture
1842  */
1843 void smp_error_interrupt(struct pt_regs *regs)
1844 {
1845         u32 v0, v1;
1846         u32 i = 0;
1847         static const char * const error_interrupt_reason[] = {
1848                 "Send CS error",                /* APIC Error Bit 0 */
1849                 "Receive CS error",             /* APIC Error Bit 1 */
1850                 "Send accept error",            /* APIC Error Bit 2 */
1851                 "Receive accept error",         /* APIC Error Bit 3 */
1852                 "Redirectable IPI",             /* APIC Error Bit 4 */
1853                 "Send illegal vector",          /* APIC Error Bit 5 */
1854                 "Received illegal vector",      /* APIC Error Bit 6 */
1855                 "Illegal register address",     /* APIC Error Bit 7 */
1856         };
1857 
1858         exit_idle();
1859         irq_enter();
1860         /* First tickle the hardware, only then report what went on. -- REW */
1861         v0 = apic_read(APIC_ESR);
1862         apic_write(APIC_ESR, 0);
1863         v1 = apic_read(APIC_ESR);
1864         ack_APIC_irq();
1865         atomic_inc(&irq_err_count);
1866 
1867         apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x(%02x)",
1868                     smp_processor_id(), v0 , v1);
1869 
1870         v1 = v1 & 0xff;
1871         while (v1) {
1872                 if (v1 & 0x1)
1873                         apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]);
1874                 i++;
1875                 v1 >>= 1;
1876         };
1877 
1878         apic_printk(APIC_DEBUG, KERN_CONT "\n");
1879 
1880         irq_exit();
1881 }
1882 
1883 /**
1884  * connect_bsp_APIC - attach the APIC to the interrupt system
1885  */
1886 void __init connect_bsp_APIC(void)
1887 {
1888 #ifdef CONFIG_X86_32
1889         if (pic_mode) {
1890                 /*
1891                  * Do not trust the local APIC being empty at bootup.
1892                  */
1893                 clear_local_APIC();
1894                 /*
1895                  * PIC mode, enable APIC mode in the IMCR, i.e.  connect BSP's
1896                  * local APIC to INT and NMI lines.
1897                  */
1898                 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
1899                                 "enabling APIC mode.\n");
1900                 imcr_pic_to_apic();
1901         }
1902 #endif
1903         if (apic->enable_apic_mode)
1904                 apic->enable_apic_mode();
1905 }
1906 
1907 /**
1908  * disconnect_bsp_APIC - detach the APIC from the interrupt system
1909  * @virt_wire_setup:    indicates, whether virtual wire mode is selected
1910  *
1911  * Virtual wire mode is necessary to deliver legacy interrupts even when the
1912  * APIC is disabled.
1913  */
1914 void disconnect_bsp_APIC(int virt_wire_setup)
1915 {
1916         unsigned int value;
1917 
1918 #ifdef CONFIG_X86_32
1919         if (pic_mode) {
1920                 /*
1921                  * Put the board back into PIC mode (has an effect only on
1922                  * certain older boards).  Note that APIC interrupts, including
1923                  * IPIs, won't work beyond this point!  The only exception are
1924                  * INIT IPIs.
1925                  */
1926                 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
1927                                 "entering PIC mode.\n");
1928                 imcr_apic_to_pic();
1929                 return;
1930         }
1931 #endif
1932 
1933         /* Go back to Virtual Wire compatibility mode */
1934 
1935         /* For the spurious interrupt use vector F, and enable it */
1936         value = apic_read(APIC_SPIV);
1937         value &= ~APIC_VECTOR_MASK;
1938         value |= APIC_SPIV_APIC_ENABLED;
1939         value |= 0xf;
1940         apic_write(APIC_SPIV, value);
1941 
1942         if (!virt_wire_setup) {
1943                 /*
1944                  * For LVT0 make it edge triggered, active high,
1945                  * external and enabled
1946                  */
1947                 value = apic_read(APIC_LVT0);
1948                 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1949                         APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1950                         APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1951                 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1952                 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
1953                 apic_write(APIC_LVT0, value);
1954         } else {
1955                 /* Disable LVT0 */
1956                 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1957         }
1958 
1959         /*
1960          * For LVT1 make it edge triggered, active high,
1961          * nmi and enabled
1962          */
1963         value = apic_read(APIC_LVT1);
1964         value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1965                         APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1966                         APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1967         value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1968         value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
1969         apic_write(APIC_LVT1, value);
1970 }
1971 
1972 void __cpuinit generic_processor_info(int apicid, int version)
1973 {
1974         int cpu, max = nr_cpu_ids;
1975         bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid,
1976                                 phys_cpu_present_map);
1977 
1978         /*
1979          * If boot cpu has not been detected yet, then only allow upto
1980          * nr_cpu_ids - 1 processors and keep one slot free for boot cpu
1981          */
1982         if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 &&
1983             apicid != boot_cpu_physical_apicid) {
1984                 int thiscpu = max + disabled_cpus - 1;
1985 
1986                 pr_warning(
1987                         "ACPI: NR_CPUS/possible_cpus limit of %i almost"
1988                         " reached. Keeping one slot for boot cpu."
1989                         "  Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
1990 
1991                 disabled_cpus++;
1992                 return;
1993         }
1994 
1995         if (num_processors >= nr_cpu_ids) {
1996                 int thiscpu = max + disabled_cpus;
1997 
1998                 pr_warning(
1999                         "ACPI: NR_CPUS/possible_cpus limit of %i reached."
2000                         "  Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
2001 
2002                 disabled_cpus++;
2003                 return;
2004         }
2005 
2006         num_processors++;
2007         if (apicid == boot_cpu_physical_apicid) {
2008                 /*
2009                  * x86_bios_cpu_apicid is required to have processors listed
2010                  * in same order as logical cpu numbers. Hence the first
2011                  * entry is BSP, and so on.
2012                  * boot_cpu_init() already hold bit 0 in cpu_present_mask
2013                  * for BSP.
2014                  */
2015                 cpu = 0;
2016         } else
2017                 cpu = cpumask_next_zero(-1, cpu_present_mask);
2018 
2019         /*
2020          * Validate version
2021          */
2022         if (version == 0x0) {
2023                 pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n",
2024                            cpu, apicid);
2025                 version = 0x10;
2026         }
2027         apic_version[apicid] = version;
2028 
2029         if (version != apic_version[boot_cpu_physical_apicid]) {
2030                 pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n",
2031                         apic_version[boot_cpu_physical_apicid], cpu, version);
2032         }
2033 
2034         physid_set(apicid, phys_cpu_present_map);
2035         if (apicid > max_physical_apicid)
2036                 max_physical_apicid = apicid;
2037 
2038 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
2039         early_per_cpu(x86_cpu_to_apicid, cpu) = apicid;
2040         early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
2041 #endif
2042 #ifdef CONFIG_X86_32
2043         early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
2044                 apic->x86_32_early_logical_apicid(cpu);
2045 #endif
2046         set_cpu_possible(cpu, true);
2047         set_cpu_present(cpu, true);
2048 }
2049 
2050 int hard_smp_processor_id(void)
2051 {
2052         return read_apic_id();
2053 }
2054 
2055 void default_init_apic_ldr(void)
2056 {
2057         unsigned long val;
2058 
2059         apic_write(APIC_DFR, APIC_DFR_VALUE);
2060         val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
2061         val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
2062         apic_write(APIC_LDR, val);
2063 }
2064 
2065 /*
2066  * Power management
2067  */
2068 #ifdef CONFIG_PM
2069 
2070 static struct {
2071         /*
2072          * 'active' is true if the local APIC was enabled by us and
2073          * not the BIOS; this signifies that we are also responsible
2074          * for disabling it before entering apm/acpi suspend
2075          */
2076         int active;
2077         /* r/w apic fields */
2078         unsigned int apic_id;
2079         unsigned int apic_taskpri;
2080         unsigned int apic_ldr;
2081         unsigned int apic_dfr;
2082         unsigned int apic_spiv;
2083         unsigned int apic_lvtt;
2084         unsigned int apic_lvtpc;
2085         unsigned int apic_lvt0;
2086         unsigned int apic_lvt1;
2087         unsigned int apic_lvterr;
2088         unsigned int apic_tmict;
2089         unsigned int apic_tdcr;
2090         unsigned int apic_thmr;
2091 } apic_pm_state;
2092 
2093 static int lapic_suspend(void)
2094 {
2095         unsigned long flags;
2096         int maxlvt;
2097 
2098         if (!apic_pm_state.active)
2099                 return 0;
2100 
2101         maxlvt = lapic_get_maxlvt();
2102 
2103         apic_pm_state.apic_id = apic_read(APIC_ID);
2104         apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
2105         apic_pm_state.apic_ldr = apic_read(APIC_LDR);
2106         apic_pm_state.apic_dfr = apic_read(APIC_DFR);
2107         apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
2108         apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
2109         if (maxlvt >= 4)
2110                 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
2111         apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
2112         apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
2113         apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
2114         apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
2115         apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
2116 #ifdef CONFIG_X86_THERMAL_VECTOR
2117         if (maxlvt >= 5)
2118                 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
2119 #endif
2120 
2121         local_irq_save(flags);
2122         disable_local_APIC();
2123 
2124         if (intr_remapping_enabled)
2125                 disable_intr_remapping();
2126 
2127         local_irq_restore(flags);
2128         return 0;
2129 }
2130 
2131 static void lapic_resume(void)
2132 {
2133         unsigned int l, h;
2134         unsigned long flags;
2135         int maxlvt;
2136 
2137         if (!apic_pm_state.active)
2138                 return;
2139 
2140         local_irq_save(flags);
2141         if (intr_remapping_enabled) {
2142                 /*
2143                  * IO-APIC and PIC have their own resume routines.
2144                  * We just mask them here to make sure the interrupt
2145                  * subsystem is completely quiet while we enable x2apic
2146                  * and interrupt-remapping.
2147                  */
2148                 mask_ioapic_entries();
2149                 legacy_pic->mask_all();
2150         }
2151 
2152         if (x2apic_mode)
2153                 enable_x2apic();
2154         else {
2155                 /*
2156                  * Make sure the APICBASE points to the right address
2157                  *
2158                  * FIXME! This will be wrong if we ever support suspend on
2159                  * SMP! We'll need to do this as part of the CPU restore!
2160                  */
2161                 if (boot_cpu_data.x86 >= 6) {
2162                         rdmsr(MSR_IA32_APICBASE, l, h);
2163                         l &= ~MSR_IA32_APICBASE_BASE;
2164                         l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
2165                         wrmsr(MSR_IA32_APICBASE, l, h);
2166                 }
2167         }
2168 
2169         maxlvt = lapic_get_maxlvt();
2170         apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
2171         apic_write(APIC_ID, apic_pm_state.apic_id);
2172         apic_write(APIC_DFR, apic_pm_state.apic_dfr);
2173         apic_write(APIC_LDR, apic_pm_state.apic_ldr);
2174         apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
2175         apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
2176         apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
2177         apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
2178 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
2179         if (maxlvt >= 5)
2180                 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
2181 #endif
2182         if (maxlvt >= 4)
2183                 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
2184         apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
2185         apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
2186         apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
2187         apic_write(APIC_ESR, 0);
2188         apic_read(APIC_ESR);
2189         apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
2190         apic_write(APIC_ESR, 0);
2191         apic_read(APIC_ESR);
2192 
2193         if (intr_remapping_enabled)
2194                 reenable_intr_remapping(x2apic_mode);
2195 
2196         local_irq_restore(flags);
2197 }
2198 
2199 /*
2200  * This device has no shutdown method - fully functioning local APICs
2201  * are needed on every CPU up until machine_halt/restart/poweroff.
2202  */
2203 
2204 static struct syscore_ops lapic_syscore_ops = {
2205         .resume         = lapic_resume,
2206         .suspend        = lapic_suspend,
2207 };
2208 
2209 static void __cpuinit apic_pm_activate(void)
2210 {
2211         apic_pm_state.active = 1;
2212 }
2213 
2214 static int __init init_lapic_sysfs(void)
2215 {
2216         /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2217         if (cpu_has_apic)
2218                 register_syscore_ops(&lapic_syscore_ops);
2219 
2220         return 0;
2221 }
2222 
2223 /* local apic needs to resume before other devices access its registers. */
2224 core_initcall(init_lapic_sysfs);
2225 
2226 #else   /* CONFIG_PM */
2227 
2228 static void apic_pm_activate(void) { }
2229 
2230 #endif  /* CONFIG_PM */
2231 
2232 #ifdef CONFIG_X86_64
2233 
2234 static int __cpuinit apic_cluster_num(void)
2235 {
2236         int i, clusters, zeros;
2237         unsigned id;
2238         u16 *bios_cpu_apicid;
2239         DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);
2240 
2241         bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
2242         bitmap_zero(clustermap, NUM_APIC_CLUSTERS);
2243 
2244         for (i = 0; i < nr_cpu_ids; i++) {
2245                 /* are we being called early in kernel startup? */
2246                 if (bios_cpu_apicid) {
2247                         id = bios_cpu_apicid[i];
2248                 } else if (i < nr_cpu_ids) {
2249                         if (cpu_present(i))
2250                                 id = per_cpu(x86_bios_cpu_apicid, i);
2251                         else
2252                                 continue;
2253                 } else
2254                         break;
2255 
2256                 if (id != BAD_APICID)
2257                         __set_bit(APIC_CLUSTERID(id), clustermap);
2258         }
2259 
2260         /* Problem:  Partially populated chassis may not have CPUs in some of
2261          * the APIC clusters they have been allocated.  Only present CPUs have
2262          * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
2263          * Since clusters are allocated sequentially, count zeros only if
2264          * they are bounded by ones.
2265          */
2266         clusters = 0;
2267         zeros = 0;
2268         for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
2269                 if (test_bit(i, clustermap)) {
2270                         clusters += 1 + zeros;
2271                         zeros = 0;
2272                 } else
2273                         ++zeros;
2274         }
2275 
2276         return clusters;
2277 }
2278 
2279 static int __cpuinitdata multi_checked;
2280 static int __cpuinitdata multi;
2281 
2282 static int __cpuinit set_multi(const struct dmi_system_id *d)
2283 {
2284         if (multi)
2285                 return 0;
2286         pr_info("APIC: %s detected, Multi Chassis\n", d->ident);
2287         multi = 1;
2288         return 0;
2289 }
2290 
2291 static const __cpuinitconst struct dmi_system_id multi_dmi_table[] = {
2292         {
2293                 .callback = set_multi,
2294                 .ident = "IBM System Summit2",
2295                 .matches = {
2296                         DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
2297                         DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"),
2298                 },
2299         },
2300         {}
2301 };
2302 
2303 static void __cpuinit dmi_check_multi(void)
2304 {
2305         if (multi_checked)
2306                 return;
2307 
2308         dmi_check_system(multi_dmi_table);
2309         multi_checked = 1;
2310 }
2311 
2312 /*
2313  * apic_is_clustered_box() -- Check if we can expect good TSC
2314  *
2315  * Thus far, the major user of this is IBM's Summit2 series:
2316  * Clustered boxes may have unsynced TSC problems if they are
2317  * multi-chassis.
2318  * Use DMI to check them
2319  */
2320 __cpuinit int apic_is_clustered_box(void)
2321 {
2322         dmi_check_multi();
2323         if (multi)
2324                 return 1;
2325 
2326         if (!is_vsmp_box())
2327                 return 0;
2328 
2329         /*
2330          * ScaleMP vSMPowered boxes have one cluster per board and TSCs are
2331          * not guaranteed to be synced between boards
2332          */
2333         if (apic_cluster_num() > 1)
2334                 return 1;
2335 
2336         return 0;
2337 }
2338 #endif
2339 
2340 /*
2341  * APIC command line parameters
2342  */
2343 static int __init setup_disableapic(char *arg)
2344 {
2345         disable_apic = 1;
2346         setup_clear_cpu_cap(X86_FEATURE_APIC);
2347         return 0;
2348 }
2349 early_param("disableapic", setup_disableapic);
2350 
2351 /* same as disableapic, for compatibility */
2352 static int __init setup_nolapic(char *arg)
2353 {
2354         return setup_disableapic(arg);
2355 }
2356 early_param("nolapic", setup_nolapic);
2357 
2358 static int __init parse_lapic_timer_c2_ok(char *arg)
2359 {
2360         local_apic_timer_c2_ok = 1;
2361         return 0;
2362 }
2363 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
2364 
2365 static int __init parse_disable_apic_timer(char *arg)
2366 {
2367         disable_apic_timer = 1;
2368         return 0;
2369 }
2370 early_param("noapictimer", parse_disable_apic_timer);
2371 
2372 static int __init parse_nolapic_timer(char *arg)
2373 {
2374         disable_apic_timer = 1;
2375         return 0;
2376 }
2377 early_param("nolapic_timer", parse_nolapic_timer);
2378 
2379 static int __init apic_set_verbosity(char *arg)
2380 {
2381         if (!arg)  {
2382 #ifdef CONFIG_X86_64
2383                 skip_ioapic_setup = 0;
2384                 return 0;
2385 #endif
2386                 return -EINVAL;
2387         }
2388 
2389         if (strcmp("debug", arg) == 0)
2390                 apic_verbosity = APIC_DEBUG;
2391         else if (strcmp("verbose", arg) == 0)
2392                 apic_verbosity = APIC_VERBOSE;
2393         else {
2394                 pr_warning("APIC Verbosity level %s not recognised"
2395                         " use apic=verbose or apic=debug\n", arg);
2396                 return -EINVAL;
2397         }
2398 
2399         return 0;
2400 }
2401 early_param("apic", apic_set_verbosity);
2402 
2403 static int __init lapic_insert_resource(void)
2404 {
2405         if (!apic_phys)
2406                 return -1;
2407 
2408         /* Put local APIC into the resource map. */
2409         lapic_resource.start = apic_phys;
2410         lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
2411         insert_resource(&iomem_resource, &lapic_resource);
2412 
2413         return 0;
2414 }
2415 
2416 /*
2417  * need call insert after e820_reserve_resources()
2418  * that is using request_resource
2419  */
2420 late_initcall(lapic_insert_resource);
2421 

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