1 /*
2 * Local APIC handling, local APIC timers
3 *
4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
5 *
6 * Fixes
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
9 * and Rolf G. Tews
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
13 * Pavel Machek and
14 * Mikael Pettersson : PM converted to driver model.
15 */
16
17 #include <linux/perf_event.h>
18 #include <linux/kernel_stat.h>
19 #include <linux/mc146818rtc.h>
20 #include <linux/acpi_pmtmr.h>
21 #include <linux/clockchips.h>
22 #include <linux/interrupt.h>
23 #include <linux/bootmem.h>
24 #include <linux/ftrace.h>
25 #include <linux/ioport.h>
26 #include <linux/export.h>
27 #include <linux/syscore_ops.h>
28 #include <linux/delay.h>
29 #include <linux/timex.h>
30 #include <linux/i8253.h>
31 #include <linux/dmar.h>
32 #include <linux/init.h>
33 #include <linux/cpu.h>
34 #include <linux/dmi.h>
35 #include <linux/smp.h>
36 #include <linux/mm.h>
37
38 #include <asm/trace/irq_vectors.h>
39 #include <asm/irq_remapping.h>
40 #include <asm/perf_event.h>
41 #include <asm/x86_init.h>
42 #include <asm/pgalloc.h>
43 #include <linux/atomic.h>
44 #include <asm/mpspec.h>
45 #include <asm/i8259.h>
46 #include <asm/proto.h>
47 #include <asm/apic.h>
48 #include <asm/io_apic.h>
49 #include <asm/desc.h>
50 #include <asm/hpet.h>
51 #include <asm/mtrr.h>
52 #include <asm/time.h>
53 #include <asm/smp.h>
54 #include <asm/mce.h>
55 #include <asm/tsc.h>
56 #include <asm/hypervisor.h>
57 #include <asm/cpu_device_id.h>
58 #include <asm/intel-family.h>
59
60 unsigned int num_processors;
61
62 unsigned disabled_cpus;
63
64 /* Processor that is doing the boot up */
65 unsigned int boot_cpu_physical_apicid = -1U;
66 EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid);
67
68 u8 boot_cpu_apic_version;
69
70 /*
71 * The highest APIC ID seen during enumeration.
72 */
73 static unsigned int max_physical_apicid;
74
75 /*
76 * Bitmask of physically existing CPUs:
77 */
78 physid_mask_t phys_cpu_present_map;
79
80 /*
81 * Processor to be disabled specified by kernel parameter
82 * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to
83 * avoid undefined behaviour caused by sending INIT from AP to BSP.
84 */
85 static unsigned int disabled_cpu_apicid __read_mostly = BAD_APICID;
86
87 /*
88 * This variable controls which CPUs receive external NMIs. By default,
89 * external NMIs are delivered only to the BSP.
90 */
91 static int apic_extnmi = APIC_EXTNMI_BSP;
92
93 /*
94 * Map cpu index to physical APIC ID
95 */
96 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID);
97 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID);
98 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid, U32_MAX);
99 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid);
100 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
101 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid);
102
103 #ifdef CONFIG_X86_32
104
105 /*
106 * On x86_32, the mapping between cpu and logical apicid may vary
107 * depending on apic in use. The following early percpu variable is
108 * used for the mapping. This is where the behaviors of x86_64 and 32
109 * actually diverge. Let's keep it ugly for now.
110 */
111 DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID);
112
113 /* Local APIC was disabled by the BIOS and enabled by the kernel */
114 static int enabled_via_apicbase;
115
116 /*
117 * Handle interrupt mode configuration register (IMCR).
118 * This register controls whether the interrupt signals
119 * that reach the BSP come from the master PIC or from the
120 * local APIC. Before entering Symmetric I/O Mode, either
121 * the BIOS or the operating system must switch out of
122 * PIC Mode by changing the IMCR.
123 */
124 static inline void imcr_pic_to_apic(void)
125 {
126 /* select IMCR register */
127 outb(0x70, 0x22);
128 /* NMI and 8259 INTR go through APIC */
129 outb(0x01, 0x23);
130 }
131
132 static inline void imcr_apic_to_pic(void)
133 {
134 /* select IMCR register */
135 outb(0x70, 0x22);
136 /* NMI and 8259 INTR go directly to BSP */
137 outb(0x00, 0x23);
138 }
139 #endif
140
141 /*
142 * Knob to control our willingness to enable the local APIC.
143 *
144 * +1=force-enable
145 */
146 static int force_enable_local_apic __initdata;
147
148 /*
149 * APIC command line parameters
150 */
151 static int __init parse_lapic(char *arg)
152 {
153 if (IS_ENABLED(CONFIG_X86_32) && !arg)
154 force_enable_local_apic = 1;
155 else if (arg && !strncmp(arg, "notscdeadline", 13))
156 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
157 return 0;
158 }
159 early_param("lapic", parse_lapic);
160
161 #ifdef CONFIG_X86_64
162 static int apic_calibrate_pmtmr __initdata;
163 static __init int setup_apicpmtimer(char *s)
164 {
165 apic_calibrate_pmtmr = 1;
166 notsc_setup(NULL);
167 return 0;
168 }
169 __setup("apicpmtimer", setup_apicpmtimer);
170 #endif
171
172 unsigned long mp_lapic_addr;
173 int disable_apic;
174 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
175 static int disable_apic_timer __initdata;
176 /* Local APIC timer works in C2 */
177 int local_apic_timer_c2_ok;
178 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
179
180 int first_system_vector = FIRST_SYSTEM_VECTOR;
181
182 /*
183 * Debug level, exported for io_apic.c
184 */
185 unsigned int apic_verbosity;
186
187 int pic_mode;
188
189 /* Have we found an MP table */
190 int smp_found_config;
191
192 static struct resource lapic_resource = {
193 .name = "Local APIC",
194 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
195 };
196
197 unsigned int lapic_timer_frequency = 0;
198
199 static void apic_pm_activate(void);
200
201 static unsigned long apic_phys;
202
203 /*
204 * Get the LAPIC version
205 */
206 static inline int lapic_get_version(void)
207 {
208 return GET_APIC_VERSION(apic_read(APIC_LVR));
209 }
210
211 /*
212 * Check, if the APIC is integrated or a separate chip
213 */
214 static inline int lapic_is_integrated(void)
215 {
216 #ifdef CONFIG_X86_64
217 return 1;
218 #else
219 return APIC_INTEGRATED(lapic_get_version());
220 #endif
221 }
222
223 /*
224 * Check, whether this is a modern or a first generation APIC
225 */
226 static int modern_apic(void)
227 {
228 /* AMD systems use old APIC versions, so check the CPU */
229 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
230 boot_cpu_data.x86 >= 0xf)
231 return 1;
232 return lapic_get_version() >= 0x14;
233 }
234
235 /*
236 * right after this call apic become NOOP driven
237 * so apic->write/read doesn't do anything
238 */
239 static void __init apic_disable(void)
240 {
241 pr_info("APIC: switched to apic NOOP\n");
242 apic = &apic_noop;
243 }
244
245 void native_apic_wait_icr_idle(void)
246 {
247 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
248 cpu_relax();
249 }
250
251 u32 native_safe_apic_wait_icr_idle(void)
252 {
253 u32 send_status;
254 int timeout;
255
256 timeout = 0;
257 do {
258 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
259 if (!send_status)
260 break;
261 inc_irq_stat(icr_read_retry_count);
262 udelay(100);
263 } while (timeout++ < 1000);
264
265 return send_status;
266 }
267
268 void native_apic_icr_write(u32 low, u32 id)
269 {
270 unsigned long flags;
271
272 local_irq_save(flags);
273 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
274 apic_write(APIC_ICR, low);
275 local_irq_restore(flags);
276 }
277
278 u64 native_apic_icr_read(void)
279 {
280 u32 icr1, icr2;
281
282 icr2 = apic_read(APIC_ICR2);
283 icr1 = apic_read(APIC_ICR);
284
285 return icr1 | ((u64)icr2 << 32);
286 }
287
288 #ifdef CONFIG_X86_32
289 /**
290 * get_physical_broadcast - Get number of physical broadcast IDs
291 */
292 int get_physical_broadcast(void)
293 {
294 return modern_apic() ? 0xff : 0xf;
295 }
296 #endif
297
298 /**
299 * lapic_get_maxlvt - get the maximum number of local vector table entries
300 */
301 int lapic_get_maxlvt(void)
302 {
303 unsigned int v;
304
305 v = apic_read(APIC_LVR);
306 /*
307 * - we always have APIC integrated on 64bit mode
308 * - 82489DXs do not report # of LVT entries
309 */
310 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
311 }
312
313 /*
314 * Local APIC timer
315 */
316
317 /* Clock divisor */
318 #define APIC_DIVISOR 16
319 #define TSC_DIVISOR 8
320
321 /*
322 * This function sets up the local APIC timer, with a timeout of
323 * 'clocks' APIC bus clock. During calibration we actually call
324 * this function twice on the boot CPU, once with a bogus timeout
325 * value, second time for real. The other (noncalibrating) CPUs
326 * call this function only once, with the real, calibrated value.
327 *
328 * We do reads before writes even if unnecessary, to get around the
329 * P5 APIC double write bug.
330 */
331 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
332 {
333 unsigned int lvtt_value, tmp_value;
334
335 lvtt_value = LOCAL_TIMER_VECTOR;
336 if (!oneshot)
337 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
338 else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
339 lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE;
340
341 if (!lapic_is_integrated())
342 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
343
344 if (!irqen)
345 lvtt_value |= APIC_LVT_MASKED;
346
347 apic_write(APIC_LVTT, lvtt_value);
348
349 if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) {
350 /*
351 * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode,
352 * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized.
353 * According to Intel, MFENCE can do the serialization here.
354 */
355 asm volatile("mfence" : : : "memory");
356
357 printk_once(KERN_DEBUG "TSC deadline timer enabled\n");
358 return;
359 }
360
361 /*
362 * Divide PICLK by 16
363 */
364 tmp_value = apic_read(APIC_TDCR);
365 apic_write(APIC_TDCR,
366 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
367 APIC_TDR_DIV_16);
368
369 if (!oneshot)
370 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
371 }
372
373 /*
374 * Setup extended LVT, AMD specific
375 *
376 * Software should use the LVT offsets the BIOS provides. The offsets
377 * are determined by the subsystems using it like those for MCE
378 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts
379 * are supported. Beginning with family 10h at least 4 offsets are
380 * available.
381 *
382 * Since the offsets must be consistent for all cores, we keep track
383 * of the LVT offsets in software and reserve the offset for the same
384 * vector also to be used on other cores. An offset is freed by
385 * setting the entry to APIC_EILVT_MASKED.
386 *
387 * If the BIOS is right, there should be no conflicts. Otherwise a
388 * "[Firmware Bug]: ..." error message is generated. However, if
389 * software does not properly determines the offsets, it is not
390 * necessarily a BIOS bug.
391 */
392
393 static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX];
394
395 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new)
396 {
397 return (old & APIC_EILVT_MASKED)
398 || (new == APIC_EILVT_MASKED)
399 || ((new & ~APIC_EILVT_MASKED) == old);
400 }
401
402 static unsigned int reserve_eilvt_offset(int offset, unsigned int new)
403 {
404 unsigned int rsvd, vector;
405
406 if (offset >= APIC_EILVT_NR_MAX)
407 return ~0;
408
409 rsvd = atomic_read(&eilvt_offsets[offset]);
410 do {
411 vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */
412 if (vector && !eilvt_entry_is_changeable(vector, new))
413 /* may not change if vectors are different */
414 return rsvd;
415 rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new);
416 } while (rsvd != new);
417
418 rsvd &= ~APIC_EILVT_MASKED;
419 if (rsvd && rsvd != vector)
420 pr_info("LVT offset %d assigned for vector 0x%02x\n",
421 offset, rsvd);
422
423 return new;
424 }
425
426 /*
427 * If mask=1, the LVT entry does not generate interrupts while mask=0
428 * enables the vector. See also the BKDGs. Must be called with
429 * preemption disabled.
430 */
431
432 int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask)
433 {
434 unsigned long reg = APIC_EILVTn(offset);
435 unsigned int new, old, reserved;
436
437 new = (mask << 16) | (msg_type << 8) | vector;
438 old = apic_read(reg);
439 reserved = reserve_eilvt_offset(offset, new);
440
441 if (reserved != new) {
442 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
443 "vector 0x%x, but the register is already in use for "
444 "vector 0x%x on another cpu\n",
445 smp_processor_id(), reg, offset, new, reserved);
446 return -EINVAL;
447 }
448
449 if (!eilvt_entry_is_changeable(old, new)) {
450 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
451 "vector 0x%x, but the register is already in use for "
452 "vector 0x%x on this cpu\n",
453 smp_processor_id(), reg, offset, new, old);
454 return -EBUSY;
455 }
456
457 apic_write(reg, new);
458
459 return 0;
460 }
461 EXPORT_SYMBOL_GPL(setup_APIC_eilvt);
462
463 /*
464 * Program the next event, relative to now
465 */
466 static int lapic_next_event(unsigned long delta,
467 struct clock_event_device *evt)
468 {
469 apic_write(APIC_TMICT, delta);
470 return 0;
471 }
472
473 static int lapic_next_deadline(unsigned long delta,
474 struct clock_event_device *evt)
475 {
476 u64 tsc;
477
478 tsc = rdtsc();
479 wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR));
480 return 0;
481 }
482
483 static int lapic_timer_shutdown(struct clock_event_device *evt)
484 {
485 unsigned int v;
486
487 /* Lapic used as dummy for broadcast ? */
488 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
489 return 0;
490
491 v = apic_read(APIC_LVTT);
492 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
493 apic_write(APIC_LVTT, v);
494 apic_write(APIC_TMICT, 0);
495 return 0;
496 }
497
498 static inline int
499 lapic_timer_set_periodic_oneshot(struct clock_event_device *evt, bool oneshot)
500 {
501 /* Lapic used as dummy for broadcast ? */
502 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
503 return 0;
504
505 __setup_APIC_LVTT(lapic_timer_frequency, oneshot, 1);
506 return 0;
507 }
508
509 static int lapic_timer_set_periodic(struct clock_event_device *evt)
510 {
511 return lapic_timer_set_periodic_oneshot(evt, false);
512 }
513
514 static int lapic_timer_set_oneshot(struct clock_event_device *evt)
515 {
516 return lapic_timer_set_periodic_oneshot(evt, true);
517 }
518
519 /*
520 * Local APIC timer broadcast function
521 */
522 static void lapic_timer_broadcast(const struct cpumask *mask)
523 {
524 #ifdef CONFIG_SMP
525 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
526 #endif
527 }
528
529
530 /*
531 * The local apic timer can be used for any function which is CPU local.
532 */
533 static struct clock_event_device lapic_clockevent = {
534 .name = "lapic",
535 .features = CLOCK_EVT_FEAT_PERIODIC |
536 CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP
537 | CLOCK_EVT_FEAT_DUMMY,
538 .shift = 32,
539 .set_state_shutdown = lapic_timer_shutdown,
540 .set_state_periodic = lapic_timer_set_periodic,
541 .set_state_oneshot = lapic_timer_set_oneshot,
542 .set_state_oneshot_stopped = lapic_timer_shutdown,
543 .set_next_event = lapic_next_event,
544 .broadcast = lapic_timer_broadcast,
545 .rating = 100,
546 .irq = -1,
547 };
548 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
549
550 #define DEADLINE_MODEL_MATCH_FUNC(model, func) \
551 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)&func }
552
553 #define DEADLINE_MODEL_MATCH_REV(model, rev) \
554 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)rev }
555
556 static u32 hsx_deadline_rev(void)
557 {
558 switch (boot_cpu_data.x86_mask) {
559 case 0x02: return 0x3a; /* EP */
560 case 0x04: return 0x0f; /* EX */
561 }
562
563 return ~0U;
564 }
565
566 static u32 bdx_deadline_rev(void)
567 {
568 switch (boot_cpu_data.x86_mask) {
569 case 0x02: return 0x00000011;
570 case 0x03: return 0x0700000e;
571 case 0x04: return 0x0f00000c;
572 case 0x05: return 0x0e000003;
573 }
574
575 return ~0U;
576 }
577
578 static const struct x86_cpu_id deadline_match[] = {
579 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_HASWELL_X, hsx_deadline_rev),
580 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_X, 0x0b000020),
581 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_BROADWELL_XEON_D, bdx_deadline_rev),
582 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_X, 0x02000014),
583
584 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_CORE, 0x22),
585 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_ULT, 0x20),
586 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_GT3E, 0x17),
587
588 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_CORE, 0x25),
589 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_GT3E, 0x17),
590
591 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_MOBILE, 0xb2),
592 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_DESKTOP, 0xb2),
593
594 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_MOBILE, 0x52),
595 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_DESKTOP, 0x52),
596
597 {},
598 };
599
600 static void apic_check_deadline_errata(void)
601 {
602 const struct x86_cpu_id *m;
603 u32 rev;
604
605 if (!boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER) ||
606 boot_cpu_has(X86_FEATURE_HYPERVISOR))
607 return;
608
609 m = x86_match_cpu(deadline_match);
610 if (!m)
611 return;
612
613 /*
614 * Function pointers will have the MSB set due to address layout,
615 * immediate revisions will not.
616 */
617 if ((long)m->driver_data < 0)
618 rev = ((u32 (*)(void))(m->driver_data))();
619 else
620 rev = (u32)m->driver_data;
621
622 if (boot_cpu_data.microcode >= rev)
623 return;
624
625 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
626 pr_err(FW_BUG "TSC_DEADLINE disabled due to Errata; "
627 "please update microcode to version: 0x%x (or later)\n", rev);
628 }
629
630 /*
631 * Setup the local APIC timer for this CPU. Copy the initialized values
632 * of the boot CPU and register the clock event in the framework.
633 */
634 static void setup_APIC_timer(void)
635 {
636 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
637
638 if (this_cpu_has(X86_FEATURE_ARAT)) {
639 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP;
640 /* Make LAPIC timer preferrable over percpu HPET */
641 lapic_clockevent.rating = 150;
642 }
643
644 memcpy(levt, &lapic_clockevent, sizeof(*levt));
645 levt->cpumask = cpumask_of(smp_processor_id());
646
647 if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) {
648 levt->name = "lapic-deadline";
649 levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC |
650 CLOCK_EVT_FEAT_DUMMY);
651 levt->set_next_event = lapic_next_deadline;
652 clockevents_config_and_register(levt,
653 tsc_khz * (1000 / TSC_DIVISOR),
654 0xF, ~0UL);
655 } else
656 clockevents_register_device(levt);
657 }
658
659 /*
660 * Install the updated TSC frequency from recalibration at the TSC
661 * deadline clockevent devices.
662 */
663 static void __lapic_update_tsc_freq(void *info)
664 {
665 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
666
667 if (!this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
668 return;
669
670 clockevents_update_freq(levt, tsc_khz * (1000 / TSC_DIVISOR));
671 }
672
673 void lapic_update_tsc_freq(void)
674 {
675 /*
676 * The clockevent device's ->mult and ->shift can both be
677 * changed. In order to avoid races, schedule the frequency
678 * update code on each CPU.
679 */
680 on_each_cpu(__lapic_update_tsc_freq, NULL, 0);
681 }
682
683 /*
684 * In this functions we calibrate APIC bus clocks to the external timer.
685 *
686 * We want to do the calibration only once since we want to have local timer
687 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
688 * frequency.
689 *
690 * This was previously done by reading the PIT/HPET and waiting for a wrap
691 * around to find out, that a tick has elapsed. I have a box, where the PIT
692 * readout is broken, so it never gets out of the wait loop again. This was
693 * also reported by others.
694 *
695 * Monitoring the jiffies value is inaccurate and the clockevents
696 * infrastructure allows us to do a simple substitution of the interrupt
697 * handler.
698 *
699 * The calibration routine also uses the pm_timer when possible, as the PIT
700 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
701 * back to normal later in the boot process).
702 */
703
704 #define LAPIC_CAL_LOOPS (HZ/10)
705
706 static __initdata int lapic_cal_loops = -1;
707 static __initdata long lapic_cal_t1, lapic_cal_t2;
708 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
709 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
710 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
711
712 /*
713 * Temporary interrupt handler.
714 */
715 static void __init lapic_cal_handler(struct clock_event_device *dev)
716 {
717 unsigned long long tsc = 0;
718 long tapic = apic_read(APIC_TMCCT);
719 unsigned long pm = acpi_pm_read_early();
720
721 if (boot_cpu_has(X86_FEATURE_TSC))
722 tsc = rdtsc();
723
724 switch (lapic_cal_loops++) {
725 case 0:
726 lapic_cal_t1 = tapic;
727 lapic_cal_tsc1 = tsc;
728 lapic_cal_pm1 = pm;
729 lapic_cal_j1 = jiffies;
730 break;
731
732 case LAPIC_CAL_LOOPS:
733 lapic_cal_t2 = tapic;
734 lapic_cal_tsc2 = tsc;
735 if (pm < lapic_cal_pm1)
736 pm += ACPI_PM_OVRRUN;
737 lapic_cal_pm2 = pm;
738 lapic_cal_j2 = jiffies;
739 break;
740 }
741 }
742
743 static int __init
744 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc)
745 {
746 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10;
747 const long pm_thresh = pm_100ms / 100;
748 unsigned long mult;
749 u64 res;
750
751 #ifndef CONFIG_X86_PM_TIMER
752 return -1;
753 #endif
754
755 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm);
756
757 /* Check, if the PM timer is available */
758 if (!deltapm)
759 return -1;
760
761 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
762
763 if (deltapm > (pm_100ms - pm_thresh) &&
764 deltapm < (pm_100ms + pm_thresh)) {
765 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n");
766 return 0;
767 }
768
769 res = (((u64)deltapm) * mult) >> 22;
770 do_div(res, 1000000);
771 pr_warning("APIC calibration not consistent "
772 "with PM-Timer: %ldms instead of 100ms\n",(long)res);
773
774 /* Correct the lapic counter value */
775 res = (((u64)(*delta)) * pm_100ms);
776 do_div(res, deltapm);
777 pr_info("APIC delta adjusted to PM-Timer: "
778 "%lu (%ld)\n", (unsigned long)res, *delta);
779 *delta = (long)res;
780
781 /* Correct the tsc counter value */
782 if (boot_cpu_has(X86_FEATURE_TSC)) {
783 res = (((u64)(*deltatsc)) * pm_100ms);
784 do_div(res, deltapm);
785 apic_printk(APIC_VERBOSE, "TSC delta adjusted to "
786 "PM-Timer: %lu (%ld)\n",
787 (unsigned long)res, *deltatsc);
788 *deltatsc = (long)res;
789 }
790
791 return 0;
792 }
793
794 static int __init calibrate_APIC_clock(void)
795 {
796 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
797 void (*real_handler)(struct clock_event_device *dev);
798 unsigned long deltaj;
799 long delta, deltatsc;
800 int pm_referenced = 0;
801
802 /**
803 * check if lapic timer has already been calibrated by platform
804 * specific routine, such as tsc calibration code. if so, we just fill
805 * in the clockevent structure and return.
806 */
807
808 if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) {
809 return 0;
810 } else if (lapic_timer_frequency) {
811 apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n",
812 lapic_timer_frequency);
813 lapic_clockevent.mult = div_sc(lapic_timer_frequency/APIC_DIVISOR,
814 TICK_NSEC, lapic_clockevent.shift);
815 lapic_clockevent.max_delta_ns =
816 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
817 lapic_clockevent.max_delta_ticks = 0x7FFFFF;
818 lapic_clockevent.min_delta_ns =
819 clockevent_delta2ns(0xF, &lapic_clockevent);
820 lapic_clockevent.min_delta_ticks = 0xF;
821 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
822 return 0;
823 }
824
825 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
826 "calibrating APIC timer ...\n");
827
828 local_irq_disable();
829
830 /* Replace the global interrupt handler */
831 real_handler = global_clock_event->event_handler;
832 global_clock_event->event_handler = lapic_cal_handler;
833
834 /*
835 * Setup the APIC counter to maximum. There is no way the lapic
836 * can underflow in the 100ms detection time frame
837 */
838 __setup_APIC_LVTT(0xffffffff, 0, 0);
839
840 /* Let the interrupts run */
841 local_irq_enable();
842
843 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
844 cpu_relax();
845
846 local_irq_disable();
847
848 /* Restore the real event handler */
849 global_clock_event->event_handler = real_handler;
850
851 /* Build delta t1-t2 as apic timer counts down */
852 delta = lapic_cal_t1 - lapic_cal_t2;
853 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
854
855 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
856
857 /* we trust the PM based calibration if possible */
858 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,
859 &delta, &deltatsc);
860
861 /* Calculate the scaled math multiplication factor */
862 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
863 lapic_clockevent.shift);
864 lapic_clockevent.max_delta_ns =
865 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent);
866 lapic_clockevent.max_delta_ticks = 0x7FFFFFFF;
867 lapic_clockevent.min_delta_ns =
868 clockevent_delta2ns(0xF, &lapic_clockevent);
869 lapic_clockevent.min_delta_ticks = 0xF;
870
871 lapic_timer_frequency = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
872
873 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
874 apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult);
875 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
876 lapic_timer_frequency);
877
878 if (boot_cpu_has(X86_FEATURE_TSC)) {
879 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
880 "%ld.%04ld MHz.\n",
881 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ),
882 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ));
883 }
884
885 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
886 "%u.%04u MHz.\n",
887 lapic_timer_frequency / (1000000 / HZ),
888 lapic_timer_frequency % (1000000 / HZ));
889
890 /*
891 * Do a sanity check on the APIC calibration result
892 */
893 if (lapic_timer_frequency < (1000000 / HZ)) {
894 local_irq_enable();
895 pr_warning("APIC frequency too slow, disabling apic timer\n");
896 return -1;
897 }
898
899 levt->features &= ~CLOCK_EVT_FEAT_DUMMY;
900
901 /*
902 * PM timer calibration failed or not turned on
903 * so lets try APIC timer based calibration
904 */
905 if (!pm_referenced) {
906 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
907
908 /*
909 * Setup the apic timer manually
910 */
911 levt->event_handler = lapic_cal_handler;
912 lapic_timer_set_periodic(levt);
913 lapic_cal_loops = -1;
914
915 /* Let the interrupts run */
916 local_irq_enable();
917
918 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
919 cpu_relax();
920
921 /* Stop the lapic timer */
922 local_irq_disable();
923 lapic_timer_shutdown(levt);
924
925 /* Jiffies delta */
926 deltaj = lapic_cal_j2 - lapic_cal_j1;
927 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
928
929 /* Check, if the jiffies result is consistent */
930 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
931 apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
932 else
933 levt->features |= CLOCK_EVT_FEAT_DUMMY;
934 }
935 local_irq_enable();
936
937 if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
938 pr_warning("APIC timer disabled due to verification failure\n");
939 return -1;
940 }
941
942 return 0;
943 }
944
945 /*
946 * Setup the boot APIC
947 *
948 * Calibrate and verify the result.
949 */
950 void __init setup_boot_APIC_clock(void)
951 {
952 /*
953 * The local apic timer can be disabled via the kernel
954 * commandline or from the CPU detection code. Register the lapic
955 * timer as a dummy clock event source on SMP systems, so the
956 * broadcast mechanism is used. On UP systems simply ignore it.
957 */
958 if (disable_apic_timer) {
959 pr_info("Disabling APIC timer\n");
960 /* No broadcast on UP ! */
961 if (num_possible_cpus() > 1) {
962 lapic_clockevent.mult = 1;
963 setup_APIC_timer();
964 }
965 return;
966 }
967
968 if (calibrate_APIC_clock()) {
969 /* No broadcast on UP ! */
970 if (num_possible_cpus() > 1)
971 setup_APIC_timer();
972 return;
973 }
974
975 /*
976 * If nmi_watchdog is set to IO_APIC, we need the
977 * PIT/HPET going. Otherwise register lapic as a dummy
978 * device.
979 */
980 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
981
982 /* Setup the lapic or request the broadcast */
983 setup_APIC_timer();
984 amd_e400_c1e_apic_setup();
985 }
986
987 void setup_secondary_APIC_clock(void)
988 {
989 setup_APIC_timer();
990 amd_e400_c1e_apic_setup();
991 }
992
993 /*
994 * The guts of the apic timer interrupt
995 */
996 static void local_apic_timer_interrupt(void)
997 {
998 int cpu = smp_processor_id();
999 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
1000
1001 /*
1002 * Normally we should not be here till LAPIC has been initialized but
1003 * in some cases like kdump, its possible that there is a pending LAPIC
1004 * timer interrupt from previous kernel's context and is delivered in
1005 * new kernel the moment interrupts are enabled.
1006 *
1007 * Interrupts are enabled early and LAPIC is setup much later, hence
1008 * its possible that when we get here evt->event_handler is NULL.
1009 * Check for event_handler being NULL and discard the interrupt as
1010 * spurious.
1011 */
1012 if (!evt->event_handler) {
1013 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu);
1014 /* Switch it off */
1015 lapic_timer_shutdown(evt);
1016 return;
1017 }
1018
1019 /*
1020 * the NMI deadlock-detector uses this.
1021 */
1022 inc_irq_stat(apic_timer_irqs);
1023
1024 evt->event_handler(evt);
1025 }
1026
1027 /*
1028 * Local APIC timer interrupt. This is the most natural way for doing
1029 * local interrupts, but local timer interrupts can be emulated by
1030 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
1031 *
1032 * [ if a single-CPU system runs an SMP kernel then we call the local
1033 * interrupt as well. Thus we cannot inline the local irq ... ]
1034 */
1035 __visible void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs)
1036 {
1037 struct pt_regs *old_regs = set_irq_regs(regs);
1038
1039 /*
1040 * NOTE! We'd better ACK the irq immediately,
1041 * because timer handling can be slow.
1042 *
1043 * update_process_times() expects us to have done irq_enter().
1044 * Besides, if we don't timer interrupts ignore the global
1045 * interrupt lock, which is the WrongThing (tm) to do.
1046 */
1047 entering_ack_irq();
1048 local_apic_timer_interrupt();
1049 exiting_irq();
1050
1051 set_irq_regs(old_regs);
1052 }
1053
1054 __visible void __irq_entry smp_trace_apic_timer_interrupt(struct pt_regs *regs)
1055 {
1056 struct pt_regs *old_regs = set_irq_regs(regs);
1057
1058 /*
1059 * NOTE! We'd better ACK the irq immediately,
1060 * because timer handling can be slow.
1061 *
1062 * update_process_times() expects us to have done irq_enter().
1063 * Besides, if we don't timer interrupts ignore the global
1064 * interrupt lock, which is the WrongThing (tm) to do.
1065 */
1066 entering_ack_irq();
1067 trace_local_timer_entry(LOCAL_TIMER_VECTOR);
1068 local_apic_timer_interrupt();
1069 trace_local_timer_exit(LOCAL_TIMER_VECTOR);
1070 exiting_irq();
1071
1072 set_irq_regs(old_regs);
1073 }
1074
1075 int setup_profiling_timer(unsigned int multiplier)
1076 {
1077 return -EINVAL;
1078 }
1079
1080 /*
1081 * Local APIC start and shutdown
1082 */
1083
1084 /**
1085 * clear_local_APIC - shutdown the local APIC
1086 *
1087 * This is called, when a CPU is disabled and before rebooting, so the state of
1088 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
1089 * leftovers during boot.
1090 */
1091 void clear_local_APIC(void)
1092 {
1093 int maxlvt;
1094 u32 v;
1095
1096 /* APIC hasn't been mapped yet */
1097 if (!x2apic_mode && !apic_phys)
1098 return;
1099
1100 maxlvt = lapic_get_maxlvt();
1101 /*
1102 * Masking an LVT entry can trigger a local APIC error
1103 * if the vector is zero. Mask LVTERR first to prevent this.
1104 */
1105 if (maxlvt >= 3) {
1106 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
1107 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
1108 }
1109 /*
1110 * Careful: we have to set masks only first to deassert
1111 * any level-triggered sources.
1112 */
1113 v = apic_read(APIC_LVTT);
1114 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
1115 v = apic_read(APIC_LVT0);
1116 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1117 v = apic_read(APIC_LVT1);
1118 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
1119 if (maxlvt >= 4) {
1120 v = apic_read(APIC_LVTPC);
1121 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
1122 }
1123
1124 /* lets not touch this if we didn't frob it */
1125 #ifdef CONFIG_X86_THERMAL_VECTOR
1126 if (maxlvt >= 5) {
1127 v = apic_read(APIC_LVTTHMR);
1128 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
1129 }
1130 #endif
1131 #ifdef CONFIG_X86_MCE_INTEL
1132 if (maxlvt >= 6) {
1133 v = apic_read(APIC_LVTCMCI);
1134 if (!(v & APIC_LVT_MASKED))
1135 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED);
1136 }
1137 #endif
1138
1139 /*
1140 * Clean APIC state for other OSs:
1141 */
1142 apic_write(APIC_LVTT, APIC_LVT_MASKED);
1143 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1144 apic_write(APIC_LVT1, APIC_LVT_MASKED);
1145 if (maxlvt >= 3)
1146 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
1147 if (maxlvt >= 4)
1148 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
1149
1150 /* Integrated APIC (!82489DX) ? */
1151 if (lapic_is_integrated()) {
1152 if (maxlvt > 3)
1153 /* Clear ESR due to Pentium errata 3AP and 11AP */
1154 apic_write(APIC_ESR, 0);
1155 apic_read(APIC_ESR);
1156 }
1157 }
1158
1159 /**
1160 * disable_local_APIC - clear and disable the local APIC
1161 */
1162 void disable_local_APIC(void)
1163 {
1164 unsigned int value;
1165
1166 /* APIC hasn't been mapped yet */
1167 if (!x2apic_mode && !apic_phys)
1168 return;
1169
1170 clear_local_APIC();
1171
1172 /*
1173 * Disable APIC (implies clearing of registers
1174 * for 82489DX!).
1175 */
1176 value = apic_read(APIC_SPIV);
1177 value &= ~APIC_SPIV_APIC_ENABLED;
1178 apic_write(APIC_SPIV, value);
1179
1180 #ifdef CONFIG_X86_32
1181 /*
1182 * When LAPIC was disabled by the BIOS and enabled by the kernel,
1183 * restore the disabled state.
1184 */
1185 if (enabled_via_apicbase) {
1186 unsigned int l, h;
1187
1188 rdmsr(MSR_IA32_APICBASE, l, h);
1189 l &= ~MSR_IA32_APICBASE_ENABLE;
1190 wrmsr(MSR_IA32_APICBASE, l, h);
1191 }
1192 #endif
1193 }
1194
1195 /*
1196 * If Linux enabled the LAPIC against the BIOS default disable it down before
1197 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
1198 * not power-off. Additionally clear all LVT entries before disable_local_APIC
1199 * for the case where Linux didn't enable the LAPIC.
1200 */
1201 void lapic_shutdown(void)
1202 {
1203 unsigned long flags;
1204
1205 if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config())
1206 return;
1207
1208 local_irq_save(flags);
1209
1210 #ifdef CONFIG_X86_32
1211 if (!enabled_via_apicbase)
1212 clear_local_APIC();
1213 else
1214 #endif
1215 disable_local_APIC();
1216
1217
1218 local_irq_restore(flags);
1219 }
1220
1221 /**
1222 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1223 */
1224 void __init sync_Arb_IDs(void)
1225 {
1226 /*
1227 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1228 * needed on AMD.
1229 */
1230 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1231 return;
1232
1233 /*
1234 * Wait for idle.
1235 */
1236 apic_wait_icr_idle();
1237
1238 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
1239 apic_write(APIC_ICR, APIC_DEST_ALLINC |
1240 APIC_INT_LEVELTRIG | APIC_DM_INIT);
1241 }
1242
1243 /*
1244 * An initial setup of the virtual wire mode.
1245 */
1246 void __init init_bsp_APIC(void)
1247 {
1248 unsigned int value;
1249
1250 /*
1251 * Don't do the setup now if we have a SMP BIOS as the
1252 * through-I/O-APIC virtual wire mode might be active.
1253 */
1254 if (smp_found_config || !boot_cpu_has(X86_FEATURE_APIC))
1255 return;
1256
1257 /*
1258 * Do not trust the local APIC being empty at bootup.
1259 */
1260 clear_local_APIC();
1261
1262 /*
1263 * Enable APIC.
1264 */
1265 value = apic_read(APIC_SPIV);
1266 value &= ~APIC_VECTOR_MASK;
1267 value |= APIC_SPIV_APIC_ENABLED;
1268
1269 #ifdef CONFIG_X86_32
1270 /* This bit is reserved on P4/Xeon and should be cleared */
1271 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
1272 (boot_cpu_data.x86 == 15))
1273 value &= ~APIC_SPIV_FOCUS_DISABLED;
1274 else
1275 #endif
1276 value |= APIC_SPIV_FOCUS_DISABLED;
1277 value |= SPURIOUS_APIC_VECTOR;
1278 apic_write(APIC_SPIV, value);
1279
1280 /*
1281 * Set up the virtual wire mode.
1282 */
1283 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1284 value = APIC_DM_NMI;
1285 if (!lapic_is_integrated()) /* 82489DX */
1286 value |= APIC_LVT_LEVEL_TRIGGER;
1287 if (apic_extnmi == APIC_EXTNMI_NONE)
1288 value |= APIC_LVT_MASKED;
1289 apic_write(APIC_LVT1, value);
1290 }
1291
1292 static void lapic_setup_esr(void)
1293 {
1294 unsigned int oldvalue, value, maxlvt;
1295
1296 if (!lapic_is_integrated()) {
1297 pr_info("No ESR for 82489DX.\n");
1298 return;
1299 }
1300
1301 if (apic->disable_esr) {
1302 /*
1303 * Something untraceable is creating bad interrupts on
1304 * secondary quads ... for the moment, just leave the
1305 * ESR disabled - we can't do anything useful with the
1306 * errors anyway - mbligh
1307 */
1308 pr_info("Leaving ESR disabled.\n");
1309 return;
1310 }
1311
1312 maxlvt = lapic_get_maxlvt();
1313 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1314 apic_write(APIC_ESR, 0);
1315 oldvalue = apic_read(APIC_ESR);
1316
1317 /* enables sending errors */
1318 value = ERROR_APIC_VECTOR;
1319 apic_write(APIC_LVTERR, value);
1320
1321 /*
1322 * spec says clear errors after enabling vector.
1323 */
1324 if (maxlvt > 3)
1325 apic_write(APIC_ESR, 0);
1326 value = apic_read(APIC_ESR);
1327 if (value != oldvalue)
1328 apic_printk(APIC_VERBOSE, "ESR value before enabling "
1329 "vector: 0x%08x after: 0x%08x\n",
1330 oldvalue, value);
1331 }
1332
1333 /**
1334 * setup_local_APIC - setup the local APIC
1335 *
1336 * Used to setup local APIC while initializing BSP or bringing up APs.
1337 * Always called with preemption disabled.
1338 */
1339 void setup_local_APIC(void)
1340 {
1341 int cpu = smp_processor_id();
1342 unsigned int value, queued;
1343 int i, j, acked = 0;
1344 unsigned long long tsc = 0, ntsc;
1345 long long max_loops = cpu_khz ? cpu_khz : 1000000;
1346
1347 if (boot_cpu_has(X86_FEATURE_TSC))
1348 tsc = rdtsc();
1349
1350 if (disable_apic) {
1351 disable_ioapic_support();
1352 return;
1353 }
1354
1355 #ifdef CONFIG_X86_32
1356 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1357 if (lapic_is_integrated() && apic->disable_esr) {
1358 apic_write(APIC_ESR, 0);
1359 apic_write(APIC_ESR, 0);
1360 apic_write(APIC_ESR, 0);
1361 apic_write(APIC_ESR, 0);
1362 }
1363 #endif
1364 perf_events_lapic_init();
1365
1366 /*
1367 * Double-check whether this APIC is really registered.
1368 * This is meaningless in clustered apic mode, so we skip it.
1369 */
1370 BUG_ON(!apic->apic_id_registered());
1371
1372 /*
1373 * Intel recommends to set DFR, LDR and TPR before enabling
1374 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1375 * document number 292116). So here it goes...
1376 */
1377 apic->init_apic_ldr();
1378
1379 #ifdef CONFIG_X86_32
1380 /*
1381 * APIC LDR is initialized. If logical_apicid mapping was
1382 * initialized during get_smp_config(), make sure it matches the
1383 * actual value.
1384 */
1385 i = early_per_cpu(x86_cpu_to_logical_apicid, cpu);
1386 WARN_ON(i != BAD_APICID && i != logical_smp_processor_id());
1387 /* always use the value from LDR */
1388 early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
1389 logical_smp_processor_id();
1390 #endif
1391
1392 /*
1393 * Set Task Priority to 'accept all'. We never change this
1394 * later on.
1395 */
1396 value = apic_read(APIC_TASKPRI);
1397 value &= ~APIC_TPRI_MASK;
1398 apic_write(APIC_TASKPRI, value);
1399
1400 /*
1401 * After a crash, we no longer service the interrupts and a pending
1402 * interrupt from previous kernel might still have ISR bit set.
1403 *
1404 * Most probably by now CPU has serviced that pending interrupt and
1405 * it might not have done the ack_APIC_irq() because it thought,
1406 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1407 * does not clear the ISR bit and cpu thinks it has already serivced
1408 * the interrupt. Hence a vector might get locked. It was noticed
1409 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1410 */
1411 do {
1412 queued = 0;
1413 for (i = APIC_ISR_NR - 1; i >= 0; i--)
1414 queued |= apic_read(APIC_IRR + i*0x10);
1415
1416 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
1417 value = apic_read(APIC_ISR + i*0x10);
1418 for (j = 31; j >= 0; j--) {
1419 if (value & (1<<j)) {
1420 ack_APIC_irq();
1421 acked++;
1422 }
1423 }
1424 }
1425 if (acked > 256) {
1426 printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n",
1427 acked);
1428 break;
1429 }
1430 if (queued) {
1431 if (boot_cpu_has(X86_FEATURE_TSC) && cpu_khz) {
1432 ntsc = rdtsc();
1433 max_loops = (cpu_khz << 10) - (ntsc - tsc);
1434 } else
1435 max_loops--;
1436 }
1437 } while (queued && max_loops > 0);
1438 WARN_ON(max_loops <= 0);
1439
1440 /*
1441 * Now that we are all set up, enable the APIC
1442 */
1443 value = apic_read(APIC_SPIV);
1444 value &= ~APIC_VECTOR_MASK;
1445 /*
1446 * Enable APIC
1447 */
1448 value |= APIC_SPIV_APIC_ENABLED;
1449
1450 #ifdef CONFIG_X86_32
1451 /*
1452 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1453 * certain networking cards. If high frequency interrupts are
1454 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1455 * entry is masked/unmasked at a high rate as well then sooner or
1456 * later IOAPIC line gets 'stuck', no more interrupts are received
1457 * from the device. If focus CPU is disabled then the hang goes
1458 * away, oh well :-(
1459 *
1460 * [ This bug can be reproduced easily with a level-triggered
1461 * PCI Ne2000 networking cards and PII/PIII processors, dual
1462 * BX chipset. ]
1463 */
1464 /*
1465 * Actually disabling the focus CPU check just makes the hang less
1466 * frequent as it makes the interrupt distributon model be more
1467 * like LRU than MRU (the short-term load is more even across CPUs).
1468 */
1469
1470 /*
1471 * - enable focus processor (bit==0)
1472 * - 64bit mode always use processor focus
1473 * so no need to set it
1474 */
1475 value &= ~APIC_SPIV_FOCUS_DISABLED;
1476 #endif
1477
1478 /*
1479 * Set spurious IRQ vector
1480 */
1481 value |= SPURIOUS_APIC_VECTOR;
1482 apic_write(APIC_SPIV, value);
1483
1484 /*
1485 * Set up LVT0, LVT1:
1486 *
1487 * set up through-local-APIC on the BP's LINT0. This is not
1488 * strictly necessary in pure symmetric-IO mode, but sometimes
1489 * we delegate interrupts to the 8259A.
1490 */
1491 /*
1492 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1493 */
1494 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1495 if (!cpu && (pic_mode || !value)) {
1496 value = APIC_DM_EXTINT;
1497 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu);
1498 } else {
1499 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1500 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu);
1501 }
1502 apic_write(APIC_LVT0, value);
1503
1504 /*
1505 * Only the BSP sees the LINT1 NMI signal by default. This can be
1506 * modified by apic_extnmi= boot option.
1507 */
1508 if ((!cpu && apic_extnmi != APIC_EXTNMI_NONE) ||
1509 apic_extnmi == APIC_EXTNMI_ALL)
1510 value = APIC_DM_NMI;
1511 else
1512 value = APIC_DM_NMI | APIC_LVT_MASKED;
1513 if (!lapic_is_integrated()) /* 82489DX */
1514 value |= APIC_LVT_LEVEL_TRIGGER;
1515 apic_write(APIC_LVT1, value);
1516
1517 #ifdef CONFIG_X86_MCE_INTEL
1518 /* Recheck CMCI information after local APIC is up on CPU #0 */
1519 if (!cpu)
1520 cmci_recheck();
1521 #endif
1522 }
1523
1524 static void end_local_APIC_setup(void)
1525 {
1526 lapic_setup_esr();
1527
1528 #ifdef CONFIG_X86_32
1529 {
1530 unsigned int value;
1531 /* Disable the local apic timer */
1532 value = apic_read(APIC_LVTT);
1533 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1534 apic_write(APIC_LVTT, value);
1535 }
1536 #endif
1537
1538 apic_pm_activate();
1539 }
1540
1541 /*
1542 * APIC setup function for application processors. Called from smpboot.c
1543 */
1544 void apic_ap_setup(void)
1545 {
1546 setup_local_APIC();
1547 end_local_APIC_setup();
1548 }
1549
1550 #ifdef CONFIG_X86_X2APIC
1551 int x2apic_mode;
1552
1553 enum {
1554 X2APIC_OFF,
1555 X2APIC_ON,
1556 X2APIC_DISABLED,
1557 };
1558 static int x2apic_state;
1559
1560 static void __x2apic_disable(void)
1561 {
1562 u64 msr;
1563
1564 if (!boot_cpu_has(X86_FEATURE_APIC))
1565 return;
1566
1567 rdmsrl(MSR_IA32_APICBASE, msr);
1568 if (!(msr & X2APIC_ENABLE))
1569 return;
1570 /* Disable xapic and x2apic first and then reenable xapic mode */
1571 wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE));
1572 wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE);
1573 printk_once(KERN_INFO "x2apic disabled\n");
1574 }
1575
1576 static void __x2apic_enable(void)
1577 {
1578 u64 msr;
1579
1580 rdmsrl(MSR_IA32_APICBASE, msr);
1581 if (msr & X2APIC_ENABLE)
1582 return;
1583 wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE);
1584 printk_once(KERN_INFO "x2apic enabled\n");
1585 }
1586
1587 static int __init setup_nox2apic(char *str)
1588 {
1589 if (x2apic_enabled()) {
1590 int apicid = native_apic_msr_read(APIC_ID);
1591
1592 if (apicid >= 255) {
1593 pr_warning("Apicid: %08x, cannot enforce nox2apic\n",
1594 apicid);
1595 return 0;
1596 }
1597 pr_warning("x2apic already enabled.\n");
1598 __x2apic_disable();
1599 }
1600 setup_clear_cpu_cap(X86_FEATURE_X2APIC);
1601 x2apic_state = X2APIC_DISABLED;
1602 x2apic_mode = 0;
1603 return 0;
1604 }
1605 early_param("nox2apic", setup_nox2apic);
1606
1607 /* Called from cpu_init() to enable x2apic on (secondary) cpus */
1608 void x2apic_setup(void)
1609 {
1610 /*
1611 * If x2apic is not in ON state, disable it if already enabled
1612 * from BIOS.
1613 */
1614 if (x2apic_state != X2APIC_ON) {
1615 __x2apic_disable();
1616 return;
1617 }
1618 __x2apic_enable();
1619 }
1620
1621 static __init void x2apic_disable(void)
1622 {
1623 u32 x2apic_id, state = x2apic_state;
1624
1625 x2apic_mode = 0;
1626 x2apic_state = X2APIC_DISABLED;
1627
1628 if (state != X2APIC_ON)
1629 return;
1630
1631 x2apic_id = read_apic_id();
1632 if (x2apic_id >= 255)
1633 panic("Cannot disable x2apic, id: %08x\n", x2apic_id);
1634
1635 __x2apic_disable();
1636 register_lapic_address(mp_lapic_addr);
1637 }
1638
1639 static __init void x2apic_enable(void)
1640 {
1641 if (x2apic_state != X2APIC_OFF)
1642 return;
1643
1644 x2apic_mode = 1;
1645 x2apic_state = X2APIC_ON;
1646 __x2apic_enable();
1647 }
1648
1649 static __init void try_to_enable_x2apic(int remap_mode)
1650 {
1651 if (x2apic_state == X2APIC_DISABLED)
1652 return;
1653
1654 if (remap_mode != IRQ_REMAP_X2APIC_MODE) {
1655 /* IR is required if there is APIC ID > 255 even when running
1656 * under KVM
1657 */
1658 if (max_physical_apicid > 255 ||
1659 !hypervisor_x2apic_available()) {
1660 pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n");
1661 x2apic_disable();
1662 return;
1663 }
1664
1665 /*
1666 * without IR all CPUs can be addressed by IOAPIC/MSI
1667 * only in physical mode
1668 */
1669 x2apic_phys = 1;
1670 }
1671 x2apic_enable();
1672 }
1673
1674 void __init check_x2apic(void)
1675 {
1676 if (x2apic_enabled()) {
1677 pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n");
1678 x2apic_mode = 1;
1679 x2apic_state = X2APIC_ON;
1680 } else if (!boot_cpu_has(X86_FEATURE_X2APIC)) {
1681 x2apic_state = X2APIC_DISABLED;
1682 }
1683 }
1684 #else /* CONFIG_X86_X2APIC */
1685 static int __init validate_x2apic(void)
1686 {
1687 if (!apic_is_x2apic_enabled())
1688 return 0;
1689 /*
1690 * Checkme: Can we simply turn off x2apic here instead of panic?
1691 */
1692 panic("BIOS has enabled x2apic but kernel doesn't support x2apic, please disable x2apic in BIOS.\n");
1693 }
1694 early_initcall(validate_x2apic);
1695
1696 static inline void try_to_enable_x2apic(int remap_mode) { }
1697 static inline void __x2apic_enable(void) { }
1698 #endif /* !CONFIG_X86_X2APIC */
1699
1700 void __init enable_IR_x2apic(void)
1701 {
1702 unsigned long flags;
1703 int ret, ir_stat;
1704
1705 if (skip_ioapic_setup) {
1706 pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n");
1707 return;
1708 }
1709
1710 ir_stat = irq_remapping_prepare();
1711 if (ir_stat < 0 && !x2apic_supported())
1712 return;
1713
1714 ret = save_ioapic_entries();
1715 if (ret) {
1716 pr_info("Saving IO-APIC state failed: %d\n", ret);
1717 return;
1718 }
1719
1720 local_irq_save(flags);
1721 legacy_pic->mask_all();
1722 mask_ioapic_entries();
1723
1724 /* If irq_remapping_prepare() succeeded, try to enable it */
1725 if (ir_stat >= 0)
1726 ir_stat = irq_remapping_enable();
1727 /* ir_stat contains the remap mode or an error code */
1728 try_to_enable_x2apic(ir_stat);
1729
1730 if (ir_stat < 0)
1731 restore_ioapic_entries();
1732 legacy_pic->restore_mask();
1733 local_irq_restore(flags);
1734 }
1735
1736 #ifdef CONFIG_X86_64
1737 /*
1738 * Detect and enable local APICs on non-SMP boards.
1739 * Original code written by Keir Fraser.
1740 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1741 * not correctly set up (usually the APIC timer won't work etc.)
1742 */
1743 static int __init detect_init_APIC(void)
1744 {
1745 if (!boot_cpu_has(X86_FEATURE_APIC)) {
1746 pr_info("No local APIC present\n");
1747 return -1;
1748 }
1749
1750 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1751 return 0;
1752 }
1753 #else
1754
1755 static int __init apic_verify(void)
1756 {
1757 u32 features, h, l;
1758
1759 /*
1760 * The APIC feature bit should now be enabled
1761 * in `cpuid'
1762 */
1763 features = cpuid_edx(1);
1764 if (!(features & (1 << X86_FEATURE_APIC))) {
1765 pr_warning("Could not enable APIC!\n");
1766 return -1;
1767 }
1768 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1769 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1770
1771 /* The BIOS may have set up the APIC at some other address */
1772 if (boot_cpu_data.x86 >= 6) {
1773 rdmsr(MSR_IA32_APICBASE, l, h);
1774 if (l & MSR_IA32_APICBASE_ENABLE)
1775 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1776 }
1777
1778 pr_info("Found and enabled local APIC!\n");
1779 return 0;
1780 }
1781
1782 int __init apic_force_enable(unsigned long addr)
1783 {
1784 u32 h, l;
1785
1786 if (disable_apic)
1787 return -1;
1788
1789 /*
1790 * Some BIOSes disable the local APIC in the APIC_BASE
1791 * MSR. This can only be done in software for Intel P6 or later
1792 * and AMD K7 (Model > 1) or later.
1793 */
1794 if (boot_cpu_data.x86 >= 6) {
1795 rdmsr(MSR_IA32_APICBASE, l, h);
1796 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
1797 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1798 l &= ~MSR_IA32_APICBASE_BASE;
1799 l |= MSR_IA32_APICBASE_ENABLE | addr;
1800 wrmsr(MSR_IA32_APICBASE, l, h);
1801 enabled_via_apicbase = 1;
1802 }
1803 }
1804 return apic_verify();
1805 }
1806
1807 /*
1808 * Detect and initialize APIC
1809 */
1810 static int __init detect_init_APIC(void)
1811 {
1812 /* Disabled by kernel option? */
1813 if (disable_apic)
1814 return -1;
1815
1816 switch (boot_cpu_data.x86_vendor) {
1817 case X86_VENDOR_AMD:
1818 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1819 (boot_cpu_data.x86 >= 15))
1820 break;
1821 goto no_apic;
1822 case X86_VENDOR_INTEL:
1823 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
1824 (boot_cpu_data.x86 == 5 && boot_cpu_has(X86_FEATURE_APIC)))
1825 break;
1826 goto no_apic;
1827 default:
1828 goto no_apic;
1829 }
1830
1831 if (!boot_cpu_has(X86_FEATURE_APIC)) {
1832 /*
1833 * Over-ride BIOS and try to enable the local APIC only if
1834 * "lapic" specified.
1835 */
1836 if (!force_enable_local_apic) {
1837 pr_info("Local APIC disabled by BIOS -- "
1838 "you can enable it with \"lapic\"\n");
1839 return -1;
1840 }
1841 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE))
1842 return -1;
1843 } else {
1844 if (apic_verify())
1845 return -1;
1846 }
1847
1848 apic_pm_activate();
1849
1850 return 0;
1851
1852 no_apic:
1853 pr_info("No local APIC present or hardware disabled\n");
1854 return -1;
1855 }
1856 #endif
1857
1858 /**
1859 * init_apic_mappings - initialize APIC mappings
1860 */
1861 void __init init_apic_mappings(void)
1862 {
1863 unsigned int new_apicid;
1864
1865 apic_check_deadline_errata();
1866
1867 if (x2apic_mode) {
1868 boot_cpu_physical_apicid = read_apic_id();
1869 return;
1870 }
1871
1872 /* If no local APIC can be found return early */
1873 if (!smp_found_config && detect_init_APIC()) {
1874 /* lets NOP'ify apic operations */
1875 pr_info("APIC: disable apic facility\n");
1876 apic_disable();
1877 } else {
1878 apic_phys = mp_lapic_addr;
1879
1880 /*
1881 * If the system has ACPI MADT tables or MP info, the LAPIC
1882 * address is already registered.
1883 */
1884 if (!acpi_lapic && !smp_found_config)
1885 register_lapic_address(apic_phys);
1886 }
1887
1888 /*
1889 * Fetch the APIC ID of the BSP in case we have a
1890 * default configuration (or the MP table is broken).
1891 */
1892 new_apicid = read_apic_id();
1893 if (boot_cpu_physical_apicid != new_apicid) {
1894 boot_cpu_physical_apicid = new_apicid;
1895 /*
1896 * yeah -- we lie about apic_version
1897 * in case if apic was disabled via boot option
1898 * but it's not a problem for SMP compiled kernel
1899 * since smp_sanity_check is prepared for such a case
1900 * and disable smp mode
1901 */
1902 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR));
1903 }
1904 }
1905
1906 void __init register_lapic_address(unsigned long address)
1907 {
1908 mp_lapic_addr = address;
1909
1910 if (!x2apic_mode) {
1911 set_fixmap_nocache(FIX_APIC_BASE, address);
1912 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
1913 APIC_BASE, address);
1914 }
1915 if (boot_cpu_physical_apicid == -1U) {
1916 boot_cpu_physical_apicid = read_apic_id();
1917 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR));
1918 }
1919 }
1920
1921 /*
1922 * Local APIC interrupts
1923 */
1924
1925 /*
1926 * This interrupt should _never_ happen with our APIC/SMP architecture
1927 */
1928 static void __smp_spurious_interrupt(u8 vector)
1929 {
1930 u32 v;
1931
1932 /*
1933 * Check if this really is a spurious interrupt and ACK it
1934 * if it is a vectored one. Just in case...
1935 * Spurious interrupts should not be ACKed.
1936 */
1937 v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1));
1938 if (v & (1 << (vector & 0x1f)))
1939 ack_APIC_irq();
1940
1941 inc_irq_stat(irq_spurious_count);
1942
1943 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1944 pr_info("spurious APIC interrupt through vector %02x on CPU#%d, "
1945 "should never happen.\n", vector, smp_processor_id());
1946 }
1947
1948 __visible void __irq_entry smp_spurious_interrupt(struct pt_regs *regs)
1949 {
1950 entering_irq();
1951 __smp_spurious_interrupt(~regs->orig_ax);
1952 exiting_irq();
1953 }
1954
1955 __visible void __irq_entry smp_trace_spurious_interrupt(struct pt_regs *regs)
1956 {
1957 u8 vector = ~regs->orig_ax;
1958
1959 entering_irq();
1960 trace_spurious_apic_entry(vector);
1961 __smp_spurious_interrupt(vector);
1962 trace_spurious_apic_exit(vector);
1963 exiting_irq();
1964 }
1965
1966 /*
1967 * This interrupt should never happen with our APIC/SMP architecture
1968 */
1969 static void __smp_error_interrupt(struct pt_regs *regs)
1970 {
1971 u32 v;
1972 u32 i = 0;
1973 static const char * const error_interrupt_reason[] = {
1974 "Send CS error", /* APIC Error Bit 0 */
1975 "Receive CS error", /* APIC Error Bit 1 */
1976 "Send accept error", /* APIC Error Bit 2 */
1977 "Receive accept error", /* APIC Error Bit 3 */
1978 "Redirectable IPI", /* APIC Error Bit 4 */
1979 "Send illegal vector", /* APIC Error Bit 5 */
1980 "Received illegal vector", /* APIC Error Bit 6 */
1981 "Illegal register address", /* APIC Error Bit 7 */
1982 };
1983
1984 /* First tickle the hardware, only then report what went on. -- REW */
1985 if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */
1986 apic_write(APIC_ESR, 0);
1987 v = apic_read(APIC_ESR);
1988 ack_APIC_irq();
1989 atomic_inc(&irq_err_count);
1990
1991 apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x",
1992 smp_processor_id(), v);
1993
1994 v &= 0xff;
1995 while (v) {
1996 if (v & 0x1)
1997 apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]);
1998 i++;
1999 v >>= 1;
2000 }
2001
2002 apic_printk(APIC_DEBUG, KERN_CONT "\n");
2003
2004 }
2005
2006 __visible void __irq_entry smp_error_interrupt(struct pt_regs *regs)
2007 {
2008 entering_irq();
2009 __smp_error_interrupt(regs);
2010 exiting_irq();
2011 }
2012
2013 __visible void __irq_entry smp_trace_error_interrupt(struct pt_regs *regs)
2014 {
2015 entering_irq();
2016 trace_error_apic_entry(ERROR_APIC_VECTOR);
2017 __smp_error_interrupt(regs);
2018 trace_error_apic_exit(ERROR_APIC_VECTOR);
2019 exiting_irq();
2020 }
2021
2022 /**
2023 * connect_bsp_APIC - attach the APIC to the interrupt system
2024 */
2025 static void __init connect_bsp_APIC(void)
2026 {
2027 #ifdef CONFIG_X86_32
2028 if (pic_mode) {
2029 /*
2030 * Do not trust the local APIC being empty at bootup.
2031 */
2032 clear_local_APIC();
2033 /*
2034 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
2035 * local APIC to INT and NMI lines.
2036 */
2037 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
2038 "enabling APIC mode.\n");
2039 imcr_pic_to_apic();
2040 }
2041 #endif
2042 }
2043
2044 /**
2045 * disconnect_bsp_APIC - detach the APIC from the interrupt system
2046 * @virt_wire_setup: indicates, whether virtual wire mode is selected
2047 *
2048 * Virtual wire mode is necessary to deliver legacy interrupts even when the
2049 * APIC is disabled.
2050 */
2051 void disconnect_bsp_APIC(int virt_wire_setup)
2052 {
2053 unsigned int value;
2054
2055 #ifdef CONFIG_X86_32
2056 if (pic_mode) {
2057 /*
2058 * Put the board back into PIC mode (has an effect only on
2059 * certain older boards). Note that APIC interrupts, including
2060 * IPIs, won't work beyond this point! The only exception are
2061 * INIT IPIs.
2062 */
2063 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
2064 "entering PIC mode.\n");
2065 imcr_apic_to_pic();
2066 return;
2067 }
2068 #endif
2069
2070 /* Go back to Virtual Wire compatibility mode */
2071
2072 /* For the spurious interrupt use vector F, and enable it */
2073 value = apic_read(APIC_SPIV);
2074 value &= ~APIC_VECTOR_MASK;
2075 value |= APIC_SPIV_APIC_ENABLED;
2076 value |= 0xf;
2077 apic_write(APIC_SPIV, value);
2078
2079 if (!virt_wire_setup) {
2080 /*
2081 * For LVT0 make it edge triggered, active high,
2082 * external and enabled
2083 */
2084 value = apic_read(APIC_LVT0);
2085 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
2086 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
2087 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
2088 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
2089 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
2090 apic_write(APIC_LVT0, value);
2091 } else {
2092 /* Disable LVT0 */
2093 apic_write(APIC_LVT0, APIC_LVT_MASKED);
2094 }
2095
2096 /*
2097 * For LVT1 make it edge triggered, active high,
2098 * nmi and enabled
2099 */
2100 value = apic_read(APIC_LVT1);
2101 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
2102 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
2103 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
2104 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
2105 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
2106 apic_write(APIC_LVT1, value);
2107 }
2108
2109 /*
2110 * The number of allocated logical CPU IDs. Since logical CPU IDs are allocated
2111 * contiguously, it equals to current allocated max logical CPU ID plus 1.
2112 * All allocated CPU IDs should be in the [0, nr_logical_cpuids) range,
2113 * so the maximum of nr_logical_cpuids is nr_cpu_ids.
2114 *
2115 * NOTE: Reserve 0 for BSP.
2116 */
2117 static int nr_logical_cpuids = 1;
2118
2119 /*
2120 * Used to store mapping between logical CPU IDs and APIC IDs.
2121 */
2122 static int cpuid_to_apicid[] = {
2123 [0 ... NR_CPUS - 1] = -1,
2124 };
2125
2126 /*
2127 * Should use this API to allocate logical CPU IDs to keep nr_logical_cpuids
2128 * and cpuid_to_apicid[] synchronized.
2129 */
2130 static int allocate_logical_cpuid(int apicid)
2131 {
2132 int i;
2133
2134 /*
2135 * cpuid <-> apicid mapping is persistent, so when a cpu is up,
2136 * check if the kernel has allocated a cpuid for it.
2137 */
2138 for (i = 0; i < nr_logical_cpuids; i++) {
2139 if (cpuid_to_apicid[i] == apicid)
2140 return i;
2141 }
2142
2143 /* Allocate a new cpuid. */
2144 if (nr_logical_cpuids >= nr_cpu_ids) {
2145 WARN_ONCE(1, "APIC: NR_CPUS/possible_cpus limit of %i reached. "
2146 "Processor %d/0x%x and the rest are ignored.\n",
2147 nr_cpu_ids, nr_logical_cpuids, apicid);
2148 return -EINVAL;
2149 }
2150
2151 cpuid_to_apicid[nr_logical_cpuids] = apicid;
2152 return nr_logical_cpuids++;
2153 }
2154
2155 int generic_processor_info(int apicid, int version)
2156 {
2157 int cpu, max = nr_cpu_ids;
2158 bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid,
2159 phys_cpu_present_map);
2160
2161 /*
2162 * boot_cpu_physical_apicid is designed to have the apicid
2163 * returned by read_apic_id(), i.e, the apicid of the
2164 * currently booting-up processor. However, on some platforms,
2165 * it is temporarily modified by the apicid reported as BSP
2166 * through MP table. Concretely:
2167 *
2168 * - arch/x86/kernel/mpparse.c: MP_processor_info()
2169 * - arch/x86/mm/amdtopology.c: amd_numa_init()
2170 *
2171 * This function is executed with the modified
2172 * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel
2173 * parameter doesn't work to disable APs on kdump 2nd kernel.
2174 *
2175 * Since fixing handling of boot_cpu_physical_apicid requires
2176 * another discussion and tests on each platform, we leave it
2177 * for now and here we use read_apic_id() directly in this
2178 * function, __generic_processor_info().
2179 */
2180 if (disabled_cpu_apicid != BAD_APICID &&
2181 disabled_cpu_apicid != read_apic_id() &&
2182 disabled_cpu_apicid == apicid) {
2183 int thiscpu = num_processors + disabled_cpus;
2184
2185 pr_warning("APIC: Disabling requested cpu."
2186 " Processor %d/0x%x ignored.\n",
2187 thiscpu, apicid);
2188
2189 disabled_cpus++;
2190 return -ENODEV;
2191 }
2192
2193 /*
2194 * If boot cpu has not been detected yet, then only allow upto
2195 * nr_cpu_ids - 1 processors and keep one slot free for boot cpu
2196 */
2197 if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 &&
2198 apicid != boot_cpu_physical_apicid) {
2199 int thiscpu = max + disabled_cpus - 1;
2200
2201 pr_warning(
2202 "APIC: NR_CPUS/possible_cpus limit of %i almost"
2203 " reached. Keeping one slot for boot cpu."
2204 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
2205
2206 disabled_cpus++;
2207 return -ENODEV;
2208 }
2209
2210 if (num_processors >= nr_cpu_ids) {
2211 int thiscpu = max + disabled_cpus;
2212
2213 pr_warning("APIC: NR_CPUS/possible_cpus limit of %i "
2214 "reached. Processor %d/0x%x ignored.\n",
2215 max, thiscpu, apicid);
2216
2217 disabled_cpus++;
2218 return -EINVAL;
2219 }
2220
2221 if (apicid == boot_cpu_physical_apicid) {
2222 /*
2223 * x86_bios_cpu_apicid is required to have processors listed
2224 * in same order as logical cpu numbers. Hence the first
2225 * entry is BSP, and so on.
2226 * boot_cpu_init() already hold bit 0 in cpu_present_mask
2227 * for BSP.
2228 */
2229 cpu = 0;
2230
2231 /* Logical cpuid 0 is reserved for BSP. */
2232 cpuid_to_apicid[0] = apicid;
2233 } else {
2234 cpu = allocate_logical_cpuid(apicid);
2235 if (cpu < 0) {
2236 disabled_cpus++;
2237 return -EINVAL;
2238 }
2239 }
2240
2241 /*
2242 * Validate version
2243 */
2244 if (version == 0x0) {
2245 pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n",
2246 cpu, apicid);
2247 version = 0x10;
2248 }
2249
2250 if (version != boot_cpu_apic_version) {
2251 pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n",
2252 boot_cpu_apic_version, cpu, version);
2253 }
2254
2255 if (apicid > max_physical_apicid)
2256 max_physical_apicid = apicid;
2257
2258 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
2259 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid;
2260 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
2261 #endif
2262 #ifdef CONFIG_X86_32
2263 early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
2264 apic->x86_32_early_logical_apicid(cpu);
2265 #endif
2266 set_cpu_possible(cpu, true);
2267 physid_set(apicid, phys_cpu_present_map);
2268 set_cpu_present(cpu, true);
2269 num_processors++;
2270
2271 return cpu;
2272 }
2273
2274 int hard_smp_processor_id(void)
2275 {
2276 return read_apic_id();
2277 }
2278
2279 void default_init_apic_ldr(void)
2280 {
2281 unsigned long val;
2282
2283 apic_write(APIC_DFR, APIC_DFR_VALUE);
2284 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
2285 val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
2286 apic_write(APIC_LDR, val);
2287 }
2288
2289 int default_cpu_mask_to_apicid(const struct cpumask *mask,
2290 struct irq_data *irqdata,
2291 unsigned int *apicid)
2292 {
2293 unsigned int cpu = cpumask_first(mask);
2294
2295 if (cpu >= nr_cpu_ids)
2296 return -EINVAL;
2297 *apicid = per_cpu(x86_cpu_to_apicid, cpu);
2298 irq_data_update_effective_affinity(irqdata, cpumask_of(cpu));
2299 return 0;
2300 }
2301
2302 int flat_cpu_mask_to_apicid(const struct cpumask *mask,
2303 struct irq_data *irqdata,
2304 unsigned int *apicid)
2305
2306 {
2307 struct cpumask *effmsk = irq_data_get_effective_affinity_mask(irqdata);
2308 unsigned long cpu_mask = cpumask_bits(mask)[0] & APIC_ALL_CPUS;
2309
2310 if (!cpu_mask)
2311 return -EINVAL;
2312 *apicid = (unsigned int)cpu_mask;
2313 cpumask_bits(effmsk)[0] = cpu_mask;
2314 return 0;
2315 }
2316
2317 /*
2318 * Override the generic EOI implementation with an optimized version.
2319 * Only called during early boot when only one CPU is active and with
2320 * interrupts disabled, so we know this does not race with actual APIC driver
2321 * use.
2322 */
2323 void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v))
2324 {
2325 struct apic **drv;
2326
2327 for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) {
2328 /* Should happen once for each apic */
2329 WARN_ON((*drv)->eoi_write == eoi_write);
2330 (*drv)->native_eoi_write = (*drv)->eoi_write;
2331 (*drv)->eoi_write = eoi_write;
2332 }
2333 }
2334
2335 static void __init apic_bsp_up_setup(void)
2336 {
2337 #ifdef CONFIG_X86_64
2338 apic_write(APIC_ID, apic->set_apic_id(boot_cpu_physical_apicid));
2339 #else
2340 /*
2341 * Hack: In case of kdump, after a crash, kernel might be booting
2342 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
2343 * might be zero if read from MP tables. Get it from LAPIC.
2344 */
2345 # ifdef CONFIG_CRASH_DUMP
2346 boot_cpu_physical_apicid = read_apic_id();
2347 # endif
2348 #endif
2349 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
2350 }
2351
2352 /**
2353 * apic_bsp_setup - Setup function for local apic and io-apic
2354 * @upmode: Force UP mode (for APIC_init_uniprocessor)
2355 *
2356 * Returns:
2357 * apic_id of BSP APIC
2358 */
2359 int __init apic_bsp_setup(bool upmode)
2360 {
2361 int id;
2362
2363 connect_bsp_APIC();
2364 if (upmode)
2365 apic_bsp_up_setup();
2366 setup_local_APIC();
2367
2368 if (x2apic_mode)
2369 id = apic_read(APIC_LDR);
2370 else
2371 id = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
2372
2373 enable_IO_APIC();
2374 end_local_APIC_setup();
2375 irq_remap_enable_fault_handling();
2376 setup_IO_APIC();
2377 /* Setup local timer */
2378 x86_init.timers.setup_percpu_clockev();
2379 return id;
2380 }
2381
2382 /*
2383 * This initializes the IO-APIC and APIC hardware if this is
2384 * a UP kernel.
2385 */
2386 int __init APIC_init_uniprocessor(void)
2387 {
2388 if (disable_apic) {
2389 pr_info("Apic disabled\n");
2390 return -1;
2391 }
2392 #ifdef CONFIG_X86_64
2393 if (!boot_cpu_has(X86_FEATURE_APIC)) {
2394 disable_apic = 1;
2395 pr_info("Apic disabled by BIOS\n");
2396 return -1;
2397 }
2398 #else
2399 if (!smp_found_config && !boot_cpu_has(X86_FEATURE_APIC))
2400 return -1;
2401
2402 /*
2403 * Complain if the BIOS pretends there is one.
2404 */
2405 if (!boot_cpu_has(X86_FEATURE_APIC) &&
2406 APIC_INTEGRATED(boot_cpu_apic_version)) {
2407 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
2408 boot_cpu_physical_apicid);
2409 return -1;
2410 }
2411 #endif
2412
2413 if (!smp_found_config)
2414 disable_ioapic_support();
2415
2416 default_setup_apic_routing();
2417 apic_bsp_setup(true);
2418 return 0;
2419 }
2420
2421 #ifdef CONFIG_UP_LATE_INIT
2422 void __init up_late_init(void)
2423 {
2424 APIC_init_uniprocessor();
2425 }
2426 #endif
2427
2428 /*
2429 * Power management
2430 */
2431 #ifdef CONFIG_PM
2432
2433 static struct {
2434 /*
2435 * 'active' is true if the local APIC was enabled by us and
2436 * not the BIOS; this signifies that we are also responsible
2437 * for disabling it before entering apm/acpi suspend
2438 */
2439 int active;
2440 /* r/w apic fields */
2441 unsigned int apic_id;
2442 unsigned int apic_taskpri;
2443 unsigned int apic_ldr;
2444 unsigned int apic_dfr;
2445 unsigned int apic_spiv;
2446 unsigned int apic_lvtt;
2447 unsigned int apic_lvtpc;
2448 unsigned int apic_lvt0;
2449 unsigned int apic_lvt1;
2450 unsigned int apic_lvterr;
2451 unsigned int apic_tmict;
2452 unsigned int apic_tdcr;
2453 unsigned int apic_thmr;
2454 unsigned int apic_cmci;
2455 } apic_pm_state;
2456
2457 static int lapic_suspend(void)
2458 {
2459 unsigned long flags;
2460 int maxlvt;
2461
2462 if (!apic_pm_state.active)
2463 return 0;
2464
2465 maxlvt = lapic_get_maxlvt();
2466
2467 apic_pm_state.apic_id = apic_read(APIC_ID);
2468 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
2469 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
2470 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
2471 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
2472 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
2473 if (maxlvt >= 4)
2474 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
2475 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
2476 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
2477 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
2478 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
2479 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
2480 #ifdef CONFIG_X86_THERMAL_VECTOR
2481 if (maxlvt >= 5)
2482 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
2483 #endif
2484 #ifdef CONFIG_X86_MCE_INTEL
2485 if (maxlvt >= 6)
2486 apic_pm_state.apic_cmci = apic_read(APIC_LVTCMCI);
2487 #endif
2488
2489 local_irq_save(flags);
2490 disable_local_APIC();
2491
2492 irq_remapping_disable();
2493
2494 local_irq_restore(flags);
2495 return 0;
2496 }
2497
2498 static void lapic_resume(void)
2499 {
2500 unsigned int l, h;
2501 unsigned long flags;
2502 int maxlvt;
2503
2504 if (!apic_pm_state.active)
2505 return;
2506
2507 local_irq_save(flags);
2508
2509 /*
2510 * IO-APIC and PIC have their own resume routines.
2511 * We just mask them here to make sure the interrupt
2512 * subsystem is completely quiet while we enable x2apic
2513 * and interrupt-remapping.
2514 */
2515 mask_ioapic_entries();
2516 legacy_pic->mask_all();
2517
2518 if (x2apic_mode) {
2519 __x2apic_enable();
2520 } else {
2521 /*
2522 * Make sure the APICBASE points to the right address
2523 *
2524 * FIXME! This will be wrong if we ever support suspend on
2525 * SMP! We'll need to do this as part of the CPU restore!
2526 */
2527 if (boot_cpu_data.x86 >= 6) {
2528 rdmsr(MSR_IA32_APICBASE, l, h);
2529 l &= ~MSR_IA32_APICBASE_BASE;
2530 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
2531 wrmsr(MSR_IA32_APICBASE, l, h);
2532 }
2533 }
2534
2535 maxlvt = lapic_get_maxlvt();
2536 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
2537 apic_write(APIC_ID, apic_pm_state.apic_id);
2538 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
2539 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
2540 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
2541 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
2542 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
2543 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
2544 #ifdef CONFIG_X86_THERMAL_VECTOR
2545 if (maxlvt >= 5)
2546 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
2547 #endif
2548 #ifdef CONFIG_X86_MCE_INTEL
2549 if (maxlvt >= 6)
2550 apic_write(APIC_LVTCMCI, apic_pm_state.apic_cmci);
2551 #endif
2552 if (maxlvt >= 4)
2553 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
2554 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
2555 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
2556 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
2557 apic_write(APIC_ESR, 0);
2558 apic_read(APIC_ESR);
2559 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
2560 apic_write(APIC_ESR, 0);
2561 apic_read(APIC_ESR);
2562
2563 irq_remapping_reenable(x2apic_mode);
2564
2565 local_irq_restore(flags);
2566 }
2567
2568 /*
2569 * This device has no shutdown method - fully functioning local APICs
2570 * are needed on every CPU up until machine_halt/restart/poweroff.
2571 */
2572
2573 static struct syscore_ops lapic_syscore_ops = {
2574 .resume = lapic_resume,
2575 .suspend = lapic_suspend,
2576 };
2577
2578 static void apic_pm_activate(void)
2579 {
2580 apic_pm_state.active = 1;
2581 }
2582
2583 static int __init init_lapic_sysfs(void)
2584 {
2585 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2586 if (boot_cpu_has(X86_FEATURE_APIC))
2587 register_syscore_ops(&lapic_syscore_ops);
2588
2589 return 0;
2590 }
2591
2592 /* local apic needs to resume before other devices access its registers. */
2593 core_initcall(init_lapic_sysfs);
2594
2595 #else /* CONFIG_PM */
2596
2597 static void apic_pm_activate(void) { }
2598
2599 #endif /* CONFIG_PM */
2600
2601 #ifdef CONFIG_X86_64
2602
2603 static int multi_checked;
2604 static int multi;
2605
2606 static int set_multi(const struct dmi_system_id *d)
2607 {
2608 if (multi)
2609 return 0;
2610 pr_info("APIC: %s detected, Multi Chassis\n", d->ident);
2611 multi = 1;
2612 return 0;
2613 }
2614
2615 static const struct dmi_system_id multi_dmi_table[] = {
2616 {
2617 .callback = set_multi,
2618 .ident = "IBM System Summit2",
2619 .matches = {
2620 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
2621 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"),
2622 },
2623 },
2624 {}
2625 };
2626
2627 static void dmi_check_multi(void)
2628 {
2629 if (multi_checked)
2630 return;
2631
2632 dmi_check_system(multi_dmi_table);
2633 multi_checked = 1;
2634 }
2635
2636 /*
2637 * apic_is_clustered_box() -- Check if we can expect good TSC
2638 *
2639 * Thus far, the major user of this is IBM's Summit2 series:
2640 * Clustered boxes may have unsynced TSC problems if they are
2641 * multi-chassis.
2642 * Use DMI to check them
2643 */
2644 int apic_is_clustered_box(void)
2645 {
2646 dmi_check_multi();
2647 return multi;
2648 }
2649 #endif
2650
2651 /*
2652 * APIC command line parameters
2653 */
2654 static int __init setup_disableapic(char *arg)
2655 {
2656 disable_apic = 1;
2657 setup_clear_cpu_cap(X86_FEATURE_APIC);
2658 return 0;
2659 }
2660 early_param("disableapic", setup_disableapic);
2661
2662 /* same as disableapic, for compatibility */
2663 static int __init setup_nolapic(char *arg)
2664 {
2665 return setup_disableapic(arg);
2666 }
2667 early_param("nolapic", setup_nolapic);
2668
2669 static int __init parse_lapic_timer_c2_ok(char *arg)
2670 {
2671 local_apic_timer_c2_ok = 1;
2672 return 0;
2673 }
2674 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
2675
2676 static int __init parse_disable_apic_timer(char *arg)
2677 {
2678 disable_apic_timer = 1;
2679 return 0;
2680 }
2681 early_param("noapictimer", parse_disable_apic_timer);
2682
2683 static int __init parse_nolapic_timer(char *arg)
2684 {
2685 disable_apic_timer = 1;
2686 return 0;
2687 }
2688 early_param("nolapic_timer", parse_nolapic_timer);
2689
2690 static int __init apic_set_verbosity(char *arg)
2691 {
2692 if (!arg) {
2693 #ifdef CONFIG_X86_64
2694 skip_ioapic_setup = 0;
2695 return 0;
2696 #endif
2697 return -EINVAL;
2698 }
2699
2700 if (strcmp("debug", arg) == 0)
2701 apic_verbosity = APIC_DEBUG;
2702 else if (strcmp("verbose", arg) == 0)
2703 apic_verbosity = APIC_VERBOSE;
2704 else {
2705 pr_warning("APIC Verbosity level %s not recognised"
2706 " use apic=verbose or apic=debug\n", arg);
2707 return -EINVAL;
2708 }
2709
2710 return 0;
2711 }
2712 early_param("apic", apic_set_verbosity);
2713
2714 static int __init lapic_insert_resource(void)
2715 {
2716 if (!apic_phys)
2717 return -1;
2718
2719 /* Put local APIC into the resource map. */
2720 lapic_resource.start = apic_phys;
2721 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
2722 insert_resource(&iomem_resource, &lapic_resource);
2723
2724 return 0;
2725 }
2726
2727 /*
2728 * need call insert after e820__reserve_resources()
2729 * that is using request_resource
2730 */
2731 late_initcall(lapic_insert_resource);
2732
2733 static int __init apic_set_disabled_cpu_apicid(char *arg)
2734 {
2735 if (!arg || !get_option(&arg, &disabled_cpu_apicid))
2736 return -EINVAL;
2737
2738 return 0;
2739 }
2740 early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid);
2741
2742 static int __init apic_set_extnmi(char *arg)
2743 {
2744 if (!arg)
2745 return -EINVAL;
2746
2747 if (!strncmp("all", arg, 3))
2748 apic_extnmi = APIC_EXTNMI_ALL;
2749 else if (!strncmp("none", arg, 4))
2750 apic_extnmi = APIC_EXTNMI_NONE;
2751 else if (!strncmp("bsp", arg, 3))
2752 apic_extnmi = APIC_EXTNMI_BSP;
2753 else {
2754 pr_warn("Unknown external NMI delivery mode `%s' ignored\n", arg);
2755 return -EINVAL;
2756 }
2757
2758 return 0;
2759 }
2760 early_param("apic_extnmi", apic_set_extnmi);
2761
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