~ [ source navigation ] ~ [ diff markup ] ~ [ identifier search ] ~

TOMOYO Linux Cross Reference
Linux/arch/x86/kernel/apic/apic.c

Version: ~ [ linux-6.2-rc3 ] ~ [ linux-6.1.5 ] ~ [ linux-6.0.19 ] ~ [ linux-5.19.17 ] ~ [ linux-5.18.19 ] ~ [ linux-5.17.15 ] ~ [ linux-5.16.20 ] ~ [ linux-5.15.87 ] ~ [ linux-5.14.21 ] ~ [ linux-5.13.19 ] ~ [ linux-5.12.19 ] ~ [ linux-5.11.22 ] ~ [ linux-5.10.162 ] ~ [ linux-5.9.16 ] ~ [ linux-5.8.18 ] ~ [ linux-5.7.19 ] ~ [ linux-5.6.19 ] ~ [ linux-5.5.19 ] ~ [ linux-5.4.228 ] ~ [ linux-5.3.18 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.269 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.302 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.337 ] ~ [ linux-4.8.17 ] ~ [ linux-4.7.10 ] ~ [ linux-4.6.7 ] ~ [ linux-4.5.7 ] ~ [ linux-4.4.302 ] ~ [ linux-4.3.6 ] ~ [ linux-4.2.8 ] ~ [ linux-4.1.52 ] ~ [ linux-4.0.9 ] ~ [ linux-3.10.108 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.9 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 /*
  2  *      Local APIC handling, local APIC timers
  3  *
  4  *      (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
  5  *
  6  *      Fixes
  7  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  8  *                                      thanks to Eric Gilmore
  9  *                                      and Rolf G. Tews
 10  *                                      for testing these extensively.
 11  *      Maciej W. Rozycki       :       Various updates and fixes.
 12  *      Mikael Pettersson       :       Power Management for UP-APIC.
 13  *      Pavel Machek and
 14  *      Mikael Pettersson       :       PM converted to driver model.
 15  */
 16 
 17 #include <linux/perf_event.h>
 18 #include <linux/kernel_stat.h>
 19 #include <linux/mc146818rtc.h>
 20 #include <linux/acpi_pmtmr.h>
 21 #include <linux/clockchips.h>
 22 #include <linux/interrupt.h>
 23 #include <linux/memblock.h>
 24 #include <linux/ftrace.h>
 25 #include <linux/ioport.h>
 26 #include <linux/export.h>
 27 #include <linux/syscore_ops.h>
 28 #include <linux/delay.h>
 29 #include <linux/timex.h>
 30 #include <linux/i8253.h>
 31 #include <linux/dmar.h>
 32 #include <linux/init.h>
 33 #include <linux/cpu.h>
 34 #include <linux/dmi.h>
 35 #include <linux/smp.h>
 36 #include <linux/mm.h>
 37 
 38 #include <asm/trace/irq_vectors.h>
 39 #include <asm/irq_remapping.h>
 40 #include <asm/perf_event.h>
 41 #include <asm/x86_init.h>
 42 #include <asm/pgalloc.h>
 43 #include <linux/atomic.h>
 44 #include <asm/mpspec.h>
 45 #include <asm/i8259.h>
 46 #include <asm/proto.h>
 47 #include <asm/traps.h>
 48 #include <asm/apic.h>
 49 #include <asm/io_apic.h>
 50 #include <asm/desc.h>
 51 #include <asm/hpet.h>
 52 #include <asm/mtrr.h>
 53 #include <asm/time.h>
 54 #include <asm/smp.h>
 55 #include <asm/mce.h>
 56 #include <asm/tsc.h>
 57 #include <asm/hypervisor.h>
 58 #include <asm/cpu_device_id.h>
 59 #include <asm/intel-family.h>
 60 #include <asm/irq_regs.h>
 61 
 62 unsigned int num_processors;
 63 
 64 unsigned disabled_cpus;
 65 
 66 /* Processor that is doing the boot up */
 67 unsigned int boot_cpu_physical_apicid = -1U;
 68 EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid);
 69 
 70 u8 boot_cpu_apic_version;
 71 
 72 /*
 73  * The highest APIC ID seen during enumeration.
 74  */
 75 static unsigned int max_physical_apicid;
 76 
 77 /*
 78  * Bitmask of physically existing CPUs:
 79  */
 80 physid_mask_t phys_cpu_present_map;
 81 
 82 /*
 83  * Processor to be disabled specified by kernel parameter
 84  * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to
 85  * avoid undefined behaviour caused by sending INIT from AP to BSP.
 86  */
 87 static unsigned int disabled_cpu_apicid __read_mostly = BAD_APICID;
 88 
 89 /*
 90  * This variable controls which CPUs receive external NMIs.  By default,
 91  * external NMIs are delivered only to the BSP.
 92  */
 93 static int apic_extnmi = APIC_EXTNMI_BSP;
 94 
 95 /*
 96  * Map cpu index to physical APIC ID
 97  */
 98 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID);
 99 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID);
100 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid, U32_MAX);
101 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid);
102 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
103 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid);
104 
105 #ifdef CONFIG_X86_32
106 
107 /*
108  * On x86_32, the mapping between cpu and logical apicid may vary
109  * depending on apic in use.  The following early percpu variable is
110  * used for the mapping.  This is where the behaviors of x86_64 and 32
111  * actually diverge.  Let's keep it ugly for now.
112  */
113 DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID);
114 
115 /* Local APIC was disabled by the BIOS and enabled by the kernel */
116 static int enabled_via_apicbase;
117 
118 /*
119  * Handle interrupt mode configuration register (IMCR).
120  * This register controls whether the interrupt signals
121  * that reach the BSP come from the master PIC or from the
122  * local APIC. Before entering Symmetric I/O Mode, either
123  * the BIOS or the operating system must switch out of
124  * PIC Mode by changing the IMCR.
125  */
126 static inline void imcr_pic_to_apic(void)
127 {
128         /* select IMCR register */
129         outb(0x70, 0x22);
130         /* NMI and 8259 INTR go through APIC */
131         outb(0x01, 0x23);
132 }
133 
134 static inline void imcr_apic_to_pic(void)
135 {
136         /* select IMCR register */
137         outb(0x70, 0x22);
138         /* NMI and 8259 INTR go directly to BSP */
139         outb(0x00, 0x23);
140 }
141 #endif
142 
143 /*
144  * Knob to control our willingness to enable the local APIC.
145  *
146  * +1=force-enable
147  */
148 static int force_enable_local_apic __initdata;
149 
150 /*
151  * APIC command line parameters
152  */
153 static int __init parse_lapic(char *arg)
154 {
155         if (IS_ENABLED(CONFIG_X86_32) && !arg)
156                 force_enable_local_apic = 1;
157         else if (arg && !strncmp(arg, "notscdeadline", 13))
158                 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
159         return 0;
160 }
161 early_param("lapic", parse_lapic);
162 
163 #ifdef CONFIG_X86_64
164 static int apic_calibrate_pmtmr __initdata;
165 static __init int setup_apicpmtimer(char *s)
166 {
167         apic_calibrate_pmtmr = 1;
168         notsc_setup(NULL);
169         return 0;
170 }
171 __setup("apicpmtimer", setup_apicpmtimer);
172 #endif
173 
174 unsigned long mp_lapic_addr;
175 int disable_apic;
176 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
177 static int disable_apic_timer __initdata;
178 /* Local APIC timer works in C2 */
179 int local_apic_timer_c2_ok;
180 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
181 
182 /*
183  * Debug level, exported for io_apic.c
184  */
185 unsigned int apic_verbosity;
186 
187 int pic_mode;
188 
189 /* Have we found an MP table */
190 int smp_found_config;
191 
192 static struct resource lapic_resource = {
193         .name = "Local APIC",
194         .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
195 };
196 
197 unsigned int lapic_timer_frequency = 0;
198 
199 static void apic_pm_activate(void);
200 
201 static unsigned long apic_phys;
202 
203 /*
204  * Get the LAPIC version
205  */
206 static inline int lapic_get_version(void)
207 {
208         return GET_APIC_VERSION(apic_read(APIC_LVR));
209 }
210 
211 /*
212  * Check, if the APIC is integrated or a separate chip
213  */
214 static inline int lapic_is_integrated(void)
215 {
216         return APIC_INTEGRATED(lapic_get_version());
217 }
218 
219 /*
220  * Check, whether this is a modern or a first generation APIC
221  */
222 static int modern_apic(void)
223 {
224         /* AMD systems use old APIC versions, so check the CPU */
225         if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
226             boot_cpu_data.x86 >= 0xf)
227                 return 1;
228 
229         /* Hygon systems use modern APIC */
230         if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
231                 return 1;
232 
233         return lapic_get_version() >= 0x14;
234 }
235 
236 /*
237  * right after this call apic become NOOP driven
238  * so apic->write/read doesn't do anything
239  */
240 static void __init apic_disable(void)
241 {
242         pr_info("APIC: switched to apic NOOP\n");
243         apic = &apic_noop;
244 }
245 
246 void native_apic_wait_icr_idle(void)
247 {
248         while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
249                 cpu_relax();
250 }
251 
252 u32 native_safe_apic_wait_icr_idle(void)
253 {
254         u32 send_status;
255         int timeout;
256 
257         timeout = 0;
258         do {
259                 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
260                 if (!send_status)
261                         break;
262                 inc_irq_stat(icr_read_retry_count);
263                 udelay(100);
264         } while (timeout++ < 1000);
265 
266         return send_status;
267 }
268 
269 void native_apic_icr_write(u32 low, u32 id)
270 {
271         unsigned long flags;
272 
273         local_irq_save(flags);
274         apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
275         apic_write(APIC_ICR, low);
276         local_irq_restore(flags);
277 }
278 
279 u64 native_apic_icr_read(void)
280 {
281         u32 icr1, icr2;
282 
283         icr2 = apic_read(APIC_ICR2);
284         icr1 = apic_read(APIC_ICR);
285 
286         return icr1 | ((u64)icr2 << 32);
287 }
288 
289 #ifdef CONFIG_X86_32
290 /**
291  * get_physical_broadcast - Get number of physical broadcast IDs
292  */
293 int get_physical_broadcast(void)
294 {
295         return modern_apic() ? 0xff : 0xf;
296 }
297 #endif
298 
299 /**
300  * lapic_get_maxlvt - get the maximum number of local vector table entries
301  */
302 int lapic_get_maxlvt(void)
303 {
304         /*
305          * - we always have APIC integrated on 64bit mode
306          * - 82489DXs do not report # of LVT entries
307          */
308         return lapic_is_integrated() ? GET_APIC_MAXLVT(apic_read(APIC_LVR)) : 2;
309 }
310 
311 /*
312  * Local APIC timer
313  */
314 
315 /* Clock divisor */
316 #define APIC_DIVISOR 16
317 #define TSC_DIVISOR  8
318 
319 /*
320  * This function sets up the local APIC timer, with a timeout of
321  * 'clocks' APIC bus clock. During calibration we actually call
322  * this function twice on the boot CPU, once with a bogus timeout
323  * value, second time for real. The other (noncalibrating) CPUs
324  * call this function only once, with the real, calibrated value.
325  *
326  * We do reads before writes even if unnecessary, to get around the
327  * P5 APIC double write bug.
328  */
329 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
330 {
331         unsigned int lvtt_value, tmp_value;
332 
333         lvtt_value = LOCAL_TIMER_VECTOR;
334         if (!oneshot)
335                 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
336         else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
337                 lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE;
338 
339         if (!lapic_is_integrated())
340                 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
341 
342         if (!irqen)
343                 lvtt_value |= APIC_LVT_MASKED;
344 
345         apic_write(APIC_LVTT, lvtt_value);
346 
347         if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) {
348                 /*
349                  * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode,
350                  * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized.
351                  * According to Intel, MFENCE can do the serialization here.
352                  */
353                 asm volatile("mfence" : : : "memory");
354 
355                 printk_once(KERN_DEBUG "TSC deadline timer enabled\n");
356                 return;
357         }
358 
359         /*
360          * Divide PICLK by 16
361          */
362         tmp_value = apic_read(APIC_TDCR);
363         apic_write(APIC_TDCR,
364                 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
365                 APIC_TDR_DIV_16);
366 
367         if (!oneshot)
368                 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
369 }
370 
371 /*
372  * Setup extended LVT, AMD specific
373  *
374  * Software should use the LVT offsets the BIOS provides.  The offsets
375  * are determined by the subsystems using it like those for MCE
376  * threshold or IBS.  On K8 only offset 0 (APIC500) and MCE interrupts
377  * are supported. Beginning with family 10h at least 4 offsets are
378  * available.
379  *
380  * Since the offsets must be consistent for all cores, we keep track
381  * of the LVT offsets in software and reserve the offset for the same
382  * vector also to be used on other cores. An offset is freed by
383  * setting the entry to APIC_EILVT_MASKED.
384  *
385  * If the BIOS is right, there should be no conflicts. Otherwise a
386  * "[Firmware Bug]: ..." error message is generated. However, if
387  * software does not properly determines the offsets, it is not
388  * necessarily a BIOS bug.
389  */
390 
391 static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX];
392 
393 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new)
394 {
395         return (old & APIC_EILVT_MASKED)
396                 || (new == APIC_EILVT_MASKED)
397                 || ((new & ~APIC_EILVT_MASKED) == old);
398 }
399 
400 static unsigned int reserve_eilvt_offset(int offset, unsigned int new)
401 {
402         unsigned int rsvd, vector;
403 
404         if (offset >= APIC_EILVT_NR_MAX)
405                 return ~0;
406 
407         rsvd = atomic_read(&eilvt_offsets[offset]);
408         do {
409                 vector = rsvd & ~APIC_EILVT_MASKED;     /* 0: unassigned */
410                 if (vector && !eilvt_entry_is_changeable(vector, new))
411                         /* may not change if vectors are different */
412                         return rsvd;
413                 rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new);
414         } while (rsvd != new);
415 
416         rsvd &= ~APIC_EILVT_MASKED;
417         if (rsvd && rsvd != vector)
418                 pr_info("LVT offset %d assigned for vector 0x%02x\n",
419                         offset, rsvd);
420 
421         return new;
422 }
423 
424 /*
425  * If mask=1, the LVT entry does not generate interrupts while mask=0
426  * enables the vector. See also the BKDGs. Must be called with
427  * preemption disabled.
428  */
429 
430 int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask)
431 {
432         unsigned long reg = APIC_EILVTn(offset);
433         unsigned int new, old, reserved;
434 
435         new = (mask << 16) | (msg_type << 8) | vector;
436         old = apic_read(reg);
437         reserved = reserve_eilvt_offset(offset, new);
438 
439         if (reserved != new) {
440                 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
441                        "vector 0x%x, but the register is already in use for "
442                        "vector 0x%x on another cpu\n",
443                        smp_processor_id(), reg, offset, new, reserved);
444                 return -EINVAL;
445         }
446 
447         if (!eilvt_entry_is_changeable(old, new)) {
448                 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
449                        "vector 0x%x, but the register is already in use for "
450                        "vector 0x%x on this cpu\n",
451                        smp_processor_id(), reg, offset, new, old);
452                 return -EBUSY;
453         }
454 
455         apic_write(reg, new);
456 
457         return 0;
458 }
459 EXPORT_SYMBOL_GPL(setup_APIC_eilvt);
460 
461 /*
462  * Program the next event, relative to now
463  */
464 static int lapic_next_event(unsigned long delta,
465                             struct clock_event_device *evt)
466 {
467         apic_write(APIC_TMICT, delta);
468         return 0;
469 }
470 
471 static int lapic_next_deadline(unsigned long delta,
472                                struct clock_event_device *evt)
473 {
474         u64 tsc;
475 
476         tsc = rdtsc();
477         wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR));
478         return 0;
479 }
480 
481 static int lapic_timer_shutdown(struct clock_event_device *evt)
482 {
483         unsigned int v;
484 
485         /* Lapic used as dummy for broadcast ? */
486         if (evt->features & CLOCK_EVT_FEAT_DUMMY)
487                 return 0;
488 
489         v = apic_read(APIC_LVTT);
490         v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
491         apic_write(APIC_LVTT, v);
492         apic_write(APIC_TMICT, 0);
493         return 0;
494 }
495 
496 static inline int
497 lapic_timer_set_periodic_oneshot(struct clock_event_device *evt, bool oneshot)
498 {
499         /* Lapic used as dummy for broadcast ? */
500         if (evt->features & CLOCK_EVT_FEAT_DUMMY)
501                 return 0;
502 
503         __setup_APIC_LVTT(lapic_timer_frequency, oneshot, 1);
504         return 0;
505 }
506 
507 static int lapic_timer_set_periodic(struct clock_event_device *evt)
508 {
509         return lapic_timer_set_periodic_oneshot(evt, false);
510 }
511 
512 static int lapic_timer_set_oneshot(struct clock_event_device *evt)
513 {
514         return lapic_timer_set_periodic_oneshot(evt, true);
515 }
516 
517 /*
518  * Local APIC timer broadcast function
519  */
520 static void lapic_timer_broadcast(const struct cpumask *mask)
521 {
522 #ifdef CONFIG_SMP
523         apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
524 #endif
525 }
526 
527 
528 /*
529  * The local apic timer can be used for any function which is CPU local.
530  */
531 static struct clock_event_device lapic_clockevent = {
532         .name                           = "lapic",
533         .features                       = CLOCK_EVT_FEAT_PERIODIC |
534                                           CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP
535                                           | CLOCK_EVT_FEAT_DUMMY,
536         .shift                          = 32,
537         .set_state_shutdown             = lapic_timer_shutdown,
538         .set_state_periodic             = lapic_timer_set_periodic,
539         .set_state_oneshot              = lapic_timer_set_oneshot,
540         .set_state_oneshot_stopped      = lapic_timer_shutdown,
541         .set_next_event                 = lapic_next_event,
542         .broadcast                      = lapic_timer_broadcast,
543         .rating                         = 100,
544         .irq                            = -1,
545 };
546 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
547 
548 #define DEADLINE_MODEL_MATCH_FUNC(model, func)  \
549         { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)&func }
550 
551 #define DEADLINE_MODEL_MATCH_REV(model, rev)    \
552         { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)rev }
553 
554 static u32 hsx_deadline_rev(void)
555 {
556         switch (boot_cpu_data.x86_stepping) {
557         case 0x02: return 0x3a; /* EP */
558         case 0x04: return 0x0f; /* EX */
559         }
560 
561         return ~0U;
562 }
563 
564 static u32 bdx_deadline_rev(void)
565 {
566         switch (boot_cpu_data.x86_stepping) {
567         case 0x02: return 0x00000011;
568         case 0x03: return 0x0700000e;
569         case 0x04: return 0x0f00000c;
570         case 0x05: return 0x0e000003;
571         }
572 
573         return ~0U;
574 }
575 
576 static u32 skx_deadline_rev(void)
577 {
578         switch (boot_cpu_data.x86_stepping) {
579         case 0x03: return 0x01000136;
580         case 0x04: return 0x02000014;
581         }
582 
583         if (boot_cpu_data.x86_stepping > 4)
584                 return 0;
585 
586         return ~0U;
587 }
588 
589 static const struct x86_cpu_id deadline_match[] = {
590         DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_HASWELL_X,        hsx_deadline_rev),
591         DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_X,      0x0b000020),
592         DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_BROADWELL_XEON_D, bdx_deadline_rev),
593         DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_SKYLAKE_X,        skx_deadline_rev),
594 
595         DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_CORE,     0x22),
596         DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_ULT,      0x20),
597         DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_GT3E,     0x17),
598 
599         DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_CORE,   0x25),
600         DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_GT3E,   0x17),
601 
602         DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_MOBILE,   0xb2),
603         DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_DESKTOP,  0xb2),
604 
605         DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_MOBILE,  0x52),
606         DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_DESKTOP, 0x52),
607 
608         {},
609 };
610 
611 static void apic_check_deadline_errata(void)
612 {
613         const struct x86_cpu_id *m;
614         u32 rev;
615 
616         if (!boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER) ||
617             boot_cpu_has(X86_FEATURE_HYPERVISOR))
618                 return;
619 
620         m = x86_match_cpu(deadline_match);
621         if (!m)
622                 return;
623 
624         /*
625          * Function pointers will have the MSB set due to address layout,
626          * immediate revisions will not.
627          */
628         if ((long)m->driver_data < 0)
629                 rev = ((u32 (*)(void))(m->driver_data))();
630         else
631                 rev = (u32)m->driver_data;
632 
633         if (boot_cpu_data.microcode >= rev)
634                 return;
635 
636         setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
637         pr_err(FW_BUG "TSC_DEADLINE disabled due to Errata; "
638                "please update microcode to version: 0x%x (or later)\n", rev);
639 }
640 
641 /*
642  * Setup the local APIC timer for this CPU. Copy the initialized values
643  * of the boot CPU and register the clock event in the framework.
644  */
645 static void setup_APIC_timer(void)
646 {
647         struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
648 
649         if (this_cpu_has(X86_FEATURE_ARAT)) {
650                 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP;
651                 /* Make LAPIC timer preferrable over percpu HPET */
652                 lapic_clockevent.rating = 150;
653         }
654 
655         memcpy(levt, &lapic_clockevent, sizeof(*levt));
656         levt->cpumask = cpumask_of(smp_processor_id());
657 
658         if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) {
659                 levt->name = "lapic-deadline";
660                 levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC |
661                                     CLOCK_EVT_FEAT_DUMMY);
662                 levt->set_next_event = lapic_next_deadline;
663                 clockevents_config_and_register(levt,
664                                                 tsc_khz * (1000 / TSC_DIVISOR),
665                                                 0xF, ~0UL);
666         } else
667                 clockevents_register_device(levt);
668 }
669 
670 /*
671  * Install the updated TSC frequency from recalibration at the TSC
672  * deadline clockevent devices.
673  */
674 static void __lapic_update_tsc_freq(void *info)
675 {
676         struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
677 
678         if (!this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
679                 return;
680 
681         clockevents_update_freq(levt, tsc_khz * (1000 / TSC_DIVISOR));
682 }
683 
684 void lapic_update_tsc_freq(void)
685 {
686         /*
687          * The clockevent device's ->mult and ->shift can both be
688          * changed. In order to avoid races, schedule the frequency
689          * update code on each CPU.
690          */
691         on_each_cpu(__lapic_update_tsc_freq, NULL, 0);
692 }
693 
694 /*
695  * In this functions we calibrate APIC bus clocks to the external timer.
696  *
697  * We want to do the calibration only once since we want to have local timer
698  * irqs syncron. CPUs connected by the same APIC bus have the very same bus
699  * frequency.
700  *
701  * This was previously done by reading the PIT/HPET and waiting for a wrap
702  * around to find out, that a tick has elapsed. I have a box, where the PIT
703  * readout is broken, so it never gets out of the wait loop again. This was
704  * also reported by others.
705  *
706  * Monitoring the jiffies value is inaccurate and the clockevents
707  * infrastructure allows us to do a simple substitution of the interrupt
708  * handler.
709  *
710  * The calibration routine also uses the pm_timer when possible, as the PIT
711  * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
712  * back to normal later in the boot process).
713  */
714 
715 #define LAPIC_CAL_LOOPS         (HZ/10)
716 
717 static __initdata int lapic_cal_loops = -1;
718 static __initdata long lapic_cal_t1, lapic_cal_t2;
719 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
720 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
721 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
722 
723 /*
724  * Temporary interrupt handler.
725  */
726 static void __init lapic_cal_handler(struct clock_event_device *dev)
727 {
728         unsigned long long tsc = 0;
729         long tapic = apic_read(APIC_TMCCT);
730         unsigned long pm = acpi_pm_read_early();
731 
732         if (boot_cpu_has(X86_FEATURE_TSC))
733                 tsc = rdtsc();
734 
735         switch (lapic_cal_loops++) {
736         case 0:
737                 lapic_cal_t1 = tapic;
738                 lapic_cal_tsc1 = tsc;
739                 lapic_cal_pm1 = pm;
740                 lapic_cal_j1 = jiffies;
741                 break;
742 
743         case LAPIC_CAL_LOOPS:
744                 lapic_cal_t2 = tapic;
745                 lapic_cal_tsc2 = tsc;
746                 if (pm < lapic_cal_pm1)
747                         pm += ACPI_PM_OVRRUN;
748                 lapic_cal_pm2 = pm;
749                 lapic_cal_j2 = jiffies;
750                 break;
751         }
752 }
753 
754 static int __init
755 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc)
756 {
757         const long pm_100ms = PMTMR_TICKS_PER_SEC / 10;
758         const long pm_thresh = pm_100ms / 100;
759         unsigned long mult;
760         u64 res;
761 
762 #ifndef CONFIG_X86_PM_TIMER
763         return -1;
764 #endif
765 
766         apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm);
767 
768         /* Check, if the PM timer is available */
769         if (!deltapm)
770                 return -1;
771 
772         mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
773 
774         if (deltapm > (pm_100ms - pm_thresh) &&
775             deltapm < (pm_100ms + pm_thresh)) {
776                 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n");
777                 return 0;
778         }
779 
780         res = (((u64)deltapm) *  mult) >> 22;
781         do_div(res, 1000000);
782         pr_warning("APIC calibration not consistent "
783                    "with PM-Timer: %ldms instead of 100ms\n",(long)res);
784 
785         /* Correct the lapic counter value */
786         res = (((u64)(*delta)) * pm_100ms);
787         do_div(res, deltapm);
788         pr_info("APIC delta adjusted to PM-Timer: "
789                 "%lu (%ld)\n", (unsigned long)res, *delta);
790         *delta = (long)res;
791 
792         /* Correct the tsc counter value */
793         if (boot_cpu_has(X86_FEATURE_TSC)) {
794                 res = (((u64)(*deltatsc)) * pm_100ms);
795                 do_div(res, deltapm);
796                 apic_printk(APIC_VERBOSE, "TSC delta adjusted to "
797                                           "PM-Timer: %lu (%ld)\n",
798                                         (unsigned long)res, *deltatsc);
799                 *deltatsc = (long)res;
800         }
801 
802         return 0;
803 }
804 
805 static int __init calibrate_APIC_clock(void)
806 {
807         struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
808         void (*real_handler)(struct clock_event_device *dev);
809         unsigned long deltaj;
810         long delta, deltatsc;
811         int pm_referenced = 0;
812 
813         /**
814          * check if lapic timer has already been calibrated by platform
815          * specific routine, such as tsc calibration code. if so, we just fill
816          * in the clockevent structure and return.
817          */
818 
819         if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) {
820                 return 0;
821         } else if (lapic_timer_frequency) {
822                 apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n",
823                                 lapic_timer_frequency);
824                 lapic_clockevent.mult = div_sc(lapic_timer_frequency/APIC_DIVISOR,
825                                         TICK_NSEC, lapic_clockevent.shift);
826                 lapic_clockevent.max_delta_ns =
827                         clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
828                 lapic_clockevent.max_delta_ticks = 0x7FFFFF;
829                 lapic_clockevent.min_delta_ns =
830                         clockevent_delta2ns(0xF, &lapic_clockevent);
831                 lapic_clockevent.min_delta_ticks = 0xF;
832                 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
833                 return 0;
834         }
835 
836         apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
837                     "calibrating APIC timer ...\n");
838 
839         local_irq_disable();
840 
841         /* Replace the global interrupt handler */
842         real_handler = global_clock_event->event_handler;
843         global_clock_event->event_handler = lapic_cal_handler;
844 
845         /*
846          * Setup the APIC counter to maximum. There is no way the lapic
847          * can underflow in the 100ms detection time frame
848          */
849         __setup_APIC_LVTT(0xffffffff, 0, 0);
850 
851         /* Let the interrupts run */
852         local_irq_enable();
853 
854         while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
855                 cpu_relax();
856 
857         local_irq_disable();
858 
859         /* Restore the real event handler */
860         global_clock_event->event_handler = real_handler;
861 
862         /* Build delta t1-t2 as apic timer counts down */
863         delta = lapic_cal_t1 - lapic_cal_t2;
864         apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
865 
866         deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
867 
868         /* we trust the PM based calibration if possible */
869         pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,
870                                         &delta, &deltatsc);
871 
872         /* Calculate the scaled math multiplication factor */
873         lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
874                                        lapic_clockevent.shift);
875         lapic_clockevent.max_delta_ns =
876                 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent);
877         lapic_clockevent.max_delta_ticks = 0x7FFFFFFF;
878         lapic_clockevent.min_delta_ns =
879                 clockevent_delta2ns(0xF, &lapic_clockevent);
880         lapic_clockevent.min_delta_ticks = 0xF;
881 
882         lapic_timer_frequency = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
883 
884         apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
885         apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult);
886         apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
887                     lapic_timer_frequency);
888 
889         if (boot_cpu_has(X86_FEATURE_TSC)) {
890                 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
891                             "%ld.%04ld MHz.\n",
892                             (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ),
893                             (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ));
894         }
895 
896         apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
897                     "%u.%04u MHz.\n",
898                     lapic_timer_frequency / (1000000 / HZ),
899                     lapic_timer_frequency % (1000000 / HZ));
900 
901         /*
902          * Do a sanity check on the APIC calibration result
903          */
904         if (lapic_timer_frequency < (1000000 / HZ)) {
905                 local_irq_enable();
906                 pr_warning("APIC frequency too slow, disabling apic timer\n");
907                 return -1;
908         }
909 
910         levt->features &= ~CLOCK_EVT_FEAT_DUMMY;
911 
912         /*
913          * PM timer calibration failed or not turned on
914          * so lets try APIC timer based calibration
915          */
916         if (!pm_referenced) {
917                 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
918 
919                 /*
920                  * Setup the apic timer manually
921                  */
922                 levt->event_handler = lapic_cal_handler;
923                 lapic_timer_set_periodic(levt);
924                 lapic_cal_loops = -1;
925 
926                 /* Let the interrupts run */
927                 local_irq_enable();
928 
929                 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
930                         cpu_relax();
931 
932                 /* Stop the lapic timer */
933                 local_irq_disable();
934                 lapic_timer_shutdown(levt);
935 
936                 /* Jiffies delta */
937                 deltaj = lapic_cal_j2 - lapic_cal_j1;
938                 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
939 
940                 /* Check, if the jiffies result is consistent */
941                 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
942                         apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
943                 else
944                         levt->features |= CLOCK_EVT_FEAT_DUMMY;
945         }
946         local_irq_enable();
947 
948         if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
949                 pr_warning("APIC timer disabled due to verification failure\n");
950                 return -1;
951         }
952 
953         return 0;
954 }
955 
956 /*
957  * Setup the boot APIC
958  *
959  * Calibrate and verify the result.
960  */
961 void __init setup_boot_APIC_clock(void)
962 {
963         /*
964          * The local apic timer can be disabled via the kernel
965          * commandline or from the CPU detection code. Register the lapic
966          * timer as a dummy clock event source on SMP systems, so the
967          * broadcast mechanism is used. On UP systems simply ignore it.
968          */
969         if (disable_apic_timer) {
970                 pr_info("Disabling APIC timer\n");
971                 /* No broadcast on UP ! */
972                 if (num_possible_cpus() > 1) {
973                         lapic_clockevent.mult = 1;
974                         setup_APIC_timer();
975                 }
976                 return;
977         }
978 
979         if (calibrate_APIC_clock()) {
980                 /* No broadcast on UP ! */
981                 if (num_possible_cpus() > 1)
982                         setup_APIC_timer();
983                 return;
984         }
985 
986         /*
987          * If nmi_watchdog is set to IO_APIC, we need the
988          * PIT/HPET going.  Otherwise register lapic as a dummy
989          * device.
990          */
991         lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
992 
993         /* Setup the lapic or request the broadcast */
994         setup_APIC_timer();
995         amd_e400_c1e_apic_setup();
996 }
997 
998 void setup_secondary_APIC_clock(void)
999 {
1000         setup_APIC_timer();
1001         amd_e400_c1e_apic_setup();
1002 }
1003 
1004 /*
1005  * The guts of the apic timer interrupt
1006  */
1007 static void local_apic_timer_interrupt(void)
1008 {
1009         struct clock_event_device *evt = this_cpu_ptr(&lapic_events);
1010 
1011         /*
1012          * Normally we should not be here till LAPIC has been initialized but
1013          * in some cases like kdump, its possible that there is a pending LAPIC
1014          * timer interrupt from previous kernel's context and is delivered in
1015          * new kernel the moment interrupts are enabled.
1016          *
1017          * Interrupts are enabled early and LAPIC is setup much later, hence
1018          * its possible that when we get here evt->event_handler is NULL.
1019          * Check for event_handler being NULL and discard the interrupt as
1020          * spurious.
1021          */
1022         if (!evt->event_handler) {
1023                 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n",
1024                            smp_processor_id());
1025                 /* Switch it off */
1026                 lapic_timer_shutdown(evt);
1027                 return;
1028         }
1029 
1030         /*
1031          * the NMI deadlock-detector uses this.
1032          */
1033         inc_irq_stat(apic_timer_irqs);
1034 
1035         evt->event_handler(evt);
1036 }
1037 
1038 /*
1039  * Local APIC timer interrupt. This is the most natural way for doing
1040  * local interrupts, but local timer interrupts can be emulated by
1041  * broadcast interrupts too. [in case the hw doesn't support APIC timers]
1042  *
1043  * [ if a single-CPU system runs an SMP kernel then we call the local
1044  *   interrupt as well. Thus we cannot inline the local irq ... ]
1045  */
1046 __visible void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs)
1047 {
1048         struct pt_regs *old_regs = set_irq_regs(regs);
1049 
1050         /*
1051          * NOTE! We'd better ACK the irq immediately,
1052          * because timer handling can be slow.
1053          *
1054          * update_process_times() expects us to have done irq_enter().
1055          * Besides, if we don't timer interrupts ignore the global
1056          * interrupt lock, which is the WrongThing (tm) to do.
1057          */
1058         entering_ack_irq();
1059         trace_local_timer_entry(LOCAL_TIMER_VECTOR);
1060         local_apic_timer_interrupt();
1061         trace_local_timer_exit(LOCAL_TIMER_VECTOR);
1062         exiting_irq();
1063 
1064         set_irq_regs(old_regs);
1065 }
1066 
1067 int setup_profiling_timer(unsigned int multiplier)
1068 {
1069         return -EINVAL;
1070 }
1071 
1072 /*
1073  * Local APIC start and shutdown
1074  */
1075 
1076 /**
1077  * clear_local_APIC - shutdown the local APIC
1078  *
1079  * This is called, when a CPU is disabled and before rebooting, so the state of
1080  * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
1081  * leftovers during boot.
1082  */
1083 void clear_local_APIC(void)
1084 {
1085         int maxlvt;
1086         u32 v;
1087 
1088         /* APIC hasn't been mapped yet */
1089         if (!x2apic_mode && !apic_phys)
1090                 return;
1091 
1092         maxlvt = lapic_get_maxlvt();
1093         /*
1094          * Masking an LVT entry can trigger a local APIC error
1095          * if the vector is zero. Mask LVTERR first to prevent this.
1096          */
1097         if (maxlvt >= 3) {
1098                 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
1099                 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
1100         }
1101         /*
1102          * Careful: we have to set masks only first to deassert
1103          * any level-triggered sources.
1104          */
1105         v = apic_read(APIC_LVTT);
1106         apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
1107         v = apic_read(APIC_LVT0);
1108         apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1109         v = apic_read(APIC_LVT1);
1110         apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
1111         if (maxlvt >= 4) {
1112                 v = apic_read(APIC_LVTPC);
1113                 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
1114         }
1115 
1116         /* lets not touch this if we didn't frob it */
1117 #ifdef CONFIG_X86_THERMAL_VECTOR
1118         if (maxlvt >= 5) {
1119                 v = apic_read(APIC_LVTTHMR);
1120                 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
1121         }
1122 #endif
1123 #ifdef CONFIG_X86_MCE_INTEL
1124         if (maxlvt >= 6) {
1125                 v = apic_read(APIC_LVTCMCI);
1126                 if (!(v & APIC_LVT_MASKED))
1127                         apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED);
1128         }
1129 #endif
1130 
1131         /*
1132          * Clean APIC state for other OSs:
1133          */
1134         apic_write(APIC_LVTT, APIC_LVT_MASKED);
1135         apic_write(APIC_LVT0, APIC_LVT_MASKED);
1136         apic_write(APIC_LVT1, APIC_LVT_MASKED);
1137         if (maxlvt >= 3)
1138                 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
1139         if (maxlvt >= 4)
1140                 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
1141 
1142         /* Integrated APIC (!82489DX) ? */
1143         if (lapic_is_integrated()) {
1144                 if (maxlvt > 3)
1145                         /* Clear ESR due to Pentium errata 3AP and 11AP */
1146                         apic_write(APIC_ESR, 0);
1147                 apic_read(APIC_ESR);
1148         }
1149 }
1150 
1151 /**
1152  * disable_local_APIC - clear and disable the local APIC
1153  */
1154 void disable_local_APIC(void)
1155 {
1156         unsigned int value;
1157 
1158         /* APIC hasn't been mapped yet */
1159         if (!x2apic_mode && !apic_phys)
1160                 return;
1161 
1162         clear_local_APIC();
1163 
1164         /*
1165          * Disable APIC (implies clearing of registers
1166          * for 82489DX!).
1167          */
1168         value = apic_read(APIC_SPIV);
1169         value &= ~APIC_SPIV_APIC_ENABLED;
1170         apic_write(APIC_SPIV, value);
1171 
1172 #ifdef CONFIG_X86_32
1173         /*
1174          * When LAPIC was disabled by the BIOS and enabled by the kernel,
1175          * restore the disabled state.
1176          */
1177         if (enabled_via_apicbase) {
1178                 unsigned int l, h;
1179 
1180                 rdmsr(MSR_IA32_APICBASE, l, h);
1181                 l &= ~MSR_IA32_APICBASE_ENABLE;
1182                 wrmsr(MSR_IA32_APICBASE, l, h);
1183         }
1184 #endif
1185 }
1186 
1187 /*
1188  * If Linux enabled the LAPIC against the BIOS default disable it down before
1189  * re-entering the BIOS on shutdown.  Otherwise the BIOS may get confused and
1190  * not power-off.  Additionally clear all LVT entries before disable_local_APIC
1191  * for the case where Linux didn't enable the LAPIC.
1192  */
1193 void lapic_shutdown(void)
1194 {
1195         unsigned long flags;
1196 
1197         if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config())
1198                 return;
1199 
1200         local_irq_save(flags);
1201 
1202 #ifdef CONFIG_X86_32
1203         if (!enabled_via_apicbase)
1204                 clear_local_APIC();
1205         else
1206 #endif
1207                 disable_local_APIC();
1208 
1209 
1210         local_irq_restore(flags);
1211 }
1212 
1213 /**
1214  * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1215  */
1216 void __init sync_Arb_IDs(void)
1217 {
1218         /*
1219          * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1220          * needed on AMD.
1221          */
1222         if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1223                 return;
1224 
1225         /*
1226          * Wait for idle.
1227          */
1228         apic_wait_icr_idle();
1229 
1230         apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
1231         apic_write(APIC_ICR, APIC_DEST_ALLINC |
1232                         APIC_INT_LEVELTRIG | APIC_DM_INIT);
1233 }
1234 
1235 enum apic_intr_mode_id apic_intr_mode;
1236 
1237 static int __init apic_intr_mode_select(void)
1238 {
1239         /* Check kernel option */
1240         if (disable_apic) {
1241                 pr_info("APIC disabled via kernel command line\n");
1242                 return APIC_PIC;
1243         }
1244 
1245         /* Check BIOS */
1246 #ifdef CONFIG_X86_64
1247         /* On 64-bit, the APIC must be integrated, Check local APIC only */
1248         if (!boot_cpu_has(X86_FEATURE_APIC)) {
1249                 disable_apic = 1;
1250                 pr_info("APIC disabled by BIOS\n");
1251                 return APIC_PIC;
1252         }
1253 #else
1254         /* On 32-bit, the APIC may be integrated APIC or 82489DX */
1255 
1256         /* Neither 82489DX nor integrated APIC ? */
1257         if (!boot_cpu_has(X86_FEATURE_APIC) && !smp_found_config) {
1258                 disable_apic = 1;
1259                 return APIC_PIC;
1260         }
1261 
1262         /* If the BIOS pretends there is an integrated APIC ? */
1263         if (!boot_cpu_has(X86_FEATURE_APIC) &&
1264                 APIC_INTEGRATED(boot_cpu_apic_version)) {
1265                 disable_apic = 1;
1266                 pr_err(FW_BUG "Local APIC %d not detected, force emulation\n",
1267                                        boot_cpu_physical_apicid);
1268                 return APIC_PIC;
1269         }
1270 #endif
1271 
1272         /* Check MP table or ACPI MADT configuration */
1273         if (!smp_found_config) {
1274                 disable_ioapic_support();
1275                 if (!acpi_lapic) {
1276                         pr_info("APIC: ACPI MADT or MP tables are not detected\n");
1277                         return APIC_VIRTUAL_WIRE_NO_CONFIG;
1278                 }
1279                 return APIC_VIRTUAL_WIRE;
1280         }
1281 
1282 #ifdef CONFIG_SMP
1283         /* If SMP should be disabled, then really disable it! */
1284         if (!setup_max_cpus) {
1285                 pr_info("APIC: SMP mode deactivated\n");
1286                 return APIC_SYMMETRIC_IO_NO_ROUTING;
1287         }
1288 
1289         if (read_apic_id() != boot_cpu_physical_apicid) {
1290                 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1291                      read_apic_id(), boot_cpu_physical_apicid);
1292                 /* Or can we switch back to PIC here? */
1293         }
1294 #endif
1295 
1296         return APIC_SYMMETRIC_IO;
1297 }
1298 
1299 /*
1300  * An initial setup of the virtual wire mode.
1301  */
1302 void __init init_bsp_APIC(void)
1303 {
1304         unsigned int value;
1305 
1306         /*
1307          * Don't do the setup now if we have a SMP BIOS as the
1308          * through-I/O-APIC virtual wire mode might be active.
1309          */
1310         if (smp_found_config || !boot_cpu_has(X86_FEATURE_APIC))
1311                 return;
1312 
1313         /*
1314          * Do not trust the local APIC being empty at bootup.
1315          */
1316         clear_local_APIC();
1317 
1318         /*
1319          * Enable APIC.
1320          */
1321         value = apic_read(APIC_SPIV);
1322         value &= ~APIC_VECTOR_MASK;
1323         value |= APIC_SPIV_APIC_ENABLED;
1324 
1325 #ifdef CONFIG_X86_32
1326         /* This bit is reserved on P4/Xeon and should be cleared */
1327         if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
1328             (boot_cpu_data.x86 == 15))
1329                 value &= ~APIC_SPIV_FOCUS_DISABLED;
1330         else
1331 #endif
1332                 value |= APIC_SPIV_FOCUS_DISABLED;
1333         value |= SPURIOUS_APIC_VECTOR;
1334         apic_write(APIC_SPIV, value);
1335 
1336         /*
1337          * Set up the virtual wire mode.
1338          */
1339         apic_write(APIC_LVT0, APIC_DM_EXTINT);
1340         value = APIC_DM_NMI;
1341         if (!lapic_is_integrated())             /* 82489DX */
1342                 value |= APIC_LVT_LEVEL_TRIGGER;
1343         if (apic_extnmi == APIC_EXTNMI_NONE)
1344                 value |= APIC_LVT_MASKED;
1345         apic_write(APIC_LVT1, value);
1346 }
1347 
1348 /* Init the interrupt delivery mode for the BSP */
1349 void __init apic_intr_mode_init(void)
1350 {
1351         bool upmode = IS_ENABLED(CONFIG_UP_LATE_INIT);
1352 
1353         apic_intr_mode = apic_intr_mode_select();
1354 
1355         switch (apic_intr_mode) {
1356         case APIC_PIC:
1357                 pr_info("APIC: Keep in PIC mode(8259)\n");
1358                 return;
1359         case APIC_VIRTUAL_WIRE:
1360                 pr_info("APIC: Switch to virtual wire mode setup\n");
1361                 default_setup_apic_routing();
1362                 break;
1363         case APIC_VIRTUAL_WIRE_NO_CONFIG:
1364                 pr_info("APIC: Switch to virtual wire mode setup with no configuration\n");
1365                 upmode = true;
1366                 default_setup_apic_routing();
1367                 break;
1368         case APIC_SYMMETRIC_IO:
1369                 pr_info("APIC: Switch to symmetric I/O mode setup\n");
1370                 default_setup_apic_routing();
1371                 break;
1372         case APIC_SYMMETRIC_IO_NO_ROUTING:
1373                 pr_info("APIC: Switch to symmetric I/O mode setup in no SMP routine\n");
1374                 break;
1375         }
1376 
1377         apic_bsp_setup(upmode);
1378 }
1379 
1380 static void lapic_setup_esr(void)
1381 {
1382         unsigned int oldvalue, value, maxlvt;
1383 
1384         if (!lapic_is_integrated()) {
1385                 pr_info("No ESR for 82489DX.\n");
1386                 return;
1387         }
1388 
1389         if (apic->disable_esr) {
1390                 /*
1391                  * Something untraceable is creating bad interrupts on
1392                  * secondary quads ... for the moment, just leave the
1393                  * ESR disabled - we can't do anything useful with the
1394                  * errors anyway - mbligh
1395                  */
1396                 pr_info("Leaving ESR disabled.\n");
1397                 return;
1398         }
1399 
1400         maxlvt = lapic_get_maxlvt();
1401         if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
1402                 apic_write(APIC_ESR, 0);
1403         oldvalue = apic_read(APIC_ESR);
1404 
1405         /* enables sending errors */
1406         value = ERROR_APIC_VECTOR;
1407         apic_write(APIC_LVTERR, value);
1408 
1409         /*
1410          * spec says clear errors after enabling vector.
1411          */
1412         if (maxlvt > 3)
1413                 apic_write(APIC_ESR, 0);
1414         value = apic_read(APIC_ESR);
1415         if (value != oldvalue)
1416                 apic_printk(APIC_VERBOSE, "ESR value before enabling "
1417                         "vector: 0x%08x  after: 0x%08x\n",
1418                         oldvalue, value);
1419 }
1420 
1421 static void apic_pending_intr_clear(void)
1422 {
1423         long long max_loops = cpu_khz ? cpu_khz : 1000000;
1424         unsigned long long tsc = 0, ntsc;
1425         unsigned int queued;
1426         unsigned long value;
1427         int i, j, acked = 0;
1428 
1429         if (boot_cpu_has(X86_FEATURE_TSC))
1430                 tsc = rdtsc();
1431         /*
1432          * After a crash, we no longer service the interrupts and a pending
1433          * interrupt from previous kernel might still have ISR bit set.
1434          *
1435          * Most probably by now CPU has serviced that pending interrupt and
1436          * it might not have done the ack_APIC_irq() because it thought,
1437          * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1438          * does not clear the ISR bit and cpu thinks it has already serivced
1439          * the interrupt. Hence a vector might get locked. It was noticed
1440          * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1441          */
1442         do {
1443                 queued = 0;
1444                 for (i = APIC_ISR_NR - 1; i >= 0; i--)
1445                         queued |= apic_read(APIC_IRR + i*0x10);
1446 
1447                 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
1448                         value = apic_read(APIC_ISR + i*0x10);
1449                         for_each_set_bit(j, &value, 32) {
1450                                 ack_APIC_irq();
1451                                 acked++;
1452                         }
1453                 }
1454                 if (acked > 256) {
1455                         pr_err("LAPIC pending interrupts after %d EOI\n", acked);
1456                         break;
1457                 }
1458                 if (queued) {
1459                         if (boot_cpu_has(X86_FEATURE_TSC) && cpu_khz) {
1460                                 ntsc = rdtsc();
1461                                 max_loops = (long long)cpu_khz << 10;
1462                                 max_loops -= ntsc - tsc;
1463                         } else {
1464                                 max_loops--;
1465                         }
1466                 }
1467         } while (queued && max_loops > 0);
1468         WARN_ON(max_loops <= 0);
1469 }
1470 
1471 /**
1472  * setup_local_APIC - setup the local APIC
1473  *
1474  * Used to setup local APIC while initializing BSP or bringing up APs.
1475  * Always called with preemption disabled.
1476  */
1477 static void setup_local_APIC(void)
1478 {
1479         int cpu = smp_processor_id();
1480         unsigned int value;
1481 #ifdef CONFIG_X86_32
1482         int logical_apicid, ldr_apicid;
1483 #endif
1484 
1485 
1486         if (disable_apic) {
1487                 disable_ioapic_support();
1488                 return;
1489         }
1490 
1491 #ifdef CONFIG_X86_32
1492         /* Pound the ESR really hard over the head with a big hammer - mbligh */
1493         if (lapic_is_integrated() && apic->disable_esr) {
1494                 apic_write(APIC_ESR, 0);
1495                 apic_write(APIC_ESR, 0);
1496                 apic_write(APIC_ESR, 0);
1497                 apic_write(APIC_ESR, 0);
1498         }
1499 #endif
1500         perf_events_lapic_init();
1501 
1502         /*
1503          * Double-check whether this APIC is really registered.
1504          * This is meaningless in clustered apic mode, so we skip it.
1505          */
1506         BUG_ON(!apic->apic_id_registered());
1507 
1508         /*
1509          * Intel recommends to set DFR, LDR and TPR before enabling
1510          * an APIC.  See e.g. "AP-388 82489DX User's Manual" (Intel
1511          * document number 292116).  So here it goes...
1512          */
1513         apic->init_apic_ldr();
1514 
1515 #ifdef CONFIG_X86_32
1516         /*
1517          * APIC LDR is initialized.  If logical_apicid mapping was
1518          * initialized during get_smp_config(), make sure it matches the
1519          * actual value.
1520          */
1521         logical_apicid = early_per_cpu(x86_cpu_to_logical_apicid, cpu);
1522         ldr_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
1523         WARN_ON(logical_apicid != BAD_APICID && logical_apicid != ldr_apicid);
1524         /* always use the value from LDR */
1525         early_per_cpu(x86_cpu_to_logical_apicid, cpu) = ldr_apicid;
1526 #endif
1527 
1528         /*
1529          * Set Task Priority to 'accept all'. We never change this
1530          * later on.
1531          */
1532         value = apic_read(APIC_TASKPRI);
1533         value &= ~APIC_TPRI_MASK;
1534         apic_write(APIC_TASKPRI, value);
1535 
1536         apic_pending_intr_clear();
1537 
1538         /*
1539          * Now that we are all set up, enable the APIC
1540          */
1541         value = apic_read(APIC_SPIV);
1542         value &= ~APIC_VECTOR_MASK;
1543         /*
1544          * Enable APIC
1545          */
1546         value |= APIC_SPIV_APIC_ENABLED;
1547 
1548 #ifdef CONFIG_X86_32
1549         /*
1550          * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1551          * certain networking cards. If high frequency interrupts are
1552          * happening on a particular IOAPIC pin, plus the IOAPIC routing
1553          * entry is masked/unmasked at a high rate as well then sooner or
1554          * later IOAPIC line gets 'stuck', no more interrupts are received
1555          * from the device. If focus CPU is disabled then the hang goes
1556          * away, oh well :-(
1557          *
1558          * [ This bug can be reproduced easily with a level-triggered
1559          *   PCI Ne2000 networking cards and PII/PIII processors, dual
1560          *   BX chipset. ]
1561          */
1562         /*
1563          * Actually disabling the focus CPU check just makes the hang less
1564          * frequent as it makes the interrupt distributon model be more
1565          * like LRU than MRU (the short-term load is more even across CPUs).
1566          */
1567 
1568         /*
1569          * - enable focus processor (bit==0)
1570          * - 64bit mode always use processor focus
1571          *   so no need to set it
1572          */
1573         value &= ~APIC_SPIV_FOCUS_DISABLED;
1574 #endif
1575 
1576         /*
1577          * Set spurious IRQ vector
1578          */
1579         value |= SPURIOUS_APIC_VECTOR;
1580         apic_write(APIC_SPIV, value);
1581 
1582         /*
1583          * Set up LVT0, LVT1:
1584          *
1585          * set up through-local-APIC on the boot CPU's LINT0. This is not
1586          * strictly necessary in pure symmetric-IO mode, but sometimes
1587          * we delegate interrupts to the 8259A.
1588          */
1589         /*
1590          * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1591          */
1592         value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1593         if (!cpu && (pic_mode || !value || skip_ioapic_setup)) {
1594                 value = APIC_DM_EXTINT;
1595                 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu);
1596         } else {
1597                 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1598                 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu);
1599         }
1600         apic_write(APIC_LVT0, value);
1601 
1602         /*
1603          * Only the BSP sees the LINT1 NMI signal by default. This can be
1604          * modified by apic_extnmi= boot option.
1605          */
1606         if ((!cpu && apic_extnmi != APIC_EXTNMI_NONE) ||
1607             apic_extnmi == APIC_EXTNMI_ALL)
1608                 value = APIC_DM_NMI;
1609         else
1610                 value = APIC_DM_NMI | APIC_LVT_MASKED;
1611 
1612         /* Is 82489DX ? */
1613         if (!lapic_is_integrated())
1614                 value |= APIC_LVT_LEVEL_TRIGGER;
1615         apic_write(APIC_LVT1, value);
1616 
1617 #ifdef CONFIG_X86_MCE_INTEL
1618         /* Recheck CMCI information after local APIC is up on CPU #0 */
1619         if (!cpu)
1620                 cmci_recheck();
1621 #endif
1622 }
1623 
1624 static void end_local_APIC_setup(void)
1625 {
1626         lapic_setup_esr();
1627 
1628 #ifdef CONFIG_X86_32
1629         {
1630                 unsigned int value;
1631                 /* Disable the local apic timer */
1632                 value = apic_read(APIC_LVTT);
1633                 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1634                 apic_write(APIC_LVTT, value);
1635         }
1636 #endif
1637 
1638         apic_pm_activate();
1639 }
1640 
1641 /*
1642  * APIC setup function for application processors. Called from smpboot.c
1643  */
1644 void apic_ap_setup(void)
1645 {
1646         setup_local_APIC();
1647         end_local_APIC_setup();
1648 }
1649 
1650 #ifdef CONFIG_X86_X2APIC
1651 int x2apic_mode;
1652 
1653 enum {
1654         X2APIC_OFF,
1655         X2APIC_ON,
1656         X2APIC_DISABLED,
1657 };
1658 static int x2apic_state;
1659 
1660 static void __x2apic_disable(void)
1661 {
1662         u64 msr;
1663 
1664         if (!boot_cpu_has(X86_FEATURE_APIC))
1665                 return;
1666 
1667         rdmsrl(MSR_IA32_APICBASE, msr);
1668         if (!(msr & X2APIC_ENABLE))
1669                 return;
1670         /* Disable xapic and x2apic first and then reenable xapic mode */
1671         wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE));
1672         wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE);
1673         printk_once(KERN_INFO "x2apic disabled\n");
1674 }
1675 
1676 static void __x2apic_enable(void)
1677 {
1678         u64 msr;
1679 
1680         rdmsrl(MSR_IA32_APICBASE, msr);
1681         if (msr & X2APIC_ENABLE)
1682                 return;
1683         wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE);
1684         printk_once(KERN_INFO "x2apic enabled\n");
1685 }
1686 
1687 static int __init setup_nox2apic(char *str)
1688 {
1689         if (x2apic_enabled()) {
1690                 int apicid = native_apic_msr_read(APIC_ID);
1691 
1692                 if (apicid >= 255) {
1693                         pr_warning("Apicid: %08x, cannot enforce nox2apic\n",
1694                                    apicid);
1695                         return 0;
1696                 }
1697                 pr_warning("x2apic already enabled.\n");
1698                 __x2apic_disable();
1699         }
1700         setup_clear_cpu_cap(X86_FEATURE_X2APIC);
1701         x2apic_state = X2APIC_DISABLED;
1702         x2apic_mode = 0;
1703         return 0;
1704 }
1705 early_param("nox2apic", setup_nox2apic);
1706 
1707 /* Called from cpu_init() to enable x2apic on (secondary) cpus */
1708 void x2apic_setup(void)
1709 {
1710         /*
1711          * If x2apic is not in ON state, disable it if already enabled
1712          * from BIOS.
1713          */
1714         if (x2apic_state != X2APIC_ON) {
1715                 __x2apic_disable();
1716                 return;
1717         }
1718         __x2apic_enable();
1719 }
1720 
1721 static __init void x2apic_disable(void)
1722 {
1723         u32 x2apic_id, state = x2apic_state;
1724 
1725         x2apic_mode = 0;
1726         x2apic_state = X2APIC_DISABLED;
1727 
1728         if (state != X2APIC_ON)
1729                 return;
1730 
1731         x2apic_id = read_apic_id();
1732         if (x2apic_id >= 255)
1733                 panic("Cannot disable x2apic, id: %08x\n", x2apic_id);
1734 
1735         __x2apic_disable();
1736         register_lapic_address(mp_lapic_addr);
1737 }
1738 
1739 static __init void x2apic_enable(void)
1740 {
1741         if (x2apic_state != X2APIC_OFF)
1742                 return;
1743 
1744         x2apic_mode = 1;
1745         x2apic_state = X2APIC_ON;
1746         __x2apic_enable();
1747 }
1748 
1749 static __init void try_to_enable_x2apic(int remap_mode)
1750 {
1751         if (x2apic_state == X2APIC_DISABLED)
1752                 return;
1753 
1754         if (remap_mode != IRQ_REMAP_X2APIC_MODE) {
1755                 /* IR is required if there is APIC ID > 255 even when running
1756                  * under KVM
1757                  */
1758                 if (max_physical_apicid > 255 ||
1759                     !x86_init.hyper.x2apic_available()) {
1760                         pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n");
1761                         x2apic_disable();
1762                         return;
1763                 }
1764 
1765                 /*
1766                  * without IR all CPUs can be addressed by IOAPIC/MSI
1767                  * only in physical mode
1768                  */
1769                 x2apic_phys = 1;
1770         }
1771         x2apic_enable();
1772 }
1773 
1774 void __init check_x2apic(void)
1775 {
1776         if (x2apic_enabled()) {
1777                 pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n");
1778                 x2apic_mode = 1;
1779                 x2apic_state = X2APIC_ON;
1780         } else if (!boot_cpu_has(X86_FEATURE_X2APIC)) {
1781                 x2apic_state = X2APIC_DISABLED;
1782         }
1783 }
1784 #else /* CONFIG_X86_X2APIC */
1785 static int __init validate_x2apic(void)
1786 {
1787         if (!apic_is_x2apic_enabled())
1788                 return 0;
1789         /*
1790          * Checkme: Can we simply turn off x2apic here instead of panic?
1791          */
1792         panic("BIOS has enabled x2apic but kernel doesn't support x2apic, please disable x2apic in BIOS.\n");
1793 }
1794 early_initcall(validate_x2apic);
1795 
1796 static inline void try_to_enable_x2apic(int remap_mode) { }
1797 static inline void __x2apic_enable(void) { }
1798 #endif /* !CONFIG_X86_X2APIC */
1799 
1800 void __init enable_IR_x2apic(void)
1801 {
1802         unsigned long flags;
1803         int ret, ir_stat;
1804 
1805         if (skip_ioapic_setup) {
1806                 pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n");
1807                 return;
1808         }
1809 
1810         ir_stat = irq_remapping_prepare();
1811         if (ir_stat < 0 && !x2apic_supported())
1812                 return;
1813 
1814         ret = save_ioapic_entries();
1815         if (ret) {
1816                 pr_info("Saving IO-APIC state failed: %d\n", ret);
1817                 return;
1818         }
1819 
1820         local_irq_save(flags);
1821         legacy_pic->mask_all();
1822         mask_ioapic_entries();
1823 
1824         /* If irq_remapping_prepare() succeeded, try to enable it */
1825         if (ir_stat >= 0)
1826                 ir_stat = irq_remapping_enable();
1827         /* ir_stat contains the remap mode or an error code */
1828         try_to_enable_x2apic(ir_stat);
1829 
1830         if (ir_stat < 0)
1831                 restore_ioapic_entries();
1832         legacy_pic->restore_mask();
1833         local_irq_restore(flags);
1834 }
1835 
1836 #ifdef CONFIG_X86_64
1837 /*
1838  * Detect and enable local APICs on non-SMP boards.
1839  * Original code written by Keir Fraser.
1840  * On AMD64 we trust the BIOS - if it says no APIC it is likely
1841  * not correctly set up (usually the APIC timer won't work etc.)
1842  */
1843 static int __init detect_init_APIC(void)
1844 {
1845         if (!boot_cpu_has(X86_FEATURE_APIC)) {
1846                 pr_info("No local APIC present\n");
1847                 return -1;
1848         }
1849 
1850         mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1851         return 0;
1852 }
1853 #else
1854 
1855 static int __init apic_verify(void)
1856 {
1857         u32 features, h, l;
1858 
1859         /*
1860          * The APIC feature bit should now be enabled
1861          * in `cpuid'
1862          */
1863         features = cpuid_edx(1);
1864         if (!(features & (1 << X86_FEATURE_APIC))) {
1865                 pr_warning("Could not enable APIC!\n");
1866                 return -1;
1867         }
1868         set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1869         mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1870 
1871         /* The BIOS may have set up the APIC at some other address */
1872         if (boot_cpu_data.x86 >= 6) {
1873                 rdmsr(MSR_IA32_APICBASE, l, h);
1874                 if (l & MSR_IA32_APICBASE_ENABLE)
1875                         mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1876         }
1877 
1878         pr_info("Found and enabled local APIC!\n");
1879         return 0;
1880 }
1881 
1882 int __init apic_force_enable(unsigned long addr)
1883 {
1884         u32 h, l;
1885 
1886         if (disable_apic)
1887                 return -1;
1888 
1889         /*
1890          * Some BIOSes disable the local APIC in the APIC_BASE
1891          * MSR. This can only be done in software for Intel P6 or later
1892          * and AMD K7 (Model > 1) or later.
1893          */
1894         if (boot_cpu_data.x86 >= 6) {
1895                 rdmsr(MSR_IA32_APICBASE, l, h);
1896                 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
1897                         pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1898                         l &= ~MSR_IA32_APICBASE_BASE;
1899                         l |= MSR_IA32_APICBASE_ENABLE | addr;
1900                         wrmsr(MSR_IA32_APICBASE, l, h);
1901                         enabled_via_apicbase = 1;
1902                 }
1903         }
1904         return apic_verify();
1905 }
1906 
1907 /*
1908  * Detect and initialize APIC
1909  */
1910 static int __init detect_init_APIC(void)
1911 {
1912         /* Disabled by kernel option? */
1913         if (disable_apic)
1914                 return -1;
1915 
1916         switch (boot_cpu_data.x86_vendor) {
1917         case X86_VENDOR_AMD:
1918                 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1919                     (boot_cpu_data.x86 >= 15))
1920                         break;
1921                 goto no_apic;
1922         case X86_VENDOR_HYGON:
1923                 break;
1924         case X86_VENDOR_INTEL:
1925                 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
1926                     (boot_cpu_data.x86 == 5 && boot_cpu_has(X86_FEATURE_APIC)))
1927                         break;
1928                 goto no_apic;
1929         default:
1930                 goto no_apic;
1931         }
1932 
1933         if (!boot_cpu_has(X86_FEATURE_APIC)) {
1934                 /*
1935                  * Over-ride BIOS and try to enable the local APIC only if
1936                  * "lapic" specified.
1937                  */
1938                 if (!force_enable_local_apic) {
1939                         pr_info("Local APIC disabled by BIOS -- "
1940                                 "you can enable it with \"lapic\"\n");
1941                         return -1;
1942                 }
1943                 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE))
1944                         return -1;
1945         } else {
1946                 if (apic_verify())
1947                         return -1;
1948         }
1949 
1950         apic_pm_activate();
1951 
1952         return 0;
1953 
1954 no_apic:
1955         pr_info("No local APIC present or hardware disabled\n");
1956         return -1;
1957 }
1958 #endif
1959 
1960 /**
1961  * init_apic_mappings - initialize APIC mappings
1962  */
1963 void __init init_apic_mappings(void)
1964 {
1965         unsigned int new_apicid;
1966 
1967         apic_check_deadline_errata();
1968 
1969         if (x2apic_mode) {
1970                 boot_cpu_physical_apicid = read_apic_id();
1971                 return;
1972         }
1973 
1974         /* If no local APIC can be found return early */
1975         if (!smp_found_config && detect_init_APIC()) {
1976                 /* lets NOP'ify apic operations */
1977                 pr_info("APIC: disable apic facility\n");
1978                 apic_disable();
1979         } else {
1980                 apic_phys = mp_lapic_addr;
1981 
1982                 /*
1983                  * If the system has ACPI MADT tables or MP info, the LAPIC
1984                  * address is already registered.
1985                  */
1986                 if (!acpi_lapic && !smp_found_config)
1987                         register_lapic_address(apic_phys);
1988         }
1989 
1990         /*
1991          * Fetch the APIC ID of the BSP in case we have a
1992          * default configuration (or the MP table is broken).
1993          */
1994         new_apicid = read_apic_id();
1995         if (boot_cpu_physical_apicid != new_apicid) {
1996                 boot_cpu_physical_apicid = new_apicid;
1997                 /*
1998                  * yeah -- we lie about apic_version
1999                  * in case if apic was disabled via boot option
2000                  * but it's not a problem for SMP compiled kernel
2001                  * since apic_intr_mode_select is prepared for such
2002                  * a case and disable smp mode
2003                  */
2004                 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR));
2005         }
2006 }
2007 
2008 void __init register_lapic_address(unsigned long address)
2009 {
2010         mp_lapic_addr = address;
2011 
2012         if (!x2apic_mode) {
2013                 set_fixmap_nocache(FIX_APIC_BASE, address);
2014                 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
2015                             APIC_BASE, address);
2016         }
2017         if (boot_cpu_physical_apicid == -1U) {
2018                 boot_cpu_physical_apicid  = read_apic_id();
2019                 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR));
2020         }
2021 }
2022 
2023 /*
2024  * Local APIC interrupts
2025  */
2026 
2027 /*
2028  * This interrupt should _never_ happen with our APIC/SMP architecture
2029  */
2030 __visible void __irq_entry smp_spurious_interrupt(struct pt_regs *regs)
2031 {
2032         u8 vector = ~regs->orig_ax;
2033         u32 v;
2034 
2035         entering_irq();
2036         trace_spurious_apic_entry(vector);
2037 
2038         inc_irq_stat(irq_spurious_count);
2039 
2040         /*
2041          * If this is a spurious interrupt then do not acknowledge
2042          */
2043         if (vector == SPURIOUS_APIC_VECTOR) {
2044                 /* See SDM vol 3 */
2045                 pr_info("Spurious APIC interrupt (vector 0xFF) on CPU#%d, should never happen.\n",
2046                         smp_processor_id());
2047                 goto out;
2048         }
2049 
2050         /*
2051          * If it is a vectored one, verify it's set in the ISR. If set,
2052          * acknowledge it.
2053          */
2054         v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1));
2055         if (v & (1 << (vector & 0x1f))) {
2056                 pr_info("Spurious interrupt (vector 0x%02x) on CPU#%d. Acked\n",
2057                         vector, smp_processor_id());
2058                 ack_APIC_irq();
2059         } else {
2060                 pr_info("Spurious interrupt (vector 0x%02x) on CPU#%d. Not pending!\n",
2061                         vector, smp_processor_id());
2062         }
2063 out:
2064         trace_spurious_apic_exit(vector);
2065         exiting_irq();
2066 }
2067 
2068 /*
2069  * This interrupt should never happen with our APIC/SMP architecture
2070  */
2071 __visible void __irq_entry smp_error_interrupt(struct pt_regs *regs)
2072 {
2073         static const char * const error_interrupt_reason[] = {
2074                 "Send CS error",                /* APIC Error Bit 0 */
2075                 "Receive CS error",             /* APIC Error Bit 1 */
2076                 "Send accept error",            /* APIC Error Bit 2 */
2077                 "Receive accept error",         /* APIC Error Bit 3 */
2078                 "Redirectable IPI",             /* APIC Error Bit 4 */
2079                 "Send illegal vector",          /* APIC Error Bit 5 */
2080                 "Received illegal vector",      /* APIC Error Bit 6 */
2081                 "Illegal register address",     /* APIC Error Bit 7 */
2082         };
2083         u32 v, i = 0;
2084 
2085         entering_irq();
2086         trace_error_apic_entry(ERROR_APIC_VECTOR);
2087 
2088         /* First tickle the hardware, only then report what went on. -- REW */
2089         if (lapic_get_maxlvt() > 3)     /* Due to the Pentium erratum 3AP. */
2090                 apic_write(APIC_ESR, 0);
2091         v = apic_read(APIC_ESR);
2092         ack_APIC_irq();
2093         atomic_inc(&irq_err_count);
2094 
2095         apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x",
2096                     smp_processor_id(), v);
2097 
2098         v &= 0xff;
2099         while (v) {
2100                 if (v & 0x1)
2101                         apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]);
2102                 i++;
2103                 v >>= 1;
2104         }
2105 
2106         apic_printk(APIC_DEBUG, KERN_CONT "\n");
2107 
2108         trace_error_apic_exit(ERROR_APIC_VECTOR);
2109         exiting_irq();
2110 }
2111 
2112 /**
2113  * connect_bsp_APIC - attach the APIC to the interrupt system
2114  */
2115 static void __init connect_bsp_APIC(void)
2116 {
2117 #ifdef CONFIG_X86_32
2118         if (pic_mode) {
2119                 /*
2120                  * Do not trust the local APIC being empty at bootup.
2121                  */
2122                 clear_local_APIC();
2123                 /*
2124                  * PIC mode, enable APIC mode in the IMCR, i.e.  connect BSP's
2125                  * local APIC to INT and NMI lines.
2126                  */
2127                 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
2128                                 "enabling APIC mode.\n");
2129                 imcr_pic_to_apic();
2130         }
2131 #endif
2132 }
2133 
2134 /**
2135  * disconnect_bsp_APIC - detach the APIC from the interrupt system
2136  * @virt_wire_setup:    indicates, whether virtual wire mode is selected
2137  *
2138  * Virtual wire mode is necessary to deliver legacy interrupts even when the
2139  * APIC is disabled.
2140  */
2141 void disconnect_bsp_APIC(int virt_wire_setup)
2142 {
2143         unsigned int value;
2144 
2145 #ifdef CONFIG_X86_32
2146         if (pic_mode) {
2147                 /*
2148                  * Put the board back into PIC mode (has an effect only on
2149                  * certain older boards).  Note that APIC interrupts, including
2150                  * IPIs, won't work beyond this point!  The only exception are
2151                  * INIT IPIs.
2152                  */
2153                 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
2154                                 "entering PIC mode.\n");
2155                 imcr_apic_to_pic();
2156                 return;
2157         }
2158 #endif
2159 
2160         /* Go back to Virtual Wire compatibility mode */
2161 
2162         /* For the spurious interrupt use vector F, and enable it */
2163         value = apic_read(APIC_SPIV);
2164         value &= ~APIC_VECTOR_MASK;
2165         value |= APIC_SPIV_APIC_ENABLED;
2166         value |= 0xf;
2167         apic_write(APIC_SPIV, value);
2168 
2169         if (!virt_wire_setup) {
2170                 /*
2171                  * For LVT0 make it edge triggered, active high,
2172                  * external and enabled
2173                  */
2174                 value = apic_read(APIC_LVT0);
2175                 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
2176                         APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
2177                         APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
2178                 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
2179                 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
2180                 apic_write(APIC_LVT0, value);
2181         } else {
2182                 /* Disable LVT0 */
2183                 apic_write(APIC_LVT0, APIC_LVT_MASKED);
2184         }
2185 
2186         /*
2187          * For LVT1 make it edge triggered, active high,
2188          * nmi and enabled
2189          */
2190         value = apic_read(APIC_LVT1);
2191         value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
2192                         APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
2193                         APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
2194         value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
2195         value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
2196         apic_write(APIC_LVT1, value);
2197 }
2198 
2199 /*
2200  * The number of allocated logical CPU IDs. Since logical CPU IDs are allocated
2201  * contiguously, it equals to current allocated max logical CPU ID plus 1.
2202  * All allocated CPU IDs should be in the [0, nr_logical_cpuids) range,
2203  * so the maximum of nr_logical_cpuids is nr_cpu_ids.
2204  *
2205  * NOTE: Reserve 0 for BSP.
2206  */
2207 static int nr_logical_cpuids = 1;
2208 
2209 /*
2210  * Used to store mapping between logical CPU IDs and APIC IDs.
2211  */
2212 static int cpuid_to_apicid[] = {
2213         [0 ... NR_CPUS - 1] = -1,
2214 };
2215 
2216 #ifdef CONFIG_SMP
2217 /**
2218  * apic_id_is_primary_thread - Check whether APIC ID belongs to a primary thread
2219  * @id: APIC ID to check
2220  */
2221 bool apic_id_is_primary_thread(unsigned int apicid)
2222 {
2223         u32 mask;
2224 
2225         if (smp_num_siblings == 1)
2226                 return true;
2227         /* Isolate the SMT bit(s) in the APICID and check for 0 */
2228         mask = (1U << (fls(smp_num_siblings) - 1)) - 1;
2229         return !(apicid & mask);
2230 }
2231 #endif
2232 
2233 /*
2234  * Should use this API to allocate logical CPU IDs to keep nr_logical_cpuids
2235  * and cpuid_to_apicid[] synchronized.
2236  */
2237 static int allocate_logical_cpuid(int apicid)
2238 {
2239         int i;
2240 
2241         /*
2242          * cpuid <-> apicid mapping is persistent, so when a cpu is up,
2243          * check if the kernel has allocated a cpuid for it.
2244          */
2245         for (i = 0; i < nr_logical_cpuids; i++) {
2246                 if (cpuid_to_apicid[i] == apicid)
2247                         return i;
2248         }
2249 
2250         /* Allocate a new cpuid. */
2251         if (nr_logical_cpuids >= nr_cpu_ids) {
2252                 WARN_ONCE(1, "APIC: NR_CPUS/possible_cpus limit of %u reached. "
2253                              "Processor %d/0x%x and the rest are ignored.\n",
2254                              nr_cpu_ids, nr_logical_cpuids, apicid);
2255                 return -EINVAL;
2256         }
2257 
2258         cpuid_to_apicid[nr_logical_cpuids] = apicid;
2259         return nr_logical_cpuids++;
2260 }
2261 
2262 int generic_processor_info(int apicid, int version)
2263 {
2264         int cpu, max = nr_cpu_ids;
2265         bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid,
2266                                 phys_cpu_present_map);
2267 
2268         /*
2269          * boot_cpu_physical_apicid is designed to have the apicid
2270          * returned by read_apic_id(), i.e, the apicid of the
2271          * currently booting-up processor. However, on some platforms,
2272          * it is temporarily modified by the apicid reported as BSP
2273          * through MP table. Concretely:
2274          *
2275          * - arch/x86/kernel/mpparse.c: MP_processor_info()
2276          * - arch/x86/mm/amdtopology.c: amd_numa_init()
2277          *
2278          * This function is executed with the modified
2279          * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel
2280          * parameter doesn't work to disable APs on kdump 2nd kernel.
2281          *
2282          * Since fixing handling of boot_cpu_physical_apicid requires
2283          * another discussion and tests on each platform, we leave it
2284          * for now and here we use read_apic_id() directly in this
2285          * function, generic_processor_info().
2286          */
2287         if (disabled_cpu_apicid != BAD_APICID &&
2288             disabled_cpu_apicid != read_apic_id() &&
2289             disabled_cpu_apicid == apicid) {
2290                 int thiscpu = num_processors + disabled_cpus;
2291 
2292                 pr_warning("APIC: Disabling requested cpu."
2293                            " Processor %d/0x%x ignored.\n",
2294                            thiscpu, apicid);
2295 
2296                 disabled_cpus++;
2297                 return -ENODEV;
2298         }
2299 
2300         /*
2301          * If boot cpu has not been detected yet, then only allow upto
2302          * nr_cpu_ids - 1 processors and keep one slot free for boot cpu
2303          */
2304         if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 &&
2305             apicid != boot_cpu_physical_apicid) {
2306                 int thiscpu = max + disabled_cpus - 1;
2307 
2308                 pr_warning(
2309                         "APIC: NR_CPUS/possible_cpus limit of %i almost"
2310                         " reached. Keeping one slot for boot cpu."
2311                         "  Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
2312 
2313                 disabled_cpus++;
2314                 return -ENODEV;
2315         }
2316 
2317         if (num_processors >= nr_cpu_ids) {
2318                 int thiscpu = max + disabled_cpus;
2319 
2320                 pr_warning("APIC: NR_CPUS/possible_cpus limit of %i "
2321                            "reached. Processor %d/0x%x ignored.\n",
2322                            max, thiscpu, apicid);
2323 
2324                 disabled_cpus++;
2325                 return -EINVAL;
2326         }
2327 
2328         if (apicid == boot_cpu_physical_apicid) {
2329                 /*
2330                  * x86_bios_cpu_apicid is required to have processors listed
2331                  * in same order as logical cpu numbers. Hence the first
2332                  * entry is BSP, and so on.
2333                  * boot_cpu_init() already hold bit 0 in cpu_present_mask
2334                  * for BSP.
2335                  */
2336                 cpu = 0;
2337 
2338                 /* Logical cpuid 0 is reserved for BSP. */
2339                 cpuid_to_apicid[0] = apicid;
2340         } else {
2341                 cpu = allocate_logical_cpuid(apicid);
2342                 if (cpu < 0) {
2343                         disabled_cpus++;
2344                         return -EINVAL;
2345                 }
2346         }
2347 
2348         /*
2349          * Validate version
2350          */
2351         if (version == 0x0) {
2352                 pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n",
2353                            cpu, apicid);
2354                 version = 0x10;
2355         }
2356 
2357         if (version != boot_cpu_apic_version) {
2358                 pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n",
2359                         boot_cpu_apic_version, cpu, version);
2360         }
2361 
2362         if (apicid > max_physical_apicid)
2363                 max_physical_apicid = apicid;
2364 
2365 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
2366         early_per_cpu(x86_cpu_to_apicid, cpu) = apicid;
2367         early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
2368 #endif
2369 #ifdef CONFIG_X86_32
2370         early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
2371                 apic->x86_32_early_logical_apicid(cpu);
2372 #endif
2373         set_cpu_possible(cpu, true);
2374         physid_set(apicid, phys_cpu_present_map);
2375         set_cpu_present(cpu, true);
2376         num_processors++;
2377 
2378         return cpu;
2379 }
2380 
2381 int hard_smp_processor_id(void)
2382 {
2383         return read_apic_id();
2384 }
2385 
2386 /*
2387  * Override the generic EOI implementation with an optimized version.
2388  * Only called during early boot when only one CPU is active and with
2389  * interrupts disabled, so we know this does not race with actual APIC driver
2390  * use.
2391  */
2392 void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v))
2393 {
2394         struct apic **drv;
2395 
2396         for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) {
2397                 /* Should happen once for each apic */
2398                 WARN_ON((*drv)->eoi_write == eoi_write);
2399                 (*drv)->native_eoi_write = (*drv)->eoi_write;
2400                 (*drv)->eoi_write = eoi_write;
2401         }
2402 }
2403 
2404 static void __init apic_bsp_up_setup(void)
2405 {
2406 #ifdef CONFIG_X86_64
2407         apic_write(APIC_ID, apic->set_apic_id(boot_cpu_physical_apicid));
2408 #else
2409         /*
2410          * Hack: In case of kdump, after a crash, kernel might be booting
2411          * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
2412          * might be zero if read from MP tables. Get it from LAPIC.
2413          */
2414 # ifdef CONFIG_CRASH_DUMP
2415         boot_cpu_physical_apicid = read_apic_id();
2416 # endif
2417 #endif
2418         physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
2419 }
2420 
2421 /**
2422  * apic_bsp_setup - Setup function for local apic and io-apic
2423  * @upmode:             Force UP mode (for APIC_init_uniprocessor)
2424  *
2425  * Returns:
2426  * apic_id of BSP APIC
2427  */
2428 void __init apic_bsp_setup(bool upmode)
2429 {
2430         connect_bsp_APIC();
2431         if (upmode)
2432                 apic_bsp_up_setup();
2433         setup_local_APIC();
2434 
2435         enable_IO_APIC();
2436         end_local_APIC_setup();
2437         irq_remap_enable_fault_handling();
2438         setup_IO_APIC();
2439 }
2440 
2441 #ifdef CONFIG_UP_LATE_INIT
2442 void __init up_late_init(void)
2443 {
2444         if (apic_intr_mode == APIC_PIC)
2445                 return;
2446 
2447         /* Setup local timer */
2448         x86_init.timers.setup_percpu_clockev();
2449 }
2450 #endif
2451 
2452 /*
2453  * Power management
2454  */
2455 #ifdef CONFIG_PM
2456 
2457 static struct {
2458         /*
2459          * 'active' is true if the local APIC was enabled by us and
2460          * not the BIOS; this signifies that we are also responsible
2461          * for disabling it before entering apm/acpi suspend
2462          */
2463         int active;
2464         /* r/w apic fields */
2465         unsigned int apic_id;
2466         unsigned int apic_taskpri;
2467         unsigned int apic_ldr;
2468         unsigned int apic_dfr;
2469         unsigned int apic_spiv;
2470         unsigned int apic_lvtt;
2471         unsigned int apic_lvtpc;
2472         unsigned int apic_lvt0;
2473         unsigned int apic_lvt1;
2474         unsigned int apic_lvterr;
2475         unsigned int apic_tmict;
2476         unsigned int apic_tdcr;
2477         unsigned int apic_thmr;
2478         unsigned int apic_cmci;
2479 } apic_pm_state;
2480 
2481 static int lapic_suspend(void)
2482 {
2483         unsigned long flags;
2484         int maxlvt;
2485 
2486         if (!apic_pm_state.active)
2487                 return 0;
2488 
2489         maxlvt = lapic_get_maxlvt();
2490 
2491         apic_pm_state.apic_id = apic_read(APIC_ID);
2492         apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
2493         apic_pm_state.apic_ldr = apic_read(APIC_LDR);
2494         apic_pm_state.apic_dfr = apic_read(APIC_DFR);
2495         apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
2496         apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
2497         if (maxlvt >= 4)
2498                 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
2499         apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
2500         apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
2501         apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
2502         apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
2503         apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
2504 #ifdef CONFIG_X86_THERMAL_VECTOR
2505         if (maxlvt >= 5)
2506                 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
2507 #endif
2508 #ifdef CONFIG_X86_MCE_INTEL
2509         if (maxlvt >= 6)
2510                 apic_pm_state.apic_cmci = apic_read(APIC_LVTCMCI);
2511 #endif
2512 
2513         local_irq_save(flags);
2514         disable_local_APIC();
2515 
2516         irq_remapping_disable();
2517 
2518         local_irq_restore(flags);
2519         return 0;
2520 }
2521 
2522 static void lapic_resume(void)
2523 {
2524         unsigned int l, h;
2525         unsigned long flags;
2526         int maxlvt;
2527 
2528         if (!apic_pm_state.active)
2529                 return;
2530 
2531         local_irq_save(flags);
2532 
2533         /*
2534          * IO-APIC and PIC have their own resume routines.
2535          * We just mask them here to make sure the interrupt
2536          * subsystem is completely quiet while we enable x2apic
2537          * and interrupt-remapping.
2538          */
2539         mask_ioapic_entries();
2540         legacy_pic->mask_all();
2541 
2542         if (x2apic_mode) {
2543                 __x2apic_enable();
2544         } else {
2545                 /*
2546                  * Make sure the APICBASE points to the right address
2547                  *
2548                  * FIXME! This will be wrong if we ever support suspend on
2549                  * SMP! We'll need to do this as part of the CPU restore!
2550                  */
2551                 if (boot_cpu_data.x86 >= 6) {
2552                         rdmsr(MSR_IA32_APICBASE, l, h);
2553                         l &= ~MSR_IA32_APICBASE_BASE;
2554                         l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
2555                         wrmsr(MSR_IA32_APICBASE, l, h);
2556                 }
2557         }
2558 
2559         maxlvt = lapic_get_maxlvt();
2560         apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
2561         apic_write(APIC_ID, apic_pm_state.apic_id);
2562         apic_write(APIC_DFR, apic_pm_state.apic_dfr);
2563         apic_write(APIC_LDR, apic_pm_state.apic_ldr);
2564         apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
2565         apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
2566         apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
2567         apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
2568 #ifdef CONFIG_X86_THERMAL_VECTOR
2569         if (maxlvt >= 5)
2570                 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
2571 #endif
2572 #ifdef CONFIG_X86_MCE_INTEL
2573         if (maxlvt >= 6)
2574                 apic_write(APIC_LVTCMCI, apic_pm_state.apic_cmci);
2575 #endif
2576         if (maxlvt >= 4)
2577                 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
2578         apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
2579         apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
2580         apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
2581         apic_write(APIC_ESR, 0);
2582         apic_read(APIC_ESR);
2583         apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
2584         apic_write(APIC_ESR, 0);
2585         apic_read(APIC_ESR);
2586 
2587         irq_remapping_reenable(x2apic_mode);
2588 
2589         local_irq_restore(flags);
2590 }
2591 
2592 /*
2593  * This device has no shutdown method - fully functioning local APICs
2594  * are needed on every CPU up until machine_halt/restart/poweroff.
2595  */
2596 
2597 static struct syscore_ops lapic_syscore_ops = {
2598         .resume         = lapic_resume,
2599         .suspend        = lapic_suspend,
2600 };
2601 
2602 static void apic_pm_activate(void)
2603 {
2604         apic_pm_state.active = 1;
2605 }
2606 
2607 static int __init init_lapic_sysfs(void)
2608 {
2609         /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2610         if (boot_cpu_has(X86_FEATURE_APIC))
2611                 register_syscore_ops(&lapic_syscore_ops);
2612 
2613         return 0;
2614 }
2615 
2616 /* local apic needs to resume before other devices access its registers. */
2617 core_initcall(init_lapic_sysfs);
2618 
2619 #else   /* CONFIG_PM */
2620 
2621 static void apic_pm_activate(void) { }
2622 
2623 #endif  /* CONFIG_PM */
2624 
2625 #ifdef CONFIG_X86_64
2626 
2627 static int multi_checked;
2628 static int multi;
2629 
2630 static int set_multi(const struct dmi_system_id *d)
2631 {
2632         if (multi)
2633                 return 0;
2634         pr_info("APIC: %s detected, Multi Chassis\n", d->ident);
2635         multi = 1;
2636         return 0;
2637 }
2638 
2639 static const struct dmi_system_id multi_dmi_table[] = {
2640         {
2641                 .callback = set_multi,
2642                 .ident = "IBM System Summit2",
2643                 .matches = {
2644                         DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
2645                         DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"),
2646                 },
2647         },
2648         {}
2649 };
2650 
2651 static void dmi_check_multi(void)
2652 {
2653         if (multi_checked)
2654                 return;
2655 
2656         dmi_check_system(multi_dmi_table);
2657         multi_checked = 1;
2658 }
2659 
2660 /*
2661  * apic_is_clustered_box() -- Check if we can expect good TSC
2662  *
2663  * Thus far, the major user of this is IBM's Summit2 series:
2664  * Clustered boxes may have unsynced TSC problems if they are
2665  * multi-chassis.
2666  * Use DMI to check them
2667  */
2668 int apic_is_clustered_box(void)
2669 {
2670         dmi_check_multi();
2671         return multi;
2672 }
2673 #endif
2674 
2675 /*
2676  * APIC command line parameters
2677  */
2678 static int __init setup_disableapic(char *arg)
2679 {
2680         disable_apic = 1;
2681         setup_clear_cpu_cap(X86_FEATURE_APIC);
2682         return 0;
2683 }
2684 early_param("disableapic", setup_disableapic);
2685 
2686 /* same as disableapic, for compatibility */
2687 static int __init setup_nolapic(char *arg)
2688 {
2689         return setup_disableapic(arg);
2690 }
2691 early_param("nolapic", setup_nolapic);
2692 
2693 static int __init parse_lapic_timer_c2_ok(char *arg)
2694 {
2695         local_apic_timer_c2_ok = 1;
2696         return 0;
2697 }
2698 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
2699 
2700 static int __init parse_disable_apic_timer(char *arg)
2701 {
2702         disable_apic_timer = 1;
2703         return 0;
2704 }
2705 early_param("noapictimer", parse_disable_apic_timer);
2706 
2707 static int __init parse_nolapic_timer(char *arg)
2708 {
2709         disable_apic_timer = 1;
2710         return 0;
2711 }
2712 early_param("nolapic_timer", parse_nolapic_timer);
2713 
2714 static int __init apic_set_verbosity(char *arg)
2715 {
2716         if (!arg)  {
2717 #ifdef CONFIG_X86_64
2718                 skip_ioapic_setup = 0;
2719                 return 0;
2720 #endif
2721                 return -EINVAL;
2722         }
2723 
2724         if (strcmp("debug", arg) == 0)
2725                 apic_verbosity = APIC_DEBUG;
2726         else if (strcmp("verbose", arg) == 0)
2727                 apic_verbosity = APIC_VERBOSE;
2728 #ifdef CONFIG_X86_64
2729         else {
2730                 pr_warning("APIC Verbosity level %s not recognised"
2731                         " use apic=verbose or apic=debug\n", arg);
2732                 return -EINVAL;
2733         }
2734 #endif
2735 
2736         return 0;
2737 }
2738 early_param("apic", apic_set_verbosity);
2739 
2740 static int __init lapic_insert_resource(void)
2741 {
2742         if (!apic_phys)
2743                 return -1;
2744 
2745         /* Put local APIC into the resource map. */
2746         lapic_resource.start = apic_phys;
2747         lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
2748         insert_resource(&iomem_resource, &lapic_resource);
2749 
2750         return 0;
2751 }
2752 
2753 /*
2754  * need call insert after e820__reserve_resources()
2755  * that is using request_resource
2756  */
2757 late_initcall(lapic_insert_resource);
2758 
2759 static int __init apic_set_disabled_cpu_apicid(char *arg)
2760 {
2761         if (!arg || !get_option(&arg, &disabled_cpu_apicid))
2762                 return -EINVAL;
2763 
2764         return 0;
2765 }
2766 early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid);
2767 
2768 static int __init apic_set_extnmi(char *arg)
2769 {
2770         if (!arg)
2771                 return -EINVAL;
2772 
2773         if (!strncmp("all", arg, 3))
2774                 apic_extnmi = APIC_EXTNMI_ALL;
2775         else if (!strncmp("none", arg, 4))
2776                 apic_extnmi = APIC_EXTNMI_NONE;
2777         else if (!strncmp("bsp", arg, 3))
2778                 apic_extnmi = APIC_EXTNMI_BSP;
2779         else {
2780                 pr_warn("Unknown external NMI delivery mode `%s' ignored\n", arg);
2781                 return -EINVAL;
2782         }
2783 
2784         return 0;
2785 }
2786 early_param("apic_extnmi", apic_set_extnmi);
2787 

~ [ source navigation ] ~ [ diff markup ] ~ [ identifier search ] ~

kernel.org | git.kernel.org | LWN.net | Project Home | Wiki (Japanese) | Wiki (English) | SVN repository | Mail admin

Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.

osdn.jp