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TOMOYO Linux Cross Reference
Linux/arch/x86/kernel/apic/apic.c

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  1 // SPDX-License-Identifier: GPL-2.0-only
  2 /*
  3  *      Local APIC handling, local APIC timers
  4  *
  5  *      (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
  6  *
  7  *      Fixes
  8  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  9  *                                      thanks to Eric Gilmore
 10  *                                      and Rolf G. Tews
 11  *                                      for testing these extensively.
 12  *      Maciej W. Rozycki       :       Various updates and fixes.
 13  *      Mikael Pettersson       :       Power Management for UP-APIC.
 14  *      Pavel Machek and
 15  *      Mikael Pettersson       :       PM converted to driver model.
 16  */
 17 
 18 #include <linux/perf_event.h>
 19 #include <linux/kernel_stat.h>
 20 #include <linux/mc146818rtc.h>
 21 #include <linux/acpi_pmtmr.h>
 22 #include <linux/clockchips.h>
 23 #include <linux/interrupt.h>
 24 #include <linux/memblock.h>
 25 #include <linux/ftrace.h>
 26 #include <linux/ioport.h>
 27 #include <linux/export.h>
 28 #include <linux/syscore_ops.h>
 29 #include <linux/delay.h>
 30 #include <linux/timex.h>
 31 #include <linux/i8253.h>
 32 #include <linux/dmar.h>
 33 #include <linux/init.h>
 34 #include <linux/cpu.h>
 35 #include <linux/dmi.h>
 36 #include <linux/smp.h>
 37 #include <linux/mm.h>
 38 
 39 #include <asm/trace/irq_vectors.h>
 40 #include <asm/irq_remapping.h>
 41 #include <asm/perf_event.h>
 42 #include <asm/x86_init.h>
 43 #include <asm/pgalloc.h>
 44 #include <linux/atomic.h>
 45 #include <asm/mpspec.h>
 46 #include <asm/i8259.h>
 47 #include <asm/proto.h>
 48 #include <asm/traps.h>
 49 #include <asm/apic.h>
 50 #include <asm/io_apic.h>
 51 #include <asm/desc.h>
 52 #include <asm/hpet.h>
 53 #include <asm/mtrr.h>
 54 #include <asm/time.h>
 55 #include <asm/smp.h>
 56 #include <asm/mce.h>
 57 #include <asm/tsc.h>
 58 #include <asm/hypervisor.h>
 59 #include <asm/cpu_device_id.h>
 60 #include <asm/intel-family.h>
 61 #include <asm/irq_regs.h>
 62 
 63 unsigned int num_processors;
 64 
 65 unsigned disabled_cpus;
 66 
 67 /* Processor that is doing the boot up */
 68 unsigned int boot_cpu_physical_apicid = -1U;
 69 EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid);
 70 
 71 u8 boot_cpu_apic_version;
 72 
 73 /*
 74  * The highest APIC ID seen during enumeration.
 75  */
 76 static unsigned int max_physical_apicid;
 77 
 78 /*
 79  * Bitmask of physically existing CPUs:
 80  */
 81 physid_mask_t phys_cpu_present_map;
 82 
 83 /*
 84  * Processor to be disabled specified by kernel parameter
 85  * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to
 86  * avoid undefined behaviour caused by sending INIT from AP to BSP.
 87  */
 88 static unsigned int disabled_cpu_apicid __read_mostly = BAD_APICID;
 89 
 90 /*
 91  * This variable controls which CPUs receive external NMIs.  By default,
 92  * external NMIs are delivered only to the BSP.
 93  */
 94 static int apic_extnmi = APIC_EXTNMI_BSP;
 95 
 96 /*
 97  * Map cpu index to physical APIC ID
 98  */
 99 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID);
100 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID);
101 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid, U32_MAX);
102 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid);
103 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
104 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid);
105 
106 #ifdef CONFIG_X86_32
107 
108 /*
109  * On x86_32, the mapping between cpu and logical apicid may vary
110  * depending on apic in use.  The following early percpu variable is
111  * used for the mapping.  This is where the behaviors of x86_64 and 32
112  * actually diverge.  Let's keep it ugly for now.
113  */
114 DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID);
115 
116 /* Local APIC was disabled by the BIOS and enabled by the kernel */
117 static int enabled_via_apicbase;
118 
119 /*
120  * Handle interrupt mode configuration register (IMCR).
121  * This register controls whether the interrupt signals
122  * that reach the BSP come from the master PIC or from the
123  * local APIC. Before entering Symmetric I/O Mode, either
124  * the BIOS or the operating system must switch out of
125  * PIC Mode by changing the IMCR.
126  */
127 static inline void imcr_pic_to_apic(void)
128 {
129         /* select IMCR register */
130         outb(0x70, 0x22);
131         /* NMI and 8259 INTR go through APIC */
132         outb(0x01, 0x23);
133 }
134 
135 static inline void imcr_apic_to_pic(void)
136 {
137         /* select IMCR register */
138         outb(0x70, 0x22);
139         /* NMI and 8259 INTR go directly to BSP */
140         outb(0x00, 0x23);
141 }
142 #endif
143 
144 /*
145  * Knob to control our willingness to enable the local APIC.
146  *
147  * +1=force-enable
148  */
149 static int force_enable_local_apic __initdata;
150 
151 /*
152  * APIC command line parameters
153  */
154 static int __init parse_lapic(char *arg)
155 {
156         if (IS_ENABLED(CONFIG_X86_32) && !arg)
157                 force_enable_local_apic = 1;
158         else if (arg && !strncmp(arg, "notscdeadline", 13))
159                 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
160         return 0;
161 }
162 early_param("lapic", parse_lapic);
163 
164 #ifdef CONFIG_X86_64
165 static int apic_calibrate_pmtmr __initdata;
166 static __init int setup_apicpmtimer(char *s)
167 {
168         apic_calibrate_pmtmr = 1;
169         notsc_setup(NULL);
170         return 0;
171 }
172 __setup("apicpmtimer", setup_apicpmtimer);
173 #endif
174 
175 unsigned long mp_lapic_addr;
176 int disable_apic;
177 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
178 static int disable_apic_timer __initdata;
179 /* Local APIC timer works in C2 */
180 int local_apic_timer_c2_ok;
181 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
182 
183 /*
184  * Debug level, exported for io_apic.c
185  */
186 int apic_verbosity;
187 
188 int pic_mode;
189 
190 /* Have we found an MP table */
191 int smp_found_config;
192 
193 static struct resource lapic_resource = {
194         .name = "Local APIC",
195         .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
196 };
197 
198 unsigned int lapic_timer_period = 0;
199 
200 static void apic_pm_activate(void);
201 
202 static unsigned long apic_phys;
203 
204 /*
205  * Get the LAPIC version
206  */
207 static inline int lapic_get_version(void)
208 {
209         return GET_APIC_VERSION(apic_read(APIC_LVR));
210 }
211 
212 /*
213  * Check, if the APIC is integrated or a separate chip
214  */
215 static inline int lapic_is_integrated(void)
216 {
217         return APIC_INTEGRATED(lapic_get_version());
218 }
219 
220 /*
221  * Check, whether this is a modern or a first generation APIC
222  */
223 static int modern_apic(void)
224 {
225         /* AMD systems use old APIC versions, so check the CPU */
226         if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
227             boot_cpu_data.x86 >= 0xf)
228                 return 1;
229 
230         /* Hygon systems use modern APIC */
231         if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
232                 return 1;
233 
234         return lapic_get_version() >= 0x14;
235 }
236 
237 /*
238  * right after this call apic become NOOP driven
239  * so apic->write/read doesn't do anything
240  */
241 static void __init apic_disable(void)
242 {
243         pr_info("APIC: switched to apic NOOP\n");
244         apic = &apic_noop;
245 }
246 
247 void native_apic_wait_icr_idle(void)
248 {
249         while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
250                 cpu_relax();
251 }
252 
253 u32 native_safe_apic_wait_icr_idle(void)
254 {
255         u32 send_status;
256         int timeout;
257 
258         timeout = 0;
259         do {
260                 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
261                 if (!send_status)
262                         break;
263                 inc_irq_stat(icr_read_retry_count);
264                 udelay(100);
265         } while (timeout++ < 1000);
266 
267         return send_status;
268 }
269 
270 void native_apic_icr_write(u32 low, u32 id)
271 {
272         unsigned long flags;
273 
274         local_irq_save(flags);
275         apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
276         apic_write(APIC_ICR, low);
277         local_irq_restore(flags);
278 }
279 
280 u64 native_apic_icr_read(void)
281 {
282         u32 icr1, icr2;
283 
284         icr2 = apic_read(APIC_ICR2);
285         icr1 = apic_read(APIC_ICR);
286 
287         return icr1 | ((u64)icr2 << 32);
288 }
289 
290 #ifdef CONFIG_X86_32
291 /**
292  * get_physical_broadcast - Get number of physical broadcast IDs
293  */
294 int get_physical_broadcast(void)
295 {
296         return modern_apic() ? 0xff : 0xf;
297 }
298 #endif
299 
300 /**
301  * lapic_get_maxlvt - get the maximum number of local vector table entries
302  */
303 int lapic_get_maxlvt(void)
304 {
305         /*
306          * - we always have APIC integrated on 64bit mode
307          * - 82489DXs do not report # of LVT entries
308          */
309         return lapic_is_integrated() ? GET_APIC_MAXLVT(apic_read(APIC_LVR)) : 2;
310 }
311 
312 /*
313  * Local APIC timer
314  */
315 
316 /* Clock divisor */
317 #define APIC_DIVISOR 16
318 #define TSC_DIVISOR  8
319 
320 /*
321  * This function sets up the local APIC timer, with a timeout of
322  * 'clocks' APIC bus clock. During calibration we actually call
323  * this function twice on the boot CPU, once with a bogus timeout
324  * value, second time for real. The other (noncalibrating) CPUs
325  * call this function only once, with the real, calibrated value.
326  *
327  * We do reads before writes even if unnecessary, to get around the
328  * P5 APIC double write bug.
329  */
330 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
331 {
332         unsigned int lvtt_value, tmp_value;
333 
334         lvtt_value = LOCAL_TIMER_VECTOR;
335         if (!oneshot)
336                 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
337         else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
338                 lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE;
339 
340         if (!lapic_is_integrated())
341                 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
342 
343         if (!irqen)
344                 lvtt_value |= APIC_LVT_MASKED;
345 
346         apic_write(APIC_LVTT, lvtt_value);
347 
348         if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) {
349                 /*
350                  * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode,
351                  * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized.
352                  * According to Intel, MFENCE can do the serialization here.
353                  */
354                 asm volatile("mfence" : : : "memory");
355 
356                 printk_once(KERN_DEBUG "TSC deadline timer enabled\n");
357                 return;
358         }
359 
360         /*
361          * Divide PICLK by 16
362          */
363         tmp_value = apic_read(APIC_TDCR);
364         apic_write(APIC_TDCR,
365                 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
366                 APIC_TDR_DIV_16);
367 
368         if (!oneshot)
369                 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
370 }
371 
372 /*
373  * Setup extended LVT, AMD specific
374  *
375  * Software should use the LVT offsets the BIOS provides.  The offsets
376  * are determined by the subsystems using it like those for MCE
377  * threshold or IBS.  On K8 only offset 0 (APIC500) and MCE interrupts
378  * are supported. Beginning with family 10h at least 4 offsets are
379  * available.
380  *
381  * Since the offsets must be consistent for all cores, we keep track
382  * of the LVT offsets in software and reserve the offset for the same
383  * vector also to be used on other cores. An offset is freed by
384  * setting the entry to APIC_EILVT_MASKED.
385  *
386  * If the BIOS is right, there should be no conflicts. Otherwise a
387  * "[Firmware Bug]: ..." error message is generated. However, if
388  * software does not properly determines the offsets, it is not
389  * necessarily a BIOS bug.
390  */
391 
392 static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX];
393 
394 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new)
395 {
396         return (old & APIC_EILVT_MASKED)
397                 || (new == APIC_EILVT_MASKED)
398                 || ((new & ~APIC_EILVT_MASKED) == old);
399 }
400 
401 static unsigned int reserve_eilvt_offset(int offset, unsigned int new)
402 {
403         unsigned int rsvd, vector;
404 
405         if (offset >= APIC_EILVT_NR_MAX)
406                 return ~0;
407 
408         rsvd = atomic_read(&eilvt_offsets[offset]);
409         do {
410                 vector = rsvd & ~APIC_EILVT_MASKED;     /* 0: unassigned */
411                 if (vector && !eilvt_entry_is_changeable(vector, new))
412                         /* may not change if vectors are different */
413                         return rsvd;
414                 rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new);
415         } while (rsvd != new);
416 
417         rsvd &= ~APIC_EILVT_MASKED;
418         if (rsvd && rsvd != vector)
419                 pr_info("LVT offset %d assigned for vector 0x%02x\n",
420                         offset, rsvd);
421 
422         return new;
423 }
424 
425 /*
426  * If mask=1, the LVT entry does not generate interrupts while mask=0
427  * enables the vector. See also the BKDGs. Must be called with
428  * preemption disabled.
429  */
430 
431 int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask)
432 {
433         unsigned long reg = APIC_EILVTn(offset);
434         unsigned int new, old, reserved;
435 
436         new = (mask << 16) | (msg_type << 8) | vector;
437         old = apic_read(reg);
438         reserved = reserve_eilvt_offset(offset, new);
439 
440         if (reserved != new) {
441                 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
442                        "vector 0x%x, but the register is already in use for "
443                        "vector 0x%x on another cpu\n",
444                        smp_processor_id(), reg, offset, new, reserved);
445                 return -EINVAL;
446         }
447 
448         if (!eilvt_entry_is_changeable(old, new)) {
449                 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
450                        "vector 0x%x, but the register is already in use for "
451                        "vector 0x%x on this cpu\n",
452                        smp_processor_id(), reg, offset, new, old);
453                 return -EBUSY;
454         }
455 
456         apic_write(reg, new);
457 
458         return 0;
459 }
460 EXPORT_SYMBOL_GPL(setup_APIC_eilvt);
461 
462 /*
463  * Program the next event, relative to now
464  */
465 static int lapic_next_event(unsigned long delta,
466                             struct clock_event_device *evt)
467 {
468         apic_write(APIC_TMICT, delta);
469         return 0;
470 }
471 
472 static int lapic_next_deadline(unsigned long delta,
473                                struct clock_event_device *evt)
474 {
475         u64 tsc;
476 
477         tsc = rdtsc();
478         wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR));
479         return 0;
480 }
481 
482 static int lapic_timer_shutdown(struct clock_event_device *evt)
483 {
484         unsigned int v;
485 
486         /* Lapic used as dummy for broadcast ? */
487         if (evt->features & CLOCK_EVT_FEAT_DUMMY)
488                 return 0;
489 
490         v = apic_read(APIC_LVTT);
491         v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
492         apic_write(APIC_LVTT, v);
493         apic_write(APIC_TMICT, 0);
494         return 0;
495 }
496 
497 static inline int
498 lapic_timer_set_periodic_oneshot(struct clock_event_device *evt, bool oneshot)
499 {
500         /* Lapic used as dummy for broadcast ? */
501         if (evt->features & CLOCK_EVT_FEAT_DUMMY)
502                 return 0;
503 
504         __setup_APIC_LVTT(lapic_timer_period, oneshot, 1);
505         return 0;
506 }
507 
508 static int lapic_timer_set_periodic(struct clock_event_device *evt)
509 {
510         return lapic_timer_set_periodic_oneshot(evt, false);
511 }
512 
513 static int lapic_timer_set_oneshot(struct clock_event_device *evt)
514 {
515         return lapic_timer_set_periodic_oneshot(evt, true);
516 }
517 
518 /*
519  * Local APIC timer broadcast function
520  */
521 static void lapic_timer_broadcast(const struct cpumask *mask)
522 {
523 #ifdef CONFIG_SMP
524         apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
525 #endif
526 }
527 
528 
529 /*
530  * The local apic timer can be used for any function which is CPU local.
531  */
532 static struct clock_event_device lapic_clockevent = {
533         .name                           = "lapic",
534         .features                       = CLOCK_EVT_FEAT_PERIODIC |
535                                           CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP
536                                           | CLOCK_EVT_FEAT_DUMMY,
537         .shift                          = 32,
538         .set_state_shutdown             = lapic_timer_shutdown,
539         .set_state_periodic             = lapic_timer_set_periodic,
540         .set_state_oneshot              = lapic_timer_set_oneshot,
541         .set_state_oneshot_stopped      = lapic_timer_shutdown,
542         .set_next_event                 = lapic_next_event,
543         .broadcast                      = lapic_timer_broadcast,
544         .rating                         = 100,
545         .irq                            = -1,
546 };
547 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
548 
549 #define DEADLINE_MODEL_MATCH_FUNC(model, func)  \
550         { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)&func }
551 
552 #define DEADLINE_MODEL_MATCH_REV(model, rev)    \
553         { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)rev }
554 
555 static u32 hsx_deadline_rev(void)
556 {
557         switch (boot_cpu_data.x86_stepping) {
558         case 0x02: return 0x3a; /* EP */
559         case 0x04: return 0x0f; /* EX */
560         }
561 
562         return ~0U;
563 }
564 
565 static u32 bdx_deadline_rev(void)
566 {
567         switch (boot_cpu_data.x86_stepping) {
568         case 0x02: return 0x00000011;
569         case 0x03: return 0x0700000e;
570         case 0x04: return 0x0f00000c;
571         case 0x05: return 0x0e000003;
572         }
573 
574         return ~0U;
575 }
576 
577 static u32 skx_deadline_rev(void)
578 {
579         switch (boot_cpu_data.x86_stepping) {
580         case 0x03: return 0x01000136;
581         case 0x04: return 0x02000014;
582         }
583 
584         if (boot_cpu_data.x86_stepping > 4)
585                 return 0;
586 
587         return ~0U;
588 }
589 
590 static const struct x86_cpu_id deadline_match[] = {
591         DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_HASWELL_X,        hsx_deadline_rev),
592         DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_X,      0x0b000020),
593         DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_BROADWELL_XEON_D, bdx_deadline_rev),
594         DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_SKYLAKE_X,        skx_deadline_rev),
595 
596         DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_CORE,     0x22),
597         DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_ULT,      0x20),
598         DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_GT3E,     0x17),
599 
600         DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_CORE,   0x25),
601         DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_GT3E,   0x17),
602 
603         DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_MOBILE,   0xb2),
604         DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_DESKTOP,  0xb2),
605 
606         DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_MOBILE,  0x52),
607         DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_DESKTOP, 0x52),
608 
609         {},
610 };
611 
612 static void apic_check_deadline_errata(void)
613 {
614         const struct x86_cpu_id *m;
615         u32 rev;
616 
617         if (!boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER) ||
618             boot_cpu_has(X86_FEATURE_HYPERVISOR))
619                 return;
620 
621         m = x86_match_cpu(deadline_match);
622         if (!m)
623                 return;
624 
625         /*
626          * Function pointers will have the MSB set due to address layout,
627          * immediate revisions will not.
628          */
629         if ((long)m->driver_data < 0)
630                 rev = ((u32 (*)(void))(m->driver_data))();
631         else
632                 rev = (u32)m->driver_data;
633 
634         if (boot_cpu_data.microcode >= rev)
635                 return;
636 
637         setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
638         pr_err(FW_BUG "TSC_DEADLINE disabled due to Errata; "
639                "please update microcode to version: 0x%x (or later)\n", rev);
640 }
641 
642 /*
643  * Setup the local APIC timer for this CPU. Copy the initialized values
644  * of the boot CPU and register the clock event in the framework.
645  */
646 static void setup_APIC_timer(void)
647 {
648         struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
649 
650         if (this_cpu_has(X86_FEATURE_ARAT)) {
651                 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP;
652                 /* Make LAPIC timer preferrable over percpu HPET */
653                 lapic_clockevent.rating = 150;
654         }
655 
656         memcpy(levt, &lapic_clockevent, sizeof(*levt));
657         levt->cpumask = cpumask_of(smp_processor_id());
658 
659         if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) {
660                 levt->name = "lapic-deadline";
661                 levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC |
662                                     CLOCK_EVT_FEAT_DUMMY);
663                 levt->set_next_event = lapic_next_deadline;
664                 clockevents_config_and_register(levt,
665                                                 tsc_khz * (1000 / TSC_DIVISOR),
666                                                 0xF, ~0UL);
667         } else
668                 clockevents_register_device(levt);
669 }
670 
671 /*
672  * Install the updated TSC frequency from recalibration at the TSC
673  * deadline clockevent devices.
674  */
675 static void __lapic_update_tsc_freq(void *info)
676 {
677         struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
678 
679         if (!this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
680                 return;
681 
682         clockevents_update_freq(levt, tsc_khz * (1000 / TSC_DIVISOR));
683 }
684 
685 void lapic_update_tsc_freq(void)
686 {
687         /*
688          * The clockevent device's ->mult and ->shift can both be
689          * changed. In order to avoid races, schedule the frequency
690          * update code on each CPU.
691          */
692         on_each_cpu(__lapic_update_tsc_freq, NULL, 0);
693 }
694 
695 /*
696  * In this functions we calibrate APIC bus clocks to the external timer.
697  *
698  * We want to do the calibration only once since we want to have local timer
699  * irqs syncron. CPUs connected by the same APIC bus have the very same bus
700  * frequency.
701  *
702  * This was previously done by reading the PIT/HPET and waiting for a wrap
703  * around to find out, that a tick has elapsed. I have a box, where the PIT
704  * readout is broken, so it never gets out of the wait loop again. This was
705  * also reported by others.
706  *
707  * Monitoring the jiffies value is inaccurate and the clockevents
708  * infrastructure allows us to do a simple substitution of the interrupt
709  * handler.
710  *
711  * The calibration routine also uses the pm_timer when possible, as the PIT
712  * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
713  * back to normal later in the boot process).
714  */
715 
716 #define LAPIC_CAL_LOOPS         (HZ/10)
717 
718 static __initdata int lapic_cal_loops = -1;
719 static __initdata long lapic_cal_t1, lapic_cal_t2;
720 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
721 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
722 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
723 
724 /*
725  * Temporary interrupt handler and polled calibration function.
726  */
727 static void __init lapic_cal_handler(struct clock_event_device *dev)
728 {
729         unsigned long long tsc = 0;
730         long tapic = apic_read(APIC_TMCCT);
731         unsigned long pm = acpi_pm_read_early();
732 
733         if (boot_cpu_has(X86_FEATURE_TSC))
734                 tsc = rdtsc();
735 
736         switch (lapic_cal_loops++) {
737         case 0:
738                 lapic_cal_t1 = tapic;
739                 lapic_cal_tsc1 = tsc;
740                 lapic_cal_pm1 = pm;
741                 lapic_cal_j1 = jiffies;
742                 break;
743 
744         case LAPIC_CAL_LOOPS:
745                 lapic_cal_t2 = tapic;
746                 lapic_cal_tsc2 = tsc;
747                 if (pm < lapic_cal_pm1)
748                         pm += ACPI_PM_OVRRUN;
749                 lapic_cal_pm2 = pm;
750                 lapic_cal_j2 = jiffies;
751                 break;
752         }
753 }
754 
755 static int __init
756 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc)
757 {
758         const long pm_100ms = PMTMR_TICKS_PER_SEC / 10;
759         const long pm_thresh = pm_100ms / 100;
760         unsigned long mult;
761         u64 res;
762 
763 #ifndef CONFIG_X86_PM_TIMER
764         return -1;
765 #endif
766 
767         apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm);
768 
769         /* Check, if the PM timer is available */
770         if (!deltapm)
771                 return -1;
772 
773         mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
774 
775         if (deltapm > (pm_100ms - pm_thresh) &&
776             deltapm < (pm_100ms + pm_thresh)) {
777                 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n");
778                 return 0;
779         }
780 
781         res = (((u64)deltapm) *  mult) >> 22;
782         do_div(res, 1000000);
783         pr_warning("APIC calibration not consistent "
784                    "with PM-Timer: %ldms instead of 100ms\n",(long)res);
785 
786         /* Correct the lapic counter value */
787         res = (((u64)(*delta)) * pm_100ms);
788         do_div(res, deltapm);
789         pr_info("APIC delta adjusted to PM-Timer: "
790                 "%lu (%ld)\n", (unsigned long)res, *delta);
791         *delta = (long)res;
792 
793         /* Correct the tsc counter value */
794         if (boot_cpu_has(X86_FEATURE_TSC)) {
795                 res = (((u64)(*deltatsc)) * pm_100ms);
796                 do_div(res, deltapm);
797                 apic_printk(APIC_VERBOSE, "TSC delta adjusted to "
798                                           "PM-Timer: %lu (%ld)\n",
799                                         (unsigned long)res, *deltatsc);
800                 *deltatsc = (long)res;
801         }
802 
803         return 0;
804 }
805 
806 static int __init lapic_init_clockevent(void)
807 {
808         if (!lapic_timer_period)
809                 return -1;
810 
811         /* Calculate the scaled math multiplication factor */
812         lapic_clockevent.mult = div_sc(lapic_timer_period/APIC_DIVISOR,
813                                         TICK_NSEC, lapic_clockevent.shift);
814         lapic_clockevent.max_delta_ns =
815                 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent);
816         lapic_clockevent.max_delta_ticks = 0x7FFFFFFF;
817         lapic_clockevent.min_delta_ns =
818                 clockevent_delta2ns(0xF, &lapic_clockevent);
819         lapic_clockevent.min_delta_ticks = 0xF;
820 
821         return 0;
822 }
823 
824 bool __init apic_needs_pit(void)
825 {
826         /*
827          * If the frequencies are not known, PIT is required for both TSC
828          * and apic timer calibration.
829          */
830         if (!tsc_khz || !cpu_khz)
831                 return true;
832 
833         /* Is there an APIC at all? */
834         if (!boot_cpu_has(X86_FEATURE_APIC))
835                 return true;
836 
837         /* Virt guests may lack ARAT, but still have DEADLINE */
838         if (!boot_cpu_has(X86_FEATURE_ARAT))
839                 return true;
840 
841         /* Deadline timer is based on TSC so no further PIT action required */
842         if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
843                 return false;
844 
845         /* APIC timer disabled? */
846         if (disable_apic_timer)
847                 return true;
848         /*
849          * The APIC timer frequency is known already, no PIT calibration
850          * required. If unknown, let the PIT be initialized.
851          */
852         return lapic_timer_period == 0;
853 }
854 
855 static int __init calibrate_APIC_clock(void)
856 {
857         struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
858         u64 tsc_perj = 0, tsc_start = 0;
859         unsigned long jif_start;
860         unsigned long deltaj;
861         long delta, deltatsc;
862         int pm_referenced = 0;
863 
864         if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
865                 return 0;
866 
867         /*
868          * Check if lapic timer has already been calibrated by platform
869          * specific routine, such as tsc calibration code. If so just fill
870          * in the clockevent structure and return.
871          */
872         if (!lapic_init_clockevent()) {
873                 apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n",
874                             lapic_timer_period);
875                 /*
876                  * Direct calibration methods must have an always running
877                  * local APIC timer, no need for broadcast timer.
878                  */
879                 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
880                 return 0;
881         }
882 
883         apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
884                     "calibrating APIC timer ...\n");
885 
886         /*
887          * There are platforms w/o global clockevent devices. Instead of
888          * making the calibration conditional on that, use a polling based
889          * approach everywhere.
890          */
891         local_irq_disable();
892 
893         /*
894          * Setup the APIC counter to maximum. There is no way the lapic
895          * can underflow in the 100ms detection time frame
896          */
897         __setup_APIC_LVTT(0xffffffff, 0, 0);
898 
899         /*
900          * Methods to terminate the calibration loop:
901          *  1) Global clockevent if available (jiffies)
902          *  2) TSC if available and frequency is known
903          */
904         jif_start = READ_ONCE(jiffies);
905 
906         if (tsc_khz) {
907                 tsc_start = rdtsc();
908                 tsc_perj = div_u64((u64)tsc_khz * 1000, HZ);
909         }
910 
911         /*
912          * Enable interrupts so the tick can fire, if a global
913          * clockevent device is available
914          */
915         local_irq_enable();
916 
917         while (lapic_cal_loops <= LAPIC_CAL_LOOPS) {
918                 /* Wait for a tick to elapse */
919                 while (1) {
920                         if (tsc_khz) {
921                                 u64 tsc_now = rdtsc();
922                                 if ((tsc_now - tsc_start) >= tsc_perj) {
923                                         tsc_start += tsc_perj;
924                                         break;
925                                 }
926                         } else {
927                                 unsigned long jif_now = READ_ONCE(jiffies);
928 
929                                 if (time_after(jif_now, jif_start)) {
930                                         jif_start = jif_now;
931                                         break;
932                                 }
933                         }
934                         cpu_relax();
935                 }
936 
937                 /* Invoke the calibration routine */
938                 local_irq_disable();
939                 lapic_cal_handler(NULL);
940                 local_irq_enable();
941         }
942 
943         local_irq_disable();
944 
945         /* Build delta t1-t2 as apic timer counts down */
946         delta = lapic_cal_t1 - lapic_cal_t2;
947         apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
948 
949         deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
950 
951         /* we trust the PM based calibration if possible */
952         pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,
953                                         &delta, &deltatsc);
954 
955         lapic_timer_period = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
956         lapic_init_clockevent();
957 
958         apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
959         apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult);
960         apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
961                     lapic_timer_period);
962 
963         if (boot_cpu_has(X86_FEATURE_TSC)) {
964                 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
965                             "%ld.%04ld MHz.\n",
966                             (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ),
967                             (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ));
968         }
969 
970         apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
971                     "%u.%04u MHz.\n",
972                     lapic_timer_period / (1000000 / HZ),
973                     lapic_timer_period % (1000000 / HZ));
974 
975         /*
976          * Do a sanity check on the APIC calibration result
977          */
978         if (lapic_timer_period < (1000000 / HZ)) {
979                 local_irq_enable();
980                 pr_warning("APIC frequency too slow, disabling apic timer\n");
981                 return -1;
982         }
983 
984         levt->features &= ~CLOCK_EVT_FEAT_DUMMY;
985 
986         /*
987          * PM timer calibration failed or not turned on so lets try APIC
988          * timer based calibration, if a global clockevent device is
989          * available.
990          */
991         if (!pm_referenced && global_clock_event) {
992                 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
993 
994                 /*
995                  * Setup the apic timer manually
996                  */
997                 levt->event_handler = lapic_cal_handler;
998                 lapic_timer_set_periodic(levt);
999                 lapic_cal_loops = -1;
1000 
1001                 /* Let the interrupts run */
1002                 local_irq_enable();
1003 
1004                 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
1005                         cpu_relax();
1006 
1007                 /* Stop the lapic timer */
1008                 local_irq_disable();
1009                 lapic_timer_shutdown(levt);
1010 
1011                 /* Jiffies delta */
1012                 deltaj = lapic_cal_j2 - lapic_cal_j1;
1013                 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
1014 
1015                 /* Check, if the jiffies result is consistent */
1016                 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
1017                         apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
1018                 else
1019                         levt->features |= CLOCK_EVT_FEAT_DUMMY;
1020         }
1021         local_irq_enable();
1022 
1023         if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
1024                 pr_warning("APIC timer disabled due to verification failure\n");
1025                 return -1;
1026         }
1027 
1028         return 0;
1029 }
1030 
1031 /*
1032  * Setup the boot APIC
1033  *
1034  * Calibrate and verify the result.
1035  */
1036 void __init setup_boot_APIC_clock(void)
1037 {
1038         /*
1039          * The local apic timer can be disabled via the kernel
1040          * commandline or from the CPU detection code. Register the lapic
1041          * timer as a dummy clock event source on SMP systems, so the
1042          * broadcast mechanism is used. On UP systems simply ignore it.
1043          */
1044         if (disable_apic_timer) {
1045                 pr_info("Disabling APIC timer\n");
1046                 /* No broadcast on UP ! */
1047                 if (num_possible_cpus() > 1) {
1048                         lapic_clockevent.mult = 1;
1049                         setup_APIC_timer();
1050                 }
1051                 return;
1052         }
1053 
1054         if (calibrate_APIC_clock()) {
1055                 /* No broadcast on UP ! */
1056                 if (num_possible_cpus() > 1)
1057                         setup_APIC_timer();
1058                 return;
1059         }
1060 
1061         /*
1062          * If nmi_watchdog is set to IO_APIC, we need the
1063          * PIT/HPET going.  Otherwise register lapic as a dummy
1064          * device.
1065          */
1066         lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
1067 
1068         /* Setup the lapic or request the broadcast */
1069         setup_APIC_timer();
1070         amd_e400_c1e_apic_setup();
1071 }
1072 
1073 void setup_secondary_APIC_clock(void)
1074 {
1075         setup_APIC_timer();
1076         amd_e400_c1e_apic_setup();
1077 }
1078 
1079 /*
1080  * The guts of the apic timer interrupt
1081  */
1082 static void local_apic_timer_interrupt(void)
1083 {
1084         struct clock_event_device *evt = this_cpu_ptr(&lapic_events);
1085 
1086         /*
1087          * Normally we should not be here till LAPIC has been initialized but
1088          * in some cases like kdump, its possible that there is a pending LAPIC
1089          * timer interrupt from previous kernel's context and is delivered in
1090          * new kernel the moment interrupts are enabled.
1091          *
1092          * Interrupts are enabled early and LAPIC is setup much later, hence
1093          * its possible that when we get here evt->event_handler is NULL.
1094          * Check for event_handler being NULL and discard the interrupt as
1095          * spurious.
1096          */
1097         if (!evt->event_handler) {
1098                 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n",
1099                            smp_processor_id());
1100                 /* Switch it off */
1101                 lapic_timer_shutdown(evt);
1102                 return;
1103         }
1104 
1105         /*
1106          * the NMI deadlock-detector uses this.
1107          */
1108         inc_irq_stat(apic_timer_irqs);
1109 
1110         evt->event_handler(evt);
1111 }
1112 
1113 /*
1114  * Local APIC timer interrupt. This is the most natural way for doing
1115  * local interrupts, but local timer interrupts can be emulated by
1116  * broadcast interrupts too. [in case the hw doesn't support APIC timers]
1117  *
1118  * [ if a single-CPU system runs an SMP kernel then we call the local
1119  *   interrupt as well. Thus we cannot inline the local irq ... ]
1120  */
1121 __visible void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs)
1122 {
1123         struct pt_regs *old_regs = set_irq_regs(regs);
1124 
1125         /*
1126          * NOTE! We'd better ACK the irq immediately,
1127          * because timer handling can be slow.
1128          *
1129          * update_process_times() expects us to have done irq_enter().
1130          * Besides, if we don't timer interrupts ignore the global
1131          * interrupt lock, which is the WrongThing (tm) to do.
1132          */
1133         entering_ack_irq();
1134         trace_local_timer_entry(LOCAL_TIMER_VECTOR);
1135         local_apic_timer_interrupt();
1136         trace_local_timer_exit(LOCAL_TIMER_VECTOR);
1137         exiting_irq();
1138 
1139         set_irq_regs(old_regs);
1140 }
1141 
1142 int setup_profiling_timer(unsigned int multiplier)
1143 {
1144         return -EINVAL;
1145 }
1146 
1147 /*
1148  * Local APIC start and shutdown
1149  */
1150 
1151 /**
1152  * clear_local_APIC - shutdown the local APIC
1153  *
1154  * This is called, when a CPU is disabled and before rebooting, so the state of
1155  * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
1156  * leftovers during boot.
1157  */
1158 void clear_local_APIC(void)
1159 {
1160         int maxlvt;
1161         u32 v;
1162 
1163         /* APIC hasn't been mapped yet */
1164         if (!x2apic_mode && !apic_phys)
1165                 return;
1166 
1167         maxlvt = lapic_get_maxlvt();
1168         /*
1169          * Masking an LVT entry can trigger a local APIC error
1170          * if the vector is zero. Mask LVTERR first to prevent this.
1171          */
1172         if (maxlvt >= 3) {
1173                 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
1174                 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
1175         }
1176         /*
1177          * Careful: we have to set masks only first to deassert
1178          * any level-triggered sources.
1179          */
1180         v = apic_read(APIC_LVTT);
1181         apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
1182         v = apic_read(APIC_LVT0);
1183         apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1184         v = apic_read(APIC_LVT1);
1185         apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
1186         if (maxlvt >= 4) {
1187                 v = apic_read(APIC_LVTPC);
1188                 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
1189         }
1190 
1191         /* lets not touch this if we didn't frob it */
1192 #ifdef CONFIG_X86_THERMAL_VECTOR
1193         if (maxlvt >= 5) {
1194                 v = apic_read(APIC_LVTTHMR);
1195                 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
1196         }
1197 #endif
1198 #ifdef CONFIG_X86_MCE_INTEL
1199         if (maxlvt >= 6) {
1200                 v = apic_read(APIC_LVTCMCI);
1201                 if (!(v & APIC_LVT_MASKED))
1202                         apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED);
1203         }
1204 #endif
1205 
1206         /*
1207          * Clean APIC state for other OSs:
1208          */
1209         apic_write(APIC_LVTT, APIC_LVT_MASKED);
1210         apic_write(APIC_LVT0, APIC_LVT_MASKED);
1211         apic_write(APIC_LVT1, APIC_LVT_MASKED);
1212         if (maxlvt >= 3)
1213                 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
1214         if (maxlvt >= 4)
1215                 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
1216 
1217         /* Integrated APIC (!82489DX) ? */
1218         if (lapic_is_integrated()) {
1219                 if (maxlvt > 3)
1220                         /* Clear ESR due to Pentium errata 3AP and 11AP */
1221                         apic_write(APIC_ESR, 0);
1222                 apic_read(APIC_ESR);
1223         }
1224 }
1225 
1226 /**
1227  * disable_local_APIC - clear and disable the local APIC
1228  */
1229 void disable_local_APIC(void)
1230 {
1231         unsigned int value;
1232 
1233         /* APIC hasn't been mapped yet */
1234         if (!x2apic_mode && !apic_phys)
1235                 return;
1236 
1237         clear_local_APIC();
1238 
1239         /*
1240          * Disable APIC (implies clearing of registers
1241          * for 82489DX!).
1242          */
1243         value = apic_read(APIC_SPIV);
1244         value &= ~APIC_SPIV_APIC_ENABLED;
1245         apic_write(APIC_SPIV, value);
1246 
1247 #ifdef CONFIG_X86_32
1248         /*
1249          * When LAPIC was disabled by the BIOS and enabled by the kernel,
1250          * restore the disabled state.
1251          */
1252         if (enabled_via_apicbase) {
1253                 unsigned int l, h;
1254 
1255                 rdmsr(MSR_IA32_APICBASE, l, h);
1256                 l &= ~MSR_IA32_APICBASE_ENABLE;
1257                 wrmsr(MSR_IA32_APICBASE, l, h);
1258         }
1259 #endif
1260 }
1261 
1262 /*
1263  * If Linux enabled the LAPIC against the BIOS default disable it down before
1264  * re-entering the BIOS on shutdown.  Otherwise the BIOS may get confused and
1265  * not power-off.  Additionally clear all LVT entries before disable_local_APIC
1266  * for the case where Linux didn't enable the LAPIC.
1267  */
1268 void lapic_shutdown(void)
1269 {
1270         unsigned long flags;
1271 
1272         if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config())
1273                 return;
1274 
1275         local_irq_save(flags);
1276 
1277 #ifdef CONFIG_X86_32
1278         if (!enabled_via_apicbase)
1279                 clear_local_APIC();
1280         else
1281 #endif
1282                 disable_local_APIC();
1283 
1284 
1285         local_irq_restore(flags);
1286 }
1287 
1288 /**
1289  * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1290  */
1291 void __init sync_Arb_IDs(void)
1292 {
1293         /*
1294          * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1295          * needed on AMD.
1296          */
1297         if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1298                 return;
1299 
1300         /*
1301          * Wait for idle.
1302          */
1303         apic_wait_icr_idle();
1304 
1305         apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
1306         apic_write(APIC_ICR, APIC_DEST_ALLINC |
1307                         APIC_INT_LEVELTRIG | APIC_DM_INIT);
1308 }
1309 
1310 enum apic_intr_mode_id apic_intr_mode;
1311 
1312 static int __init apic_intr_mode_select(void)
1313 {
1314         /* Check kernel option */
1315         if (disable_apic) {
1316                 pr_info("APIC disabled via kernel command line\n");
1317                 return APIC_PIC;
1318         }
1319 
1320         /* Check BIOS */
1321 #ifdef CONFIG_X86_64
1322         /* On 64-bit, the APIC must be integrated, Check local APIC only */
1323         if (!boot_cpu_has(X86_FEATURE_APIC)) {
1324                 disable_apic = 1;
1325                 pr_info("APIC disabled by BIOS\n");
1326                 return APIC_PIC;
1327         }
1328 #else
1329         /* On 32-bit, the APIC may be integrated APIC or 82489DX */
1330 
1331         /* Neither 82489DX nor integrated APIC ? */
1332         if (!boot_cpu_has(X86_FEATURE_APIC) && !smp_found_config) {
1333                 disable_apic = 1;
1334                 return APIC_PIC;
1335         }
1336 
1337         /* If the BIOS pretends there is an integrated APIC ? */
1338         if (!boot_cpu_has(X86_FEATURE_APIC) &&
1339                 APIC_INTEGRATED(boot_cpu_apic_version)) {
1340                 disable_apic = 1;
1341                 pr_err(FW_BUG "Local APIC %d not detected, force emulation\n",
1342                                        boot_cpu_physical_apicid);
1343                 return APIC_PIC;
1344         }
1345 #endif
1346 
1347         /* Check MP table or ACPI MADT configuration */
1348         if (!smp_found_config) {
1349                 disable_ioapic_support();
1350                 if (!acpi_lapic) {
1351                         pr_info("APIC: ACPI MADT or MP tables are not detected\n");
1352                         return APIC_VIRTUAL_WIRE_NO_CONFIG;
1353                 }
1354                 return APIC_VIRTUAL_WIRE;
1355         }
1356 
1357 #ifdef CONFIG_SMP
1358         /* If SMP should be disabled, then really disable it! */
1359         if (!setup_max_cpus) {
1360                 pr_info("APIC: SMP mode deactivated\n");
1361                 return APIC_SYMMETRIC_IO_NO_ROUTING;
1362         }
1363 
1364         if (read_apic_id() != boot_cpu_physical_apicid) {
1365                 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1366                      read_apic_id(), boot_cpu_physical_apicid);
1367                 /* Or can we switch back to PIC here? */
1368         }
1369 #endif
1370 
1371         return APIC_SYMMETRIC_IO;
1372 }
1373 
1374 /*
1375  * An initial setup of the virtual wire mode.
1376  */
1377 void __init init_bsp_APIC(void)
1378 {
1379         unsigned int value;
1380 
1381         /*
1382          * Don't do the setup now if we have a SMP BIOS as the
1383          * through-I/O-APIC virtual wire mode might be active.
1384          */
1385         if (smp_found_config || !boot_cpu_has(X86_FEATURE_APIC))
1386                 return;
1387 
1388         /*
1389          * Do not trust the local APIC being empty at bootup.
1390          */
1391         clear_local_APIC();
1392 
1393         /*
1394          * Enable APIC.
1395          */
1396         value = apic_read(APIC_SPIV);
1397         value &= ~APIC_VECTOR_MASK;
1398         value |= APIC_SPIV_APIC_ENABLED;
1399 
1400 #ifdef CONFIG_X86_32
1401         /* This bit is reserved on P4/Xeon and should be cleared */
1402         if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
1403             (boot_cpu_data.x86 == 15))
1404                 value &= ~APIC_SPIV_FOCUS_DISABLED;
1405         else
1406 #endif
1407                 value |= APIC_SPIV_FOCUS_DISABLED;
1408         value |= SPURIOUS_APIC_VECTOR;
1409         apic_write(APIC_SPIV, value);
1410 
1411         /*
1412          * Set up the virtual wire mode.
1413          */
1414         apic_write(APIC_LVT0, APIC_DM_EXTINT);
1415         value = APIC_DM_NMI;
1416         if (!lapic_is_integrated())             /* 82489DX */
1417                 value |= APIC_LVT_LEVEL_TRIGGER;
1418         if (apic_extnmi == APIC_EXTNMI_NONE)
1419                 value |= APIC_LVT_MASKED;
1420         apic_write(APIC_LVT1, value);
1421 }
1422 
1423 static void __init apic_bsp_setup(bool upmode);
1424 
1425 /* Init the interrupt delivery mode for the BSP */
1426 void __init apic_intr_mode_init(void)
1427 {
1428         bool upmode = IS_ENABLED(CONFIG_UP_LATE_INIT);
1429 
1430         apic_intr_mode = apic_intr_mode_select();
1431 
1432         switch (apic_intr_mode) {
1433         case APIC_PIC:
1434                 pr_info("APIC: Keep in PIC mode(8259)\n");
1435                 return;
1436         case APIC_VIRTUAL_WIRE:
1437                 pr_info("APIC: Switch to virtual wire mode setup\n");
1438                 default_setup_apic_routing();
1439                 break;
1440         case APIC_VIRTUAL_WIRE_NO_CONFIG:
1441                 pr_info("APIC: Switch to virtual wire mode setup with no configuration\n");
1442                 upmode = true;
1443                 default_setup_apic_routing();
1444                 break;
1445         case APIC_SYMMETRIC_IO:
1446                 pr_info("APIC: Switch to symmetric I/O mode setup\n");
1447                 default_setup_apic_routing();
1448                 break;
1449         case APIC_SYMMETRIC_IO_NO_ROUTING:
1450                 pr_info("APIC: Switch to symmetric I/O mode setup in no SMP routine\n");
1451                 break;
1452         }
1453 
1454         apic_bsp_setup(upmode);
1455 }
1456 
1457 static void lapic_setup_esr(void)
1458 {
1459         unsigned int oldvalue, value, maxlvt;
1460 
1461         if (!lapic_is_integrated()) {
1462                 pr_info("No ESR for 82489DX.\n");
1463                 return;
1464         }
1465 
1466         if (apic->disable_esr) {
1467                 /*
1468                  * Something untraceable is creating bad interrupts on
1469                  * secondary quads ... for the moment, just leave the
1470                  * ESR disabled - we can't do anything useful with the
1471                  * errors anyway - mbligh
1472                  */
1473                 pr_info("Leaving ESR disabled.\n");
1474                 return;
1475         }
1476 
1477         maxlvt = lapic_get_maxlvt();
1478         if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
1479                 apic_write(APIC_ESR, 0);
1480         oldvalue = apic_read(APIC_ESR);
1481 
1482         /* enables sending errors */
1483         value = ERROR_APIC_VECTOR;
1484         apic_write(APIC_LVTERR, value);
1485 
1486         /*
1487          * spec says clear errors after enabling vector.
1488          */
1489         if (maxlvt > 3)
1490                 apic_write(APIC_ESR, 0);
1491         value = apic_read(APIC_ESR);
1492         if (value != oldvalue)
1493                 apic_printk(APIC_VERBOSE, "ESR value before enabling "
1494                         "vector: 0x%08x  after: 0x%08x\n",
1495                         oldvalue, value);
1496 }
1497 
1498 #define APIC_IR_REGS            APIC_ISR_NR
1499 #define APIC_IR_BITS            (APIC_IR_REGS * 32)
1500 #define APIC_IR_MAPSIZE         (APIC_IR_BITS / BITS_PER_LONG)
1501 
1502 union apic_ir {
1503         unsigned long   map[APIC_IR_MAPSIZE];
1504         u32             regs[APIC_IR_REGS];
1505 };
1506 
1507 static bool apic_check_and_ack(union apic_ir *irr, union apic_ir *isr)
1508 {
1509         int i, bit;
1510 
1511         /* Read the IRRs */
1512         for (i = 0; i < APIC_IR_REGS; i++)
1513                 irr->regs[i] = apic_read(APIC_IRR + i * 0x10);
1514 
1515         /* Read the ISRs */
1516         for (i = 0; i < APIC_IR_REGS; i++)
1517                 isr->regs[i] = apic_read(APIC_ISR + i * 0x10);
1518 
1519         /*
1520          * If the ISR map is not empty. ACK the APIC and run another round
1521          * to verify whether a pending IRR has been unblocked and turned
1522          * into a ISR.
1523          */
1524         if (!bitmap_empty(isr->map, APIC_IR_BITS)) {
1525                 /*
1526                  * There can be multiple ISR bits set when a high priority
1527                  * interrupt preempted a lower priority one. Issue an ACK
1528                  * per set bit.
1529                  */
1530                 for_each_set_bit(bit, isr->map, APIC_IR_BITS)
1531                         ack_APIC_irq();
1532                 return true;
1533         }
1534 
1535         return !bitmap_empty(irr->map, APIC_IR_BITS);
1536 }
1537 
1538 /*
1539  * After a crash, we no longer service the interrupts and a pending
1540  * interrupt from previous kernel might still have ISR bit set.
1541  *
1542  * Most probably by now the CPU has serviced that pending interrupt and it
1543  * might not have done the ack_APIC_irq() because it thought, interrupt
1544  * came from i8259 as ExtInt. LAPIC did not get EOI so it does not clear
1545  * the ISR bit and cpu thinks it has already serivced the interrupt. Hence
1546  * a vector might get locked. It was noticed for timer irq (vector
1547  * 0x31). Issue an extra EOI to clear ISR.
1548  *
1549  * If there are pending IRR bits they turn into ISR bits after a higher
1550  * priority ISR bit has been acked.
1551  */
1552 static void apic_pending_intr_clear(void)
1553 {
1554         union apic_ir irr, isr;
1555         unsigned int i;
1556 
1557         /* 512 loops are way oversized and give the APIC a chance to obey. */
1558         for (i = 0; i < 512; i++) {
1559                 if (!apic_check_and_ack(&irr, &isr))
1560                         return;
1561         }
1562         /* Dump the IRR/ISR content if that failed */
1563         pr_warn("APIC: Stale IRR: %256pb ISR: %256pb\n", irr.map, isr.map);
1564 }
1565 
1566 /**
1567  * setup_local_APIC - setup the local APIC
1568  *
1569  * Used to setup local APIC while initializing BSP or bringing up APs.
1570  * Always called with preemption disabled.
1571  */
1572 static void setup_local_APIC(void)
1573 {
1574         int cpu = smp_processor_id();
1575         unsigned int value;
1576 
1577 
1578         if (disable_apic) {
1579                 disable_ioapic_support();
1580                 return;
1581         }
1582 
1583         /*
1584          * If this comes from kexec/kcrash the APIC might be enabled in
1585          * SPIV. Soft disable it before doing further initialization.
1586          */
1587         value = apic_read(APIC_SPIV);
1588         value &= ~APIC_SPIV_APIC_ENABLED;
1589         apic_write(APIC_SPIV, value);
1590 
1591 #ifdef CONFIG_X86_32
1592         /* Pound the ESR really hard over the head with a big hammer - mbligh */
1593         if (lapic_is_integrated() && apic->disable_esr) {
1594                 apic_write(APIC_ESR, 0);
1595                 apic_write(APIC_ESR, 0);
1596                 apic_write(APIC_ESR, 0);
1597                 apic_write(APIC_ESR, 0);
1598         }
1599 #endif
1600         perf_events_lapic_init();
1601 
1602         /*
1603          * Double-check whether this APIC is really registered.
1604          * This is meaningless in clustered apic mode, so we skip it.
1605          */
1606         BUG_ON(!apic->apic_id_registered());
1607 
1608         /*
1609          * Intel recommends to set DFR, LDR and TPR before enabling
1610          * an APIC.  See e.g. "AP-388 82489DX User's Manual" (Intel
1611          * document number 292116).  So here it goes...
1612          */
1613         apic->init_apic_ldr();
1614 
1615 #ifdef CONFIG_X86_32
1616         if (apic->dest_logical) {
1617                 int logical_apicid, ldr_apicid;
1618 
1619                 /*
1620                  * APIC LDR is initialized.  If logical_apicid mapping was
1621                  * initialized during get_smp_config(), make sure it matches
1622                  * the actual value.
1623                  */
1624                 logical_apicid = early_per_cpu(x86_cpu_to_logical_apicid, cpu);
1625                 ldr_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
1626                 if (logical_apicid != BAD_APICID)
1627                         WARN_ON(logical_apicid != ldr_apicid);
1628                 /* Always use the value from LDR. */
1629                 early_per_cpu(x86_cpu_to_logical_apicid, cpu) = ldr_apicid;
1630         }
1631 #endif
1632 
1633         /*
1634          * Set Task Priority to 'accept all'. We never change this
1635          * later on.
1636          */
1637         value = apic_read(APIC_TASKPRI);
1638         value &= ~APIC_TPRI_MASK;
1639         apic_write(APIC_TASKPRI, value);
1640 
1641         /* Clear eventually stale ISR/IRR bits */
1642         apic_pending_intr_clear();
1643 
1644         /*
1645          * Now that we are all set up, enable the APIC
1646          */
1647         value = apic_read(APIC_SPIV);
1648         value &= ~APIC_VECTOR_MASK;
1649         /*
1650          * Enable APIC
1651          */
1652         value |= APIC_SPIV_APIC_ENABLED;
1653 
1654 #ifdef CONFIG_X86_32
1655         /*
1656          * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1657          * certain networking cards. If high frequency interrupts are
1658          * happening on a particular IOAPIC pin, plus the IOAPIC routing
1659          * entry is masked/unmasked at a high rate as well then sooner or
1660          * later IOAPIC line gets 'stuck', no more interrupts are received
1661          * from the device. If focus CPU is disabled then the hang goes
1662          * away, oh well :-(
1663          *
1664          * [ This bug can be reproduced easily with a level-triggered
1665          *   PCI Ne2000 networking cards and PII/PIII processors, dual
1666          *   BX chipset. ]
1667          */
1668         /*
1669          * Actually disabling the focus CPU check just makes the hang less
1670          * frequent as it makes the interrupt distributon model be more
1671          * like LRU than MRU (the short-term load is more even across CPUs).
1672          */
1673 
1674         /*
1675          * - enable focus processor (bit==0)
1676          * - 64bit mode always use processor focus
1677          *   so no need to set it
1678          */
1679         value &= ~APIC_SPIV_FOCUS_DISABLED;
1680 #endif
1681 
1682         /*
1683          * Set spurious IRQ vector
1684          */
1685         value |= SPURIOUS_APIC_VECTOR;
1686         apic_write(APIC_SPIV, value);
1687 
1688         /*
1689          * Set up LVT0, LVT1:
1690          *
1691          * set up through-local-APIC on the boot CPU's LINT0. This is not
1692          * strictly necessary in pure symmetric-IO mode, but sometimes
1693          * we delegate interrupts to the 8259A.
1694          */
1695         /*
1696          * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1697          */
1698         value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1699         if (!cpu && (pic_mode || !value || skip_ioapic_setup)) {
1700                 value = APIC_DM_EXTINT;
1701                 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu);
1702         } else {
1703                 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1704                 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu);
1705         }
1706         apic_write(APIC_LVT0, value);
1707 
1708         /*
1709          * Only the BSP sees the LINT1 NMI signal by default. This can be
1710          * modified by apic_extnmi= boot option.
1711          */
1712         if ((!cpu && apic_extnmi != APIC_EXTNMI_NONE) ||
1713             apic_extnmi == APIC_EXTNMI_ALL)
1714                 value = APIC_DM_NMI;
1715         else
1716                 value = APIC_DM_NMI | APIC_LVT_MASKED;
1717 
1718         /* Is 82489DX ? */
1719         if (!lapic_is_integrated())
1720                 value |= APIC_LVT_LEVEL_TRIGGER;
1721         apic_write(APIC_LVT1, value);
1722 
1723 #ifdef CONFIG_X86_MCE_INTEL
1724         /* Recheck CMCI information after local APIC is up on CPU #0 */
1725         if (!cpu)
1726                 cmci_recheck();
1727 #endif
1728 }
1729 
1730 static void end_local_APIC_setup(void)
1731 {
1732         lapic_setup_esr();
1733 
1734 #ifdef CONFIG_X86_32
1735         {
1736                 unsigned int value;
1737                 /* Disable the local apic timer */
1738                 value = apic_read(APIC_LVTT);
1739                 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1740                 apic_write(APIC_LVTT, value);
1741         }
1742 #endif
1743 
1744         apic_pm_activate();
1745 }
1746 
1747 /*
1748  * APIC setup function for application processors. Called from smpboot.c
1749  */
1750 void apic_ap_setup(void)
1751 {
1752         setup_local_APIC();
1753         end_local_APIC_setup();
1754 }
1755 
1756 #ifdef CONFIG_X86_X2APIC
1757 int x2apic_mode;
1758 
1759 enum {
1760         X2APIC_OFF,
1761         X2APIC_ON,
1762         X2APIC_DISABLED,
1763 };
1764 static int x2apic_state;
1765 
1766 static void __x2apic_disable(void)
1767 {
1768         u64 msr;
1769 
1770         if (!boot_cpu_has(X86_FEATURE_APIC))
1771                 return;
1772 
1773         rdmsrl(MSR_IA32_APICBASE, msr);
1774         if (!(msr & X2APIC_ENABLE))
1775                 return;
1776         /* Disable xapic and x2apic first and then reenable xapic mode */
1777         wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE));
1778         wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE);
1779         printk_once(KERN_INFO "x2apic disabled\n");
1780 }
1781 
1782 static void __x2apic_enable(void)
1783 {
1784         u64 msr;
1785 
1786         rdmsrl(MSR_IA32_APICBASE, msr);
1787         if (msr & X2APIC_ENABLE)
1788                 return;
1789         wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE);
1790         printk_once(KERN_INFO "x2apic enabled\n");
1791 }
1792 
1793 static int __init setup_nox2apic(char *str)
1794 {
1795         if (x2apic_enabled()) {
1796                 int apicid = native_apic_msr_read(APIC_ID);
1797 
1798                 if (apicid >= 255) {
1799                         pr_warning("Apicid: %08x, cannot enforce nox2apic\n",
1800                                    apicid);
1801                         return 0;
1802                 }
1803                 pr_warning("x2apic already enabled.\n");
1804                 __x2apic_disable();
1805         }
1806         setup_clear_cpu_cap(X86_FEATURE_X2APIC);
1807         x2apic_state = X2APIC_DISABLED;
1808         x2apic_mode = 0;
1809         return 0;
1810 }
1811 early_param("nox2apic", setup_nox2apic);
1812 
1813 /* Called from cpu_init() to enable x2apic on (secondary) cpus */
1814 void x2apic_setup(void)
1815 {
1816         /*
1817          * If x2apic is not in ON state, disable it if already enabled
1818          * from BIOS.
1819          */
1820         if (x2apic_state != X2APIC_ON) {
1821                 __x2apic_disable();
1822                 return;
1823         }
1824         __x2apic_enable();
1825 }
1826 
1827 static __init void x2apic_disable(void)
1828 {
1829         u32 x2apic_id, state = x2apic_state;
1830 
1831         x2apic_mode = 0;
1832         x2apic_state = X2APIC_DISABLED;
1833 
1834         if (state != X2APIC_ON)
1835                 return;
1836 
1837         x2apic_id = read_apic_id();
1838         if (x2apic_id >= 255)
1839                 panic("Cannot disable x2apic, id: %08x\n", x2apic_id);
1840 
1841         __x2apic_disable();
1842         register_lapic_address(mp_lapic_addr);
1843 }
1844 
1845 static __init void x2apic_enable(void)
1846 {
1847         if (x2apic_state != X2APIC_OFF)
1848                 return;
1849 
1850         x2apic_mode = 1;
1851         x2apic_state = X2APIC_ON;
1852         __x2apic_enable();
1853 }
1854 
1855 static __init void try_to_enable_x2apic(int remap_mode)
1856 {
1857         if (x2apic_state == X2APIC_DISABLED)
1858                 return;
1859 
1860         if (remap_mode != IRQ_REMAP_X2APIC_MODE) {
1861                 /* IR is required if there is APIC ID > 255 even when running
1862                  * under KVM
1863                  */
1864                 if (max_physical_apicid > 255 ||
1865                     !x86_init.hyper.x2apic_available()) {
1866                         pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n");
1867                         x2apic_disable();
1868                         return;
1869                 }
1870 
1871                 /*
1872                  * without IR all CPUs can be addressed by IOAPIC/MSI
1873                  * only in physical mode
1874                  */
1875                 x2apic_phys = 1;
1876         }
1877         x2apic_enable();
1878 }
1879 
1880 void __init check_x2apic(void)
1881 {
1882         if (x2apic_enabled()) {
1883                 pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n");
1884                 x2apic_mode = 1;
1885                 x2apic_state = X2APIC_ON;
1886         } else if (!boot_cpu_has(X86_FEATURE_X2APIC)) {
1887                 x2apic_state = X2APIC_DISABLED;
1888         }
1889 }
1890 #else /* CONFIG_X86_X2APIC */
1891 static int __init validate_x2apic(void)
1892 {
1893         if (!apic_is_x2apic_enabled())
1894                 return 0;
1895         /*
1896          * Checkme: Can we simply turn off x2apic here instead of panic?
1897          */
1898         panic("BIOS has enabled x2apic but kernel doesn't support x2apic, please disable x2apic in BIOS.\n");
1899 }
1900 early_initcall(validate_x2apic);
1901 
1902 static inline void try_to_enable_x2apic(int remap_mode) { }
1903 static inline void __x2apic_enable(void) { }
1904 #endif /* !CONFIG_X86_X2APIC */
1905 
1906 void __init enable_IR_x2apic(void)
1907 {
1908         unsigned long flags;
1909         int ret, ir_stat;
1910 
1911         if (skip_ioapic_setup) {
1912                 pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n");
1913                 return;
1914         }
1915 
1916         ir_stat = irq_remapping_prepare();
1917         if (ir_stat < 0 && !x2apic_supported())
1918                 return;
1919 
1920         ret = save_ioapic_entries();
1921         if (ret) {
1922                 pr_info("Saving IO-APIC state failed: %d\n", ret);
1923                 return;
1924         }
1925 
1926         local_irq_save(flags);
1927         legacy_pic->mask_all();
1928         mask_ioapic_entries();
1929 
1930         /* If irq_remapping_prepare() succeeded, try to enable it */
1931         if (ir_stat >= 0)
1932                 ir_stat = irq_remapping_enable();
1933         /* ir_stat contains the remap mode or an error code */
1934         try_to_enable_x2apic(ir_stat);
1935 
1936         if (ir_stat < 0)
1937                 restore_ioapic_entries();
1938         legacy_pic->restore_mask();
1939         local_irq_restore(flags);
1940 }
1941 
1942 #ifdef CONFIG_X86_64
1943 /*
1944  * Detect and enable local APICs on non-SMP boards.
1945  * Original code written by Keir Fraser.
1946  * On AMD64 we trust the BIOS - if it says no APIC it is likely
1947  * not correctly set up (usually the APIC timer won't work etc.)
1948  */
1949 static int __init detect_init_APIC(void)
1950 {
1951         if (!boot_cpu_has(X86_FEATURE_APIC)) {
1952                 pr_info("No local APIC present\n");
1953                 return -1;
1954         }
1955 
1956         mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1957         return 0;
1958 }
1959 #else
1960 
1961 static int __init apic_verify(void)
1962 {
1963         u32 features, h, l;
1964 
1965         /*
1966          * The APIC feature bit should now be enabled
1967          * in `cpuid'
1968          */
1969         features = cpuid_edx(1);
1970         if (!(features & (1 << X86_FEATURE_APIC))) {
1971                 pr_warning("Could not enable APIC!\n");
1972                 return -1;
1973         }
1974         set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1975         mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1976 
1977         /* The BIOS may have set up the APIC at some other address */
1978         if (boot_cpu_data.x86 >= 6) {
1979                 rdmsr(MSR_IA32_APICBASE, l, h);
1980                 if (l & MSR_IA32_APICBASE_ENABLE)
1981                         mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1982         }
1983 
1984         pr_info("Found and enabled local APIC!\n");
1985         return 0;
1986 }
1987 
1988 int __init apic_force_enable(unsigned long addr)
1989 {
1990         u32 h, l;
1991 
1992         if (disable_apic)
1993                 return -1;
1994 
1995         /*
1996          * Some BIOSes disable the local APIC in the APIC_BASE
1997          * MSR. This can only be done in software for Intel P6 or later
1998          * and AMD K7 (Model > 1) or later.
1999          */
2000         if (boot_cpu_data.x86 >= 6) {
2001                 rdmsr(MSR_IA32_APICBASE, l, h);
2002                 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
2003                         pr_info("Local APIC disabled by BIOS -- reenabling.\n");
2004                         l &= ~MSR_IA32_APICBASE_BASE;
2005                         l |= MSR_IA32_APICBASE_ENABLE | addr;
2006                         wrmsr(MSR_IA32_APICBASE, l, h);
2007                         enabled_via_apicbase = 1;
2008                 }
2009         }
2010         return apic_verify();
2011 }
2012 
2013 /*
2014  * Detect and initialize APIC
2015  */
2016 static int __init detect_init_APIC(void)
2017 {
2018         /* Disabled by kernel option? */
2019         if (disable_apic)
2020                 return -1;
2021 
2022         switch (boot_cpu_data.x86_vendor) {
2023         case X86_VENDOR_AMD:
2024                 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
2025                     (boot_cpu_data.x86 >= 15))
2026                         break;
2027                 goto no_apic;
2028         case X86_VENDOR_HYGON:
2029                 break;
2030         case X86_VENDOR_INTEL:
2031                 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
2032                     (boot_cpu_data.x86 == 5 && boot_cpu_has(X86_FEATURE_APIC)))
2033                         break;
2034                 goto no_apic;
2035         default:
2036                 goto no_apic;
2037         }
2038 
2039         if (!boot_cpu_has(X86_FEATURE_APIC)) {
2040                 /*
2041                  * Over-ride BIOS and try to enable the local APIC only if
2042                  * "lapic" specified.
2043                  */
2044                 if (!force_enable_local_apic) {
2045                         pr_info("Local APIC disabled by BIOS -- "
2046                                 "you can enable it with \"lapic\"\n");
2047                         return -1;
2048                 }
2049                 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE))
2050                         return -1;
2051         } else {
2052                 if (apic_verify())
2053                         return -1;
2054         }
2055 
2056         apic_pm_activate();
2057 
2058         return 0;
2059 
2060 no_apic:
2061         pr_info("No local APIC present or hardware disabled\n");
2062         return -1;
2063 }
2064 #endif
2065 
2066 /**
2067  * init_apic_mappings - initialize APIC mappings
2068  */
2069 void __init init_apic_mappings(void)
2070 {
2071         unsigned int new_apicid;
2072 
2073         apic_check_deadline_errata();
2074 
2075         if (x2apic_mode) {
2076                 boot_cpu_physical_apicid = read_apic_id();
2077                 return;
2078         }
2079 
2080         /* If no local APIC can be found return early */
2081         if (!smp_found_config && detect_init_APIC()) {
2082                 /* lets NOP'ify apic operations */
2083                 pr_info("APIC: disable apic facility\n");
2084                 apic_disable();
2085         } else {
2086                 apic_phys = mp_lapic_addr;
2087 
2088                 /*
2089                  * If the system has ACPI MADT tables or MP info, the LAPIC
2090                  * address is already registered.
2091                  */
2092                 if (!acpi_lapic && !smp_found_config)
2093                         register_lapic_address(apic_phys);
2094         }
2095 
2096         /*
2097          * Fetch the APIC ID of the BSP in case we have a
2098          * default configuration (or the MP table is broken).
2099          */
2100         new_apicid = read_apic_id();
2101         if (boot_cpu_physical_apicid != new_apicid) {
2102                 boot_cpu_physical_apicid = new_apicid;
2103                 /*
2104                  * yeah -- we lie about apic_version
2105                  * in case if apic was disabled via boot option
2106                  * but it's not a problem for SMP compiled kernel
2107                  * since apic_intr_mode_select is prepared for such
2108                  * a case and disable smp mode
2109                  */
2110                 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR));
2111         }
2112 }
2113 
2114 void __init register_lapic_address(unsigned long address)
2115 {
2116         mp_lapic_addr = address;
2117 
2118         if (!x2apic_mode) {
2119                 set_fixmap_nocache(FIX_APIC_BASE, address);
2120                 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
2121                             APIC_BASE, address);
2122         }
2123         if (boot_cpu_physical_apicid == -1U) {
2124                 boot_cpu_physical_apicid  = read_apic_id();
2125                 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR));
2126         }
2127 }
2128 
2129 /*
2130  * Local APIC interrupts
2131  */
2132 
2133 /*
2134  * This interrupt should _never_ happen with our APIC/SMP architecture
2135  */
2136 __visible void __irq_entry smp_spurious_interrupt(struct pt_regs *regs)
2137 {
2138         u8 vector = ~regs->orig_ax;
2139         u32 v;
2140 
2141         entering_irq();
2142         trace_spurious_apic_entry(vector);
2143 
2144         inc_irq_stat(irq_spurious_count);
2145 
2146         /*
2147          * If this is a spurious interrupt then do not acknowledge
2148          */
2149         if (vector == SPURIOUS_APIC_VECTOR) {
2150                 /* See SDM vol 3 */
2151                 pr_info("Spurious APIC interrupt (vector 0xFF) on CPU#%d, should never happen.\n",
2152                         smp_processor_id());
2153                 goto out;
2154         }
2155 
2156         /*
2157          * If it is a vectored one, verify it's set in the ISR. If set,
2158          * acknowledge it.
2159          */
2160         v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1));
2161         if (v & (1 << (vector & 0x1f))) {
2162                 pr_info("Spurious interrupt (vector 0x%02x) on CPU#%d. Acked\n",
2163                         vector, smp_processor_id());
2164                 ack_APIC_irq();
2165         } else {
2166                 pr_info("Spurious interrupt (vector 0x%02x) on CPU#%d. Not pending!\n",
2167                         vector, smp_processor_id());
2168         }
2169 out:
2170         trace_spurious_apic_exit(vector);
2171         exiting_irq();
2172 }
2173 
2174 /*
2175  * This interrupt should never happen with our APIC/SMP architecture
2176  */
2177 __visible void __irq_entry smp_error_interrupt(struct pt_regs *regs)
2178 {
2179         static const char * const error_interrupt_reason[] = {
2180                 "Send CS error",                /* APIC Error Bit 0 */
2181                 "Receive CS error",             /* APIC Error Bit 1 */
2182                 "Send accept error",            /* APIC Error Bit 2 */
2183                 "Receive accept error",         /* APIC Error Bit 3 */
2184                 "Redirectable IPI",             /* APIC Error Bit 4 */
2185                 "Send illegal vector",          /* APIC Error Bit 5 */
2186                 "Received illegal vector",      /* APIC Error Bit 6 */
2187                 "Illegal register address",     /* APIC Error Bit 7 */
2188         };
2189         u32 v, i = 0;
2190 
2191         entering_irq();
2192         trace_error_apic_entry(ERROR_APIC_VECTOR);
2193 
2194         /* First tickle the hardware, only then report what went on. -- REW */
2195         if (lapic_get_maxlvt() > 3)     /* Due to the Pentium erratum 3AP. */
2196                 apic_write(APIC_ESR, 0);
2197         v = apic_read(APIC_ESR);
2198         ack_APIC_irq();
2199         atomic_inc(&irq_err_count);
2200 
2201         apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x",
2202                     smp_processor_id(), v);
2203 
2204         v &= 0xff;
2205         while (v) {
2206                 if (v & 0x1)
2207                         apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]);
2208                 i++;
2209                 v >>= 1;
2210         }
2211 
2212         apic_printk(APIC_DEBUG, KERN_CONT "\n");
2213 
2214         trace_error_apic_exit(ERROR_APIC_VECTOR);
2215         exiting_irq();
2216 }
2217 
2218 /**
2219  * connect_bsp_APIC - attach the APIC to the interrupt system
2220  */
2221 static void __init connect_bsp_APIC(void)
2222 {
2223 #ifdef CONFIG_X86_32
2224         if (pic_mode) {
2225                 /*
2226                  * Do not trust the local APIC being empty at bootup.
2227                  */
2228                 clear_local_APIC();
2229                 /*
2230                  * PIC mode, enable APIC mode in the IMCR, i.e.  connect BSP's
2231                  * local APIC to INT and NMI lines.
2232                  */
2233                 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
2234                                 "enabling APIC mode.\n");
2235                 imcr_pic_to_apic();
2236         }
2237 #endif
2238 }
2239 
2240 /**
2241  * disconnect_bsp_APIC - detach the APIC from the interrupt system
2242  * @virt_wire_setup:    indicates, whether virtual wire mode is selected
2243  *
2244  * Virtual wire mode is necessary to deliver legacy interrupts even when the
2245  * APIC is disabled.
2246  */
2247 void disconnect_bsp_APIC(int virt_wire_setup)
2248 {
2249         unsigned int value;
2250 
2251 #ifdef CONFIG_X86_32
2252         if (pic_mode) {
2253                 /*
2254                  * Put the board back into PIC mode (has an effect only on
2255                  * certain older boards).  Note that APIC interrupts, including
2256                  * IPIs, won't work beyond this point!  The only exception are
2257                  * INIT IPIs.
2258                  */
2259                 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
2260                                 "entering PIC mode.\n");
2261                 imcr_apic_to_pic();
2262                 return;
2263         }
2264 #endif
2265 
2266         /* Go back to Virtual Wire compatibility mode */
2267 
2268         /* For the spurious interrupt use vector F, and enable it */
2269         value = apic_read(APIC_SPIV);
2270         value &= ~APIC_VECTOR_MASK;
2271         value |= APIC_SPIV_APIC_ENABLED;
2272         value |= 0xf;
2273         apic_write(APIC_SPIV, value);
2274 
2275         if (!virt_wire_setup) {
2276                 /*
2277                  * For LVT0 make it edge triggered, active high,
2278                  * external and enabled
2279                  */
2280                 value = apic_read(APIC_LVT0);
2281                 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
2282                         APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
2283                         APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
2284                 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
2285                 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
2286                 apic_write(APIC_LVT0, value);
2287         } else {
2288                 /* Disable LVT0 */
2289                 apic_write(APIC_LVT0, APIC_LVT_MASKED);
2290         }
2291 
2292         /*
2293          * For LVT1 make it edge triggered, active high,
2294          * nmi and enabled
2295          */
2296         value = apic_read(APIC_LVT1);
2297         value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
2298                         APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
2299                         APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
2300         value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
2301         value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
2302         apic_write(APIC_LVT1, value);
2303 }
2304 
2305 /*
2306  * The number of allocated logical CPU IDs. Since logical CPU IDs are allocated
2307  * contiguously, it equals to current allocated max logical CPU ID plus 1.
2308  * All allocated CPU IDs should be in the [0, nr_logical_cpuids) range,
2309  * so the maximum of nr_logical_cpuids is nr_cpu_ids.
2310  *
2311  * NOTE: Reserve 0 for BSP.
2312  */
2313 static int nr_logical_cpuids = 1;
2314 
2315 /*
2316  * Used to store mapping between logical CPU IDs and APIC IDs.
2317  */
2318 static int cpuid_to_apicid[] = {
2319         [0 ... NR_CPUS - 1] = -1,
2320 };
2321 
2322 #ifdef CONFIG_SMP
2323 /**
2324  * apic_id_is_primary_thread - Check whether APIC ID belongs to a primary thread
2325  * @id: APIC ID to check
2326  */
2327 bool apic_id_is_primary_thread(unsigned int apicid)
2328 {
2329         u32 mask;
2330 
2331         if (smp_num_siblings == 1)
2332                 return true;
2333         /* Isolate the SMT bit(s) in the APICID and check for 0 */
2334         mask = (1U << (fls(smp_num_siblings) - 1)) - 1;
2335         return !(apicid & mask);
2336 }
2337 #endif
2338 
2339 /*
2340  * Should use this API to allocate logical CPU IDs to keep nr_logical_cpuids
2341  * and cpuid_to_apicid[] synchronized.
2342  */
2343 static int allocate_logical_cpuid(int apicid)
2344 {
2345         int i;
2346 
2347         /*
2348          * cpuid <-> apicid mapping is persistent, so when a cpu is up,
2349          * check if the kernel has allocated a cpuid for it.
2350          */
2351         for (i = 0; i < nr_logical_cpuids; i++) {
2352                 if (cpuid_to_apicid[i] == apicid)
2353                         return i;
2354         }
2355 
2356         /* Allocate a new cpuid. */
2357         if (nr_logical_cpuids >= nr_cpu_ids) {
2358                 WARN_ONCE(1, "APIC: NR_CPUS/possible_cpus limit of %u reached. "
2359                              "Processor %d/0x%x and the rest are ignored.\n",
2360                              nr_cpu_ids, nr_logical_cpuids, apicid);
2361                 return -EINVAL;
2362         }
2363 
2364         cpuid_to_apicid[nr_logical_cpuids] = apicid;
2365         return nr_logical_cpuids++;
2366 }
2367 
2368 int generic_processor_info(int apicid, int version)
2369 {
2370         int cpu, max = nr_cpu_ids;
2371         bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid,
2372                                 phys_cpu_present_map);
2373 
2374         /*
2375          * boot_cpu_physical_apicid is designed to have the apicid
2376          * returned by read_apic_id(), i.e, the apicid of the
2377          * currently booting-up processor. However, on some platforms,
2378          * it is temporarily modified by the apicid reported as BSP
2379          * through MP table. Concretely:
2380          *
2381          * - arch/x86/kernel/mpparse.c: MP_processor_info()
2382          * - arch/x86/mm/amdtopology.c: amd_numa_init()
2383          *
2384          * This function is executed with the modified
2385          * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel
2386          * parameter doesn't work to disable APs on kdump 2nd kernel.
2387          *
2388          * Since fixing handling of boot_cpu_physical_apicid requires
2389          * another discussion and tests on each platform, we leave it
2390          * for now and here we use read_apic_id() directly in this
2391          * function, generic_processor_info().
2392          */
2393         if (disabled_cpu_apicid != BAD_APICID &&
2394             disabled_cpu_apicid != read_apic_id() &&
2395             disabled_cpu_apicid == apicid) {
2396                 int thiscpu = num_processors + disabled_cpus;
2397 
2398                 pr_warning("APIC: Disabling requested cpu."
2399                            " Processor %d/0x%x ignored.\n",
2400                            thiscpu, apicid);
2401 
2402                 disabled_cpus++;
2403                 return -ENODEV;
2404         }
2405 
2406         /*
2407          * If boot cpu has not been detected yet, then only allow upto
2408          * nr_cpu_ids - 1 processors and keep one slot free for boot cpu
2409          */
2410         if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 &&
2411             apicid != boot_cpu_physical_apicid) {
2412                 int thiscpu = max + disabled_cpus - 1;
2413 
2414                 pr_warning(
2415                         "APIC: NR_CPUS/possible_cpus limit of %i almost"
2416                         " reached. Keeping one slot for boot cpu."
2417                         "  Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
2418 
2419                 disabled_cpus++;
2420                 return -ENODEV;
2421         }
2422 
2423         if (num_processors >= nr_cpu_ids) {
2424                 int thiscpu = max + disabled_cpus;
2425 
2426                 pr_warning("APIC: NR_CPUS/possible_cpus limit of %i "
2427                            "reached. Processor %d/0x%x ignored.\n",
2428                            max, thiscpu, apicid);
2429 
2430                 disabled_cpus++;
2431                 return -EINVAL;
2432         }
2433 
2434         if (apicid == boot_cpu_physical_apicid) {
2435                 /*
2436                  * x86_bios_cpu_apicid is required to have processors listed
2437                  * in same order as logical cpu numbers. Hence the first
2438                  * entry is BSP, and so on.
2439                  * boot_cpu_init() already hold bit 0 in cpu_present_mask
2440                  * for BSP.
2441                  */
2442                 cpu = 0;
2443 
2444                 /* Logical cpuid 0 is reserved for BSP. */
2445                 cpuid_to_apicid[0] = apicid;
2446         } else {
2447                 cpu = allocate_logical_cpuid(apicid);
2448                 if (cpu < 0) {
2449                         disabled_cpus++;
2450                         return -EINVAL;
2451                 }
2452         }
2453 
2454         /*
2455          * Validate version
2456          */
2457         if (version == 0x0) {
2458                 pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n",
2459                            cpu, apicid);
2460                 version = 0x10;
2461         }
2462 
2463         if (version != boot_cpu_apic_version) {
2464                 pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n",
2465                         boot_cpu_apic_version, cpu, version);
2466         }
2467 
2468         if (apicid > max_physical_apicid)
2469                 max_physical_apicid = apicid;
2470 
2471 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
2472         early_per_cpu(x86_cpu_to_apicid, cpu) = apicid;
2473         early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
2474 #endif
2475 #ifdef CONFIG_X86_32
2476         early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
2477                 apic->x86_32_early_logical_apicid(cpu);
2478 #endif
2479         set_cpu_possible(cpu, true);
2480         physid_set(apicid, phys_cpu_present_map);
2481         set_cpu_present(cpu, true);
2482         num_processors++;
2483 
2484         return cpu;
2485 }
2486 
2487 int hard_smp_processor_id(void)
2488 {
2489         return read_apic_id();
2490 }
2491 
2492 /*
2493  * Override the generic EOI implementation with an optimized version.
2494  * Only called during early boot when only one CPU is active and with
2495  * interrupts disabled, so we know this does not race with actual APIC driver
2496  * use.
2497  */
2498 void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v))
2499 {
2500         struct apic **drv;
2501 
2502         for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) {
2503                 /* Should happen once for each apic */
2504                 WARN_ON((*drv)->eoi_write == eoi_write);
2505                 (*drv)->native_eoi_write = (*drv)->eoi_write;
2506                 (*drv)->eoi_write = eoi_write;
2507         }
2508 }
2509 
2510 static void __init apic_bsp_up_setup(void)
2511 {
2512 #ifdef CONFIG_X86_64
2513         apic_write(APIC_ID, apic->set_apic_id(boot_cpu_physical_apicid));
2514 #else
2515         /*
2516          * Hack: In case of kdump, after a crash, kernel might be booting
2517          * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
2518          * might be zero if read from MP tables. Get it from LAPIC.
2519          */
2520 # ifdef CONFIG_CRASH_DUMP
2521         boot_cpu_physical_apicid = read_apic_id();
2522 # endif
2523 #endif
2524         physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
2525 }
2526 
2527 /**
2528  * apic_bsp_setup - Setup function for local apic and io-apic
2529  * @upmode:             Force UP mode (for APIC_init_uniprocessor)
2530  */
2531 static void __init apic_bsp_setup(bool upmode)
2532 {
2533         connect_bsp_APIC();
2534         if (upmode)
2535                 apic_bsp_up_setup();
2536         setup_local_APIC();
2537 
2538         enable_IO_APIC();
2539         end_local_APIC_setup();
2540         irq_remap_enable_fault_handling();
2541         setup_IO_APIC();
2542 }
2543 
2544 #ifdef CONFIG_UP_LATE_INIT
2545 void __init up_late_init(void)
2546 {
2547         if (apic_intr_mode == APIC_PIC)
2548                 return;
2549 
2550         /* Setup local timer */
2551         x86_init.timers.setup_percpu_clockev();
2552 }
2553 #endif
2554 
2555 /*
2556  * Power management
2557  */
2558 #ifdef CONFIG_PM
2559 
2560 static struct {
2561         /*
2562          * 'active' is true if the local APIC was enabled by us and
2563          * not the BIOS; this signifies that we are also responsible
2564          * for disabling it before entering apm/acpi suspend
2565          */
2566         int active;
2567         /* r/w apic fields */
2568         unsigned int apic_id;
2569         unsigned int apic_taskpri;
2570         unsigned int apic_ldr;
2571         unsigned int apic_dfr;
2572         unsigned int apic_spiv;
2573         unsigned int apic_lvtt;
2574         unsigned int apic_lvtpc;
2575         unsigned int apic_lvt0;
2576         unsigned int apic_lvt1;
2577         unsigned int apic_lvterr;
2578         unsigned int apic_tmict;
2579         unsigned int apic_tdcr;
2580         unsigned int apic_thmr;
2581         unsigned int apic_cmci;
2582 } apic_pm_state;
2583 
2584 static int lapic_suspend(void)
2585 {
2586         unsigned long flags;
2587         int maxlvt;
2588 
2589         if (!apic_pm_state.active)
2590                 return 0;
2591 
2592         maxlvt = lapic_get_maxlvt();
2593 
2594         apic_pm_state.apic_id = apic_read(APIC_ID);
2595         apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
2596         apic_pm_state.apic_ldr = apic_read(APIC_LDR);
2597         apic_pm_state.apic_dfr = apic_read(APIC_DFR);
2598         apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
2599         apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
2600         if (maxlvt >= 4)
2601                 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
2602         apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
2603         apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
2604         apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
2605         apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
2606         apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
2607 #ifdef CONFIG_X86_THERMAL_VECTOR
2608         if (maxlvt >= 5)
2609                 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
2610 #endif
2611 #ifdef CONFIG_X86_MCE_INTEL
2612         if (maxlvt >= 6)
2613                 apic_pm_state.apic_cmci = apic_read(APIC_LVTCMCI);
2614 #endif
2615 
2616         local_irq_save(flags);
2617         disable_local_APIC();
2618 
2619         irq_remapping_disable();
2620 
2621         local_irq_restore(flags);
2622         return 0;
2623 }
2624 
2625 static void lapic_resume(void)
2626 {
2627         unsigned int l, h;
2628         unsigned long flags;
2629         int maxlvt;
2630 
2631         if (!apic_pm_state.active)
2632                 return;
2633 
2634         local_irq_save(flags);
2635 
2636         /*
2637          * IO-APIC and PIC have their own resume routines.
2638          * We just mask them here to make sure the interrupt
2639          * subsystem is completely quiet while we enable x2apic
2640          * and interrupt-remapping.
2641          */
2642         mask_ioapic_entries();
2643         legacy_pic->mask_all();
2644 
2645         if (x2apic_mode) {
2646                 __x2apic_enable();
2647         } else {
2648                 /*
2649                  * Make sure the APICBASE points to the right address
2650                  *
2651                  * FIXME! This will be wrong if we ever support suspend on
2652                  * SMP! We'll need to do this as part of the CPU restore!
2653                  */
2654                 if (boot_cpu_data.x86 >= 6) {
2655                         rdmsr(MSR_IA32_APICBASE, l, h);
2656                         l &= ~MSR_IA32_APICBASE_BASE;
2657                         l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
2658                         wrmsr(MSR_IA32_APICBASE, l, h);
2659                 }
2660         }
2661 
2662         maxlvt = lapic_get_maxlvt();
2663         apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
2664         apic_write(APIC_ID, apic_pm_state.apic_id);
2665         apic_write(APIC_DFR, apic_pm_state.apic_dfr);
2666         apic_write(APIC_LDR, apic_pm_state.apic_ldr);
2667         apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
2668         apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
2669         apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
2670         apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
2671 #ifdef CONFIG_X86_THERMAL_VECTOR
2672         if (maxlvt >= 5)
2673                 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
2674 #endif
2675 #ifdef CONFIG_X86_MCE_INTEL
2676         if (maxlvt >= 6)
2677                 apic_write(APIC_LVTCMCI, apic_pm_state.apic_cmci);
2678 #endif
2679         if (maxlvt >= 4)
2680                 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
2681         apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
2682         apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
2683         apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
2684         apic_write(APIC_ESR, 0);
2685         apic_read(APIC_ESR);
2686         apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
2687         apic_write(APIC_ESR, 0);
2688         apic_read(APIC_ESR);
2689 
2690         irq_remapping_reenable(x2apic_mode);
2691 
2692         local_irq_restore(flags);
2693 }
2694 
2695 /*
2696  * This device has no shutdown method - fully functioning local APICs
2697  * are needed on every CPU up until machine_halt/restart/poweroff.
2698  */
2699 
2700 static struct syscore_ops lapic_syscore_ops = {
2701         .resume         = lapic_resume,
2702         .suspend        = lapic_suspend,
2703 };
2704 
2705 static void apic_pm_activate(void)
2706 {
2707         apic_pm_state.active = 1;
2708 }
2709 
2710 static int __init init_lapic_sysfs(void)
2711 {
2712         /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2713         if (boot_cpu_has(X86_FEATURE_APIC))
2714                 register_syscore_ops(&lapic_syscore_ops);
2715 
2716         return 0;
2717 }
2718 
2719 /* local apic needs to resume before other devices access its registers. */
2720 core_initcall(init_lapic_sysfs);
2721 
2722 #else   /* CONFIG_PM */
2723 
2724 static void apic_pm_activate(void) { }
2725 
2726 #endif  /* CONFIG_PM */
2727 
2728 #ifdef CONFIG_X86_64
2729 
2730 static int multi_checked;
2731 static int multi;
2732 
2733 static int set_multi(const struct dmi_system_id *d)
2734 {
2735         if (multi)
2736                 return 0;
2737         pr_info("APIC: %s detected, Multi Chassis\n", d->ident);
2738         multi = 1;
2739         return 0;
2740 }
2741 
2742 static const struct dmi_system_id multi_dmi_table[] = {
2743         {
2744                 .callback = set_multi,
2745                 .ident = "IBM System Summit2",
2746                 .matches = {
2747                         DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
2748                         DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"),
2749                 },
2750         },
2751         {}
2752 };
2753 
2754 static void dmi_check_multi(void)
2755 {
2756         if (multi_checked)
2757                 return;
2758 
2759         dmi_check_system(multi_dmi_table);
2760         multi_checked = 1;
2761 }
2762 
2763 /*
2764  * apic_is_clustered_box() -- Check if we can expect good TSC
2765  *
2766  * Thus far, the major user of this is IBM's Summit2 series:
2767  * Clustered boxes may have unsynced TSC problems if they are
2768  * multi-chassis.
2769  * Use DMI to check them
2770  */
2771 int apic_is_clustered_box(void)
2772 {
2773         dmi_check_multi();
2774         return multi;
2775 }
2776 #endif
2777 
2778 /*
2779  * APIC command line parameters
2780  */
2781 static int __init setup_disableapic(char *arg)
2782 {
2783         disable_apic = 1;
2784         setup_clear_cpu_cap(X86_FEATURE_APIC);
2785         return 0;
2786 }
2787 early_param("disableapic", setup_disableapic);
2788 
2789 /* same as disableapic, for compatibility */
2790 static int __init setup_nolapic(char *arg)
2791 {
2792         return setup_disableapic(arg);
2793 }
2794 early_param("nolapic", setup_nolapic);
2795 
2796 static int __init parse_lapic_timer_c2_ok(char *arg)
2797 {
2798         local_apic_timer_c2_ok = 1;
2799         return 0;
2800 }
2801 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
2802 
2803 static int __init parse_disable_apic_timer(char *arg)
2804 {
2805         disable_apic_timer = 1;
2806         return 0;
2807 }
2808 early_param("noapictimer", parse_disable_apic_timer);
2809 
2810 static int __init parse_nolapic_timer(char *arg)
2811 {
2812         disable_apic_timer = 1;
2813         return 0;
2814 }
2815 early_param("nolapic_timer", parse_nolapic_timer);
2816 
2817 static int __init apic_set_verbosity(char *arg)
2818 {
2819         if (!arg)  {
2820 #ifdef CONFIG_X86_64
2821                 skip_ioapic_setup = 0;
2822                 return 0;
2823 #endif
2824                 return -EINVAL;
2825         }
2826 
2827         if (strcmp("debug", arg) == 0)
2828                 apic_verbosity = APIC_DEBUG;
2829         else if (strcmp("verbose", arg) == 0)
2830                 apic_verbosity = APIC_VERBOSE;
2831 #ifdef CONFIG_X86_64
2832         else {
2833                 pr_warning("APIC Verbosity level %s not recognised"
2834                         " use apic=verbose or apic=debug\n", arg);
2835                 return -EINVAL;
2836         }
2837 #endif
2838 
2839         return 0;
2840 }
2841 early_param("apic", apic_set_verbosity);
2842 
2843 static int __init lapic_insert_resource(void)
2844 {
2845         if (!apic_phys)
2846                 return -1;
2847 
2848         /* Put local APIC into the resource map. */
2849         lapic_resource.start = apic_phys;
2850         lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
2851         insert_resource(&iomem_resource, &lapic_resource);
2852 
2853         return 0;
2854 }
2855 
2856 /*
2857  * need call insert after e820__reserve_resources()
2858  * that is using request_resource
2859  */
2860 late_initcall(lapic_insert_resource);
2861 
2862 static int __init apic_set_disabled_cpu_apicid(char *arg)
2863 {
2864         if (!arg || !get_option(&arg, &disabled_cpu_apicid))
2865                 return -EINVAL;
2866 
2867         return 0;
2868 }
2869 early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid);
2870 
2871 static int __init apic_set_extnmi(char *arg)
2872 {
2873         if (!arg)
2874                 return -EINVAL;
2875 
2876         if (!strncmp("all", arg, 3))
2877                 apic_extnmi = APIC_EXTNMI_ALL;
2878         else if (!strncmp("none", arg, 4))
2879                 apic_extnmi = APIC_EXTNMI_NONE;
2880         else if (!strncmp("bsp", arg, 3))
2881                 apic_extnmi = APIC_EXTNMI_BSP;
2882         else {
2883                 pr_warn("Unknown external NMI delivery mode `%s' ignored\n", arg);
2884                 return -EINVAL;
2885         }
2886 
2887         return 0;
2888 }
2889 early_param("apic_extnmi", apic_set_extnmi);
2890 

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