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Linux/arch/x86/kernel/apic/vector.c

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  1 /*
  2  * Local APIC related interfaces to support IOAPIC, MSI, etc.
  3  *
  4  * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
  5  *      Moved from arch/x86/kernel/apic/io_apic.c.
  6  * Jiang Liu <jiang.liu@linux.intel.com>
  7  *      Enable support of hierarchical irqdomains
  8  *
  9  * This program is free software; you can redistribute it and/or modify
 10  * it under the terms of the GNU General Public License version 2 as
 11  * published by the Free Software Foundation.
 12  */
 13 #include <linux/interrupt.h>
 14 #include <linux/irq.h>
 15 #include <linux/seq_file.h>
 16 #include <linux/init.h>
 17 #include <linux/compiler.h>
 18 #include <linux/slab.h>
 19 #include <asm/irqdomain.h>
 20 #include <asm/hw_irq.h>
 21 #include <asm/apic.h>
 22 #include <asm/i8259.h>
 23 #include <asm/desc.h>
 24 #include <asm/irq_remapping.h>
 25 
 26 #include <asm/trace/irq_vectors.h>
 27 
 28 struct apic_chip_data {
 29         struct irq_cfg          hw_irq_cfg;
 30         unsigned int            vector;
 31         unsigned int            prev_vector;
 32         unsigned int            cpu;
 33         unsigned int            prev_cpu;
 34         unsigned int            irq;
 35         struct hlist_node       clist;
 36         unsigned int            move_in_progress        : 1,
 37                                 is_managed              : 1,
 38                                 can_reserve             : 1,
 39                                 has_reserved            : 1;
 40 };
 41 
 42 struct irq_domain *x86_vector_domain;
 43 EXPORT_SYMBOL_GPL(x86_vector_domain);
 44 static DEFINE_RAW_SPINLOCK(vector_lock);
 45 static cpumask_var_t vector_searchmask;
 46 static struct irq_chip lapic_controller;
 47 static struct irq_matrix *vector_matrix;
 48 #ifdef CONFIG_SMP
 49 static DEFINE_PER_CPU(struct hlist_head, cleanup_list);
 50 #endif
 51 
 52 void lock_vector_lock(void)
 53 {
 54         /* Used to the online set of cpus does not change
 55          * during assign_irq_vector.
 56          */
 57         raw_spin_lock(&vector_lock);
 58 }
 59 
 60 void unlock_vector_lock(void)
 61 {
 62         raw_spin_unlock(&vector_lock);
 63 }
 64 
 65 void init_irq_alloc_info(struct irq_alloc_info *info,
 66                          const struct cpumask *mask)
 67 {
 68         memset(info, 0, sizeof(*info));
 69         info->mask = mask;
 70 }
 71 
 72 void copy_irq_alloc_info(struct irq_alloc_info *dst, struct irq_alloc_info *src)
 73 {
 74         if (src)
 75                 *dst = *src;
 76         else
 77                 memset(dst, 0, sizeof(*dst));
 78 }
 79 
 80 static struct apic_chip_data *apic_chip_data(struct irq_data *irqd)
 81 {
 82         if (!irqd)
 83                 return NULL;
 84 
 85         while (irqd->parent_data)
 86                 irqd = irqd->parent_data;
 87 
 88         return irqd->chip_data;
 89 }
 90 
 91 struct irq_cfg *irqd_cfg(struct irq_data *irqd)
 92 {
 93         struct apic_chip_data *apicd = apic_chip_data(irqd);
 94 
 95         return apicd ? &apicd->hw_irq_cfg : NULL;
 96 }
 97 EXPORT_SYMBOL_GPL(irqd_cfg);
 98 
 99 struct irq_cfg *irq_cfg(unsigned int irq)
100 {
101         return irqd_cfg(irq_get_irq_data(irq));
102 }
103 
104 static struct apic_chip_data *alloc_apic_chip_data(int node)
105 {
106         struct apic_chip_data *apicd;
107 
108         apicd = kzalloc_node(sizeof(*apicd), GFP_KERNEL, node);
109         if (apicd)
110                 INIT_HLIST_NODE(&apicd->clist);
111         return apicd;
112 }
113 
114 static void free_apic_chip_data(struct apic_chip_data *apicd)
115 {
116         kfree(apicd);
117 }
118 
119 static void apic_update_irq_cfg(struct irq_data *irqd, unsigned int vector,
120                                 unsigned int cpu)
121 {
122         struct apic_chip_data *apicd = apic_chip_data(irqd);
123 
124         lockdep_assert_held(&vector_lock);
125 
126         apicd->hw_irq_cfg.vector = vector;
127         apicd->hw_irq_cfg.dest_apicid = apic->calc_dest_apicid(cpu);
128         irq_data_update_effective_affinity(irqd, cpumask_of(cpu));
129         trace_vector_config(irqd->irq, vector, cpu,
130                             apicd->hw_irq_cfg.dest_apicid);
131 }
132 
133 static void apic_update_vector(struct irq_data *irqd, unsigned int newvec,
134                                unsigned int newcpu)
135 {
136         struct apic_chip_data *apicd = apic_chip_data(irqd);
137         struct irq_desc *desc = irq_data_to_desc(irqd);
138         bool managed = irqd_affinity_is_managed(irqd);
139 
140         lockdep_assert_held(&vector_lock);
141 
142         trace_vector_update(irqd->irq, newvec, newcpu, apicd->vector,
143                             apicd->cpu);
144 
145         /*
146          * If there is no vector associated or if the associated vector is
147          * the shutdown vector, which is associated to make PCI/MSI
148          * shutdown mode work, then there is nothing to release. Clear out
149          * prev_vector for this and the offlined target case.
150          */
151         apicd->prev_vector = 0;
152         if (!apicd->vector || apicd->vector == MANAGED_IRQ_SHUTDOWN_VECTOR)
153                 goto setnew;
154         /*
155          * If the target CPU of the previous vector is online, then mark
156          * the vector as move in progress and store it for cleanup when the
157          * first interrupt on the new vector arrives. If the target CPU is
158          * offline then the regular release mechanism via the cleanup
159          * vector is not possible and the vector can be immediately freed
160          * in the underlying matrix allocator.
161          */
162         if (cpu_online(apicd->cpu)) {
163                 apicd->move_in_progress = true;
164                 apicd->prev_vector = apicd->vector;
165                 apicd->prev_cpu = apicd->cpu;
166         } else {
167                 irq_matrix_free(vector_matrix, apicd->cpu, apicd->vector,
168                                 managed);
169         }
170 
171 setnew:
172         apicd->vector = newvec;
173         apicd->cpu = newcpu;
174         BUG_ON(!IS_ERR_OR_NULL(per_cpu(vector_irq, newcpu)[newvec]));
175         per_cpu(vector_irq, newcpu)[newvec] = desc;
176 }
177 
178 static void vector_assign_managed_shutdown(struct irq_data *irqd)
179 {
180         unsigned int cpu = cpumask_first(cpu_online_mask);
181 
182         apic_update_irq_cfg(irqd, MANAGED_IRQ_SHUTDOWN_VECTOR, cpu);
183 }
184 
185 static int reserve_managed_vector(struct irq_data *irqd)
186 {
187         const struct cpumask *affmsk = irq_data_get_affinity_mask(irqd);
188         struct apic_chip_data *apicd = apic_chip_data(irqd);
189         unsigned long flags;
190         int ret;
191 
192         raw_spin_lock_irqsave(&vector_lock, flags);
193         apicd->is_managed = true;
194         ret = irq_matrix_reserve_managed(vector_matrix, affmsk);
195         raw_spin_unlock_irqrestore(&vector_lock, flags);
196         trace_vector_reserve_managed(irqd->irq, ret);
197         return ret;
198 }
199 
200 static void reserve_irq_vector_locked(struct irq_data *irqd)
201 {
202         struct apic_chip_data *apicd = apic_chip_data(irqd);
203 
204         irq_matrix_reserve(vector_matrix);
205         apicd->can_reserve = true;
206         apicd->has_reserved = true;
207         irqd_set_can_reserve(irqd);
208         trace_vector_reserve(irqd->irq, 0);
209         vector_assign_managed_shutdown(irqd);
210 }
211 
212 static int reserve_irq_vector(struct irq_data *irqd)
213 {
214         unsigned long flags;
215 
216         raw_spin_lock_irqsave(&vector_lock, flags);
217         reserve_irq_vector_locked(irqd);
218         raw_spin_unlock_irqrestore(&vector_lock, flags);
219         return 0;
220 }
221 
222 static int allocate_vector(struct irq_data *irqd, const struct cpumask *dest)
223 {
224         struct apic_chip_data *apicd = apic_chip_data(irqd);
225         bool resvd = apicd->has_reserved;
226         unsigned int cpu = apicd->cpu;
227         int vector = apicd->vector;
228 
229         lockdep_assert_held(&vector_lock);
230 
231         /*
232          * If the current target CPU is online and in the new requested
233          * affinity mask, there is no point in moving the interrupt from
234          * one CPU to another.
235          */
236         if (vector && cpu_online(cpu) && cpumask_test_cpu(cpu, dest))
237                 return 0;
238 
239         /*
240          * Careful here. @apicd might either have move_in_progress set or
241          * be enqueued for cleanup. Assigning a new vector would either
242          * leave a stale vector on some CPU around or in case of a pending
243          * cleanup corrupt the hlist.
244          */
245         if (apicd->move_in_progress || !hlist_unhashed(&apicd->clist))
246                 return -EBUSY;
247 
248         vector = irq_matrix_alloc(vector_matrix, dest, resvd, &cpu);
249         if (vector > 0)
250                 apic_update_vector(irqd, vector, cpu);
251         trace_vector_alloc(irqd->irq, vector, resvd, vector);
252         return vector;
253 }
254 
255 static int assign_vector_locked(struct irq_data *irqd,
256                                 const struct cpumask *dest)
257 {
258         struct apic_chip_data *apicd = apic_chip_data(irqd);
259         int vector = allocate_vector(irqd, dest);
260 
261         if (vector < 0)
262                 return vector;
263 
264         apic_update_irq_cfg(irqd, apicd->vector, apicd->cpu);
265         return 0;
266 }
267 
268 static int assign_irq_vector(struct irq_data *irqd, const struct cpumask *dest)
269 {
270         unsigned long flags;
271         int ret;
272 
273         raw_spin_lock_irqsave(&vector_lock, flags);
274         cpumask_and(vector_searchmask, dest, cpu_online_mask);
275         ret = assign_vector_locked(irqd, vector_searchmask);
276         raw_spin_unlock_irqrestore(&vector_lock, flags);
277         return ret;
278 }
279 
280 static int assign_irq_vector_any_locked(struct irq_data *irqd)
281 {
282         /* Get the affinity mask - either irq_default_affinity or (user) set */
283         const struct cpumask *affmsk = irq_data_get_affinity_mask(irqd);
284         int node = irq_data_get_node(irqd);
285 
286         if (node == NUMA_NO_NODE)
287                 goto all;
288         /* Try the intersection of @affmsk and node mask */
289         cpumask_and(vector_searchmask, cpumask_of_node(node), affmsk);
290         if (!assign_vector_locked(irqd, vector_searchmask))
291                 return 0;
292         /* Try the node mask */
293         if (!assign_vector_locked(irqd, cpumask_of_node(node)))
294                 return 0;
295 all:
296         /* Try the full affinity mask */
297         cpumask_and(vector_searchmask, affmsk, cpu_online_mask);
298         if (!assign_vector_locked(irqd, vector_searchmask))
299                 return 0;
300         /* Try the full online mask */
301         return assign_vector_locked(irqd, cpu_online_mask);
302 }
303 
304 static int
305 assign_irq_vector_policy(struct irq_data *irqd, struct irq_alloc_info *info)
306 {
307         if (irqd_affinity_is_managed(irqd))
308                 return reserve_managed_vector(irqd);
309         if (info->mask)
310                 return assign_irq_vector(irqd, info->mask);
311         /*
312          * Make only a global reservation with no guarantee. A real vector
313          * is associated at activation time.
314          */
315         return reserve_irq_vector(irqd);
316 }
317 
318 static int
319 assign_managed_vector(struct irq_data *irqd, const struct cpumask *dest)
320 {
321         const struct cpumask *affmsk = irq_data_get_affinity_mask(irqd);
322         struct apic_chip_data *apicd = apic_chip_data(irqd);
323         int vector, cpu;
324 
325         cpumask_and(vector_searchmask, vector_searchmask, affmsk);
326         cpu = cpumask_first(vector_searchmask);
327         if (cpu >= nr_cpu_ids)
328                 return -EINVAL;
329         /* set_affinity might call here for nothing */
330         if (apicd->vector && cpumask_test_cpu(apicd->cpu, vector_searchmask))
331                 return 0;
332         vector = irq_matrix_alloc_managed(vector_matrix, cpu);
333         trace_vector_alloc_managed(irqd->irq, vector, vector);
334         if (vector < 0)
335                 return vector;
336         apic_update_vector(irqd, vector, cpu);
337         apic_update_irq_cfg(irqd, vector, cpu);
338         return 0;
339 }
340 
341 static void clear_irq_vector(struct irq_data *irqd)
342 {
343         struct apic_chip_data *apicd = apic_chip_data(irqd);
344         bool managed = irqd_affinity_is_managed(irqd);
345         unsigned int vector = apicd->vector;
346 
347         lockdep_assert_held(&vector_lock);
348 
349         if (!vector)
350                 return;
351 
352         trace_vector_clear(irqd->irq, vector, apicd->cpu, apicd->prev_vector,
353                            apicd->prev_cpu);
354 
355         per_cpu(vector_irq, apicd->cpu)[vector] = VECTOR_UNUSED;
356         irq_matrix_free(vector_matrix, apicd->cpu, vector, managed);
357         apicd->vector = 0;
358 
359         /* Clean up move in progress */
360         vector = apicd->prev_vector;
361         if (!vector)
362                 return;
363 
364         per_cpu(vector_irq, apicd->prev_cpu)[vector] = VECTOR_UNUSED;
365         irq_matrix_free(vector_matrix, apicd->prev_cpu, vector, managed);
366         apicd->prev_vector = 0;
367         apicd->move_in_progress = 0;
368         hlist_del_init(&apicd->clist);
369 }
370 
371 static void x86_vector_deactivate(struct irq_domain *dom, struct irq_data *irqd)
372 {
373         struct apic_chip_data *apicd = apic_chip_data(irqd);
374         unsigned long flags;
375 
376         trace_vector_deactivate(irqd->irq, apicd->is_managed,
377                                 apicd->can_reserve, false);
378 
379         /* Regular fixed assigned interrupt */
380         if (!apicd->is_managed && !apicd->can_reserve)
381                 return;
382         /* If the interrupt has a global reservation, nothing to do */
383         if (apicd->has_reserved)
384                 return;
385 
386         raw_spin_lock_irqsave(&vector_lock, flags);
387         clear_irq_vector(irqd);
388         if (apicd->can_reserve)
389                 reserve_irq_vector_locked(irqd);
390         else
391                 vector_assign_managed_shutdown(irqd);
392         raw_spin_unlock_irqrestore(&vector_lock, flags);
393 }
394 
395 static int activate_reserved(struct irq_data *irqd)
396 {
397         struct apic_chip_data *apicd = apic_chip_data(irqd);
398         int ret;
399 
400         ret = assign_irq_vector_any_locked(irqd);
401         if (!ret) {
402                 apicd->has_reserved = false;
403                 /*
404                  * Core might have disabled reservation mode after
405                  * allocating the irq descriptor. Ideally this should
406                  * happen before allocation time, but that would require
407                  * completely convoluted ways of transporting that
408                  * information.
409                  */
410                 if (!irqd_can_reserve(irqd))
411                         apicd->can_reserve = false;
412         }
413         return ret;
414 }
415 
416 static int activate_managed(struct irq_data *irqd)
417 {
418         const struct cpumask *dest = irq_data_get_affinity_mask(irqd);
419         int ret;
420 
421         cpumask_and(vector_searchmask, dest, cpu_online_mask);
422         if (WARN_ON_ONCE(cpumask_empty(vector_searchmask))) {
423                 /* Something in the core code broke! Survive gracefully */
424                 pr_err("Managed startup for irq %u, but no CPU\n", irqd->irq);
425                 return -EINVAL;
426         }
427 
428         ret = assign_managed_vector(irqd, vector_searchmask);
429         /*
430          * This should not happen. The vector reservation got buggered.  Handle
431          * it gracefully.
432          */
433         if (WARN_ON_ONCE(ret < 0)) {
434                 pr_err("Managed startup irq %u, no vector available\n",
435                        irqd->irq);
436         }
437        return ret;
438 }
439 
440 static int x86_vector_activate(struct irq_domain *dom, struct irq_data *irqd,
441                                bool reserve)
442 {
443         struct apic_chip_data *apicd = apic_chip_data(irqd);
444         unsigned long flags;
445         int ret = 0;
446 
447         trace_vector_activate(irqd->irq, apicd->is_managed,
448                               apicd->can_reserve, reserve);
449 
450         /* Nothing to do for fixed assigned vectors */
451         if (!apicd->can_reserve && !apicd->is_managed)
452                 return 0;
453 
454         raw_spin_lock_irqsave(&vector_lock, flags);
455         if (reserve || irqd_is_managed_and_shutdown(irqd))
456                 vector_assign_managed_shutdown(irqd);
457         else if (apicd->is_managed)
458                 ret = activate_managed(irqd);
459         else if (apicd->has_reserved)
460                 ret = activate_reserved(irqd);
461         raw_spin_unlock_irqrestore(&vector_lock, flags);
462         return ret;
463 }
464 
465 static void vector_free_reserved_and_managed(struct irq_data *irqd)
466 {
467         const struct cpumask *dest = irq_data_get_affinity_mask(irqd);
468         struct apic_chip_data *apicd = apic_chip_data(irqd);
469 
470         trace_vector_teardown(irqd->irq, apicd->is_managed,
471                               apicd->has_reserved);
472 
473         if (apicd->has_reserved)
474                 irq_matrix_remove_reserved(vector_matrix);
475         if (apicd->is_managed)
476                 irq_matrix_remove_managed(vector_matrix, dest);
477 }
478 
479 static void x86_vector_free_irqs(struct irq_domain *domain,
480                                  unsigned int virq, unsigned int nr_irqs)
481 {
482         struct apic_chip_data *apicd;
483         struct irq_data *irqd;
484         unsigned long flags;
485         int i;
486 
487         for (i = 0; i < nr_irqs; i++) {
488                 irqd = irq_domain_get_irq_data(x86_vector_domain, virq + i);
489                 if (irqd && irqd->chip_data) {
490                         raw_spin_lock_irqsave(&vector_lock, flags);
491                         clear_irq_vector(irqd);
492                         vector_free_reserved_and_managed(irqd);
493                         apicd = irqd->chip_data;
494                         irq_domain_reset_irq_data(irqd);
495                         raw_spin_unlock_irqrestore(&vector_lock, flags);
496                         free_apic_chip_data(apicd);
497                 }
498         }
499 }
500 
501 static bool vector_configure_legacy(unsigned int virq, struct irq_data *irqd,
502                                     struct apic_chip_data *apicd)
503 {
504         unsigned long flags;
505         bool realloc = false;
506 
507         apicd->vector = ISA_IRQ_VECTOR(virq);
508         apicd->cpu = 0;
509 
510         raw_spin_lock_irqsave(&vector_lock, flags);
511         /*
512          * If the interrupt is activated, then it must stay at this vector
513          * position. That's usually the timer interrupt (0).
514          */
515         if (irqd_is_activated(irqd)) {
516                 trace_vector_setup(virq, true, 0);
517                 apic_update_irq_cfg(irqd, apicd->vector, apicd->cpu);
518         } else {
519                 /* Release the vector */
520                 apicd->can_reserve = true;
521                 irqd_set_can_reserve(irqd);
522                 clear_irq_vector(irqd);
523                 realloc = true;
524         }
525         raw_spin_unlock_irqrestore(&vector_lock, flags);
526         return realloc;
527 }
528 
529 static int x86_vector_alloc_irqs(struct irq_domain *domain, unsigned int virq,
530                                  unsigned int nr_irqs, void *arg)
531 {
532         struct irq_alloc_info *info = arg;
533         struct apic_chip_data *apicd;
534         struct irq_data *irqd;
535         int i, err, node;
536 
537         if (disable_apic)
538                 return -ENXIO;
539 
540         /* Currently vector allocator can't guarantee contiguous allocations */
541         if ((info->flags & X86_IRQ_ALLOC_CONTIGUOUS_VECTORS) && nr_irqs > 1)
542                 return -ENOSYS;
543 
544         for (i = 0; i < nr_irqs; i++) {
545                 irqd = irq_domain_get_irq_data(domain, virq + i);
546                 BUG_ON(!irqd);
547                 node = irq_data_get_node(irqd);
548                 WARN_ON_ONCE(irqd->chip_data);
549                 apicd = alloc_apic_chip_data(node);
550                 if (!apicd) {
551                         err = -ENOMEM;
552                         goto error;
553                 }
554 
555                 apicd->irq = virq + i;
556                 irqd->chip = &lapic_controller;
557                 irqd->chip_data = apicd;
558                 irqd->hwirq = virq + i;
559                 irqd_set_single_target(irqd);
560                 /*
561                  * Legacy vectors are already assigned when the IOAPIC
562                  * takes them over. They stay on the same vector. This is
563                  * required for check_timer() to work correctly as it might
564                  * switch back to legacy mode. Only update the hardware
565                  * config.
566                  */
567                 if (info->flags & X86_IRQ_ALLOC_LEGACY) {
568                         if (!vector_configure_legacy(virq + i, irqd, apicd))
569                                 continue;
570                 }
571 
572                 err = assign_irq_vector_policy(irqd, info);
573                 trace_vector_setup(virq + i, false, err);
574                 if (err) {
575                         irqd->chip_data = NULL;
576                         free_apic_chip_data(apicd);
577                         goto error;
578                 }
579         }
580 
581         return 0;
582 
583 error:
584         x86_vector_free_irqs(domain, virq, i);
585         return err;
586 }
587 
588 #ifdef CONFIG_GENERIC_IRQ_DEBUGFS
589 static void x86_vector_debug_show(struct seq_file *m, struct irq_domain *d,
590                                   struct irq_data *irqd, int ind)
591 {
592         struct apic_chip_data apicd;
593         unsigned long flags;
594         int irq;
595 
596         if (!irqd) {
597                 irq_matrix_debug_show(m, vector_matrix, ind);
598                 return;
599         }
600 
601         irq = irqd->irq;
602         if (irq < nr_legacy_irqs() && !test_bit(irq, &io_apic_irqs)) {
603                 seq_printf(m, "%*sVector: %5d\n", ind, "", ISA_IRQ_VECTOR(irq));
604                 seq_printf(m, "%*sTarget: Legacy PIC all CPUs\n", ind, "");
605                 return;
606         }
607 
608         if (!irqd->chip_data) {
609                 seq_printf(m, "%*sVector: Not assigned\n", ind, "");
610                 return;
611         }
612 
613         raw_spin_lock_irqsave(&vector_lock, flags);
614         memcpy(&apicd, irqd->chip_data, sizeof(apicd));
615         raw_spin_unlock_irqrestore(&vector_lock, flags);
616 
617         seq_printf(m, "%*sVector: %5u\n", ind, "", apicd.vector);
618         seq_printf(m, "%*sTarget: %5u\n", ind, "", apicd.cpu);
619         if (apicd.prev_vector) {
620                 seq_printf(m, "%*sPrevious vector: %5u\n", ind, "", apicd.prev_vector);
621                 seq_printf(m, "%*sPrevious target: %5u\n", ind, "", apicd.prev_cpu);
622         }
623         seq_printf(m, "%*smove_in_progress: %u\n", ind, "", apicd.move_in_progress ? 1 : 0);
624         seq_printf(m, "%*sis_managed:       %u\n", ind, "", apicd.is_managed ? 1 : 0);
625         seq_printf(m, "%*scan_reserve:      %u\n", ind, "", apicd.can_reserve ? 1 : 0);
626         seq_printf(m, "%*shas_reserved:     %u\n", ind, "", apicd.has_reserved ? 1 : 0);
627         seq_printf(m, "%*scleanup_pending:  %u\n", ind, "", !hlist_unhashed(&apicd.clist));
628 }
629 #endif
630 
631 static const struct irq_domain_ops x86_vector_domain_ops = {
632         .alloc          = x86_vector_alloc_irqs,
633         .free           = x86_vector_free_irqs,
634         .activate       = x86_vector_activate,
635         .deactivate     = x86_vector_deactivate,
636 #ifdef CONFIG_GENERIC_IRQ_DEBUGFS
637         .debug_show     = x86_vector_debug_show,
638 #endif
639 };
640 
641 int __init arch_probe_nr_irqs(void)
642 {
643         int nr;
644 
645         if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
646                 nr_irqs = NR_VECTORS * nr_cpu_ids;
647 
648         nr = (gsi_top + nr_legacy_irqs()) + 8 * nr_cpu_ids;
649 #if defined(CONFIG_PCI_MSI)
650         /*
651          * for MSI and HT dyn irq
652          */
653         if (gsi_top <= NR_IRQS_LEGACY)
654                 nr +=  8 * nr_cpu_ids;
655         else
656                 nr += gsi_top * 16;
657 #endif
658         if (nr < nr_irqs)
659                 nr_irqs = nr;
660 
661         /*
662          * We don't know if PIC is present at this point so we need to do
663          * probe() to get the right number of legacy IRQs.
664          */
665         return legacy_pic->probe();
666 }
667 
668 void lapic_assign_legacy_vector(unsigned int irq, bool replace)
669 {
670         /*
671          * Use assign system here so it wont get accounted as allocated
672          * and moveable in the cpu hotplug check and it prevents managed
673          * irq reservation from touching it.
674          */
675         irq_matrix_assign_system(vector_matrix, ISA_IRQ_VECTOR(irq), replace);
676 }
677 
678 void __init lapic_assign_system_vectors(void)
679 {
680         unsigned int i, vector = 0;
681 
682         for_each_set_bit_from(vector, system_vectors, NR_VECTORS)
683                 irq_matrix_assign_system(vector_matrix, vector, false);
684 
685         if (nr_legacy_irqs() > 1)
686                 lapic_assign_legacy_vector(PIC_CASCADE_IR, false);
687 
688         /* System vectors are reserved, online it */
689         irq_matrix_online(vector_matrix);
690 
691         /* Mark the preallocated legacy interrupts */
692         for (i = 0; i < nr_legacy_irqs(); i++) {
693                 if (i != PIC_CASCADE_IR)
694                         irq_matrix_assign(vector_matrix, ISA_IRQ_VECTOR(i));
695         }
696 }
697 
698 int __init arch_early_irq_init(void)
699 {
700         struct fwnode_handle *fn;
701 
702         fn = irq_domain_alloc_named_fwnode("VECTOR");
703         BUG_ON(!fn);
704         x86_vector_domain = irq_domain_create_tree(fn, &x86_vector_domain_ops,
705                                                    NULL);
706         BUG_ON(x86_vector_domain == NULL);
707         irq_domain_free_fwnode(fn);
708         irq_set_default_host(x86_vector_domain);
709 
710         arch_init_msi_domain(x86_vector_domain);
711 
712         BUG_ON(!alloc_cpumask_var(&vector_searchmask, GFP_KERNEL));
713 
714         /*
715          * Allocate the vector matrix allocator data structure and limit the
716          * search area.
717          */
718         vector_matrix = irq_alloc_matrix(NR_VECTORS, FIRST_EXTERNAL_VECTOR,
719                                          FIRST_SYSTEM_VECTOR);
720         BUG_ON(!vector_matrix);
721 
722         return arch_early_ioapic_init();
723 }
724 
725 #ifdef CONFIG_SMP
726 
727 static struct irq_desc *__setup_vector_irq(int vector)
728 {
729         int isairq = vector - ISA_IRQ_VECTOR(0);
730 
731         /* Check whether the irq is in the legacy space */
732         if (isairq < 0 || isairq >= nr_legacy_irqs())
733                 return VECTOR_UNUSED;
734         /* Check whether the irq is handled by the IOAPIC */
735         if (test_bit(isairq, &io_apic_irqs))
736                 return VECTOR_UNUSED;
737         return irq_to_desc(isairq);
738 }
739 
740 /* Online the local APIC infrastructure and initialize the vectors */
741 void lapic_online(void)
742 {
743         unsigned int vector;
744 
745         lockdep_assert_held(&vector_lock);
746 
747         /* Online the vector matrix array for this CPU */
748         irq_matrix_online(vector_matrix);
749 
750         /*
751          * The interrupt affinity logic never targets interrupts to offline
752          * CPUs. The exception are the legacy PIC interrupts. In general
753          * they are only targeted to CPU0, but depending on the platform
754          * they can be distributed to any online CPU in hardware. The
755          * kernel has no influence on that. So all active legacy vectors
756          * must be installed on all CPUs. All non legacy interrupts can be
757          * cleared.
758          */
759         for (vector = 0; vector < NR_VECTORS; vector++)
760                 this_cpu_write(vector_irq[vector], __setup_vector_irq(vector));
761 }
762 
763 void lapic_offline(void)
764 {
765         lock_vector_lock();
766         irq_matrix_offline(vector_matrix);
767         unlock_vector_lock();
768 }
769 
770 static int apic_set_affinity(struct irq_data *irqd,
771                              const struct cpumask *dest, bool force)
772 {
773         struct apic_chip_data *apicd = apic_chip_data(irqd);
774         int err;
775 
776         /*
777          * Core code can call here for inactive interrupts. For inactive
778          * interrupts which use managed or reservation mode there is no
779          * point in going through the vector assignment right now as the
780          * activation will assign a vector which fits the destination
781          * cpumask. Let the core code store the destination mask and be
782          * done with it.
783          */
784         if (!irqd_is_activated(irqd) &&
785             (apicd->is_managed || apicd->can_reserve))
786                 return IRQ_SET_MASK_OK;
787 
788         raw_spin_lock(&vector_lock);
789         cpumask_and(vector_searchmask, dest, cpu_online_mask);
790         if (irqd_affinity_is_managed(irqd))
791                 err = assign_managed_vector(irqd, vector_searchmask);
792         else
793                 err = assign_vector_locked(irqd, vector_searchmask);
794         raw_spin_unlock(&vector_lock);
795         return err ? err : IRQ_SET_MASK_OK;
796 }
797 
798 #else
799 # define apic_set_affinity      NULL
800 #endif
801 
802 static int apic_retrigger_irq(struct irq_data *irqd)
803 {
804         struct apic_chip_data *apicd = apic_chip_data(irqd);
805         unsigned long flags;
806 
807         raw_spin_lock_irqsave(&vector_lock, flags);
808         apic->send_IPI(apicd->cpu, apicd->vector);
809         raw_spin_unlock_irqrestore(&vector_lock, flags);
810 
811         return 1;
812 }
813 
814 void apic_ack_irq(struct irq_data *irqd)
815 {
816         irq_move_irq(irqd);
817         ack_APIC_irq();
818 }
819 
820 void apic_ack_edge(struct irq_data *irqd)
821 {
822         irq_complete_move(irqd_cfg(irqd));
823         apic_ack_irq(irqd);
824 }
825 
826 static struct irq_chip lapic_controller = {
827         .name                   = "APIC",
828         .irq_ack                = apic_ack_edge,
829         .irq_set_affinity       = apic_set_affinity,
830         .irq_retrigger          = apic_retrigger_irq,
831 };
832 
833 #ifdef CONFIG_SMP
834 
835 static void free_moved_vector(struct apic_chip_data *apicd)
836 {
837         unsigned int vector = apicd->prev_vector;
838         unsigned int cpu = apicd->prev_cpu;
839         bool managed = apicd->is_managed;
840 
841         /*
842          * This should never happen. Managed interrupts are not
843          * migrated except on CPU down, which does not involve the
844          * cleanup vector. But try to keep the accounting correct
845          * nevertheless.
846          */
847         WARN_ON_ONCE(managed);
848 
849         trace_vector_free_moved(apicd->irq, cpu, vector, managed);
850         irq_matrix_free(vector_matrix, cpu, vector, managed);
851         per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED;
852         hlist_del_init(&apicd->clist);
853         apicd->prev_vector = 0;
854         apicd->move_in_progress = 0;
855 }
856 
857 asmlinkage __visible void __irq_entry smp_irq_move_cleanup_interrupt(void)
858 {
859         struct hlist_head *clhead = this_cpu_ptr(&cleanup_list);
860         struct apic_chip_data *apicd;
861         struct hlist_node *tmp;
862 
863         entering_ack_irq();
864         /* Prevent vectors vanishing under us */
865         raw_spin_lock(&vector_lock);
866 
867         hlist_for_each_entry_safe(apicd, tmp, clhead, clist) {
868                 unsigned int irr, vector = apicd->prev_vector;
869 
870                 /*
871                  * Paranoia: Check if the vector that needs to be cleaned
872                  * up is registered at the APICs IRR. If so, then this is
873                  * not the best time to clean it up. Clean it up in the
874                  * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
875                  * to this CPU. IRQ_MOVE_CLEANUP_VECTOR is the lowest
876                  * priority external vector, so on return from this
877                  * interrupt the device interrupt will happen first.
878                  */
879                 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
880                 if (irr & (1U << (vector % 32))) {
881                         apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
882                         continue;
883                 }
884                 free_moved_vector(apicd);
885         }
886 
887         raw_spin_unlock(&vector_lock);
888         exiting_irq();
889 }
890 
891 static void __send_cleanup_vector(struct apic_chip_data *apicd)
892 {
893         unsigned int cpu;
894 
895         raw_spin_lock(&vector_lock);
896         apicd->move_in_progress = 0;
897         cpu = apicd->prev_cpu;
898         if (cpu_online(cpu)) {
899                 hlist_add_head(&apicd->clist, per_cpu_ptr(&cleanup_list, cpu));
900                 apic->send_IPI(cpu, IRQ_MOVE_CLEANUP_VECTOR);
901         } else {
902                 apicd->prev_vector = 0;
903         }
904         raw_spin_unlock(&vector_lock);
905 }
906 
907 void send_cleanup_vector(struct irq_cfg *cfg)
908 {
909         struct apic_chip_data *apicd;
910 
911         apicd = container_of(cfg, struct apic_chip_data, hw_irq_cfg);
912         if (apicd->move_in_progress)
913                 __send_cleanup_vector(apicd);
914 }
915 
916 static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector)
917 {
918         struct apic_chip_data *apicd;
919 
920         apicd = container_of(cfg, struct apic_chip_data, hw_irq_cfg);
921         if (likely(!apicd->move_in_progress))
922                 return;
923 
924         if (vector == apicd->vector && apicd->cpu == smp_processor_id())
925                 __send_cleanup_vector(apicd);
926 }
927 
928 void irq_complete_move(struct irq_cfg *cfg)
929 {
930         __irq_complete_move(cfg, ~get_irq_regs()->orig_ax);
931 }
932 
933 /*
934  * Called from fixup_irqs() with @desc->lock held and interrupts disabled.
935  */
936 void irq_force_complete_move(struct irq_desc *desc)
937 {
938         struct apic_chip_data *apicd;
939         struct irq_data *irqd;
940         unsigned int vector;
941 
942         /*
943          * The function is called for all descriptors regardless of which
944          * irqdomain they belong to. For example if an IRQ is provided by
945          * an irq_chip as part of a GPIO driver, the chip data for that
946          * descriptor is specific to the irq_chip in question.
947          *
948          * Check first that the chip_data is what we expect
949          * (apic_chip_data) before touching it any further.
950          */
951         irqd = irq_domain_get_irq_data(x86_vector_domain,
952                                        irq_desc_get_irq(desc));
953         if (!irqd)
954                 return;
955 
956         raw_spin_lock(&vector_lock);
957         apicd = apic_chip_data(irqd);
958         if (!apicd)
959                 goto unlock;
960 
961         /*
962          * If prev_vector is empty, no action required.
963          */
964         vector = apicd->prev_vector;
965         if (!vector)
966                 goto unlock;
967 
968         /*
969          * This is tricky. If the cleanup of the old vector has not been
970          * done yet, then the following setaffinity call will fail with
971          * -EBUSY. This can leave the interrupt in a stale state.
972          *
973          * All CPUs are stuck in stop machine with interrupts disabled so
974          * calling __irq_complete_move() would be completely pointless.
975          *
976          * 1) The interrupt is in move_in_progress state. That means that we
977          *    have not seen an interrupt since the io_apic was reprogrammed to
978          *    the new vector.
979          *
980          * 2) The interrupt has fired on the new vector, but the cleanup IPIs
981          *    have not been processed yet.
982          */
983         if (apicd->move_in_progress) {
984                 /*
985                  * In theory there is a race:
986                  *
987                  * set_ioapic(new_vector) <-- Interrupt is raised before update
988                  *                            is effective, i.e. it's raised on
989                  *                            the old vector.
990                  *
991                  * So if the target cpu cannot handle that interrupt before
992                  * the old vector is cleaned up, we get a spurious interrupt
993                  * and in the worst case the ioapic irq line becomes stale.
994                  *
995                  * But in case of cpu hotplug this should be a non issue
996                  * because if the affinity update happens right before all
997                  * cpus rendevouz in stop machine, there is no way that the
998                  * interrupt can be blocked on the target cpu because all cpus
999                  * loops first with interrupts enabled in stop machine, so the
1000                  * old vector is not yet cleaned up when the interrupt fires.
1001                  *
1002                  * So the only way to run into this issue is if the delivery
1003                  * of the interrupt on the apic/system bus would be delayed
1004                  * beyond the point where the target cpu disables interrupts
1005                  * in stop machine. I doubt that it can happen, but at least
1006                  * there is a theroretical chance. Virtualization might be
1007                  * able to expose this, but AFAICT the IOAPIC emulation is not
1008                  * as stupid as the real hardware.
1009                  *
1010                  * Anyway, there is nothing we can do about that at this point
1011                  * w/o refactoring the whole fixup_irq() business completely.
1012                  * We print at least the irq number and the old vector number,
1013                  * so we have the necessary information when a problem in that
1014                  * area arises.
1015                  */
1016                 pr_warn("IRQ fixup: irq %d move in progress, old vector %d\n",
1017                         irqd->irq, vector);
1018         }
1019         free_moved_vector(apicd);
1020 unlock:
1021         raw_spin_unlock(&vector_lock);
1022 }
1023 
1024 #ifdef CONFIG_HOTPLUG_CPU
1025 /*
1026  * Note, this is not accurate accounting, but at least good enough to
1027  * prevent that the actual interrupt move will run out of vectors.
1028  */
1029 int lapic_can_unplug_cpu(void)
1030 {
1031         unsigned int rsvd, avl, tomove, cpu = smp_processor_id();
1032         int ret = 0;
1033 
1034         raw_spin_lock(&vector_lock);
1035         tomove = irq_matrix_allocated(vector_matrix);
1036         avl = irq_matrix_available(vector_matrix, true);
1037         if (avl < tomove) {
1038                 pr_warn("CPU %u has %u vectors, %u available. Cannot disable CPU\n",
1039                         cpu, tomove, avl);
1040                 ret = -ENOSPC;
1041                 goto out;
1042         }
1043         rsvd = irq_matrix_reserved(vector_matrix);
1044         if (avl < rsvd) {
1045                 pr_warn("Reserved vectors %u > available %u. IRQ request may fail\n",
1046                         rsvd, avl);
1047         }
1048 out:
1049         raw_spin_unlock(&vector_lock);
1050         return ret;
1051 }
1052 #endif /* HOTPLUG_CPU */
1053 #endif /* SMP */
1054 
1055 static void __init print_APIC_field(int base)
1056 {
1057         int i;
1058 
1059         printk(KERN_DEBUG);
1060 
1061         for (i = 0; i < 8; i++)
1062                 pr_cont("%08x", apic_read(base + i*0x10));
1063 
1064         pr_cont("\n");
1065 }
1066 
1067 static void __init print_local_APIC(void *dummy)
1068 {
1069         unsigned int i, v, ver, maxlvt;
1070         u64 icr;
1071 
1072         pr_debug("printing local APIC contents on CPU#%d/%d:\n",
1073                  smp_processor_id(), hard_smp_processor_id());
1074         v = apic_read(APIC_ID);
1075         pr_info("... APIC ID:      %08x (%01x)\n", v, read_apic_id());
1076         v = apic_read(APIC_LVR);
1077         pr_info("... APIC VERSION: %08x\n", v);
1078         ver = GET_APIC_VERSION(v);
1079         maxlvt = lapic_get_maxlvt();
1080 
1081         v = apic_read(APIC_TASKPRI);
1082         pr_debug("... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1083 
1084         /* !82489DX */
1085         if (APIC_INTEGRATED(ver)) {
1086                 if (!APIC_XAPIC(ver)) {
1087                         v = apic_read(APIC_ARBPRI);
1088                         pr_debug("... APIC ARBPRI: %08x (%02x)\n",
1089                                  v, v & APIC_ARBPRI_MASK);
1090                 }
1091                 v = apic_read(APIC_PROCPRI);
1092                 pr_debug("... APIC PROCPRI: %08x\n", v);
1093         }
1094 
1095         /*
1096          * Remote read supported only in the 82489DX and local APIC for
1097          * Pentium processors.
1098          */
1099         if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1100                 v = apic_read(APIC_RRR);
1101                 pr_debug("... APIC RRR: %08x\n", v);
1102         }
1103 
1104         v = apic_read(APIC_LDR);
1105         pr_debug("... APIC LDR: %08x\n", v);
1106         if (!x2apic_enabled()) {
1107                 v = apic_read(APIC_DFR);
1108                 pr_debug("... APIC DFR: %08x\n", v);
1109         }
1110         v = apic_read(APIC_SPIV);
1111         pr_debug("... APIC SPIV: %08x\n", v);
1112 
1113         pr_debug("... APIC ISR field:\n");
1114         print_APIC_field(APIC_ISR);
1115         pr_debug("... APIC TMR field:\n");
1116         print_APIC_field(APIC_TMR);
1117         pr_debug("... APIC IRR field:\n");
1118         print_APIC_field(APIC_IRR);
1119 
1120         /* !82489DX */
1121         if (APIC_INTEGRATED(ver)) {
1122                 /* Due to the Pentium erratum 3AP. */
1123                 if (maxlvt > 3)
1124                         apic_write(APIC_ESR, 0);
1125 
1126                 v = apic_read(APIC_ESR);
1127                 pr_debug("... APIC ESR: %08x\n", v);
1128         }
1129 
1130         icr = apic_icr_read();
1131         pr_debug("... APIC ICR: %08x\n", (u32)icr);
1132         pr_debug("... APIC ICR2: %08x\n", (u32)(icr >> 32));
1133 
1134         v = apic_read(APIC_LVTT);
1135         pr_debug("... APIC LVTT: %08x\n", v);
1136 
1137         if (maxlvt > 3) {
1138                 /* PC is LVT#4. */
1139                 v = apic_read(APIC_LVTPC);
1140                 pr_debug("... APIC LVTPC: %08x\n", v);
1141         }
1142         v = apic_read(APIC_LVT0);
1143         pr_debug("... APIC LVT0: %08x\n", v);
1144         v = apic_read(APIC_LVT1);
1145         pr_debug("... APIC LVT1: %08x\n", v);
1146 
1147         if (maxlvt > 2) {
1148                 /* ERR is LVT#3. */
1149                 v = apic_read(APIC_LVTERR);
1150                 pr_debug("... APIC LVTERR: %08x\n", v);
1151         }
1152 
1153         v = apic_read(APIC_TMICT);
1154         pr_debug("... APIC TMICT: %08x\n", v);
1155         v = apic_read(APIC_TMCCT);
1156         pr_debug("... APIC TMCCT: %08x\n", v);
1157         v = apic_read(APIC_TDCR);
1158         pr_debug("... APIC TDCR: %08x\n", v);
1159 
1160         if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
1161                 v = apic_read(APIC_EFEAT);
1162                 maxlvt = (v >> 16) & 0xff;
1163                 pr_debug("... APIC EFEAT: %08x\n", v);
1164                 v = apic_read(APIC_ECTRL);
1165                 pr_debug("... APIC ECTRL: %08x\n", v);
1166                 for (i = 0; i < maxlvt; i++) {
1167                         v = apic_read(APIC_EILVTn(i));
1168                         pr_debug("... APIC EILVT%d: %08x\n", i, v);
1169                 }
1170         }
1171         pr_cont("\n");
1172 }
1173 
1174 static void __init print_local_APICs(int maxcpu)
1175 {
1176         int cpu;
1177 
1178         if (!maxcpu)
1179                 return;
1180 
1181         preempt_disable();
1182         for_each_online_cpu(cpu) {
1183                 if (cpu >= maxcpu)
1184                         break;
1185                 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1186         }
1187         preempt_enable();
1188 }
1189 
1190 static void __init print_PIC(void)
1191 {
1192         unsigned int v;
1193         unsigned long flags;
1194 
1195         if (!nr_legacy_irqs())
1196                 return;
1197 
1198         pr_debug("\nprinting PIC contents\n");
1199 
1200         raw_spin_lock_irqsave(&i8259A_lock, flags);
1201 
1202         v = inb(0xa1) << 8 | inb(0x21);
1203         pr_debug("... PIC  IMR: %04x\n", v);
1204 
1205         v = inb(0xa0) << 8 | inb(0x20);
1206         pr_debug("... PIC  IRR: %04x\n", v);
1207 
1208         outb(0x0b, 0xa0);
1209         outb(0x0b, 0x20);
1210         v = inb(0xa0) << 8 | inb(0x20);
1211         outb(0x0a, 0xa0);
1212         outb(0x0a, 0x20);
1213 
1214         raw_spin_unlock_irqrestore(&i8259A_lock, flags);
1215 
1216         pr_debug("... PIC  ISR: %04x\n", v);
1217 
1218         v = inb(0x4d1) << 8 | inb(0x4d0);
1219         pr_debug("... PIC ELCR: %04x\n", v);
1220 }
1221 
1222 static int show_lapic __initdata = 1;
1223 static __init int setup_show_lapic(char *arg)
1224 {
1225         int num = -1;
1226 
1227         if (strcmp(arg, "all") == 0) {
1228                 show_lapic = CONFIG_NR_CPUS;
1229         } else {
1230                 get_option(&arg, &num);
1231                 if (num >= 0)
1232                         show_lapic = num;
1233         }
1234 
1235         return 1;
1236 }
1237 __setup("show_lapic=", setup_show_lapic);
1238 
1239 static int __init print_ICs(void)
1240 {
1241         if (apic_verbosity == APIC_QUIET)
1242                 return 0;
1243 
1244         print_PIC();
1245 
1246         /* don't print out if apic is not there */
1247         if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config())
1248                 return 0;
1249 
1250         print_local_APICs(show_lapic);
1251         print_IO_APICs();
1252 
1253         return 0;
1254 }
1255 
1256 late_initcall(print_ICs);
1257 

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