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TOMOYO Linux Cross Reference
Linux/arch/x86/kernel/apic/vector.c

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  1 /*
  2  * Local APIC related interfaces to support IOAPIC, MSI, etc.
  3  *
  4  * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
  5  *      Moved from arch/x86/kernel/apic/io_apic.c.
  6  * Jiang Liu <jiang.liu@linux.intel.com>
  7  *      Enable support of hierarchical irqdomains
  8  *
  9  * This program is free software; you can redistribute it and/or modify
 10  * it under the terms of the GNU General Public License version 2 as
 11  * published by the Free Software Foundation.
 12  */
 13 #include <linux/interrupt.h>
 14 #include <linux/irq.h>
 15 #include <linux/seq_file.h>
 16 #include <linux/init.h>
 17 #include <linux/compiler.h>
 18 #include <linux/slab.h>
 19 #include <asm/irqdomain.h>
 20 #include <asm/hw_irq.h>
 21 #include <asm/apic.h>
 22 #include <asm/i8259.h>
 23 #include <asm/desc.h>
 24 #include <asm/irq_remapping.h>
 25 
 26 #include <asm/trace/irq_vectors.h>
 27 
 28 struct apic_chip_data {
 29         struct irq_cfg          hw_irq_cfg;
 30         unsigned int            vector;
 31         unsigned int            prev_vector;
 32         unsigned int            cpu;
 33         unsigned int            prev_cpu;
 34         unsigned int            irq;
 35         struct hlist_node       clist;
 36         unsigned int            move_in_progress        : 1,
 37                                 is_managed              : 1,
 38                                 can_reserve             : 1,
 39                                 has_reserved            : 1;
 40 };
 41 
 42 struct irq_domain *x86_vector_domain;
 43 EXPORT_SYMBOL_GPL(x86_vector_domain);
 44 static DEFINE_RAW_SPINLOCK(vector_lock);
 45 static cpumask_var_t vector_searchmask;
 46 static struct irq_chip lapic_controller;
 47 static struct irq_matrix *vector_matrix;
 48 #ifdef CONFIG_SMP
 49 static DEFINE_PER_CPU(struct hlist_head, cleanup_list);
 50 #endif
 51 
 52 void lock_vector_lock(void)
 53 {
 54         /* Used to the online set of cpus does not change
 55          * during assign_irq_vector.
 56          */
 57         raw_spin_lock(&vector_lock);
 58 }
 59 
 60 void unlock_vector_lock(void)
 61 {
 62         raw_spin_unlock(&vector_lock);
 63 }
 64 
 65 void init_irq_alloc_info(struct irq_alloc_info *info,
 66                          const struct cpumask *mask)
 67 {
 68         memset(info, 0, sizeof(*info));
 69         info->mask = mask;
 70 }
 71 
 72 void copy_irq_alloc_info(struct irq_alloc_info *dst, struct irq_alloc_info *src)
 73 {
 74         if (src)
 75                 *dst = *src;
 76         else
 77                 memset(dst, 0, sizeof(*dst));
 78 }
 79 
 80 static struct apic_chip_data *apic_chip_data(struct irq_data *irqd)
 81 {
 82         if (!irqd)
 83                 return NULL;
 84 
 85         while (irqd->parent_data)
 86                 irqd = irqd->parent_data;
 87 
 88         return irqd->chip_data;
 89 }
 90 
 91 struct irq_cfg *irqd_cfg(struct irq_data *irqd)
 92 {
 93         struct apic_chip_data *apicd = apic_chip_data(irqd);
 94 
 95         return apicd ? &apicd->hw_irq_cfg : NULL;
 96 }
 97 EXPORT_SYMBOL_GPL(irqd_cfg);
 98 
 99 struct irq_cfg *irq_cfg(unsigned int irq)
100 {
101         return irqd_cfg(irq_get_irq_data(irq));
102 }
103 
104 static struct apic_chip_data *alloc_apic_chip_data(int node)
105 {
106         struct apic_chip_data *apicd;
107 
108         apicd = kzalloc_node(sizeof(*apicd), GFP_KERNEL, node);
109         if (apicd)
110                 INIT_HLIST_NODE(&apicd->clist);
111         return apicd;
112 }
113 
114 static void free_apic_chip_data(struct apic_chip_data *apicd)
115 {
116         kfree(apicd);
117 }
118 
119 static void apic_update_irq_cfg(struct irq_data *irqd, unsigned int vector,
120                                 unsigned int cpu)
121 {
122         struct apic_chip_data *apicd = apic_chip_data(irqd);
123 
124         lockdep_assert_held(&vector_lock);
125 
126         apicd->hw_irq_cfg.vector = vector;
127         apicd->hw_irq_cfg.dest_apicid = apic->calc_dest_apicid(cpu);
128         irq_data_update_effective_affinity(irqd, cpumask_of(cpu));
129         trace_vector_config(irqd->irq, vector, cpu,
130                             apicd->hw_irq_cfg.dest_apicid);
131 }
132 
133 static void apic_update_vector(struct irq_data *irqd, unsigned int newvec,
134                                unsigned int newcpu)
135 {
136         struct apic_chip_data *apicd = apic_chip_data(irqd);
137         struct irq_desc *desc = irq_data_to_desc(irqd);
138         bool managed = irqd_affinity_is_managed(irqd);
139 
140         lockdep_assert_held(&vector_lock);
141 
142         trace_vector_update(irqd->irq, newvec, newcpu, apicd->vector,
143                             apicd->cpu);
144 
145         /*
146          * If there is no vector associated or if the associated vector is
147          * the shutdown vector, which is associated to make PCI/MSI
148          * shutdown mode work, then there is nothing to release. Clear out
149          * prev_vector for this and the offlined target case.
150          */
151         apicd->prev_vector = 0;
152         if (!apicd->vector || apicd->vector == MANAGED_IRQ_SHUTDOWN_VECTOR)
153                 goto setnew;
154         /*
155          * If the target CPU of the previous vector is online, then mark
156          * the vector as move in progress and store it for cleanup when the
157          * first interrupt on the new vector arrives. If the target CPU is
158          * offline then the regular release mechanism via the cleanup
159          * vector is not possible and the vector can be immediately freed
160          * in the underlying matrix allocator.
161          */
162         if (cpu_online(apicd->cpu)) {
163                 apicd->move_in_progress = true;
164                 apicd->prev_vector = apicd->vector;
165                 apicd->prev_cpu = apicd->cpu;
166         } else {
167                 irq_matrix_free(vector_matrix, apicd->cpu, apicd->vector,
168                                 managed);
169         }
170 
171 setnew:
172         apicd->vector = newvec;
173         apicd->cpu = newcpu;
174         BUG_ON(!IS_ERR_OR_NULL(per_cpu(vector_irq, newcpu)[newvec]));
175         per_cpu(vector_irq, newcpu)[newvec] = desc;
176 }
177 
178 static void vector_assign_managed_shutdown(struct irq_data *irqd)
179 {
180         unsigned int cpu = cpumask_first(cpu_online_mask);
181 
182         apic_update_irq_cfg(irqd, MANAGED_IRQ_SHUTDOWN_VECTOR, cpu);
183 }
184 
185 static int reserve_managed_vector(struct irq_data *irqd)
186 {
187         const struct cpumask *affmsk = irq_data_get_affinity_mask(irqd);
188         struct apic_chip_data *apicd = apic_chip_data(irqd);
189         unsigned long flags;
190         int ret;
191 
192         raw_spin_lock_irqsave(&vector_lock, flags);
193         apicd->is_managed = true;
194         ret = irq_matrix_reserve_managed(vector_matrix, affmsk);
195         raw_spin_unlock_irqrestore(&vector_lock, flags);
196         trace_vector_reserve_managed(irqd->irq, ret);
197         return ret;
198 }
199 
200 static void reserve_irq_vector_locked(struct irq_data *irqd)
201 {
202         struct apic_chip_data *apicd = apic_chip_data(irqd);
203 
204         irq_matrix_reserve(vector_matrix);
205         apicd->can_reserve = true;
206         apicd->has_reserved = true;
207         irqd_set_can_reserve(irqd);
208         trace_vector_reserve(irqd->irq, 0);
209         vector_assign_managed_shutdown(irqd);
210 }
211 
212 static int reserve_irq_vector(struct irq_data *irqd)
213 {
214         unsigned long flags;
215 
216         raw_spin_lock_irqsave(&vector_lock, flags);
217         reserve_irq_vector_locked(irqd);
218         raw_spin_unlock_irqrestore(&vector_lock, flags);
219         return 0;
220 }
221 
222 static int
223 assign_vector_locked(struct irq_data *irqd, const struct cpumask *dest)
224 {
225         struct apic_chip_data *apicd = apic_chip_data(irqd);
226         bool resvd = apicd->has_reserved;
227         unsigned int cpu = apicd->cpu;
228         int vector = apicd->vector;
229 
230         lockdep_assert_held(&vector_lock);
231 
232         /*
233          * If the current target CPU is online and in the new requested
234          * affinity mask, there is no point in moving the interrupt from
235          * one CPU to another.
236          */
237         if (vector && cpu_online(cpu) && cpumask_test_cpu(cpu, dest))
238                 return 0;
239 
240         /*
241          * Careful here. @apicd might either have move_in_progress set or
242          * be enqueued for cleanup. Assigning a new vector would either
243          * leave a stale vector on some CPU around or in case of a pending
244          * cleanup corrupt the hlist.
245          */
246         if (apicd->move_in_progress || !hlist_unhashed(&apicd->clist))
247                 return -EBUSY;
248 
249         vector = irq_matrix_alloc(vector_matrix, dest, resvd, &cpu);
250         trace_vector_alloc(irqd->irq, vector, resvd, vector);
251         if (vector < 0)
252                 return vector;
253         apic_update_vector(irqd, vector, cpu);
254         apic_update_irq_cfg(irqd, vector, cpu);
255 
256         return 0;
257 }
258 
259 static int assign_irq_vector(struct irq_data *irqd, const struct cpumask *dest)
260 {
261         unsigned long flags;
262         int ret;
263 
264         raw_spin_lock_irqsave(&vector_lock, flags);
265         cpumask_and(vector_searchmask, dest, cpu_online_mask);
266         ret = assign_vector_locked(irqd, vector_searchmask);
267         raw_spin_unlock_irqrestore(&vector_lock, flags);
268         return ret;
269 }
270 
271 static int assign_irq_vector_any_locked(struct irq_data *irqd)
272 {
273         /* Get the affinity mask - either irq_default_affinity or (user) set */
274         const struct cpumask *affmsk = irq_data_get_affinity_mask(irqd);
275         int node = irq_data_get_node(irqd);
276 
277         if (node == NUMA_NO_NODE)
278                 goto all;
279         /* Try the intersection of @affmsk and node mask */
280         cpumask_and(vector_searchmask, cpumask_of_node(node), affmsk);
281         if (!assign_vector_locked(irqd, vector_searchmask))
282                 return 0;
283         /* Try the node mask */
284         if (!assign_vector_locked(irqd, cpumask_of_node(node)))
285                 return 0;
286 all:
287         /* Try the full affinity mask */
288         cpumask_and(vector_searchmask, affmsk, cpu_online_mask);
289         if (!assign_vector_locked(irqd, vector_searchmask))
290                 return 0;
291         /* Try the full online mask */
292         return assign_vector_locked(irqd, cpu_online_mask);
293 }
294 
295 static int
296 assign_irq_vector_policy(struct irq_data *irqd, struct irq_alloc_info *info)
297 {
298         if (irqd_affinity_is_managed(irqd))
299                 return reserve_managed_vector(irqd);
300         if (info->mask)
301                 return assign_irq_vector(irqd, info->mask);
302         /*
303          * Make only a global reservation with no guarantee. A real vector
304          * is associated at activation time.
305          */
306         return reserve_irq_vector(irqd);
307 }
308 
309 static int
310 assign_managed_vector(struct irq_data *irqd, const struct cpumask *dest)
311 {
312         const struct cpumask *affmsk = irq_data_get_affinity_mask(irqd);
313         struct apic_chip_data *apicd = apic_chip_data(irqd);
314         int vector, cpu;
315 
316         cpumask_and(vector_searchmask, dest, affmsk);
317 
318         /* set_affinity might call here for nothing */
319         if (apicd->vector && cpumask_test_cpu(apicd->cpu, vector_searchmask))
320                 return 0;
321         vector = irq_matrix_alloc_managed(vector_matrix, vector_searchmask,
322                                           &cpu);
323         trace_vector_alloc_managed(irqd->irq, vector, vector);
324         if (vector < 0)
325                 return vector;
326         apic_update_vector(irqd, vector, cpu);
327         apic_update_irq_cfg(irqd, vector, cpu);
328         return 0;
329 }
330 
331 static void clear_irq_vector(struct irq_data *irqd)
332 {
333         struct apic_chip_data *apicd = apic_chip_data(irqd);
334         bool managed = irqd_affinity_is_managed(irqd);
335         unsigned int vector = apicd->vector;
336 
337         lockdep_assert_held(&vector_lock);
338 
339         if (!vector)
340                 return;
341 
342         trace_vector_clear(irqd->irq, vector, apicd->cpu, apicd->prev_vector,
343                            apicd->prev_cpu);
344 
345         per_cpu(vector_irq, apicd->cpu)[vector] = VECTOR_UNUSED;
346         irq_matrix_free(vector_matrix, apicd->cpu, vector, managed);
347         apicd->vector = 0;
348 
349         /* Clean up move in progress */
350         vector = apicd->prev_vector;
351         if (!vector)
352                 return;
353 
354         per_cpu(vector_irq, apicd->prev_cpu)[vector] = VECTOR_UNUSED;
355         irq_matrix_free(vector_matrix, apicd->prev_cpu, vector, managed);
356         apicd->prev_vector = 0;
357         apicd->move_in_progress = 0;
358         hlist_del_init(&apicd->clist);
359 }
360 
361 static void x86_vector_deactivate(struct irq_domain *dom, struct irq_data *irqd)
362 {
363         struct apic_chip_data *apicd = apic_chip_data(irqd);
364         unsigned long flags;
365 
366         trace_vector_deactivate(irqd->irq, apicd->is_managed,
367                                 apicd->can_reserve, false);
368 
369         /* Regular fixed assigned interrupt */
370         if (!apicd->is_managed && !apicd->can_reserve)
371                 return;
372         /* If the interrupt has a global reservation, nothing to do */
373         if (apicd->has_reserved)
374                 return;
375 
376         raw_spin_lock_irqsave(&vector_lock, flags);
377         clear_irq_vector(irqd);
378         if (apicd->can_reserve)
379                 reserve_irq_vector_locked(irqd);
380         else
381                 vector_assign_managed_shutdown(irqd);
382         raw_spin_unlock_irqrestore(&vector_lock, flags);
383 }
384 
385 static int activate_reserved(struct irq_data *irqd)
386 {
387         struct apic_chip_data *apicd = apic_chip_data(irqd);
388         int ret;
389 
390         ret = assign_irq_vector_any_locked(irqd);
391         if (!ret) {
392                 apicd->has_reserved = false;
393                 /*
394                  * Core might have disabled reservation mode after
395                  * allocating the irq descriptor. Ideally this should
396                  * happen before allocation time, but that would require
397                  * completely convoluted ways of transporting that
398                  * information.
399                  */
400                 if (!irqd_can_reserve(irqd))
401                         apicd->can_reserve = false;
402         }
403         return ret;
404 }
405 
406 static int activate_managed(struct irq_data *irqd)
407 {
408         const struct cpumask *dest = irq_data_get_affinity_mask(irqd);
409         int ret;
410 
411         cpumask_and(vector_searchmask, dest, cpu_online_mask);
412         if (WARN_ON_ONCE(cpumask_empty(vector_searchmask))) {
413                 /* Something in the core code broke! Survive gracefully */
414                 pr_err("Managed startup for irq %u, but no CPU\n", irqd->irq);
415                 return -EINVAL;
416         }
417 
418         ret = assign_managed_vector(irqd, vector_searchmask);
419         /*
420          * This should not happen. The vector reservation got buggered.  Handle
421          * it gracefully.
422          */
423         if (WARN_ON_ONCE(ret < 0)) {
424                 pr_err("Managed startup irq %u, no vector available\n",
425                        irqd->irq);
426         }
427         return ret;
428 }
429 
430 static int x86_vector_activate(struct irq_domain *dom, struct irq_data *irqd,
431                                bool reserve)
432 {
433         struct apic_chip_data *apicd = apic_chip_data(irqd);
434         unsigned long flags;
435         int ret = 0;
436 
437         trace_vector_activate(irqd->irq, apicd->is_managed,
438                               apicd->can_reserve, reserve);
439 
440         /* Nothing to do for fixed assigned vectors */
441         if (!apicd->can_reserve && !apicd->is_managed)
442                 return 0;
443 
444         raw_spin_lock_irqsave(&vector_lock, flags);
445         if (reserve || irqd_is_managed_and_shutdown(irqd))
446                 vector_assign_managed_shutdown(irqd);
447         else if (apicd->is_managed)
448                 ret = activate_managed(irqd);
449         else if (apicd->has_reserved)
450                 ret = activate_reserved(irqd);
451         raw_spin_unlock_irqrestore(&vector_lock, flags);
452         return ret;
453 }
454 
455 static void vector_free_reserved_and_managed(struct irq_data *irqd)
456 {
457         const struct cpumask *dest = irq_data_get_affinity_mask(irqd);
458         struct apic_chip_data *apicd = apic_chip_data(irqd);
459 
460         trace_vector_teardown(irqd->irq, apicd->is_managed,
461                               apicd->has_reserved);
462 
463         if (apicd->has_reserved)
464                 irq_matrix_remove_reserved(vector_matrix);
465         if (apicd->is_managed)
466                 irq_matrix_remove_managed(vector_matrix, dest);
467 }
468 
469 static void x86_vector_free_irqs(struct irq_domain *domain,
470                                  unsigned int virq, unsigned int nr_irqs)
471 {
472         struct apic_chip_data *apicd;
473         struct irq_data *irqd;
474         unsigned long flags;
475         int i;
476 
477         for (i = 0; i < nr_irqs; i++) {
478                 irqd = irq_domain_get_irq_data(x86_vector_domain, virq + i);
479                 if (irqd && irqd->chip_data) {
480                         raw_spin_lock_irqsave(&vector_lock, flags);
481                         clear_irq_vector(irqd);
482                         vector_free_reserved_and_managed(irqd);
483                         apicd = irqd->chip_data;
484                         irq_domain_reset_irq_data(irqd);
485                         raw_spin_unlock_irqrestore(&vector_lock, flags);
486                         free_apic_chip_data(apicd);
487                 }
488         }
489 }
490 
491 static bool vector_configure_legacy(unsigned int virq, struct irq_data *irqd,
492                                     struct apic_chip_data *apicd)
493 {
494         unsigned long flags;
495         bool realloc = false;
496 
497         apicd->vector = ISA_IRQ_VECTOR(virq);
498         apicd->cpu = 0;
499 
500         raw_spin_lock_irqsave(&vector_lock, flags);
501         /*
502          * If the interrupt is activated, then it must stay at this vector
503          * position. That's usually the timer interrupt (0).
504          */
505         if (irqd_is_activated(irqd)) {
506                 trace_vector_setup(virq, true, 0);
507                 apic_update_irq_cfg(irqd, apicd->vector, apicd->cpu);
508         } else {
509                 /* Release the vector */
510                 apicd->can_reserve = true;
511                 irqd_set_can_reserve(irqd);
512                 clear_irq_vector(irqd);
513                 realloc = true;
514         }
515         raw_spin_unlock_irqrestore(&vector_lock, flags);
516         return realloc;
517 }
518 
519 static int x86_vector_alloc_irqs(struct irq_domain *domain, unsigned int virq,
520                                  unsigned int nr_irqs, void *arg)
521 {
522         struct irq_alloc_info *info = arg;
523         struct apic_chip_data *apicd;
524         struct irq_data *irqd;
525         int i, err, node;
526 
527         if (disable_apic)
528                 return -ENXIO;
529 
530         /* Currently vector allocator can't guarantee contiguous allocations */
531         if ((info->flags & X86_IRQ_ALLOC_CONTIGUOUS_VECTORS) && nr_irqs > 1)
532                 return -ENOSYS;
533 
534         for (i = 0; i < nr_irqs; i++) {
535                 irqd = irq_domain_get_irq_data(domain, virq + i);
536                 BUG_ON(!irqd);
537                 node = irq_data_get_node(irqd);
538                 WARN_ON_ONCE(irqd->chip_data);
539                 apicd = alloc_apic_chip_data(node);
540                 if (!apicd) {
541                         err = -ENOMEM;
542                         goto error;
543                 }
544 
545                 apicd->irq = virq + i;
546                 irqd->chip = &lapic_controller;
547                 irqd->chip_data = apicd;
548                 irqd->hwirq = virq + i;
549                 irqd_set_single_target(irqd);
550                 /*
551                  * Legacy vectors are already assigned when the IOAPIC
552                  * takes them over. They stay on the same vector. This is
553                  * required for check_timer() to work correctly as it might
554                  * switch back to legacy mode. Only update the hardware
555                  * config.
556                  */
557                 if (info->flags & X86_IRQ_ALLOC_LEGACY) {
558                         if (!vector_configure_legacy(virq + i, irqd, apicd))
559                                 continue;
560                 }
561 
562                 err = assign_irq_vector_policy(irqd, info);
563                 trace_vector_setup(virq + i, false, err);
564                 if (err) {
565                         irqd->chip_data = NULL;
566                         free_apic_chip_data(apicd);
567                         goto error;
568                 }
569         }
570 
571         return 0;
572 
573 error:
574         x86_vector_free_irqs(domain, virq, i);
575         return err;
576 }
577 
578 #ifdef CONFIG_GENERIC_IRQ_DEBUGFS
579 static void x86_vector_debug_show(struct seq_file *m, struct irq_domain *d,
580                                   struct irq_data *irqd, int ind)
581 {
582         struct apic_chip_data apicd;
583         unsigned long flags;
584         int irq;
585 
586         if (!irqd) {
587                 irq_matrix_debug_show(m, vector_matrix, ind);
588                 return;
589         }
590 
591         irq = irqd->irq;
592         if (irq < nr_legacy_irqs() && !test_bit(irq, &io_apic_irqs)) {
593                 seq_printf(m, "%*sVector: %5d\n", ind, "", ISA_IRQ_VECTOR(irq));
594                 seq_printf(m, "%*sTarget: Legacy PIC all CPUs\n", ind, "");
595                 return;
596         }
597 
598         if (!irqd->chip_data) {
599                 seq_printf(m, "%*sVector: Not assigned\n", ind, "");
600                 return;
601         }
602 
603         raw_spin_lock_irqsave(&vector_lock, flags);
604         memcpy(&apicd, irqd->chip_data, sizeof(apicd));
605         raw_spin_unlock_irqrestore(&vector_lock, flags);
606 
607         seq_printf(m, "%*sVector: %5u\n", ind, "", apicd.vector);
608         seq_printf(m, "%*sTarget: %5u\n", ind, "", apicd.cpu);
609         if (apicd.prev_vector) {
610                 seq_printf(m, "%*sPrevious vector: %5u\n", ind, "", apicd.prev_vector);
611                 seq_printf(m, "%*sPrevious target: %5u\n", ind, "", apicd.prev_cpu);
612         }
613         seq_printf(m, "%*smove_in_progress: %u\n", ind, "", apicd.move_in_progress ? 1 : 0);
614         seq_printf(m, "%*sis_managed:       %u\n", ind, "", apicd.is_managed ? 1 : 0);
615         seq_printf(m, "%*scan_reserve:      %u\n", ind, "", apicd.can_reserve ? 1 : 0);
616         seq_printf(m, "%*shas_reserved:     %u\n", ind, "", apicd.has_reserved ? 1 : 0);
617         seq_printf(m, "%*scleanup_pending:  %u\n", ind, "", !hlist_unhashed(&apicd.clist));
618 }
619 #endif
620 
621 static const struct irq_domain_ops x86_vector_domain_ops = {
622         .alloc          = x86_vector_alloc_irqs,
623         .free           = x86_vector_free_irqs,
624         .activate       = x86_vector_activate,
625         .deactivate     = x86_vector_deactivate,
626 #ifdef CONFIG_GENERIC_IRQ_DEBUGFS
627         .debug_show     = x86_vector_debug_show,
628 #endif
629 };
630 
631 int __init arch_probe_nr_irqs(void)
632 {
633         int nr;
634 
635         if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
636                 nr_irqs = NR_VECTORS * nr_cpu_ids;
637 
638         nr = (gsi_top + nr_legacy_irqs()) + 8 * nr_cpu_ids;
639 #if defined(CONFIG_PCI_MSI)
640         /*
641          * for MSI and HT dyn irq
642          */
643         if (gsi_top <= NR_IRQS_LEGACY)
644                 nr +=  8 * nr_cpu_ids;
645         else
646                 nr += gsi_top * 16;
647 #endif
648         if (nr < nr_irqs)
649                 nr_irqs = nr;
650 
651         /*
652          * We don't know if PIC is present at this point so we need to do
653          * probe() to get the right number of legacy IRQs.
654          */
655         return legacy_pic->probe();
656 }
657 
658 void lapic_assign_legacy_vector(unsigned int irq, bool replace)
659 {
660         /*
661          * Use assign system here so it wont get accounted as allocated
662          * and moveable in the cpu hotplug check and it prevents managed
663          * irq reservation from touching it.
664          */
665         irq_matrix_assign_system(vector_matrix, ISA_IRQ_VECTOR(irq), replace);
666 }
667 
668 void __init lapic_assign_system_vectors(void)
669 {
670         unsigned int i, vector = 0;
671 
672         for_each_set_bit_from(vector, system_vectors, NR_VECTORS)
673                 irq_matrix_assign_system(vector_matrix, vector, false);
674 
675         if (nr_legacy_irqs() > 1)
676                 lapic_assign_legacy_vector(PIC_CASCADE_IR, false);
677 
678         /* System vectors are reserved, online it */
679         irq_matrix_online(vector_matrix);
680 
681         /* Mark the preallocated legacy interrupts */
682         for (i = 0; i < nr_legacy_irqs(); i++) {
683                 if (i != PIC_CASCADE_IR)
684                         irq_matrix_assign(vector_matrix, ISA_IRQ_VECTOR(i));
685         }
686 }
687 
688 int __init arch_early_irq_init(void)
689 {
690         struct fwnode_handle *fn;
691 
692         fn = irq_domain_alloc_named_fwnode("VECTOR");
693         BUG_ON(!fn);
694         x86_vector_domain = irq_domain_create_tree(fn, &x86_vector_domain_ops,
695                                                    NULL);
696         BUG_ON(x86_vector_domain == NULL);
697         irq_domain_free_fwnode(fn);
698         irq_set_default_host(x86_vector_domain);
699 
700         arch_init_msi_domain(x86_vector_domain);
701 
702         BUG_ON(!alloc_cpumask_var(&vector_searchmask, GFP_KERNEL));
703 
704         /*
705          * Allocate the vector matrix allocator data structure and limit the
706          * search area.
707          */
708         vector_matrix = irq_alloc_matrix(NR_VECTORS, FIRST_EXTERNAL_VECTOR,
709                                          FIRST_SYSTEM_VECTOR);
710         BUG_ON(!vector_matrix);
711 
712         return arch_early_ioapic_init();
713 }
714 
715 #ifdef CONFIG_SMP
716 
717 static struct irq_desc *__setup_vector_irq(int vector)
718 {
719         int isairq = vector - ISA_IRQ_VECTOR(0);
720 
721         /* Check whether the irq is in the legacy space */
722         if (isairq < 0 || isairq >= nr_legacy_irqs())
723                 return VECTOR_UNUSED;
724         /* Check whether the irq is handled by the IOAPIC */
725         if (test_bit(isairq, &io_apic_irqs))
726                 return VECTOR_UNUSED;
727         return irq_to_desc(isairq);
728 }
729 
730 /* Online the local APIC infrastructure and initialize the vectors */
731 void lapic_online(void)
732 {
733         unsigned int vector;
734 
735         lockdep_assert_held(&vector_lock);
736 
737         /* Online the vector matrix array for this CPU */
738         irq_matrix_online(vector_matrix);
739 
740         /*
741          * The interrupt affinity logic never targets interrupts to offline
742          * CPUs. The exception are the legacy PIC interrupts. In general
743          * they are only targeted to CPU0, but depending on the platform
744          * they can be distributed to any online CPU in hardware. The
745          * kernel has no influence on that. So all active legacy vectors
746          * must be installed on all CPUs. All non legacy interrupts can be
747          * cleared.
748          */
749         for (vector = 0; vector < NR_VECTORS; vector++)
750                 this_cpu_write(vector_irq[vector], __setup_vector_irq(vector));
751 }
752 
753 void lapic_offline(void)
754 {
755         lock_vector_lock();
756         irq_matrix_offline(vector_matrix);
757         unlock_vector_lock();
758 }
759 
760 static int apic_set_affinity(struct irq_data *irqd,
761                              const struct cpumask *dest, bool force)
762 {
763         struct apic_chip_data *apicd = apic_chip_data(irqd);
764         int err;
765 
766         /*
767          * Core code can call here for inactive interrupts. For inactive
768          * interrupts which use managed or reservation mode there is no
769          * point in going through the vector assignment right now as the
770          * activation will assign a vector which fits the destination
771          * cpumask. Let the core code store the destination mask and be
772          * done with it.
773          */
774         if (!irqd_is_activated(irqd) &&
775             (apicd->is_managed || apicd->can_reserve))
776                 return IRQ_SET_MASK_OK;
777 
778         raw_spin_lock(&vector_lock);
779         cpumask_and(vector_searchmask, dest, cpu_online_mask);
780         if (irqd_affinity_is_managed(irqd))
781                 err = assign_managed_vector(irqd, vector_searchmask);
782         else
783                 err = assign_vector_locked(irqd, vector_searchmask);
784         raw_spin_unlock(&vector_lock);
785         return err ? err : IRQ_SET_MASK_OK;
786 }
787 
788 #else
789 # define apic_set_affinity      NULL
790 #endif
791 
792 static int apic_retrigger_irq(struct irq_data *irqd)
793 {
794         struct apic_chip_data *apicd = apic_chip_data(irqd);
795         unsigned long flags;
796 
797         raw_spin_lock_irqsave(&vector_lock, flags);
798         apic->send_IPI(apicd->cpu, apicd->vector);
799         raw_spin_unlock_irqrestore(&vector_lock, flags);
800 
801         return 1;
802 }
803 
804 void apic_ack_irq(struct irq_data *irqd)
805 {
806         irq_move_irq(irqd);
807         ack_APIC_irq();
808 }
809 
810 void apic_ack_edge(struct irq_data *irqd)
811 {
812         irq_complete_move(irqd_cfg(irqd));
813         apic_ack_irq(irqd);
814 }
815 
816 static struct irq_chip lapic_controller = {
817         .name                   = "APIC",
818         .irq_ack                = apic_ack_edge,
819         .irq_set_affinity       = apic_set_affinity,
820         .irq_retrigger          = apic_retrigger_irq,
821 };
822 
823 #ifdef CONFIG_SMP
824 
825 static void free_moved_vector(struct apic_chip_data *apicd)
826 {
827         unsigned int vector = apicd->prev_vector;
828         unsigned int cpu = apicd->prev_cpu;
829         bool managed = apicd->is_managed;
830 
831         /*
832          * This should never happen. Managed interrupts are not
833          * migrated except on CPU down, which does not involve the
834          * cleanup vector. But try to keep the accounting correct
835          * nevertheless.
836          */
837         WARN_ON_ONCE(managed);
838 
839         trace_vector_free_moved(apicd->irq, cpu, vector, managed);
840         irq_matrix_free(vector_matrix, cpu, vector, managed);
841         per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED;
842         hlist_del_init(&apicd->clist);
843         apicd->prev_vector = 0;
844         apicd->move_in_progress = 0;
845 }
846 
847 asmlinkage __visible void __irq_entry smp_irq_move_cleanup_interrupt(void)
848 {
849         struct hlist_head *clhead = this_cpu_ptr(&cleanup_list);
850         struct apic_chip_data *apicd;
851         struct hlist_node *tmp;
852 
853         entering_ack_irq();
854         /* Prevent vectors vanishing under us */
855         raw_spin_lock(&vector_lock);
856 
857         hlist_for_each_entry_safe(apicd, tmp, clhead, clist) {
858                 unsigned int irr, vector = apicd->prev_vector;
859 
860                 /*
861                  * Paranoia: Check if the vector that needs to be cleaned
862                  * up is registered at the APICs IRR. If so, then this is
863                  * not the best time to clean it up. Clean it up in the
864                  * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
865                  * to this CPU. IRQ_MOVE_CLEANUP_VECTOR is the lowest
866                  * priority external vector, so on return from this
867                  * interrupt the device interrupt will happen first.
868                  */
869                 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
870                 if (irr & (1U << (vector % 32))) {
871                         apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
872                         continue;
873                 }
874                 free_moved_vector(apicd);
875         }
876 
877         raw_spin_unlock(&vector_lock);
878         exiting_irq();
879 }
880 
881 static void __send_cleanup_vector(struct apic_chip_data *apicd)
882 {
883         unsigned int cpu;
884 
885         raw_spin_lock(&vector_lock);
886         apicd->move_in_progress = 0;
887         cpu = apicd->prev_cpu;
888         if (cpu_online(cpu)) {
889                 hlist_add_head(&apicd->clist, per_cpu_ptr(&cleanup_list, cpu));
890                 apic->send_IPI(cpu, IRQ_MOVE_CLEANUP_VECTOR);
891         } else {
892                 apicd->prev_vector = 0;
893         }
894         raw_spin_unlock(&vector_lock);
895 }
896 
897 void send_cleanup_vector(struct irq_cfg *cfg)
898 {
899         struct apic_chip_data *apicd;
900 
901         apicd = container_of(cfg, struct apic_chip_data, hw_irq_cfg);
902         if (apicd->move_in_progress)
903                 __send_cleanup_vector(apicd);
904 }
905 
906 static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector)
907 {
908         struct apic_chip_data *apicd;
909 
910         apicd = container_of(cfg, struct apic_chip_data, hw_irq_cfg);
911         if (likely(!apicd->move_in_progress))
912                 return;
913 
914         if (vector == apicd->vector && apicd->cpu == smp_processor_id())
915                 __send_cleanup_vector(apicd);
916 }
917 
918 void irq_complete_move(struct irq_cfg *cfg)
919 {
920         __irq_complete_move(cfg, ~get_irq_regs()->orig_ax);
921 }
922 
923 /*
924  * Called from fixup_irqs() with @desc->lock held and interrupts disabled.
925  */
926 void irq_force_complete_move(struct irq_desc *desc)
927 {
928         struct apic_chip_data *apicd;
929         struct irq_data *irqd;
930         unsigned int vector;
931 
932         /*
933          * The function is called for all descriptors regardless of which
934          * irqdomain they belong to. For example if an IRQ is provided by
935          * an irq_chip as part of a GPIO driver, the chip data for that
936          * descriptor is specific to the irq_chip in question.
937          *
938          * Check first that the chip_data is what we expect
939          * (apic_chip_data) before touching it any further.
940          */
941         irqd = irq_domain_get_irq_data(x86_vector_domain,
942                                        irq_desc_get_irq(desc));
943         if (!irqd)
944                 return;
945 
946         raw_spin_lock(&vector_lock);
947         apicd = apic_chip_data(irqd);
948         if (!apicd)
949                 goto unlock;
950 
951         /*
952          * If prev_vector is empty, no action required.
953          */
954         vector = apicd->prev_vector;
955         if (!vector)
956                 goto unlock;
957 
958         /*
959          * This is tricky. If the cleanup of the old vector has not been
960          * done yet, then the following setaffinity call will fail with
961          * -EBUSY. This can leave the interrupt in a stale state.
962          *
963          * All CPUs are stuck in stop machine with interrupts disabled so
964          * calling __irq_complete_move() would be completely pointless.
965          *
966          * 1) The interrupt is in move_in_progress state. That means that we
967          *    have not seen an interrupt since the io_apic was reprogrammed to
968          *    the new vector.
969          *
970          * 2) The interrupt has fired on the new vector, but the cleanup IPIs
971          *    have not been processed yet.
972          */
973         if (apicd->move_in_progress) {
974                 /*
975                  * In theory there is a race:
976                  *
977                  * set_ioapic(new_vector) <-- Interrupt is raised before update
978                  *                            is effective, i.e. it's raised on
979                  *                            the old vector.
980                  *
981                  * So if the target cpu cannot handle that interrupt before
982                  * the old vector is cleaned up, we get a spurious interrupt
983                  * and in the worst case the ioapic irq line becomes stale.
984                  *
985                  * But in case of cpu hotplug this should be a non issue
986                  * because if the affinity update happens right before all
987                  * cpus rendevouz in stop machine, there is no way that the
988                  * interrupt can be blocked on the target cpu because all cpus
989                  * loops first with interrupts enabled in stop machine, so the
990                  * old vector is not yet cleaned up when the interrupt fires.
991                  *
992                  * So the only way to run into this issue is if the delivery
993                  * of the interrupt on the apic/system bus would be delayed
994                  * beyond the point where the target cpu disables interrupts
995                  * in stop machine. I doubt that it can happen, but at least
996                  * there is a theroretical chance. Virtualization might be
997                  * able to expose this, but AFAICT the IOAPIC emulation is not
998                  * as stupid as the real hardware.
999                  *
1000                  * Anyway, there is nothing we can do about that at this point
1001                  * w/o refactoring the whole fixup_irq() business completely.
1002                  * We print at least the irq number and the old vector number,
1003                  * so we have the necessary information when a problem in that
1004                  * area arises.
1005                  */
1006                 pr_warn("IRQ fixup: irq %d move in progress, old vector %d\n",
1007                         irqd->irq, vector);
1008         }
1009         free_moved_vector(apicd);
1010 unlock:
1011         raw_spin_unlock(&vector_lock);
1012 }
1013 
1014 #ifdef CONFIG_HOTPLUG_CPU
1015 /*
1016  * Note, this is not accurate accounting, but at least good enough to
1017  * prevent that the actual interrupt move will run out of vectors.
1018  */
1019 int lapic_can_unplug_cpu(void)
1020 {
1021         unsigned int rsvd, avl, tomove, cpu = smp_processor_id();
1022         int ret = 0;
1023 
1024         raw_spin_lock(&vector_lock);
1025         tomove = irq_matrix_allocated(vector_matrix);
1026         avl = irq_matrix_available(vector_matrix, true);
1027         if (avl < tomove) {
1028                 pr_warn("CPU %u has %u vectors, %u available. Cannot disable CPU\n",
1029                         cpu, tomove, avl);
1030                 ret = -ENOSPC;
1031                 goto out;
1032         }
1033         rsvd = irq_matrix_reserved(vector_matrix);
1034         if (avl < rsvd) {
1035                 pr_warn("Reserved vectors %u > available %u. IRQ request may fail\n",
1036                         rsvd, avl);
1037         }
1038 out:
1039         raw_spin_unlock(&vector_lock);
1040         return ret;
1041 }
1042 #endif /* HOTPLUG_CPU */
1043 #endif /* SMP */
1044 
1045 static void __init print_APIC_field(int base)
1046 {
1047         int i;
1048 
1049         printk(KERN_DEBUG);
1050 
1051         for (i = 0; i < 8; i++)
1052                 pr_cont("%08x", apic_read(base + i*0x10));
1053 
1054         pr_cont("\n");
1055 }
1056 
1057 static void __init print_local_APIC(void *dummy)
1058 {
1059         unsigned int i, v, ver, maxlvt;
1060         u64 icr;
1061 
1062         pr_debug("printing local APIC contents on CPU#%d/%d:\n",
1063                  smp_processor_id(), hard_smp_processor_id());
1064         v = apic_read(APIC_ID);
1065         pr_info("... APIC ID:      %08x (%01x)\n", v, read_apic_id());
1066         v = apic_read(APIC_LVR);
1067         pr_info("... APIC VERSION: %08x\n", v);
1068         ver = GET_APIC_VERSION(v);
1069         maxlvt = lapic_get_maxlvt();
1070 
1071         v = apic_read(APIC_TASKPRI);
1072         pr_debug("... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1073 
1074         /* !82489DX */
1075         if (APIC_INTEGRATED(ver)) {
1076                 if (!APIC_XAPIC(ver)) {
1077                         v = apic_read(APIC_ARBPRI);
1078                         pr_debug("... APIC ARBPRI: %08x (%02x)\n",
1079                                  v, v & APIC_ARBPRI_MASK);
1080                 }
1081                 v = apic_read(APIC_PROCPRI);
1082                 pr_debug("... APIC PROCPRI: %08x\n", v);
1083         }
1084 
1085         /*
1086          * Remote read supported only in the 82489DX and local APIC for
1087          * Pentium processors.
1088          */
1089         if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1090                 v = apic_read(APIC_RRR);
1091                 pr_debug("... APIC RRR: %08x\n", v);
1092         }
1093 
1094         v = apic_read(APIC_LDR);
1095         pr_debug("... APIC LDR: %08x\n", v);
1096         if (!x2apic_enabled()) {
1097                 v = apic_read(APIC_DFR);
1098                 pr_debug("... APIC DFR: %08x\n", v);
1099         }
1100         v = apic_read(APIC_SPIV);
1101         pr_debug("... APIC SPIV: %08x\n", v);
1102 
1103         pr_debug("... APIC ISR field:\n");
1104         print_APIC_field(APIC_ISR);
1105         pr_debug("... APIC TMR field:\n");
1106         print_APIC_field(APIC_TMR);
1107         pr_debug("... APIC IRR field:\n");
1108         print_APIC_field(APIC_IRR);
1109 
1110         /* !82489DX */
1111         if (APIC_INTEGRATED(ver)) {
1112                 /* Due to the Pentium erratum 3AP. */
1113                 if (maxlvt > 3)
1114                         apic_write(APIC_ESR, 0);
1115 
1116                 v = apic_read(APIC_ESR);
1117                 pr_debug("... APIC ESR: %08x\n", v);
1118         }
1119 
1120         icr = apic_icr_read();
1121         pr_debug("... APIC ICR: %08x\n", (u32)icr);
1122         pr_debug("... APIC ICR2: %08x\n", (u32)(icr >> 32));
1123 
1124         v = apic_read(APIC_LVTT);
1125         pr_debug("... APIC LVTT: %08x\n", v);
1126 
1127         if (maxlvt > 3) {
1128                 /* PC is LVT#4. */
1129                 v = apic_read(APIC_LVTPC);
1130                 pr_debug("... APIC LVTPC: %08x\n", v);
1131         }
1132         v = apic_read(APIC_LVT0);
1133         pr_debug("... APIC LVT0: %08x\n", v);
1134         v = apic_read(APIC_LVT1);
1135         pr_debug("... APIC LVT1: %08x\n", v);
1136 
1137         if (maxlvt > 2) {
1138                 /* ERR is LVT#3. */
1139                 v = apic_read(APIC_LVTERR);
1140                 pr_debug("... APIC LVTERR: %08x\n", v);
1141         }
1142 
1143         v = apic_read(APIC_TMICT);
1144         pr_debug("... APIC TMICT: %08x\n", v);
1145         v = apic_read(APIC_TMCCT);
1146         pr_debug("... APIC TMCCT: %08x\n", v);
1147         v = apic_read(APIC_TDCR);
1148         pr_debug("... APIC TDCR: %08x\n", v);
1149 
1150         if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
1151                 v = apic_read(APIC_EFEAT);
1152                 maxlvt = (v >> 16) & 0xff;
1153                 pr_debug("... APIC EFEAT: %08x\n", v);
1154                 v = apic_read(APIC_ECTRL);
1155                 pr_debug("... APIC ECTRL: %08x\n", v);
1156                 for (i = 0; i < maxlvt; i++) {
1157                         v = apic_read(APIC_EILVTn(i));
1158                         pr_debug("... APIC EILVT%d: %08x\n", i, v);
1159                 }
1160         }
1161         pr_cont("\n");
1162 }
1163 
1164 static void __init print_local_APICs(int maxcpu)
1165 {
1166         int cpu;
1167 
1168         if (!maxcpu)
1169                 return;
1170 
1171         preempt_disable();
1172         for_each_online_cpu(cpu) {
1173                 if (cpu >= maxcpu)
1174                         break;
1175                 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1176         }
1177         preempt_enable();
1178 }
1179 
1180 static void __init print_PIC(void)
1181 {
1182         unsigned int v;
1183         unsigned long flags;
1184 
1185         if (!nr_legacy_irqs())
1186                 return;
1187 
1188         pr_debug("\nprinting PIC contents\n");
1189 
1190         raw_spin_lock_irqsave(&i8259A_lock, flags);
1191 
1192         v = inb(0xa1) << 8 | inb(0x21);
1193         pr_debug("... PIC  IMR: %04x\n", v);
1194 
1195         v = inb(0xa0) << 8 | inb(0x20);
1196         pr_debug("... PIC  IRR: %04x\n", v);
1197 
1198         outb(0x0b, 0xa0);
1199         outb(0x0b, 0x20);
1200         v = inb(0xa0) << 8 | inb(0x20);
1201         outb(0x0a, 0xa0);
1202         outb(0x0a, 0x20);
1203 
1204         raw_spin_unlock_irqrestore(&i8259A_lock, flags);
1205 
1206         pr_debug("... PIC  ISR: %04x\n", v);
1207 
1208         v = inb(0x4d1) << 8 | inb(0x4d0);
1209         pr_debug("... PIC ELCR: %04x\n", v);
1210 }
1211 
1212 static int show_lapic __initdata = 1;
1213 static __init int setup_show_lapic(char *arg)
1214 {
1215         int num = -1;
1216 
1217         if (strcmp(arg, "all") == 0) {
1218                 show_lapic = CONFIG_NR_CPUS;
1219         } else {
1220                 get_option(&arg, &num);
1221                 if (num >= 0)
1222                         show_lapic = num;
1223         }
1224 
1225         return 1;
1226 }
1227 __setup("show_lapic=", setup_show_lapic);
1228 
1229 static int __init print_ICs(void)
1230 {
1231         if (apic_verbosity == APIC_QUIET)
1232                 return 0;
1233 
1234         print_PIC();
1235 
1236         /* don't print out if apic is not there */
1237         if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config())
1238                 return 0;
1239 
1240         print_local_APICs(show_lapic);
1241         print_IO_APICs();
1242 
1243         return 0;
1244 }
1245 
1246 late_initcall(print_ICs);
1247 

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