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TOMOYO Linux Cross Reference
Linux/arch/x86/kernel/apic/x2apic_uv_x.c

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  1 /*
  2  * This file is subject to the terms and conditions of the GNU General Public
  3  * License.  See the file "COPYING" in the main directory of this archive
  4  * for more details.
  5  *
  6  * SGI UV APIC functions (note: not an Intel compatible APIC)
  7  *
  8  * (C) Copyright 2020 Hewlett Packard Enterprise Development LP
  9  * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved.
 10  */
 11 #include <linux/crash_dump.h>
 12 #include <linux/cpuhotplug.h>
 13 #include <linux/cpumask.h>
 14 #include <linux/proc_fs.h>
 15 #include <linux/memory.h>
 16 #include <linux/export.h>
 17 #include <linux/pci.h>
 18 #include <linux/acpi.h>
 19 #include <linux/efi.h>
 20 
 21 #include <asm/e820/api.h>
 22 #include <asm/uv/uv_mmrs.h>
 23 #include <asm/uv/uv_hub.h>
 24 #include <asm/uv/bios.h>
 25 #include <asm/uv/uv.h>
 26 #include <asm/apic.h>
 27 
 28 static enum uv_system_type      uv_system_type;
 29 static int                      uv_hubbed_system;
 30 static int                      uv_hubless_system;
 31 static u64                      gru_start_paddr, gru_end_paddr;
 32 static union uvh_apicid         uvh_apicid;
 33 static int                      uv_node_id;
 34 
 35 /* Unpack AT/OEM/TABLE ID's to be NULL terminated strings */
 36 static u8 uv_archtype[UV_AT_SIZE + 1];
 37 static u8 oem_id[ACPI_OEM_ID_SIZE + 1];
 38 static u8 oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1];
 39 
 40 /* Information derived from CPUID and some UV MMRs */
 41 static struct {
 42         unsigned int apicid_shift;
 43         unsigned int apicid_mask;
 44         unsigned int socketid_shift;    /* aka pnode_shift for UV2/3 */
 45         unsigned int pnode_mask;
 46         unsigned int nasid_shift;
 47         unsigned int gpa_shift;
 48         unsigned int gnode_shift;
 49         unsigned int m_skt;
 50         unsigned int n_skt;
 51 } uv_cpuid;
 52 
 53 static int uv_min_hub_revision_id;
 54 
 55 static struct apic apic_x2apic_uv_x;
 56 static struct uv_hub_info_s uv_hub_info_node0;
 57 
 58 /* Set this to use hardware error handler instead of kernel panic: */
 59 static int disable_uv_undefined_panic = 1;
 60 
 61 unsigned long uv_undefined(char *str)
 62 {
 63         if (likely(!disable_uv_undefined_panic))
 64                 panic("UV: error: undefined MMR: %s\n", str);
 65         else
 66                 pr_crit("UV: error: undefined MMR: %s\n", str);
 67 
 68         /* Cause a machine fault: */
 69         return ~0ul;
 70 }
 71 EXPORT_SYMBOL(uv_undefined);
 72 
 73 static unsigned long __init uv_early_read_mmr(unsigned long addr)
 74 {
 75         unsigned long val, *mmr;
 76 
 77         mmr = early_ioremap(UV_LOCAL_MMR_BASE | addr, sizeof(*mmr));
 78         val = *mmr;
 79         early_iounmap(mmr, sizeof(*mmr));
 80 
 81         return val;
 82 }
 83 
 84 static inline bool is_GRU_range(u64 start, u64 end)
 85 {
 86         if (!gru_start_paddr)
 87                 return false;
 88 
 89         return start >= gru_start_paddr && end <= gru_end_paddr;
 90 }
 91 
 92 static bool uv_is_untracked_pat_range(u64 start, u64 end)
 93 {
 94         return is_ISA_range(start, end) || is_GRU_range(start, end);
 95 }
 96 
 97 static void __init early_get_pnodeid(void)
 98 {
 99         int pnode;
100 
101         uv_cpuid.m_skt = 0;
102         if (UVH_RH10_GAM_ADDR_MAP_CONFIG) {
103                 union uvh_rh10_gam_addr_map_config_u  m_n_config;
104 
105                 m_n_config.v = uv_early_read_mmr(UVH_RH10_GAM_ADDR_MAP_CONFIG);
106                 uv_cpuid.n_skt = m_n_config.s.n_skt;
107                 uv_cpuid.nasid_shift = 0;
108         } else if (UVH_RH_GAM_ADDR_MAP_CONFIG) {
109                 union uvh_rh_gam_addr_map_config_u  m_n_config;
110 
111         m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_ADDR_MAP_CONFIG);
112                 uv_cpuid.n_skt = m_n_config.s.n_skt;
113                 if (is_uv(UV3))
114                         uv_cpuid.m_skt = m_n_config.s3.m_skt;
115                 if (is_uv(UV2))
116                         uv_cpuid.m_skt = m_n_config.s2.m_skt;
117                 uv_cpuid.nasid_shift = 1;
118         } else {
119                 unsigned long GAM_ADDR_MAP_CONFIG = 0;
120 
121                 WARN(GAM_ADDR_MAP_CONFIG == 0,
122                         "UV: WARN: GAM_ADDR_MAP_CONFIG is not available\n");
123                 uv_cpuid.n_skt = 0;
124                 uv_cpuid.nasid_shift = 0;
125         }
126 
127         if (is_uv(UV4|UVY))
128                 uv_cpuid.gnode_shift = 2; /* min partition is 4 sockets */
129 
130         uv_cpuid.pnode_mask = (1 << uv_cpuid.n_skt) - 1;
131         pnode = (uv_node_id >> uv_cpuid.nasid_shift) & uv_cpuid.pnode_mask;
132         uv_cpuid.gpa_shift = 46;        /* Default unless changed */
133 
134         pr_info("UV: n_skt:%d pnmsk:%x pn:%x\n",
135                 uv_cpuid.n_skt, uv_cpuid.pnode_mask, pnode);
136 }
137 
138 /* Running on a UV Hubbed system, determine which UV Hub Type it is */
139 static int __init early_set_hub_type(void)
140 {
141         union uvh_node_id_u node_id;
142 
143         /*
144          * The NODE_ID MMR is always at offset 0.
145          * Contains the chip part # + revision.
146          * Node_id field started with 15 bits,
147          * ... now 7 but upper 8 are masked to 0.
148          * All blades/nodes have the same part # and hub revision.
149          */
150         node_id.v = uv_early_read_mmr(UVH_NODE_ID);
151         uv_node_id = node_id.sx.node_id;
152 
153         switch (node_id.s.part_number) {
154 
155         case UV5_HUB_PART_NUMBER:
156                 uv_min_hub_revision_id = node_id.s.revision
157                                          + UV5_HUB_REVISION_BASE;
158                 uv_hub_type_set(UV5);
159                 break;
160 
161         /* UV4/4A only have a revision difference */
162         case UV4_HUB_PART_NUMBER:
163                 uv_min_hub_revision_id = node_id.s.revision
164                                          + UV4_HUB_REVISION_BASE - 1;
165                 uv_hub_type_set(UV4);
166                 if (uv_min_hub_revision_id == UV4A_HUB_REVISION_BASE)
167                         uv_hub_type_set(UV4|UV4A);
168                 break;
169 
170         case UV3_HUB_PART_NUMBER:
171         case UV3_HUB_PART_NUMBER_X:
172                 uv_min_hub_revision_id = node_id.s.revision
173                                          + UV3_HUB_REVISION_BASE;
174                 uv_hub_type_set(UV3);
175                 break;
176 
177         case UV2_HUB_PART_NUMBER:
178         case UV2_HUB_PART_NUMBER_X:
179                 uv_min_hub_revision_id = node_id.s.revision
180                                          + UV2_HUB_REVISION_BASE - 1;
181                 uv_hub_type_set(UV2);
182                 break;
183 
184         default:
185                 return 0;
186         }
187 
188         pr_info("UV: part#:%x rev:%d rev_id:%d UVtype:0x%x\n",
189                 node_id.s.part_number, node_id.s.revision,
190                 uv_min_hub_revision_id, is_uv(~0));
191 
192         return 1;
193 }
194 
195 static void __init uv_tsc_check_sync(void)
196 {
197         u64 mmr;
198         int sync_state;
199         int mmr_shift;
200         char *state;
201 
202         /* Different returns from different UV BIOS versions */
203         mmr = uv_early_read_mmr(UVH_TSC_SYNC_MMR);
204         mmr_shift =
205                 is_uv2_hub() ? UVH_TSC_SYNC_SHIFT_UV2K : UVH_TSC_SYNC_SHIFT;
206         sync_state = (mmr >> mmr_shift) & UVH_TSC_SYNC_MASK;
207 
208         /* Check if TSC is valid for all sockets */
209         switch (sync_state) {
210         case UVH_TSC_SYNC_VALID:
211                 state = "in sync";
212                 mark_tsc_async_resets("UV BIOS");
213                 break;
214 
215         /* If BIOS state unknown, don't do anything */
216         case UVH_TSC_SYNC_UNKNOWN:
217                 state = "unknown";
218                 break;
219 
220         /* Otherwise, BIOS indicates problem with TSC */
221         default:
222                 state = "unstable";
223                 mark_tsc_unstable("UV BIOS");
224                 break;
225         }
226         pr_info("UV: TSC sync state from BIOS:0%d(%s)\n", sync_state, state);
227 }
228 
229 /* Selector for (4|4A|5) structs */
230 #define uvxy_field(sname, field, undef) (       \
231         is_uv(UV4A) ? sname.s4a.field :         \
232         is_uv(UV4) ? sname.s4.field :           \
233         is_uv(UV3) ? sname.s3.field :           \
234         undef)
235 
236 /* [Copied from arch/x86/kernel/cpu/topology.c:detect_extended_topology()] */
237 
238 #define SMT_LEVEL                       0       /* Leaf 0xb SMT level */
239 #define INVALID_TYPE                    0       /* Leaf 0xb sub-leaf types */
240 #define SMT_TYPE                        1
241 #define CORE_TYPE                       2
242 #define LEAFB_SUBTYPE(ecx)              (((ecx) >> 8) & 0xff)
243 #define BITS_SHIFT_NEXT_LEVEL(eax)      ((eax) & 0x1f)
244 
245 static void set_x2apic_bits(void)
246 {
247         unsigned int eax, ebx, ecx, edx, sub_index;
248         unsigned int sid_shift;
249 
250         cpuid(0, &eax, &ebx, &ecx, &edx);
251         if (eax < 0xb) {
252                 pr_info("UV: CPU does not have CPUID.11\n");
253                 return;
254         }
255 
256         cpuid_count(0xb, SMT_LEVEL, &eax, &ebx, &ecx, &edx);
257         if (ebx == 0 || (LEAFB_SUBTYPE(ecx) != SMT_TYPE)) {
258                 pr_info("UV: CPUID.11 not implemented\n");
259                 return;
260         }
261 
262         sid_shift = BITS_SHIFT_NEXT_LEVEL(eax);
263         sub_index = 1;
264         do {
265                 cpuid_count(0xb, sub_index, &eax, &ebx, &ecx, &edx);
266                 if (LEAFB_SUBTYPE(ecx) == CORE_TYPE) {
267                         sid_shift = BITS_SHIFT_NEXT_LEVEL(eax);
268                         break;
269                 }
270                 sub_index++;
271         } while (LEAFB_SUBTYPE(ecx) != INVALID_TYPE);
272 
273         uv_cpuid.apicid_shift   = 0;
274         uv_cpuid.apicid_mask    = (~(-1 << sid_shift));
275         uv_cpuid.socketid_shift = sid_shift;
276 }
277 
278 static void __init early_get_apic_socketid_shift(void)
279 {
280         if (is_uv2_hub() || is_uv3_hub())
281                 uvh_apicid.v = uv_early_read_mmr(UVH_APICID);
282 
283         set_x2apic_bits();
284 
285         pr_info("UV: apicid_shift:%d apicid_mask:0x%x\n", uv_cpuid.apicid_shift, uv_cpuid.apicid_mask);
286         pr_info("UV: socketid_shift:%d pnode_mask:0x%x\n", uv_cpuid.socketid_shift, uv_cpuid.pnode_mask);
287 }
288 
289 static void __init uv_stringify(int len, char *to, char *from)
290 {
291         /* Relies on 'to' being NULL chars so result will be NULL terminated */
292         strncpy(to, from, len-1);
293 
294         /* Trim trailing spaces */
295         (void)strim(to);
296 }
297 
298 /* Find UV arch type entry in UVsystab */
299 static unsigned long __init early_find_archtype(struct uv_systab *st)
300 {
301         int i;
302 
303         for (i = 0; st->entry[i].type != UV_SYSTAB_TYPE_UNUSED; i++) {
304                 unsigned long ptr = st->entry[i].offset;
305 
306                 if (!ptr)
307                         continue;
308                 ptr += (unsigned long)st;
309                 if (st->entry[i].type == UV_SYSTAB_TYPE_ARCH_TYPE)
310                         return ptr;
311         }
312         return 0;
313 }
314 
315 /* Validate UV arch type field in UVsystab */
316 static int __init decode_arch_type(unsigned long ptr)
317 {
318         struct uv_arch_type_entry *uv_ate = (struct uv_arch_type_entry *)ptr;
319         int n = strlen(uv_ate->archtype);
320 
321         if (n > 0 && n < sizeof(uv_ate->archtype)) {
322                 pr_info("UV: UVarchtype received from BIOS\n");
323                 uv_stringify(sizeof(uv_archtype), uv_archtype, uv_ate->archtype);
324                 return 1;
325         }
326         return 0;
327 }
328 
329 /* Determine if UV arch type entry might exist in UVsystab */
330 static int __init early_get_arch_type(void)
331 {
332         unsigned long uvst_physaddr, uvst_size, ptr;
333         struct uv_systab *st;
334         u32 rev;
335         int ret;
336 
337         uvst_physaddr = get_uv_systab_phys(0);
338         if (!uvst_physaddr)
339                 return 0;
340 
341         st = early_memremap_ro(uvst_physaddr, sizeof(struct uv_systab));
342         if (!st) {
343                 pr_err("UV: Cannot access UVsystab, remap failed\n");
344                 return 0;
345         }
346 
347         rev = st->revision;
348         if (rev < UV_SYSTAB_VERSION_UV5) {
349                 early_memunmap(st, sizeof(struct uv_systab));
350                 return 0;
351         }
352 
353         uvst_size = st->size;
354         early_memunmap(st, sizeof(struct uv_systab));
355         st = early_memremap_ro(uvst_physaddr, uvst_size);
356         if (!st) {
357                 pr_err("UV: Cannot access UVarchtype, remap failed\n");
358                 return 0;
359         }
360 
361         ptr = early_find_archtype(st);
362         if (!ptr) {
363                 early_memunmap(st, uvst_size);
364                 return 0;
365         }
366 
367         ret = decode_arch_type(ptr);
368         early_memunmap(st, uvst_size);
369         return ret;
370 }
371 
372 static int __init uv_set_system_type(char *_oem_id, char *_oem_table_id)
373 {
374         /* Save OEM_ID passed from ACPI MADT */
375         uv_stringify(sizeof(oem_id), oem_id, _oem_id);
376 
377         /* Check if BIOS sent us a UVarchtype */
378         if (!early_get_arch_type())
379 
380                 /* If not use OEM ID for UVarchtype */
381                 uv_stringify(sizeof(uv_archtype), uv_archtype, oem_id);
382 
383         /* Check if not hubbed */
384         if (strncmp(uv_archtype, "SGI", 3) != 0) {
385 
386                 /* (Not hubbed), check if not hubless */
387                 if (strncmp(uv_archtype, "NSGI", 4) != 0)
388 
389                         /* (Not hubless), not a UV */
390                         return 0;
391 
392                 /* Is UV hubless system */
393                 uv_hubless_system = 0x01;
394 
395                 /* UV5 Hubless */
396                 if (strncmp(uv_archtype, "NSGI5", 5) == 0)
397                         uv_hubless_system |= 0x20;
398 
399                 /* UV4 Hubless: CH */
400                 else if (strncmp(uv_archtype, "NSGI4", 5) == 0)
401                         uv_hubless_system |= 0x10;
402 
403                 /* UV3 Hubless: UV300/MC990X w/o hub */
404                 else
405                         uv_hubless_system |= 0x8;
406 
407                 /* Copy APIC type */
408                 uv_stringify(sizeof(oem_table_id), oem_table_id, _oem_table_id);
409 
410                 pr_info("UV: OEM IDs %s/%s, SystemType %d, HUBLESS ID %x\n",
411                         oem_id, oem_table_id, uv_system_type, uv_hubless_system);
412                 return 0;
413         }
414 
415         if (numa_off) {
416                 pr_err("UV: NUMA is off, disabling UV support\n");
417                 return 0;
418         }
419 
420         /* Set hubbed type if true */
421         uv_hub_info->hub_revision =
422                 !strncmp(uv_archtype, "SGI5", 4) ? UV5_HUB_REVISION_BASE :
423                 !strncmp(uv_archtype, "SGI4", 4) ? UV4_HUB_REVISION_BASE :
424                 !strncmp(uv_archtype, "SGI3", 4) ? UV3_HUB_REVISION_BASE :
425                 !strcmp(uv_archtype, "SGI2") ? UV2_HUB_REVISION_BASE : 0;
426 
427         switch (uv_hub_info->hub_revision) {
428         case UV5_HUB_REVISION_BASE:
429                 uv_hubbed_system = 0x21;
430                 uv_hub_type_set(UV5);
431                 break;
432 
433         case UV4_HUB_REVISION_BASE:
434                 uv_hubbed_system = 0x11;
435                 uv_hub_type_set(UV4);
436                 break;
437 
438         case UV3_HUB_REVISION_BASE:
439                 uv_hubbed_system = 0x9;
440                 uv_hub_type_set(UV3);
441                 break;
442 
443         case UV2_HUB_REVISION_BASE:
444                 uv_hubbed_system = 0x5;
445                 uv_hub_type_set(UV2);
446                 break;
447 
448         default:
449                 return 0;
450         }
451 
452         /* Get UV hub chip part number & revision */
453         early_set_hub_type();
454 
455         /* Other UV setup functions */
456         early_get_pnodeid();
457         early_get_apic_socketid_shift();
458         x86_platform.is_untracked_pat_range = uv_is_untracked_pat_range;
459         x86_platform.nmi_init = uv_nmi_init;
460         uv_tsc_check_sync();
461 
462         return 1;
463 }
464 
465 /* Called early to probe for the correct APIC driver */
466 static int __init uv_acpi_madt_oem_check(char *_oem_id, char *_oem_table_id)
467 {
468         /* Set up early hub info fields for Node 0 */
469         uv_cpu_info->p_uv_hub_info = &uv_hub_info_node0;
470 
471         /* If not UV, return. */
472         if (uv_set_system_type(_oem_id, _oem_table_id) == 0)
473                 return 0;
474 
475         /* Save and Decode OEM Table ID */
476         uv_stringify(sizeof(oem_table_id), oem_table_id, _oem_table_id);
477 
478         /* This is the most common hardware variant, x2apic mode */
479         if (!strcmp(oem_table_id, "UVX"))
480                 uv_system_type = UV_X2APIC;
481 
482         /* Only used for very small systems, usually 1 chassis, legacy mode  */
483         else if (!strcmp(oem_table_id, "UVL"))
484                 uv_system_type = UV_LEGACY_APIC;
485 
486         else
487                 goto badbios;
488 
489         pr_info("UV: OEM IDs %s/%s, System/UVType %d/0x%x, HUB RevID %d\n",
490                 oem_id, oem_table_id, uv_system_type, is_uv(UV_ANY),
491                 uv_min_hub_revision_id);
492 
493         return 0;
494 
495 badbios:
496         pr_err("UV: UVarchtype:%s not supported\n", uv_archtype);
497         BUG();
498 }
499 
500 enum uv_system_type get_uv_system_type(void)
501 {
502         return uv_system_type;
503 }
504 
505 int uv_get_hubless_system(void)
506 {
507         return uv_hubless_system;
508 }
509 EXPORT_SYMBOL_GPL(uv_get_hubless_system);
510 
511 ssize_t uv_get_archtype(char *buf, int len)
512 {
513         return scnprintf(buf, len, "%s/%s", uv_archtype, oem_table_id);
514 }
515 EXPORT_SYMBOL_GPL(uv_get_archtype);
516 
517 int is_uv_system(void)
518 {
519         return uv_system_type != UV_NONE;
520 }
521 EXPORT_SYMBOL_GPL(is_uv_system);
522 
523 int is_uv_hubbed(int uvtype)
524 {
525         return (uv_hubbed_system & uvtype);
526 }
527 EXPORT_SYMBOL_GPL(is_uv_hubbed);
528 
529 static int is_uv_hubless(int uvtype)
530 {
531         return (uv_hubless_system & uvtype);
532 }
533 
534 void **__uv_hub_info_list;
535 EXPORT_SYMBOL_GPL(__uv_hub_info_list);
536 
537 DEFINE_PER_CPU(struct uv_cpu_info_s, __uv_cpu_info);
538 EXPORT_PER_CPU_SYMBOL_GPL(__uv_cpu_info);
539 
540 short uv_possible_blades;
541 EXPORT_SYMBOL_GPL(uv_possible_blades);
542 
543 unsigned long sn_rtc_cycles_per_second;
544 EXPORT_SYMBOL(sn_rtc_cycles_per_second);
545 
546 /* The following values are used for the per node hub info struct */
547 static __initdata unsigned short                *_node_to_pnode;
548 static __initdata unsigned short                _min_socket, _max_socket;
549 static __initdata unsigned short                _min_pnode, _max_pnode, _gr_table_len;
550 static __initdata struct uv_gam_range_entry     *uv_gre_table;
551 static __initdata struct uv_gam_parameters      *uv_gp_table;
552 static __initdata unsigned short                *_socket_to_node;
553 static __initdata unsigned short                *_socket_to_pnode;
554 static __initdata unsigned short                *_pnode_to_socket;
555 
556 static __initdata struct uv_gam_range_s         *_gr_table;
557 
558 #define SOCK_EMPTY      ((unsigned short)~0)
559 
560 /* Default UV memory block size is 2GB */
561 static unsigned long mem_block_size __initdata = (2UL << 30);
562 
563 /* Kernel parameter to specify UV mem block size */
564 static int __init parse_mem_block_size(char *ptr)
565 {
566         unsigned long size = memparse(ptr, NULL);
567 
568         /* Size will be rounded down by set_block_size() below */
569         mem_block_size = size;
570         return 0;
571 }
572 early_param("uv_memblksize", parse_mem_block_size);
573 
574 static __init int adj_blksize(u32 lgre)
575 {
576         unsigned long base = (unsigned long)lgre << UV_GAM_RANGE_SHFT;
577         unsigned long size;
578 
579         for (size = mem_block_size; size > MIN_MEMORY_BLOCK_SIZE; size >>= 1)
580                 if (IS_ALIGNED(base, size))
581                         break;
582 
583         if (size >= mem_block_size)
584                 return 0;
585 
586         mem_block_size = size;
587         return 1;
588 }
589 
590 static __init void set_block_size(void)
591 {
592         unsigned int order = ffs(mem_block_size);
593 
594         if (order) {
595                 /* adjust for ffs return of 1..64 */
596                 set_memory_block_size_order(order - 1);
597                 pr_info("UV: mem_block_size set to 0x%lx\n", mem_block_size);
598         } else {
599                 /* bad or zero value, default to 1UL << 31 (2GB) */
600                 pr_err("UV: mem_block_size error with 0x%lx\n", mem_block_size);
601                 set_memory_block_size_order(31);
602         }
603 }
604 
605 /* Build GAM range lookup table: */
606 static __init void build_uv_gr_table(void)
607 {
608         struct uv_gam_range_entry *gre = uv_gre_table;
609         struct uv_gam_range_s *grt;
610         unsigned long last_limit = 0, ram_limit = 0;
611         int bytes, i, sid, lsid = -1, indx = 0, lindx = -1;
612 
613         if (!gre)
614                 return;
615 
616         bytes = _gr_table_len * sizeof(struct uv_gam_range_s);
617         grt = kzalloc(bytes, GFP_KERNEL);
618         BUG_ON(!grt);
619         _gr_table = grt;
620 
621         for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
622                 if (gre->type == UV_GAM_RANGE_TYPE_HOLE) {
623                         if (!ram_limit) {
624                                 /* Mark hole between RAM/non-RAM: */
625                                 ram_limit = last_limit;
626                                 last_limit = gre->limit;
627                                 lsid++;
628                                 continue;
629                         }
630                         last_limit = gre->limit;
631                         pr_info("UV: extra hole in GAM RE table @%d\n", (int)(gre - uv_gre_table));
632                         continue;
633                 }
634                 if (_max_socket < gre->sockid) {
635                         pr_err("UV: GAM table sockid(%d) too large(>%d) @%d\n", gre->sockid, _max_socket, (int)(gre - uv_gre_table));
636                         continue;
637                 }
638                 sid = gre->sockid - _min_socket;
639                 if (lsid < sid) {
640                         /* New range: */
641                         grt = &_gr_table[indx];
642                         grt->base = lindx;
643                         grt->nasid = gre->nasid;
644                         grt->limit = last_limit = gre->limit;
645                         lsid = sid;
646                         lindx = indx++;
647                         continue;
648                 }
649                 /* Update range: */
650                 if (lsid == sid && !ram_limit) {
651                         /* .. if contiguous: */
652                         if (grt->limit == last_limit) {
653                                 grt->limit = last_limit = gre->limit;
654                                 continue;
655                         }
656                 }
657                 /* Non-contiguous RAM range: */
658                 if (!ram_limit) {
659                         grt++;
660                         grt->base = lindx;
661                         grt->nasid = gre->nasid;
662                         grt->limit = last_limit = gre->limit;
663                         continue;
664                 }
665                 /* Non-contiguous/non-RAM: */
666                 grt++;
667                 /* base is this entry */
668                 grt->base = grt - _gr_table;
669                 grt->nasid = gre->nasid;
670                 grt->limit = last_limit = gre->limit;
671                 lsid++;
672         }
673 
674         /* Shorten table if possible */
675         grt++;
676         i = grt - _gr_table;
677         if (i < _gr_table_len) {
678                 void *ret;
679 
680                 bytes = i * sizeof(struct uv_gam_range_s);
681                 ret = krealloc(_gr_table, bytes, GFP_KERNEL);
682                 if (ret) {
683                         _gr_table = ret;
684                         _gr_table_len = i;
685                 }
686         }
687 
688         /* Display resultant GAM range table: */
689         for (i = 0, grt = _gr_table; i < _gr_table_len; i++, grt++) {
690                 unsigned long start, end;
691                 int gb = grt->base;
692 
693                 start = gb < 0 ?  0 : (unsigned long)_gr_table[gb].limit << UV_GAM_RANGE_SHFT;
694                 end = (unsigned long)grt->limit << UV_GAM_RANGE_SHFT;
695 
696                 pr_info("UV: GAM Range %2d %04x 0x%013lx-0x%013lx (%d)\n", i, grt->nasid, start, end, gb);
697         }
698 }
699 
700 static int uv_wakeup_secondary(int phys_apicid, unsigned long start_rip)
701 {
702         unsigned long val;
703         int pnode;
704 
705         pnode = uv_apicid_to_pnode(phys_apicid);
706 
707         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
708             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
709             ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
710             APIC_DM_INIT;
711 
712         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
713 
714         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
715             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
716             ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
717             APIC_DM_STARTUP;
718 
719         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
720 
721         return 0;
722 }
723 
724 static void uv_send_IPI_one(int cpu, int vector)
725 {
726         unsigned long apicid = per_cpu(x86_cpu_to_apicid, cpu);
727         int pnode = uv_apicid_to_pnode(apicid);
728         unsigned long dmode, val;
729 
730         if (vector == NMI_VECTOR)
731                 dmode = APIC_DELIVERY_MODE_NMI;
732         else
733                 dmode = APIC_DELIVERY_MODE_FIXED;
734 
735         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
736                 (apicid << UVH_IPI_INT_APIC_ID_SHFT) |
737                 (dmode << UVH_IPI_INT_DELIVERY_MODE_SHFT) |
738                 (vector << UVH_IPI_INT_VECTOR_SHFT);
739 
740         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
741 }
742 
743 static void uv_send_IPI_mask(const struct cpumask *mask, int vector)
744 {
745         unsigned int cpu;
746 
747         for_each_cpu(cpu, mask)
748                 uv_send_IPI_one(cpu, vector);
749 }
750 
751 static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
752 {
753         unsigned int this_cpu = smp_processor_id();
754         unsigned int cpu;
755 
756         for_each_cpu(cpu, mask) {
757                 if (cpu != this_cpu)
758                         uv_send_IPI_one(cpu, vector);
759         }
760 }
761 
762 static void uv_send_IPI_allbutself(int vector)
763 {
764         unsigned int this_cpu = smp_processor_id();
765         unsigned int cpu;
766 
767         for_each_online_cpu(cpu) {
768                 if (cpu != this_cpu)
769                         uv_send_IPI_one(cpu, vector);
770         }
771 }
772 
773 static void uv_send_IPI_all(int vector)
774 {
775         uv_send_IPI_mask(cpu_online_mask, vector);
776 }
777 
778 static int uv_apic_id_valid(u32 apicid)
779 {
780         return 1;
781 }
782 
783 static int uv_apic_id_registered(void)
784 {
785         return 1;
786 }
787 
788 static void uv_init_apic_ldr(void)
789 {
790 }
791 
792 static u32 apic_uv_calc_apicid(unsigned int cpu)
793 {
794         return apic_default_calc_apicid(cpu);
795 }
796 
797 static unsigned int x2apic_get_apic_id(unsigned long id)
798 {
799         return id;
800 }
801 
802 static u32 set_apic_id(unsigned int id)
803 {
804         return id;
805 }
806 
807 static unsigned int uv_read_apic_id(void)
808 {
809         return x2apic_get_apic_id(apic_read(APIC_ID));
810 }
811 
812 static int uv_phys_pkg_id(int initial_apicid, int index_msb)
813 {
814         return uv_read_apic_id() >> index_msb;
815 }
816 
817 static void uv_send_IPI_self(int vector)
818 {
819         apic_write(APIC_SELF_IPI, vector);
820 }
821 
822 static int uv_probe(void)
823 {
824         return apic == &apic_x2apic_uv_x;
825 }
826 
827 static struct apic apic_x2apic_uv_x __ro_after_init = {
828 
829         .name                           = "UV large system",
830         .probe                          = uv_probe,
831         .acpi_madt_oem_check            = uv_acpi_madt_oem_check,
832         .apic_id_valid                  = uv_apic_id_valid,
833         .apic_id_registered             = uv_apic_id_registered,
834 
835         .delivery_mode                  = APIC_DELIVERY_MODE_FIXED,
836         .dest_mode_logical              = false,
837 
838         .disable_esr                    = 0,
839 
840         .check_apicid_used              = NULL,
841         .init_apic_ldr                  = uv_init_apic_ldr,
842         .ioapic_phys_id_map             = NULL,
843         .setup_apic_routing             = NULL,
844         .cpu_present_to_apicid          = default_cpu_present_to_apicid,
845         .apicid_to_cpu_present          = NULL,
846         .check_phys_apicid_present      = default_check_phys_apicid_present,
847         .phys_pkg_id                    = uv_phys_pkg_id,
848 
849         .get_apic_id                    = x2apic_get_apic_id,
850         .set_apic_id                    = set_apic_id,
851 
852         .calc_dest_apicid               = apic_uv_calc_apicid,
853 
854         .send_IPI                       = uv_send_IPI_one,
855         .send_IPI_mask                  = uv_send_IPI_mask,
856         .send_IPI_mask_allbutself       = uv_send_IPI_mask_allbutself,
857         .send_IPI_allbutself            = uv_send_IPI_allbutself,
858         .send_IPI_all                   = uv_send_IPI_all,
859         .send_IPI_self                  = uv_send_IPI_self,
860 
861         .wakeup_secondary_cpu           = uv_wakeup_secondary,
862         .inquire_remote_apic            = NULL,
863 
864         .read                           = native_apic_msr_read,
865         .write                          = native_apic_msr_write,
866         .eoi_write                      = native_apic_msr_eoi_write,
867         .icr_read                       = native_x2apic_icr_read,
868         .icr_write                      = native_x2apic_icr_write,
869         .wait_icr_idle                  = native_x2apic_wait_icr_idle,
870         .safe_wait_icr_idle             = native_safe_x2apic_wait_icr_idle,
871 };
872 
873 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH      3
874 #define DEST_SHIFT UVXH_RH_GAM_ALIAS_0_REDIRECT_CONFIG_DEST_BASE_SHFT
875 
876 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
877 {
878         union uvh_rh_gam_alias_2_overlay_config_u alias;
879         union uvh_rh_gam_alias_2_redirect_config_u redirect;
880         unsigned long m_redirect;
881         unsigned long m_overlay;
882         int i;
883 
884         for (i = 0; i < UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH; i++) {
885                 switch (i) {
886                 case 0:
887                         m_redirect = UVH_RH_GAM_ALIAS_0_REDIRECT_CONFIG;
888                         m_overlay  = UVH_RH_GAM_ALIAS_0_OVERLAY_CONFIG;
889                         break;
890                 case 1:
891                         m_redirect = UVH_RH_GAM_ALIAS_1_REDIRECT_CONFIG;
892                         m_overlay  = UVH_RH_GAM_ALIAS_1_OVERLAY_CONFIG;
893                         break;
894                 case 2:
895                         m_redirect = UVH_RH_GAM_ALIAS_2_REDIRECT_CONFIG;
896                         m_overlay  = UVH_RH_GAM_ALIAS_2_OVERLAY_CONFIG;
897                         break;
898                 }
899                 alias.v = uv_read_local_mmr(m_overlay);
900                 if (alias.s.enable && alias.s.base == 0) {
901                         *size = (1UL << alias.s.m_alias);
902                         redirect.v = uv_read_local_mmr(m_redirect);
903                         *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
904                         return;
905                 }
906         }
907         *base = *size = 0;
908 }
909 
910 enum map_type {map_wb, map_uc};
911 static const char * const mt[] = { "WB", "UC" };
912 
913 static __init void map_high(char *id, unsigned long base, int pshift, int bshift, int max_pnode, enum map_type map_type)
914 {
915         unsigned long bytes, paddr;
916 
917         paddr = base << pshift;
918         bytes = (1UL << bshift) * (max_pnode + 1);
919         if (!paddr) {
920                 pr_info("UV: Map %s_HI base address NULL\n", id);
921                 return;
922         }
923         if (map_type == map_uc)
924                 init_extra_mapping_uc(paddr, bytes);
925         else
926                 init_extra_mapping_wb(paddr, bytes);
927 
928         pr_info("UV: Map %s_HI 0x%lx - 0x%lx %s (%d segments)\n",
929                 id, paddr, paddr + bytes, mt[map_type], max_pnode + 1);
930 }
931 
932 static __init void map_gru_high(int max_pnode)
933 {
934         union uvh_rh_gam_gru_overlay_config_u gru;
935         unsigned long mask, base;
936         int shift;
937 
938         if (UVH_RH_GAM_GRU_OVERLAY_CONFIG) {
939                 gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG);
940                 shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_BASE_SHFT;
941                 mask = UVH_RH_GAM_GRU_OVERLAY_CONFIG_BASE_MASK;
942         } else if (UVH_RH10_GAM_GRU_OVERLAY_CONFIG) {
943                 gru.v = uv_read_local_mmr(UVH_RH10_GAM_GRU_OVERLAY_CONFIG);
944                 shift = UVH_RH10_GAM_GRU_OVERLAY_CONFIG_BASE_SHFT;
945                 mask = UVH_RH10_GAM_GRU_OVERLAY_CONFIG_BASE_MASK;
946         } else {
947                 pr_err("UV: GRU unavailable (no MMR)\n");
948                 return;
949         }
950 
951         if (!gru.s.enable) {
952                 pr_info("UV: GRU disabled (by BIOS)\n");
953                 return;
954         }
955 
956         base = (gru.v & mask) >> shift;
957         map_high("GRU", base, shift, shift, max_pnode, map_wb);
958         gru_start_paddr = ((u64)base << shift);
959         gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1);
960 }
961 
962 static __init void map_mmr_high(int max_pnode)
963 {
964         unsigned long base;
965         int shift;
966         bool enable;
967 
968         if (UVH_RH10_GAM_MMR_OVERLAY_CONFIG) {
969                 union uvh_rh10_gam_mmr_overlay_config_u mmr;
970 
971                 mmr.v = uv_read_local_mmr(UVH_RH10_GAM_MMR_OVERLAY_CONFIG);
972                 enable = mmr.s.enable;
973                 base = mmr.s.base;
974                 shift = UVH_RH10_GAM_MMR_OVERLAY_CONFIG_BASE_SHFT;
975         } else if (UVH_RH_GAM_MMR_OVERLAY_CONFIG) {
976                 union uvh_rh_gam_mmr_overlay_config_u mmr;
977 
978                 mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG);
979                 enable = mmr.s.enable;
980                 base = mmr.s.base;
981                 shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_BASE_SHFT;
982         } else {
983                 pr_err("UV:%s:RH_GAM_MMR_OVERLAY_CONFIG MMR undefined?\n",
984                         __func__);
985                 return;
986         }
987 
988         if (enable)
989                 map_high("MMR", base, shift, shift, max_pnode, map_uc);
990         else
991                 pr_info("UV: MMR disabled\n");
992 }
993 
994 /* Arch specific ENUM cases */
995 enum mmioh_arch {
996         UV2_MMIOH = -1,
997         UVY_MMIOH0, UVY_MMIOH1,
998         UVX_MMIOH0, UVX_MMIOH1,
999 };
1000 
1001 /* Calculate and Map MMIOH Regions */
1002 static void __init calc_mmioh_map(enum mmioh_arch index,
1003         int min_pnode, int max_pnode,
1004         int shift, unsigned long base, int m_io, int n_io)
1005 {
1006         unsigned long mmr, nasid_mask;
1007         int nasid, min_nasid, max_nasid, lnasid, mapped;
1008         int i, fi, li, n, max_io;
1009         char id[8];
1010 
1011         /* One (UV2) mapping */
1012         if (index == UV2_MMIOH) {
1013                 strncpy(id, "MMIOH", sizeof(id));
1014                 max_io = max_pnode;
1015                 mapped = 0;
1016                 goto map_exit;
1017         }
1018 
1019         /* small and large MMIOH mappings */
1020         switch (index) {
1021         case UVY_MMIOH0:
1022                 mmr = UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG0;
1023                 nasid_mask = UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0_BASE_MASK;
1024                 n = UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG0_DEPTH;
1025                 min_nasid = min_pnode;
1026                 max_nasid = max_pnode;
1027                 mapped = 1;
1028                 break;
1029         case UVY_MMIOH1:
1030                 mmr = UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG1;
1031                 nasid_mask = UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG1_BASE_MASK;
1032                 n = UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG1_DEPTH;
1033                 min_nasid = min_pnode;
1034                 max_nasid = max_pnode;
1035                 mapped = 1;
1036                 break;
1037         case UVX_MMIOH0:
1038                 mmr = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0;
1039                 nasid_mask = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_BASE_MASK;
1040                 n = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_DEPTH;
1041                 min_nasid = min_pnode * 2;
1042                 max_nasid = max_pnode * 2;
1043                 mapped = 1;
1044                 break;
1045         case UVX_MMIOH1:
1046                 mmr = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1;
1047                 nasid_mask = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_BASE_MASK;
1048                 n = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_DEPTH;
1049                 min_nasid = min_pnode * 2;
1050                 max_nasid = max_pnode * 2;
1051                 mapped = 1;
1052                 break;
1053         default:
1054                 pr_err("UV:%s:Invalid mapping type:%d\n", __func__, index);
1055                 return;
1056         }
1057 
1058         /* enum values chosen so (index mod 2) is MMIOH 0/1 (low/high) */
1059         snprintf(id, sizeof(id), "MMIOH%d", index%2);
1060 
1061         max_io = lnasid = fi = li = -1;
1062         for (i = 0; i < n; i++) {
1063                 unsigned long m_redirect = mmr + i * 8;
1064                 unsigned long redirect = uv_read_local_mmr(m_redirect);
1065 
1066                 nasid = redirect & nasid_mask;
1067                 if (i == 0)
1068                         pr_info("UV: %s redirect base 0x%lx(@0x%lx) 0x%04x\n",
1069                                 id, redirect, m_redirect, nasid);
1070 
1071                 /* Invalid NASID check */
1072                 if (nasid < min_nasid || max_nasid < nasid) {
1073                         pr_err("UV:%s:Invalid NASID:%x (range:%x..%x)\n",
1074                                 __func__, index, min_nasid, max_nasid);
1075                         nasid = -1;
1076                 }
1077 
1078                 if (nasid == lnasid) {
1079                         li = i;
1080                         /* Last entry check: */
1081                         if (i != n-1)
1082                                 continue;
1083                 }
1084 
1085                 /* Check if we have a cached (or last) redirect to print: */
1086                 if (lnasid != -1 || (i == n-1 && nasid != -1))  {
1087                         unsigned long addr1, addr2;
1088                         int f, l;
1089 
1090                         if (lnasid == -1) {
1091                                 f = l = i;
1092                                 lnasid = nasid;
1093                         } else {
1094                                 f = fi;
1095                                 l = li;
1096                         }
1097                         addr1 = (base << shift) + f * (1ULL << m_io);
1098                         addr2 = (base << shift) + (l + 1) * (1ULL << m_io);
1099                         pr_info("UV: %s[%03d..%03d] NASID 0x%04x ADDR 0x%016lx - 0x%016lx\n",
1100                                 id, fi, li, lnasid, addr1, addr2);
1101                         if (max_io < l)
1102                                 max_io = l;
1103                 }
1104                 fi = li = i;
1105                 lnasid = nasid;
1106         }
1107 
1108 map_exit:
1109         pr_info("UV: %s base:0x%lx shift:%d m_io:%d max_io:%d max_pnode:0x%x\n",
1110                 id, base, shift, m_io, max_io, max_pnode);
1111 
1112         if (max_io >= 0 && !mapped)
1113                 map_high(id, base, shift, m_io, max_io, map_uc);
1114 }
1115 
1116 static __init void map_mmioh_high(int min_pnode, int max_pnode)
1117 {
1118         /* UVY flavor */
1119         if (UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0) {
1120                 union uvh_rh10_gam_mmioh_overlay_config0_u mmioh0;
1121                 union uvh_rh10_gam_mmioh_overlay_config1_u mmioh1;
1122 
1123                 mmioh0.v = uv_read_local_mmr(UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0);
1124                 if (unlikely(mmioh0.s.enable == 0))
1125                         pr_info("UV: MMIOH0 disabled\n");
1126                 else
1127                         calc_mmioh_map(UVY_MMIOH0, min_pnode, max_pnode,
1128                                 UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0_BASE_SHFT,
1129                                 mmioh0.s.base, mmioh0.s.m_io, mmioh0.s.n_io);
1130 
1131                 mmioh1.v = uv_read_local_mmr(UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG1);
1132                 if (unlikely(mmioh1.s.enable == 0))
1133                         pr_info("UV: MMIOH1 disabled\n");
1134                 else
1135                         calc_mmioh_map(UVY_MMIOH1, min_pnode, max_pnode,
1136                                 UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG1_BASE_SHFT,
1137                                 mmioh1.s.base, mmioh1.s.m_io, mmioh1.s.n_io);
1138                 return;
1139         }
1140         /* UVX flavor */
1141         if (UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0) {
1142                 union uvh_rh_gam_mmioh_overlay_config0_u mmioh0;
1143                 union uvh_rh_gam_mmioh_overlay_config1_u mmioh1;
1144 
1145                 mmioh0.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0);
1146                 if (unlikely(mmioh0.s.enable == 0))
1147                         pr_info("UV: MMIOH0 disabled\n");
1148                 else {
1149                         unsigned long base = uvxy_field(mmioh0, base, 0);
1150                         int m_io = uvxy_field(mmioh0, m_io, 0);
1151                         int n_io = uvxy_field(mmioh0, n_io, 0);
1152 
1153                         calc_mmioh_map(UVX_MMIOH0, min_pnode, max_pnode,
1154                                 UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_BASE_SHFT,
1155                                 base, m_io, n_io);
1156                 }
1157 
1158                 mmioh1.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1);
1159                 if (unlikely(mmioh1.s.enable == 0))
1160                         pr_info("UV: MMIOH1 disabled\n");
1161                 else {
1162                         unsigned long base = uvxy_field(mmioh1, base, 0);
1163                         int m_io = uvxy_field(mmioh1, m_io, 0);
1164                         int n_io = uvxy_field(mmioh1, n_io, 0);
1165 
1166                         calc_mmioh_map(UVX_MMIOH1, min_pnode, max_pnode,
1167                                 UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_BASE_SHFT,
1168                                 base, m_io, n_io);
1169                 }
1170                 return;
1171         }
1172 
1173         /* UV2 flavor */
1174         if (UVH_RH_GAM_MMIOH_OVERLAY_CONFIG) {
1175                 union uvh_rh_gam_mmioh_overlay_config_u mmioh;
1176 
1177                 mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG);
1178                 if (unlikely(mmioh.s2.enable == 0))
1179                         pr_info("UV: MMIOH disabled\n");
1180                 else
1181                         calc_mmioh_map(UV2_MMIOH, min_pnode, max_pnode,
1182                                 UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_BASE_SHFT,
1183                                 mmioh.s2.base, mmioh.s2.m_io, mmioh.s2.n_io);
1184                 return;
1185         }
1186 }
1187 
1188 static __init void map_low_mmrs(void)
1189 {
1190         if (UV_GLOBAL_MMR32_BASE)
1191                 init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
1192 
1193         if (UV_LOCAL_MMR_BASE)
1194                 init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
1195 }
1196 
1197 static __init void uv_rtc_init(void)
1198 {
1199         long status;
1200         u64 ticks_per_sec;
1201 
1202         status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK, &ticks_per_sec);
1203 
1204         if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
1205                 pr_warn("UV: unable to determine platform RTC clock frequency, guessing.\n");
1206 
1207                 /* BIOS gives wrong value for clock frequency, so guess: */
1208                 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
1209         } else {
1210                 sn_rtc_cycles_per_second = ticks_per_sec;
1211         }
1212 }
1213 
1214 /* Direct Legacy VGA I/O traffic to designated IOH */
1215 static int uv_set_vga_state(struct pci_dev *pdev, bool decode, unsigned int command_bits, u32 flags)
1216 {
1217         int domain, bus, rc;
1218 
1219         if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
1220                 return 0;
1221 
1222         if ((command_bits & PCI_COMMAND_IO) == 0)
1223                 return 0;
1224 
1225         domain = pci_domain_nr(pdev->bus);
1226         bus = pdev->bus->number;
1227 
1228         rc = uv_bios_set_legacy_vga_target(decode, domain, bus);
1229 
1230         return rc;
1231 }
1232 
1233 /*
1234  * Called on each CPU to initialize the per_cpu UV data area.
1235  * FIXME: hotplug not supported yet
1236  */
1237 void uv_cpu_init(void)
1238 {
1239         /* CPU 0 initialization will be done via uv_system_init. */
1240         if (smp_processor_id() == 0)
1241                 return;
1242 
1243         uv_hub_info->nr_online_cpus++;
1244 }
1245 
1246 struct mn {
1247         unsigned char   m_val;
1248         unsigned char   n_val;
1249         unsigned char   m_shift;
1250         unsigned char   n_lshift;
1251 };
1252 
1253 /* Initialize caller's MN struct and fill in values */
1254 static void get_mn(struct mn *mnp)
1255 {
1256         memset(mnp, 0, sizeof(*mnp));
1257         mnp->n_val      = uv_cpuid.n_skt;
1258         if (is_uv(UV4|UVY)) {
1259                 mnp->m_val      = 0;
1260                 mnp->n_lshift   = 0;
1261         } else if (is_uv3_hub()) {
1262                 union uvyh_gr0_gam_gr_config_u m_gr_config;
1263 
1264                 mnp->m_val      = uv_cpuid.m_skt;
1265                 m_gr_config.v   = uv_read_local_mmr(UVH_GR0_GAM_GR_CONFIG);
1266                 mnp->n_lshift   = m_gr_config.s3.m_skt;
1267         } else if (is_uv2_hub()) {
1268                 mnp->m_val      = uv_cpuid.m_skt;
1269                 mnp->n_lshift   = mnp->m_val == 40 ? 40 : 39;
1270         }
1271         mnp->m_shift = mnp->m_val ? 64 - mnp->m_val : 0;
1272 }
1273 
1274 static void __init uv_init_hub_info(struct uv_hub_info_s *hi)
1275 {
1276         struct mn mn;
1277 
1278         get_mn(&mn);
1279         hi->gpa_mask = mn.m_val ?
1280                 (1UL << (mn.m_val + mn.n_val)) - 1 :
1281                 (1UL << uv_cpuid.gpa_shift) - 1;
1282 
1283         hi->m_val               = mn.m_val;
1284         hi->n_val               = mn.n_val;
1285         hi->m_shift             = mn.m_shift;
1286         hi->n_lshift            = mn.n_lshift ? mn.n_lshift : 0;
1287         hi->hub_revision        = uv_hub_info->hub_revision;
1288         hi->hub_type            = uv_hub_info->hub_type;
1289         hi->pnode_mask          = uv_cpuid.pnode_mask;
1290         hi->nasid_shift         = uv_cpuid.nasid_shift;
1291         hi->min_pnode           = _min_pnode;
1292         hi->min_socket          = _min_socket;
1293         hi->pnode_to_socket     = _pnode_to_socket;
1294         hi->socket_to_node      = _socket_to_node;
1295         hi->socket_to_pnode     = _socket_to_pnode;
1296         hi->gr_table_len        = _gr_table_len;
1297         hi->gr_table            = _gr_table;
1298 
1299         uv_cpuid.gnode_shift    = max_t(unsigned int, uv_cpuid.gnode_shift, mn.n_val);
1300         hi->gnode_extra         = (uv_node_id & ~((1 << uv_cpuid.gnode_shift) - 1)) >> 1;
1301         if (mn.m_val)
1302                 hi->gnode_upper = (u64)hi->gnode_extra << mn.m_val;
1303 
1304         if (uv_gp_table) {
1305                 hi->global_mmr_base     = uv_gp_table->mmr_base;
1306                 hi->global_mmr_shift    = uv_gp_table->mmr_shift;
1307                 hi->global_gru_base     = uv_gp_table->gru_base;
1308                 hi->global_gru_shift    = uv_gp_table->gru_shift;
1309                 hi->gpa_shift           = uv_gp_table->gpa_shift;
1310                 hi->gpa_mask            = (1UL << hi->gpa_shift) - 1;
1311         } else {
1312                 hi->global_mmr_base     =
1313                         uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG) &
1314                         ~UV_MMR_ENABLE;
1315                 hi->global_mmr_shift    = _UV_GLOBAL_MMR64_PNODE_SHIFT;
1316         }
1317 
1318         get_lowmem_redirect(&hi->lowmem_remap_base, &hi->lowmem_remap_top);
1319 
1320         hi->apic_pnode_shift = uv_cpuid.socketid_shift;
1321 
1322         /* Show system specific info: */
1323         pr_info("UV: N:%d M:%d m_shift:%d n_lshift:%d\n", hi->n_val, hi->m_val, hi->m_shift, hi->n_lshift);
1324         pr_info("UV: gpa_mask/shift:0x%lx/%d pnode_mask:0x%x apic_pns:%d\n", hi->gpa_mask, hi->gpa_shift, hi->pnode_mask, hi->apic_pnode_shift);
1325         pr_info("UV: mmr_base/shift:0x%lx/%ld\n", hi->global_mmr_base, hi->global_mmr_shift);
1326         if (hi->global_gru_base)
1327                 pr_info("UV: gru_base/shift:0x%lx/%ld\n",
1328                         hi->global_gru_base, hi->global_gru_shift);
1329 
1330         pr_info("UV: gnode_upper:0x%lx gnode_extra:0x%x\n", hi->gnode_upper, hi->gnode_extra);
1331 }
1332 
1333 static void __init decode_gam_params(unsigned long ptr)
1334 {
1335         uv_gp_table = (struct uv_gam_parameters *)ptr;
1336 
1337         pr_info("UV: GAM Params...\n");
1338         pr_info("UV: mmr_base/shift:0x%llx/%d gru_base/shift:0x%llx/%d gpa_shift:%d\n",
1339                 uv_gp_table->mmr_base, uv_gp_table->mmr_shift,
1340                 uv_gp_table->gru_base, uv_gp_table->gru_shift,
1341                 uv_gp_table->gpa_shift);
1342 }
1343 
1344 static void __init decode_gam_rng_tbl(unsigned long ptr)
1345 {
1346         struct uv_gam_range_entry *gre = (struct uv_gam_range_entry *)ptr;
1347         unsigned long lgre = 0;
1348         int index = 0;
1349         int sock_min = 999999, pnode_min = 99999;
1350         int sock_max = -1, pnode_max = -1;
1351 
1352         uv_gre_table = gre;
1353         for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
1354                 unsigned long size = ((unsigned long)(gre->limit - lgre)
1355                                         << UV_GAM_RANGE_SHFT);
1356                 int order = 0;
1357                 char suffix[] = " KMGTPE";
1358                 int flag = ' ';
1359 
1360                 while (size > 9999 && order < sizeof(suffix)) {
1361                         size /= 1024;
1362                         order++;
1363                 }
1364 
1365                 /* adjust max block size to current range start */
1366                 if (gre->type == 1 || gre->type == 2)
1367                         if (adj_blksize(lgre))
1368                                 flag = '*';
1369 
1370                 if (!index) {
1371                         pr_info("UV: GAM Range Table...\n");
1372                         pr_info("UV:  # %20s %14s %6s %4s %5s %3s %2s\n", "Range", "", "Size", "Type", "NASID", "SID", "PN");
1373                 }
1374                 pr_info("UV: %2d: 0x%014lx-0x%014lx%c %5lu%c %3d   %04x  %02x %02x\n",
1375                         index++,
1376                         (unsigned long)lgre << UV_GAM_RANGE_SHFT,
1377                         (unsigned long)gre->limit << UV_GAM_RANGE_SHFT,
1378                         flag, size, suffix[order],
1379                         gre->type, gre->nasid, gre->sockid, gre->pnode);
1380 
1381                 /* update to next range start */
1382                 lgre = gre->limit;
1383                 if (sock_min > gre->sockid)
1384                         sock_min = gre->sockid;
1385                 if (sock_max < gre->sockid)
1386                         sock_max = gre->sockid;
1387                 if (pnode_min > gre->pnode)
1388                         pnode_min = gre->pnode;
1389                 if (pnode_max < gre->pnode)
1390                         pnode_max = gre->pnode;
1391         }
1392         _min_socket     = sock_min;
1393         _max_socket     = sock_max;
1394         _min_pnode      = pnode_min;
1395         _max_pnode      = pnode_max;
1396         _gr_table_len   = index;
1397 
1398         pr_info("UV: GRT: %d entries, sockets(min:%x,max:%x) pnodes(min:%x,max:%x)\n", index, _min_socket, _max_socket, _min_pnode, _max_pnode);
1399 }
1400 
1401 /* Walk through UVsystab decoding the fields */
1402 static int __init decode_uv_systab(void)
1403 {
1404         struct uv_systab *st;
1405         int i;
1406 
1407         /* Get mapped UVsystab pointer */
1408         st = uv_systab;
1409 
1410         /* If UVsystab is version 1, there is no extended UVsystab */
1411         if (st && st->revision == UV_SYSTAB_VERSION_1)
1412                 return 0;
1413 
1414         if ((!st) || (st->revision < UV_SYSTAB_VERSION_UV4_LATEST)) {
1415                 int rev = st ? st->revision : 0;
1416 
1417                 pr_err("UV: BIOS UVsystab mismatch, (%x < %x)\n",
1418                         rev, UV_SYSTAB_VERSION_UV4_LATEST);
1419                 pr_err("UV: Does not support UV, switch to non-UV x86_64\n");
1420                 uv_system_type = UV_NONE;
1421 
1422                 return -EINVAL;
1423         }
1424 
1425         for (i = 0; st->entry[i].type != UV_SYSTAB_TYPE_UNUSED; i++) {
1426                 unsigned long ptr = st->entry[i].offset;
1427 
1428                 if (!ptr)
1429                         continue;
1430 
1431                 /* point to payload */
1432                 ptr += (unsigned long)st;
1433 
1434                 switch (st->entry[i].type) {
1435                 case UV_SYSTAB_TYPE_GAM_PARAMS:
1436                         decode_gam_params(ptr);
1437                         break;
1438 
1439                 case UV_SYSTAB_TYPE_GAM_RNG_TBL:
1440                         decode_gam_rng_tbl(ptr);
1441                         break;
1442 
1443                 case UV_SYSTAB_TYPE_ARCH_TYPE:
1444                         /* already processed in early startup */
1445                         break;
1446 
1447                 default:
1448                         pr_err("UV:%s:Unrecognized UV_SYSTAB_TYPE:%d, skipped\n",
1449                                 __func__, st->entry[i].type);
1450                         break;
1451                 }
1452         }
1453         return 0;
1454 }
1455 
1456 /* Set up physical blade translations from UVH_NODE_PRESENT_TABLE */
1457 static __init void boot_init_possible_blades(struct uv_hub_info_s *hub_info)
1458 {
1459         unsigned long np;
1460         int i, uv_pb = 0;
1461 
1462         if (UVH_NODE_PRESENT_TABLE) {
1463                 pr_info("UV: NODE_PRESENT_DEPTH = %d\n",
1464                         UVH_NODE_PRESENT_TABLE_DEPTH);
1465                 for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
1466                         np = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
1467                         pr_info("UV: NODE_PRESENT(%d) = 0x%016lx\n", i, np);
1468                         uv_pb += hweight64(np);
1469                 }
1470         }
1471         if (UVH_NODE_PRESENT_0) {
1472                 np = uv_read_local_mmr(UVH_NODE_PRESENT_0);
1473                 pr_info("UV: NODE_PRESENT_0 = 0x%016lx\n", np);
1474                 uv_pb += hweight64(np);
1475         }
1476         if (UVH_NODE_PRESENT_1) {
1477                 np = uv_read_local_mmr(UVH_NODE_PRESENT_1);
1478                 pr_info("UV: NODE_PRESENT_1 = 0x%016lx\n", np);
1479                 uv_pb += hweight64(np);
1480         }
1481         if (uv_possible_blades != uv_pb)
1482                 uv_possible_blades = uv_pb;
1483 
1484         pr_info("UV: number nodes/possible blades %d\n", uv_pb);
1485 }
1486 
1487 static void __init build_socket_tables(void)
1488 {
1489         struct uv_gam_range_entry *gre = uv_gre_table;
1490         int num, nump;
1491         int cpu, i, lnid;
1492         int minsock = _min_socket;
1493         int maxsock = _max_socket;
1494         int minpnode = _min_pnode;
1495         int maxpnode = _max_pnode;
1496         size_t bytes;
1497 
1498         if (!gre) {
1499                 if (is_uv2_hub() || is_uv3_hub()) {
1500                         pr_info("UV: No UVsystab socket table, ignoring\n");
1501                         return;
1502                 }
1503                 pr_err("UV: Error: UVsystab address translations not available!\n");
1504                 BUG();
1505         }
1506 
1507         /* Build socket id -> node id, pnode */
1508         num = maxsock - minsock + 1;
1509         bytes = num * sizeof(_socket_to_node[0]);
1510         _socket_to_node = kmalloc(bytes, GFP_KERNEL);
1511         _socket_to_pnode = kmalloc(bytes, GFP_KERNEL);
1512 
1513         nump = maxpnode - minpnode + 1;
1514         bytes = nump * sizeof(_pnode_to_socket[0]);
1515         _pnode_to_socket = kmalloc(bytes, GFP_KERNEL);
1516         BUG_ON(!_socket_to_node || !_socket_to_pnode || !_pnode_to_socket);
1517 
1518         for (i = 0; i < num; i++)
1519                 _socket_to_node[i] = _socket_to_pnode[i] = SOCK_EMPTY;
1520 
1521         for (i = 0; i < nump; i++)
1522                 _pnode_to_socket[i] = SOCK_EMPTY;
1523 
1524         /* Fill in pnode/node/addr conversion list values: */
1525         pr_info("UV: GAM Building socket/pnode conversion tables\n");
1526         for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
1527                 if (gre->type == UV_GAM_RANGE_TYPE_HOLE)
1528                         continue;
1529                 i = gre->sockid - minsock;
1530                 /* Duplicate: */
1531                 if (_socket_to_pnode[i] != SOCK_EMPTY)
1532                         continue;
1533                 _socket_to_pnode[i] = gre->pnode;
1534 
1535                 i = gre->pnode - minpnode;
1536                 _pnode_to_socket[i] = gre->sockid;
1537 
1538                 pr_info("UV: sid:%02x type:%d nasid:%04x pn:%02x pn2s:%2x\n",
1539                         gre->sockid, gre->type, gre->nasid,
1540                         _socket_to_pnode[gre->sockid - minsock],
1541                         _pnode_to_socket[gre->pnode - minpnode]);
1542         }
1543 
1544         /* Set socket -> node values: */
1545         lnid = NUMA_NO_NODE;
1546         for_each_present_cpu(cpu) {
1547                 int nid = cpu_to_node(cpu);
1548                 int apicid, sockid;
1549 
1550                 if (lnid == nid)
1551                         continue;
1552                 lnid = nid;
1553                 apicid = per_cpu(x86_cpu_to_apicid, cpu);
1554                 sockid = apicid >> uv_cpuid.socketid_shift;
1555                 _socket_to_node[sockid - minsock] = nid;
1556                 pr_info("UV: sid:%02x: apicid:%04x node:%2d\n",
1557                         sockid, apicid, nid);
1558         }
1559 
1560         /* Set up physical blade to pnode translation from GAM Range Table: */
1561         bytes = num_possible_nodes() * sizeof(_node_to_pnode[0]);
1562         _node_to_pnode = kmalloc(bytes, GFP_KERNEL);
1563         BUG_ON(!_node_to_pnode);
1564 
1565         for (lnid = 0; lnid < num_possible_nodes(); lnid++) {
1566                 unsigned short sockid;
1567 
1568                 for (sockid = minsock; sockid <= maxsock; sockid++) {
1569                         if (lnid == _socket_to_node[sockid - minsock]) {
1570                                 _node_to_pnode[lnid] = _socket_to_pnode[sockid - minsock];
1571                                 break;
1572                         }
1573                 }
1574                 if (sockid > maxsock) {
1575                         pr_err("UV: socket for node %d not found!\n", lnid);
1576                         BUG();
1577                 }
1578         }
1579 
1580         /*
1581          * If socket id == pnode or socket id == node for all nodes,
1582          *   system runs faster by removing corresponding conversion table.
1583          */
1584         pr_info("UV: Checking socket->node/pnode for identity maps\n");
1585         if (minsock == 0) {
1586                 for (i = 0; i < num; i++)
1587                         if (_socket_to_node[i] == SOCK_EMPTY || i != _socket_to_node[i])
1588                                 break;
1589                 if (i >= num) {
1590                         kfree(_socket_to_node);
1591                         _socket_to_node = NULL;
1592                         pr_info("UV: 1:1 socket_to_node table removed\n");
1593                 }
1594         }
1595         if (minsock == minpnode) {
1596                 for (i = 0; i < num; i++)
1597                         if (_socket_to_pnode[i] != SOCK_EMPTY &&
1598                                 _socket_to_pnode[i] != i + minpnode)
1599                                 break;
1600                 if (i >= num) {
1601                         kfree(_socket_to_pnode);
1602                         _socket_to_pnode = NULL;
1603                         pr_info("UV: 1:1 socket_to_pnode table removed\n");
1604                 }
1605         }
1606 }
1607 
1608 /* Check which reboot to use */
1609 static void check_efi_reboot(void)
1610 {
1611         /* If EFI reboot not available, use ACPI reboot */
1612         if (!efi_enabled(EFI_BOOT))
1613                 reboot_type = BOOT_ACPI;
1614 }
1615 
1616 /*
1617  * User proc fs file handling now deprecated.
1618  * Recommend using /sys/firmware/sgi_uv/... instead.
1619  */
1620 static int __maybe_unused proc_hubbed_show(struct seq_file *file, void *data)
1621 {
1622         pr_notice_once("%s: using deprecated /proc/sgi_uv/hubbed, use /sys/firmware/sgi_uv/hub_type\n",
1623                        current->comm);
1624         seq_printf(file, "0x%x\n", uv_hubbed_system);
1625         return 0;
1626 }
1627 
1628 static int __maybe_unused proc_hubless_show(struct seq_file *file, void *data)
1629 {
1630         pr_notice_once("%s: using deprecated /proc/sgi_uv/hubless, use /sys/firmware/sgi_uv/hubless\n",
1631                        current->comm);
1632         seq_printf(file, "0x%x\n", uv_hubless_system);
1633         return 0;
1634 }
1635 
1636 static int __maybe_unused proc_archtype_show(struct seq_file *file, void *data)
1637 {
1638         pr_notice_once("%s: using deprecated /proc/sgi_uv/archtype, use /sys/firmware/sgi_uv/archtype\n",
1639                        current->comm);
1640         seq_printf(file, "%s/%s\n", uv_archtype, oem_table_id);
1641         return 0;
1642 }
1643 
1644 static __init void uv_setup_proc_files(int hubless)
1645 {
1646         struct proc_dir_entry *pde;
1647 
1648         pde = proc_mkdir(UV_PROC_NODE, NULL);
1649         proc_create_single("archtype", 0, pde, proc_archtype_show);
1650         if (hubless)
1651                 proc_create_single("hubless", 0, pde, proc_hubless_show);
1652         else
1653                 proc_create_single("hubbed", 0, pde, proc_hubbed_show);
1654 }
1655 
1656 /* Initialize UV hubless systems */
1657 static __init int uv_system_init_hubless(void)
1658 {
1659         int rc;
1660 
1661         /* Setup PCH NMI handler */
1662         uv_nmi_setup_hubless();
1663 
1664         /* Init kernel/BIOS interface */
1665         rc = uv_bios_init();
1666         if (rc < 0)
1667                 return rc;
1668 
1669         /* Process UVsystab */
1670         rc = decode_uv_systab();
1671         if (rc < 0)
1672                 return rc;
1673 
1674         /* Create user access node */
1675         if (rc >= 0)
1676                 uv_setup_proc_files(1);
1677 
1678         check_efi_reboot();
1679 
1680         return rc;
1681 }
1682 
1683 static void __init uv_system_init_hub(void)
1684 {
1685         struct uv_hub_info_s hub_info = {0};
1686         int bytes, cpu, nodeid;
1687         unsigned short min_pnode = 9999, max_pnode = 0;
1688         char *hub = is_uv5_hub() ? "UV500" :
1689                     is_uv4_hub() ? "UV400" :
1690                     is_uv3_hub() ? "UV300" :
1691                     is_uv2_hub() ? "UV2000/3000" : NULL;
1692 
1693         if (!hub) {
1694                 pr_err("UV: Unknown/unsupported UV hub\n");
1695                 return;
1696         }
1697         pr_info("UV: Found %s hub\n", hub);
1698 
1699         map_low_mmrs();
1700 
1701         /* Get uv_systab for decoding, setup UV BIOS calls */
1702         uv_bios_init();
1703 
1704         /* If there's an UVsystab problem then abort UV init: */
1705         if (decode_uv_systab() < 0) {
1706                 pr_err("UV: Mangled UVsystab format\n");
1707                 return;
1708         }
1709 
1710         build_socket_tables();
1711         build_uv_gr_table();
1712         set_block_size();
1713         uv_init_hub_info(&hub_info);
1714         uv_possible_blades = num_possible_nodes();
1715         if (!_node_to_pnode)
1716                 boot_init_possible_blades(&hub_info);
1717 
1718         /* uv_num_possible_blades() is really the hub count: */
1719         pr_info("UV: Found %d hubs, %d nodes, %d CPUs\n", uv_num_possible_blades(), num_possible_nodes(), num_possible_cpus());
1720 
1721         uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id, &sn_region_size, &system_serial_number);
1722         hub_info.coherency_domain_number = sn_coherency_id;
1723         uv_rtc_init();
1724 
1725         bytes = sizeof(void *) * uv_num_possible_blades();
1726         __uv_hub_info_list = kzalloc(bytes, GFP_KERNEL);
1727         BUG_ON(!__uv_hub_info_list);
1728 
1729         bytes = sizeof(struct uv_hub_info_s);
1730         for_each_node(nodeid) {
1731                 struct uv_hub_info_s *new_hub;
1732 
1733                 if (__uv_hub_info_list[nodeid]) {
1734                         pr_err("UV: Node %d UV HUB already initialized!?\n", nodeid);
1735                         BUG();
1736                 }
1737 
1738                 /* Allocate new per hub info list */
1739                 new_hub = (nodeid == 0) ?  &uv_hub_info_node0 : kzalloc_node(bytes, GFP_KERNEL, nodeid);
1740                 BUG_ON(!new_hub);
1741                 __uv_hub_info_list[nodeid] = new_hub;
1742                 new_hub = uv_hub_info_list(nodeid);
1743                 BUG_ON(!new_hub);
1744                 *new_hub = hub_info;
1745 
1746                 /* Use information from GAM table if available: */
1747                 if (_node_to_pnode)
1748                         new_hub->pnode = _node_to_pnode[nodeid];
1749                 else /* Or fill in during CPU loop: */
1750                         new_hub->pnode = 0xffff;
1751 
1752                 new_hub->numa_blade_id = uv_node_to_blade_id(nodeid);
1753                 new_hub->memory_nid = NUMA_NO_NODE;
1754                 new_hub->nr_possible_cpus = 0;
1755                 new_hub->nr_online_cpus = 0;
1756         }
1757 
1758         /* Initialize per CPU info: */
1759         for_each_possible_cpu(cpu) {
1760                 int apicid = per_cpu(x86_cpu_to_apicid, cpu);
1761                 int numa_node_id;
1762                 unsigned short pnode;
1763 
1764                 nodeid = cpu_to_node(cpu);
1765                 numa_node_id = numa_cpu_node(cpu);
1766                 pnode = uv_apicid_to_pnode(apicid);
1767 
1768                 uv_cpu_info_per(cpu)->p_uv_hub_info = uv_hub_info_list(nodeid);
1769                 uv_cpu_info_per(cpu)->blade_cpu_id = uv_cpu_hub_info(cpu)->nr_possible_cpus++;
1770                 if (uv_cpu_hub_info(cpu)->memory_nid == NUMA_NO_NODE)
1771                         uv_cpu_hub_info(cpu)->memory_nid = cpu_to_node(cpu);
1772 
1773                 /* Init memoryless node: */
1774                 if (nodeid != numa_node_id &&
1775                     uv_hub_info_list(numa_node_id)->pnode == 0xffff)
1776                         uv_hub_info_list(numa_node_id)->pnode = pnode;
1777                 else if (uv_cpu_hub_info(cpu)->pnode == 0xffff)
1778                         uv_cpu_hub_info(cpu)->pnode = pnode;
1779         }
1780 
1781         for_each_node(nodeid) {
1782                 unsigned short pnode = uv_hub_info_list(nodeid)->pnode;
1783 
1784                 /* Add pnode info for pre-GAM list nodes without CPUs: */
1785                 if (pnode == 0xffff) {
1786                         unsigned long paddr;
1787 
1788                         paddr = node_start_pfn(nodeid) << PAGE_SHIFT;
1789                         pnode = uv_gpa_to_pnode(uv_soc_phys_ram_to_gpa(paddr));
1790                         uv_hub_info_list(nodeid)->pnode = pnode;
1791                 }
1792                 min_pnode = min(pnode, min_pnode);
1793                 max_pnode = max(pnode, max_pnode);
1794                 pr_info("UV: UVHUB node:%2d pn:%02x nrcpus:%d\n",
1795                         nodeid,
1796                         uv_hub_info_list(nodeid)->pnode,
1797                         uv_hub_info_list(nodeid)->nr_possible_cpus);
1798         }
1799 
1800         pr_info("UV: min_pnode:%02x max_pnode:%02x\n", min_pnode, max_pnode);
1801         map_gru_high(max_pnode);
1802         map_mmr_high(max_pnode);
1803         map_mmioh_high(min_pnode, max_pnode);
1804 
1805         uv_nmi_setup();
1806         uv_cpu_init();
1807         uv_setup_proc_files(0);
1808 
1809         /* Register Legacy VGA I/O redirection handler: */
1810         pci_register_set_vga_state(uv_set_vga_state);
1811 
1812         check_efi_reboot();
1813 }
1814 
1815 /*
1816  * There is a different code path needed to initialize a UV system that does
1817  * not have a "UV HUB" (referred to as "hubless").
1818  */
1819 void __init uv_system_init(void)
1820 {
1821         if (likely(!is_uv_system() && !is_uv_hubless(1)))
1822                 return;
1823 
1824         if (is_uv_system())
1825                 uv_system_init_hub();
1826         else
1827                 uv_system_init_hubless();
1828 }
1829 
1830 apic_driver(apic_x2apic_uv_x);
1831 

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