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TOMOYO Linux Cross Reference
Linux/arch/x86/kernel/cpu/common.c

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  1 #include <linux/bootmem.h>
  2 #include <linux/linkage.h>
  3 #include <linux/bitops.h>
  4 #include <linux/kernel.h>
  5 #include <linux/module.h>
  6 #include <linux/percpu.h>
  7 #include <linux/string.h>
  8 #include <linux/delay.h>
  9 #include <linux/sched.h>
 10 #include <linux/init.h>
 11 #include <linux/kgdb.h>
 12 #include <linux/smp.h>
 13 #include <linux/io.h>
 14 
 15 #include <asm/stackprotector.h>
 16 #include <asm/perf_event.h>
 17 #include <asm/mmu_context.h>
 18 #include <asm/archrandom.h>
 19 #include <asm/hypervisor.h>
 20 #include <asm/processor.h>
 21 #include <asm/debugreg.h>
 22 #include <asm/sections.h>
 23 #include <linux/topology.h>
 24 #include <linux/cpumask.h>
 25 #include <asm/pgtable.h>
 26 #include <linux/atomic.h>
 27 #include <asm/proto.h>
 28 #include <asm/setup.h>
 29 #include <asm/apic.h>
 30 #include <asm/desc.h>
 31 #include <asm/i387.h>
 32 #include <asm/fpu-internal.h>
 33 #include <asm/mtrr.h>
 34 #include <linux/numa.h>
 35 #include <asm/asm.h>
 36 #include <asm/cpu.h>
 37 #include <asm/mce.h>
 38 #include <asm/msr.h>
 39 #include <asm/pat.h>
 40 #include <asm/microcode.h>
 41 #include <asm/microcode_intel.h>
 42 
 43 #ifdef CONFIG_X86_LOCAL_APIC
 44 #include <asm/uv/uv.h>
 45 #endif
 46 
 47 #include "cpu.h"
 48 
 49 /* all of these masks are initialized in setup_cpu_local_masks() */
 50 cpumask_var_t cpu_initialized_mask;
 51 cpumask_var_t cpu_callout_mask;
 52 cpumask_var_t cpu_callin_mask;
 53 
 54 /* representing cpus for which sibling maps can be computed */
 55 cpumask_var_t cpu_sibling_setup_mask;
 56 
 57 /* correctly size the local cpu masks */
 58 void __init setup_cpu_local_masks(void)
 59 {
 60         alloc_bootmem_cpumask_var(&cpu_initialized_mask);
 61         alloc_bootmem_cpumask_var(&cpu_callin_mask);
 62         alloc_bootmem_cpumask_var(&cpu_callout_mask);
 63         alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
 64 }
 65 
 66 static void default_init(struct cpuinfo_x86 *c)
 67 {
 68 #ifdef CONFIG_X86_64
 69         cpu_detect_cache_sizes(c);
 70 #else
 71         /* Not much we can do here... */
 72         /* Check if at least it has cpuid */
 73         if (c->cpuid_level == -1) {
 74                 /* No cpuid. It must be an ancient CPU */
 75                 if (c->x86 == 4)
 76                         strcpy(c->x86_model_id, "486");
 77                 else if (c->x86 == 3)
 78                         strcpy(c->x86_model_id, "386");
 79         }
 80 #endif
 81 }
 82 
 83 static const struct cpu_dev default_cpu = {
 84         .c_init         = default_init,
 85         .c_vendor       = "Unknown",
 86         .c_x86_vendor   = X86_VENDOR_UNKNOWN,
 87 };
 88 
 89 static const struct cpu_dev *this_cpu = &default_cpu;
 90 
 91 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
 92 #ifdef CONFIG_X86_64
 93         /*
 94          * We need valid kernel segments for data and code in long mode too
 95          * IRET will check the segment types  kkeil 2000/10/28
 96          * Also sysret mandates a special GDT layout
 97          *
 98          * TLS descriptors are currently at a different place compared to i386.
 99          * Hopefully nobody expects them at a fixed place (Wine?)
100          */
101         [GDT_ENTRY_KERNEL32_CS]         = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
102         [GDT_ENTRY_KERNEL_CS]           = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
103         [GDT_ENTRY_KERNEL_DS]           = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
104         [GDT_ENTRY_DEFAULT_USER32_CS]   = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
105         [GDT_ENTRY_DEFAULT_USER_DS]     = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
106         [GDT_ENTRY_DEFAULT_USER_CS]     = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
107 #else
108         [GDT_ENTRY_KERNEL_CS]           = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
109         [GDT_ENTRY_KERNEL_DS]           = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
110         [GDT_ENTRY_DEFAULT_USER_CS]     = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
111         [GDT_ENTRY_DEFAULT_USER_DS]     = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
112         /*
113          * Segments used for calling PnP BIOS have byte granularity.
114          * They code segments and data segments have fixed 64k limits,
115          * the transfer segment sizes are set at run time.
116          */
117         /* 32-bit code */
118         [GDT_ENTRY_PNPBIOS_CS32]        = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
119         /* 16-bit code */
120         [GDT_ENTRY_PNPBIOS_CS16]        = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
121         /* 16-bit data */
122         [GDT_ENTRY_PNPBIOS_DS]          = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
123         /* 16-bit data */
124         [GDT_ENTRY_PNPBIOS_TS1]         = GDT_ENTRY_INIT(0x0092, 0, 0),
125         /* 16-bit data */
126         [GDT_ENTRY_PNPBIOS_TS2]         = GDT_ENTRY_INIT(0x0092, 0, 0),
127         /*
128          * The APM segments have byte granularity and their bases
129          * are set at run time.  All have 64k limits.
130          */
131         /* 32-bit code */
132         [GDT_ENTRY_APMBIOS_BASE]        = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
133         /* 16-bit code */
134         [GDT_ENTRY_APMBIOS_BASE+1]      = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
135         /* data */
136         [GDT_ENTRY_APMBIOS_BASE+2]      = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
137 
138         [GDT_ENTRY_ESPFIX_SS]           = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
139         [GDT_ENTRY_PERCPU]              = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
140         GDT_STACK_CANARY_INIT
141 #endif
142 } };
143 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
144 
145 static int __init x86_xsave_setup(char *s)
146 {
147         setup_clear_cpu_cap(X86_FEATURE_XSAVE);
148         setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
149         setup_clear_cpu_cap(X86_FEATURE_AVX);
150         setup_clear_cpu_cap(X86_FEATURE_AVX2);
151         return 1;
152 }
153 __setup("noxsave", x86_xsave_setup);
154 
155 static int __init x86_xsaveopt_setup(char *s)
156 {
157         setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
158         return 1;
159 }
160 __setup("noxsaveopt", x86_xsaveopt_setup);
161 
162 #ifdef CONFIG_X86_32
163 static int cachesize_override = -1;
164 static int disable_x86_serial_nr = 1;
165 
166 static int __init cachesize_setup(char *str)
167 {
168         get_option(&str, &cachesize_override);
169         return 1;
170 }
171 __setup("cachesize=", cachesize_setup);
172 
173 static int __init x86_fxsr_setup(char *s)
174 {
175         setup_clear_cpu_cap(X86_FEATURE_FXSR);
176         setup_clear_cpu_cap(X86_FEATURE_XMM);
177         return 1;
178 }
179 __setup("nofxsr", x86_fxsr_setup);
180 
181 static int __init x86_sep_setup(char *s)
182 {
183         setup_clear_cpu_cap(X86_FEATURE_SEP);
184         return 1;
185 }
186 __setup("nosep", x86_sep_setup);
187 
188 /* Standard macro to see if a specific flag is changeable */
189 static inline int flag_is_changeable_p(u32 flag)
190 {
191         u32 f1, f2;
192 
193         /*
194          * Cyrix and IDT cpus allow disabling of CPUID
195          * so the code below may return different results
196          * when it is executed before and after enabling
197          * the CPUID. Add "volatile" to not allow gcc to
198          * optimize the subsequent calls to this function.
199          */
200         asm volatile ("pushfl           \n\t"
201                       "pushfl           \n\t"
202                       "popl %0          \n\t"
203                       "movl %0, %1      \n\t"
204                       "xorl %2, %0      \n\t"
205                       "pushl %0         \n\t"
206                       "popfl            \n\t"
207                       "pushfl           \n\t"
208                       "popl %0          \n\t"
209                       "popfl            \n\t"
210 
211                       : "=&r" (f1), "=&r" (f2)
212                       : "ir" (flag));
213 
214         return ((f1^f2) & flag) != 0;
215 }
216 
217 /* Probe for the CPUID instruction */
218 int have_cpuid_p(void)
219 {
220         return flag_is_changeable_p(X86_EFLAGS_ID);
221 }
222 
223 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
224 {
225         unsigned long lo, hi;
226 
227         if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
228                 return;
229 
230         /* Disable processor serial number: */
231 
232         rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
233         lo |= 0x200000;
234         wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
235 
236         printk(KERN_NOTICE "CPU serial number disabled.\n");
237         clear_cpu_cap(c, X86_FEATURE_PN);
238 
239         /* Disabling the serial number may affect the cpuid level */
240         c->cpuid_level = cpuid_eax(0);
241 }
242 
243 static int __init x86_serial_nr_setup(char *s)
244 {
245         disable_x86_serial_nr = 0;
246         return 1;
247 }
248 __setup("serialnumber", x86_serial_nr_setup);
249 #else
250 static inline int flag_is_changeable_p(u32 flag)
251 {
252         return 1;
253 }
254 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
255 {
256 }
257 #endif
258 
259 static __init int setup_disable_smep(char *arg)
260 {
261         setup_clear_cpu_cap(X86_FEATURE_SMEP);
262         return 1;
263 }
264 __setup("nosmep", setup_disable_smep);
265 
266 static __always_inline void setup_smep(struct cpuinfo_x86 *c)
267 {
268         if (cpu_has(c, X86_FEATURE_SMEP))
269                 set_in_cr4(X86_CR4_SMEP);
270 }
271 
272 static __init int setup_disable_smap(char *arg)
273 {
274         setup_clear_cpu_cap(X86_FEATURE_SMAP);
275         return 1;
276 }
277 __setup("nosmap", setup_disable_smap);
278 
279 static __always_inline void setup_smap(struct cpuinfo_x86 *c)
280 {
281         unsigned long eflags;
282 
283         /* This should have been cleared long ago */
284         raw_local_save_flags(eflags);
285         BUG_ON(eflags & X86_EFLAGS_AC);
286 
287         if (cpu_has(c, X86_FEATURE_SMAP)) {
288 #ifdef CONFIG_X86_SMAP
289                 set_in_cr4(X86_CR4_SMAP);
290 #else
291                 clear_in_cr4(X86_CR4_SMAP);
292 #endif
293         }
294 }
295 
296 /*
297  * Some CPU features depend on higher CPUID levels, which may not always
298  * be available due to CPUID level capping or broken virtualization
299  * software.  Add those features to this table to auto-disable them.
300  */
301 struct cpuid_dependent_feature {
302         u32 feature;
303         u32 level;
304 };
305 
306 static const struct cpuid_dependent_feature
307 cpuid_dependent_features[] = {
308         { X86_FEATURE_MWAIT,            0x00000005 },
309         { X86_FEATURE_DCA,              0x00000009 },
310         { X86_FEATURE_XSAVE,            0x0000000d },
311         { 0, 0 }
312 };
313 
314 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
315 {
316         const struct cpuid_dependent_feature *df;
317 
318         for (df = cpuid_dependent_features; df->feature; df++) {
319 
320                 if (!cpu_has(c, df->feature))
321                         continue;
322                 /*
323                  * Note: cpuid_level is set to -1 if unavailable, but
324                  * extended_extended_level is set to 0 if unavailable
325                  * and the legitimate extended levels are all negative
326                  * when signed; hence the weird messing around with
327                  * signs here...
328                  */
329                 if (!((s32)df->level < 0 ?
330                      (u32)df->level > (u32)c->extended_cpuid_level :
331                      (s32)df->level > (s32)c->cpuid_level))
332                         continue;
333 
334                 clear_cpu_cap(c, df->feature);
335                 if (!warn)
336                         continue;
337 
338                 printk(KERN_WARNING
339                        "CPU: CPU feature %s disabled, no CPUID level 0x%x\n",
340                                 x86_cap_flags[df->feature], df->level);
341         }
342 }
343 
344 /*
345  * Naming convention should be: <Name> [(<Codename>)]
346  * This table only is used unless init_<vendor>() below doesn't set it;
347  * in particular, if CPUID levels 0x80000002..4 are supported, this
348  * isn't used
349  */
350 
351 /* Look up CPU names by table lookup. */
352 static const char *table_lookup_model(struct cpuinfo_x86 *c)
353 {
354 #ifdef CONFIG_X86_32
355         const struct legacy_cpu_model_info *info;
356 
357         if (c->x86_model >= 16)
358                 return NULL;    /* Range check */
359 
360         if (!this_cpu)
361                 return NULL;
362 
363         info = this_cpu->legacy_models;
364 
365         while (info->family) {
366                 if (info->family == c->x86)
367                         return info->model_names[c->x86_model];
368                 info++;
369         }
370 #endif
371         return NULL;            /* Not found */
372 }
373 
374 __u32 cpu_caps_cleared[NCAPINTS];
375 __u32 cpu_caps_set[NCAPINTS];
376 
377 void load_percpu_segment(int cpu)
378 {
379 #ifdef CONFIG_X86_32
380         loadsegment(fs, __KERNEL_PERCPU);
381 #else
382         loadsegment(gs, 0);
383         wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu));
384 #endif
385         load_stack_canary_segment();
386 }
387 
388 /*
389  * Current gdt points %fs at the "master" per-cpu area: after this,
390  * it's on the real one.
391  */
392 void switch_to_new_gdt(int cpu)
393 {
394         struct desc_ptr gdt_descr;
395 
396         gdt_descr.address = (long)get_cpu_gdt_table(cpu);
397         gdt_descr.size = GDT_SIZE - 1;
398         load_gdt(&gdt_descr);
399         /* Reload the per-cpu base */
400 
401         load_percpu_segment(cpu);
402 }
403 
404 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
405 
406 static void get_model_name(struct cpuinfo_x86 *c)
407 {
408         unsigned int *v;
409         char *p, *q;
410 
411         if (c->extended_cpuid_level < 0x80000004)
412                 return;
413 
414         v = (unsigned int *)c->x86_model_id;
415         cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
416         cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
417         cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
418         c->x86_model_id[48] = 0;
419 
420         /*
421          * Intel chips right-justify this string for some dumb reason;
422          * undo that brain damage:
423          */
424         p = q = &c->x86_model_id[0];
425         while (*p == ' ')
426                 p++;
427         if (p != q) {
428                 while (*p)
429                         *q++ = *p++;
430                 while (q <= &c->x86_model_id[48])
431                         *q++ = '\0';    /* Zero-pad the rest */
432         }
433 }
434 
435 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
436 {
437         unsigned int n, dummy, ebx, ecx, edx, l2size;
438 
439         n = c->extended_cpuid_level;
440 
441         if (n >= 0x80000005) {
442                 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
443                 c->x86_cache_size = (ecx>>24) + (edx>>24);
444 #ifdef CONFIG_X86_64
445                 /* On K8 L1 TLB is inclusive, so don't count it */
446                 c->x86_tlbsize = 0;
447 #endif
448         }
449 
450         if (n < 0x80000006)     /* Some chips just has a large L1. */
451                 return;
452 
453         cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
454         l2size = ecx >> 16;
455 
456 #ifdef CONFIG_X86_64
457         c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
458 #else
459         /* do processor-specific cache resizing */
460         if (this_cpu->legacy_cache_size)
461                 l2size = this_cpu->legacy_cache_size(c, l2size);
462 
463         /* Allow user to override all this if necessary. */
464         if (cachesize_override != -1)
465                 l2size = cachesize_override;
466 
467         if (l2size == 0)
468                 return;         /* Again, no L2 cache is possible */
469 #endif
470 
471         c->x86_cache_size = l2size;
472 }
473 
474 u16 __read_mostly tlb_lli_4k[NR_INFO];
475 u16 __read_mostly tlb_lli_2m[NR_INFO];
476 u16 __read_mostly tlb_lli_4m[NR_INFO];
477 u16 __read_mostly tlb_lld_4k[NR_INFO];
478 u16 __read_mostly tlb_lld_2m[NR_INFO];
479 u16 __read_mostly tlb_lld_4m[NR_INFO];
480 
481 /*
482  * tlb_flushall_shift shows the balance point in replacing cr3 write
483  * with multiple 'invlpg'. It will do this replacement when
484  *   flush_tlb_lines <= active_lines/2^tlb_flushall_shift.
485  * If tlb_flushall_shift is -1, means the replacement will be disabled.
486  */
487 s8  __read_mostly tlb_flushall_shift = -1;
488 
489 void cpu_detect_tlb(struct cpuinfo_x86 *c)
490 {
491         if (this_cpu->c_detect_tlb)
492                 this_cpu->c_detect_tlb(c);
493 
494         printk(KERN_INFO "Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n" \
495                 "Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d\n"          \
496                 "tlb_flushall_shift: %d\n",
497                 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES],
498                 tlb_lli_4m[ENTRIES], tlb_lld_4k[ENTRIES],
499                 tlb_lld_2m[ENTRIES], tlb_lld_4m[ENTRIES],
500                 tlb_flushall_shift);
501 }
502 
503 void detect_ht(struct cpuinfo_x86 *c)
504 {
505 #ifdef CONFIG_X86_HT
506         u32 eax, ebx, ecx, edx;
507         int index_msb, core_bits;
508         static bool printed;
509 
510         if (!cpu_has(c, X86_FEATURE_HT))
511                 return;
512 
513         if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
514                 goto out;
515 
516         if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
517                 return;
518 
519         cpuid(1, &eax, &ebx, &ecx, &edx);
520 
521         smp_num_siblings = (ebx & 0xff0000) >> 16;
522 
523         if (smp_num_siblings == 1) {
524                 printk_once(KERN_INFO "CPU0: Hyper-Threading is disabled\n");
525                 goto out;
526         }
527 
528         if (smp_num_siblings <= 1)
529                 goto out;
530 
531         index_msb = get_count_order(smp_num_siblings);
532         c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb);
533 
534         smp_num_siblings = smp_num_siblings / c->x86_max_cores;
535 
536         index_msb = get_count_order(smp_num_siblings);
537 
538         core_bits = get_count_order(c->x86_max_cores);
539 
540         c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) &
541                                        ((1 << core_bits) - 1);
542 
543 out:
544         if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) {
545                 printk(KERN_INFO  "CPU: Physical Processor ID: %d\n",
546                        c->phys_proc_id);
547                 printk(KERN_INFO  "CPU: Processor Core ID: %d\n",
548                        c->cpu_core_id);
549                 printed = 1;
550         }
551 #endif
552 }
553 
554 static void get_cpu_vendor(struct cpuinfo_x86 *c)
555 {
556         char *v = c->x86_vendor_id;
557         int i;
558 
559         for (i = 0; i < X86_VENDOR_NUM; i++) {
560                 if (!cpu_devs[i])
561                         break;
562 
563                 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
564                     (cpu_devs[i]->c_ident[1] &&
565                      !strcmp(v, cpu_devs[i]->c_ident[1]))) {
566 
567                         this_cpu = cpu_devs[i];
568                         c->x86_vendor = this_cpu->c_x86_vendor;
569                         return;
570                 }
571         }
572 
573         printk_once(KERN_ERR
574                         "CPU: vendor_id '%s' unknown, using generic init.\n" \
575                         "CPU: Your system may be unstable.\n", v);
576 
577         c->x86_vendor = X86_VENDOR_UNKNOWN;
578         this_cpu = &default_cpu;
579 }
580 
581 void cpu_detect(struct cpuinfo_x86 *c)
582 {
583         /* Get vendor name */
584         cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
585               (unsigned int *)&c->x86_vendor_id[0],
586               (unsigned int *)&c->x86_vendor_id[8],
587               (unsigned int *)&c->x86_vendor_id[4]);
588 
589         c->x86 = 4;
590         /* Intel-defined flags: level 0x00000001 */
591         if (c->cpuid_level >= 0x00000001) {
592                 u32 junk, tfms, cap0, misc;
593 
594                 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
595                 c->x86 = (tfms >> 8) & 0xf;
596                 c->x86_model = (tfms >> 4) & 0xf;
597                 c->x86_mask = tfms & 0xf;
598 
599                 if (c->x86 == 0xf)
600                         c->x86 += (tfms >> 20) & 0xff;
601                 if (c->x86 >= 0x6)
602                         c->x86_model += ((tfms >> 16) & 0xf) << 4;
603 
604                 if (cap0 & (1<<19)) {
605                         c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
606                         c->x86_cache_alignment = c->x86_clflush_size;
607                 }
608         }
609 }
610 
611 void get_cpu_cap(struct cpuinfo_x86 *c)
612 {
613         u32 tfms, xlvl;
614         u32 ebx;
615 
616         /* Intel-defined flags: level 0x00000001 */
617         if (c->cpuid_level >= 0x00000001) {
618                 u32 capability, excap;
619 
620                 cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
621                 c->x86_capability[0] = capability;
622                 c->x86_capability[4] = excap;
623         }
624 
625         /* Additional Intel-defined flags: level 0x00000007 */
626         if (c->cpuid_level >= 0x00000007) {
627                 u32 eax, ebx, ecx, edx;
628 
629                 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
630 
631                 c->x86_capability[9] = ebx;
632         }
633 
634         /* AMD-defined flags: level 0x80000001 */
635         xlvl = cpuid_eax(0x80000000);
636         c->extended_cpuid_level = xlvl;
637 
638         if ((xlvl & 0xffff0000) == 0x80000000) {
639                 if (xlvl >= 0x80000001) {
640                         c->x86_capability[1] = cpuid_edx(0x80000001);
641                         c->x86_capability[6] = cpuid_ecx(0x80000001);
642                 }
643         }
644 
645         if (c->extended_cpuid_level >= 0x80000008) {
646                 u32 eax = cpuid_eax(0x80000008);
647 
648                 c->x86_virt_bits = (eax >> 8) & 0xff;
649                 c->x86_phys_bits = eax & 0xff;
650         }
651 #ifdef CONFIG_X86_32
652         else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
653                 c->x86_phys_bits = 36;
654 #endif
655 
656         if (c->extended_cpuid_level >= 0x80000007)
657                 c->x86_power = cpuid_edx(0x80000007);
658 
659         init_scattered_cpuid_features(c);
660 }
661 
662 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
663 {
664 #ifdef CONFIG_X86_32
665         int i;
666 
667         /*
668          * First of all, decide if this is a 486 or higher
669          * It's a 486 if we can modify the AC flag
670          */
671         if (flag_is_changeable_p(X86_EFLAGS_AC))
672                 c->x86 = 4;
673         else
674                 c->x86 = 3;
675 
676         for (i = 0; i < X86_VENDOR_NUM; i++)
677                 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
678                         c->x86_vendor_id[0] = 0;
679                         cpu_devs[i]->c_identify(c);
680                         if (c->x86_vendor_id[0]) {
681                                 get_cpu_vendor(c);
682                                 break;
683                         }
684                 }
685 #endif
686 }
687 
688 /*
689  * Do minimum CPU detection early.
690  * Fields really needed: vendor, cpuid_level, family, model, mask,
691  * cache alignment.
692  * The others are not touched to avoid unwanted side effects.
693  *
694  * WARNING: this function is only called on the BP.  Don't add code here
695  * that is supposed to run on all CPUs.
696  */
697 static void __init early_identify_cpu(struct cpuinfo_x86 *c)
698 {
699 #ifdef CONFIG_X86_64
700         c->x86_clflush_size = 64;
701         c->x86_phys_bits = 36;
702         c->x86_virt_bits = 48;
703 #else
704         c->x86_clflush_size = 32;
705         c->x86_phys_bits = 32;
706         c->x86_virt_bits = 32;
707 #endif
708         c->x86_cache_alignment = c->x86_clflush_size;
709 
710         memset(&c->x86_capability, 0, sizeof c->x86_capability);
711         c->extended_cpuid_level = 0;
712 
713         if (!have_cpuid_p())
714                 identify_cpu_without_cpuid(c);
715 
716         /* cyrix could have cpuid enabled via c_identify()*/
717         if (!have_cpuid_p())
718                 return;
719 
720         cpu_detect(c);
721         get_cpu_vendor(c);
722         get_cpu_cap(c);
723         fpu_detect(c);
724 
725         if (this_cpu->c_early_init)
726                 this_cpu->c_early_init(c);
727 
728         c->cpu_index = 0;
729         filter_cpuid_features(c, false);
730 
731         if (this_cpu->c_bsp_init)
732                 this_cpu->c_bsp_init(c);
733 
734         setup_force_cpu_cap(X86_FEATURE_ALWAYS);
735 }
736 
737 void __init early_cpu_init(void)
738 {
739         const struct cpu_dev *const *cdev;
740         int count = 0;
741 
742 #ifdef CONFIG_PROCESSOR_SELECT
743         printk(KERN_INFO "KERNEL supported cpus:\n");
744 #endif
745 
746         for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
747                 const struct cpu_dev *cpudev = *cdev;
748 
749                 if (count >= X86_VENDOR_NUM)
750                         break;
751                 cpu_devs[count] = cpudev;
752                 count++;
753 
754 #ifdef CONFIG_PROCESSOR_SELECT
755                 {
756                         unsigned int j;
757 
758                         for (j = 0; j < 2; j++) {
759                                 if (!cpudev->c_ident[j])
760                                         continue;
761                                 printk(KERN_INFO "  %s %s\n", cpudev->c_vendor,
762                                         cpudev->c_ident[j]);
763                         }
764                 }
765 #endif
766         }
767         early_identify_cpu(&boot_cpu_data);
768 }
769 
770 /*
771  * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
772  * unfortunately, that's not true in practice because of early VIA
773  * chips and (more importantly) broken virtualizers that are not easy
774  * to detect. In the latter case it doesn't even *fail* reliably, so
775  * probing for it doesn't even work. Disable it completely on 32-bit
776  * unless we can find a reliable way to detect all the broken cases.
777  * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
778  */
779 static void detect_nopl(struct cpuinfo_x86 *c)
780 {
781 #ifdef CONFIG_X86_32
782         clear_cpu_cap(c, X86_FEATURE_NOPL);
783 #else
784         set_cpu_cap(c, X86_FEATURE_NOPL);
785 #endif
786 }
787 
788 static void generic_identify(struct cpuinfo_x86 *c)
789 {
790         c->extended_cpuid_level = 0;
791 
792         if (!have_cpuid_p())
793                 identify_cpu_without_cpuid(c);
794 
795         /* cyrix could have cpuid enabled via c_identify()*/
796         if (!have_cpuid_p())
797                 return;
798 
799         cpu_detect(c);
800 
801         get_cpu_vendor(c);
802 
803         get_cpu_cap(c);
804 
805         if (c->cpuid_level >= 0x00000001) {
806                 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
807 #ifdef CONFIG_X86_32
808 # ifdef CONFIG_X86_HT
809                 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
810 # else
811                 c->apicid = c->initial_apicid;
812 # endif
813 #endif
814                 c->phys_proc_id = c->initial_apicid;
815         }
816 
817         get_model_name(c); /* Default name */
818 
819         detect_nopl(c);
820 }
821 
822 /*
823  * This does the hard work of actually picking apart the CPU stuff...
824  */
825 static void identify_cpu(struct cpuinfo_x86 *c)
826 {
827         int i;
828 
829         c->loops_per_jiffy = loops_per_jiffy;
830         c->x86_cache_size = -1;
831         c->x86_vendor = X86_VENDOR_UNKNOWN;
832         c->x86_model = c->x86_mask = 0; /* So far unknown... */
833         c->x86_vendor_id[0] = '\0'; /* Unset */
834         c->x86_model_id[0] = '\0';  /* Unset */
835         c->x86_max_cores = 1;
836         c->x86_coreid_bits = 0;
837 #ifdef CONFIG_X86_64
838         c->x86_clflush_size = 64;
839         c->x86_phys_bits = 36;
840         c->x86_virt_bits = 48;
841 #else
842         c->cpuid_level = -1;    /* CPUID not detected */
843         c->x86_clflush_size = 32;
844         c->x86_phys_bits = 32;
845         c->x86_virt_bits = 32;
846 #endif
847         c->x86_cache_alignment = c->x86_clflush_size;
848         memset(&c->x86_capability, 0, sizeof c->x86_capability);
849 
850         generic_identify(c);
851 
852         if (this_cpu->c_identify)
853                 this_cpu->c_identify(c);
854 
855         /* Clear/Set all flags overriden by options, after probe */
856         for (i = 0; i < NCAPINTS; i++) {
857                 c->x86_capability[i] &= ~cpu_caps_cleared[i];
858                 c->x86_capability[i] |= cpu_caps_set[i];
859         }
860 
861 #ifdef CONFIG_X86_64
862         c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
863 #endif
864 
865         /*
866          * Vendor-specific initialization.  In this section we
867          * canonicalize the feature flags, meaning if there are
868          * features a certain CPU supports which CPUID doesn't
869          * tell us, CPUID claiming incorrect flags, or other bugs,
870          * we handle them here.
871          *
872          * At the end of this section, c->x86_capability better
873          * indicate the features this CPU genuinely supports!
874          */
875         if (this_cpu->c_init)
876                 this_cpu->c_init(c);
877 
878         /* Disable the PN if appropriate */
879         squash_the_stupid_serial_number(c);
880 
881         /* Set up SMEP/SMAP */
882         setup_smep(c);
883         setup_smap(c);
884 
885         /*
886          * The vendor-specific functions might have changed features.
887          * Now we do "generic changes."
888          */
889 
890         /* Filter out anything that depends on CPUID levels we don't have */
891         filter_cpuid_features(c, true);
892 
893         /* If the model name is still unset, do table lookup. */
894         if (!c->x86_model_id[0]) {
895                 const char *p;
896                 p = table_lookup_model(c);
897                 if (p)
898                         strcpy(c->x86_model_id, p);
899                 else
900                         /* Last resort... */
901                         sprintf(c->x86_model_id, "%02x/%02x",
902                                 c->x86, c->x86_model);
903         }
904 
905 #ifdef CONFIG_X86_64
906         detect_ht(c);
907 #endif
908 
909         init_hypervisor(c);
910         x86_init_rdrand(c);
911 
912         /*
913          * Clear/Set all flags overriden by options, need do it
914          * before following smp all cpus cap AND.
915          */
916         for (i = 0; i < NCAPINTS; i++) {
917                 c->x86_capability[i] &= ~cpu_caps_cleared[i];
918                 c->x86_capability[i] |= cpu_caps_set[i];
919         }
920 
921         /*
922          * On SMP, boot_cpu_data holds the common feature set between
923          * all CPUs; so make sure that we indicate which features are
924          * common between the CPUs.  The first time this routine gets
925          * executed, c == &boot_cpu_data.
926          */
927         if (c != &boot_cpu_data) {
928                 /* AND the already accumulated flags with these */
929                 for (i = 0; i < NCAPINTS; i++)
930                         boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
931 
932                 /* OR, i.e. replicate the bug flags */
933                 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++)
934                         c->x86_capability[i] |= boot_cpu_data.x86_capability[i];
935         }
936 
937         /* Init Machine Check Exception if available. */
938         mcheck_cpu_init(c);
939 
940         select_idle_routine(c);
941 
942 #ifdef CONFIG_NUMA
943         numa_add_cpu(smp_processor_id());
944 #endif
945 }
946 
947 #ifdef CONFIG_X86_64
948 static void vgetcpu_set_mode(void)
949 {
950         if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP))
951                 vgetcpu_mode = VGETCPU_RDTSCP;
952         else
953                 vgetcpu_mode = VGETCPU_LSL;
954 }
955 #endif
956 
957 void __init identify_boot_cpu(void)
958 {
959         identify_cpu(&boot_cpu_data);
960         init_amd_e400_c1e_mask();
961 #ifdef CONFIG_X86_32
962         sysenter_setup();
963         enable_sep_cpu();
964 #else
965         vgetcpu_set_mode();
966 #endif
967         cpu_detect_tlb(&boot_cpu_data);
968 }
969 
970 void identify_secondary_cpu(struct cpuinfo_x86 *c)
971 {
972         BUG_ON(c == &boot_cpu_data);
973         identify_cpu(c);
974 #ifdef CONFIG_X86_32
975         enable_sep_cpu();
976 #endif
977         mtrr_ap_init();
978 }
979 
980 struct msr_range {
981         unsigned        min;
982         unsigned        max;
983 };
984 
985 static const struct msr_range msr_range_array[] = {
986         { 0x00000000, 0x00000418},
987         { 0xc0000000, 0xc000040b},
988         { 0xc0010000, 0xc0010142},
989         { 0xc0011000, 0xc001103b},
990 };
991 
992 static void __print_cpu_msr(void)
993 {
994         unsigned index_min, index_max;
995         unsigned index;
996         u64 val;
997         int i;
998 
999         for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) {
1000                 index_min = msr_range_array[i].min;
1001                 index_max = msr_range_array[i].max;
1002 
1003                 for (index = index_min; index < index_max; index++) {
1004                         if (rdmsrl_safe(index, &val))
1005                                 continue;
1006                         printk(KERN_INFO " MSR%08x: %016llx\n", index, val);
1007                 }
1008         }
1009 }
1010 
1011 static int show_msr;
1012 
1013 static __init int setup_show_msr(char *arg)
1014 {
1015         int num;
1016 
1017         get_option(&arg, &num);
1018 
1019         if (num > 0)
1020                 show_msr = num;
1021         return 1;
1022 }
1023 __setup("show_msr=", setup_show_msr);
1024 
1025 static __init int setup_noclflush(char *arg)
1026 {
1027         setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
1028         return 1;
1029 }
1030 __setup("noclflush", setup_noclflush);
1031 
1032 void print_cpu_info(struct cpuinfo_x86 *c)
1033 {
1034         const char *vendor = NULL;
1035 
1036         if (c->x86_vendor < X86_VENDOR_NUM) {
1037                 vendor = this_cpu->c_vendor;
1038         } else {
1039                 if (c->cpuid_level >= 0)
1040                         vendor = c->x86_vendor_id;
1041         }
1042 
1043         if (vendor && !strstr(c->x86_model_id, vendor))
1044                 printk(KERN_CONT "%s ", vendor);
1045 
1046         if (c->x86_model_id[0])
1047                 printk(KERN_CONT "%s", strim(c->x86_model_id));
1048         else
1049                 printk(KERN_CONT "%d86", c->x86);
1050 
1051         printk(KERN_CONT " (fam: %02x, model: %02x", c->x86, c->x86_model);
1052 
1053         if (c->x86_mask || c->cpuid_level >= 0)
1054                 printk(KERN_CONT ", stepping: %02x)\n", c->x86_mask);
1055         else
1056                 printk(KERN_CONT ")\n");
1057 
1058         print_cpu_msr(c);
1059 }
1060 
1061 void print_cpu_msr(struct cpuinfo_x86 *c)
1062 {
1063         if (c->cpu_index < show_msr)
1064                 __print_cpu_msr();
1065 }
1066 
1067 static __init int setup_disablecpuid(char *arg)
1068 {
1069         int bit;
1070 
1071         if (get_option(&arg, &bit) && bit < NCAPINTS*32)
1072                 setup_clear_cpu_cap(bit);
1073         else
1074                 return 0;
1075 
1076         return 1;
1077 }
1078 __setup("clearcpuid=", setup_disablecpuid);
1079 
1080 #ifdef CONFIG_X86_64
1081 struct desc_ptr idt_descr = { NR_VECTORS * 16 - 1, (unsigned long) idt_table };
1082 struct desc_ptr debug_idt_descr = { NR_VECTORS * 16 - 1,
1083                                     (unsigned long) debug_idt_table };
1084 
1085 DEFINE_PER_CPU_FIRST(union irq_stack_union,
1086                      irq_stack_union) __aligned(PAGE_SIZE) __visible;
1087 
1088 /*
1089  * The following four percpu variables are hot.  Align current_task to
1090  * cacheline size such that all four fall in the same cacheline.
1091  */
1092 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned =
1093         &init_task;
1094 EXPORT_PER_CPU_SYMBOL(current_task);
1095 
1096 DEFINE_PER_CPU(unsigned long, kernel_stack) =
1097         (unsigned long)&init_thread_union - KERNEL_STACK_OFFSET + THREAD_SIZE;
1098 EXPORT_PER_CPU_SYMBOL(kernel_stack);
1099 
1100 DEFINE_PER_CPU(char *, irq_stack_ptr) =
1101         init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64;
1102 
1103 DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1;
1104 
1105 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1106 EXPORT_PER_CPU_SYMBOL(__preempt_count);
1107 
1108 DEFINE_PER_CPU(struct task_struct *, fpu_owner_task);
1109 
1110 /*
1111  * Special IST stacks which the CPU switches to when it calls
1112  * an IST-marked descriptor entry. Up to 7 stacks (hardware
1113  * limit), all of them are 4K, except the debug stack which
1114  * is 8K.
1115  */
1116 static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = {
1117           [0 ... N_EXCEPTION_STACKS - 1]        = EXCEPTION_STKSZ,
1118           [DEBUG_STACK - 1]                     = DEBUG_STKSZ
1119 };
1120 
1121 static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks
1122         [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]);
1123 
1124 /* May not be marked __init: used by software suspend */
1125 void syscall_init(void)
1126 {
1127         /*
1128          * LSTAR and STAR live in a bit strange symbiosis.
1129          * They both write to the same internal register. STAR allows to
1130          * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
1131          */
1132         wrmsrl(MSR_STAR,  ((u64)__USER32_CS)<<48  | ((u64)__KERNEL_CS)<<32);
1133         wrmsrl(MSR_LSTAR, system_call);
1134         wrmsrl(MSR_CSTAR, ignore_sysret);
1135 
1136 #ifdef CONFIG_IA32_EMULATION
1137         syscall32_cpu_init();
1138 #endif
1139 
1140         /* Flags to clear on syscall */
1141         wrmsrl(MSR_SYSCALL_MASK,
1142                X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|
1143                X86_EFLAGS_IOPL|X86_EFLAGS_AC);
1144 }
1145 
1146 /*
1147  * Copies of the original ist values from the tss are only accessed during
1148  * debugging, no special alignment required.
1149  */
1150 DEFINE_PER_CPU(struct orig_ist, orig_ist);
1151 
1152 static DEFINE_PER_CPU(unsigned long, debug_stack_addr);
1153 DEFINE_PER_CPU(int, debug_stack_usage);
1154 
1155 int is_debug_stack(unsigned long addr)
1156 {
1157         return __get_cpu_var(debug_stack_usage) ||
1158                 (addr <= __get_cpu_var(debug_stack_addr) &&
1159                  addr > (__get_cpu_var(debug_stack_addr) - DEBUG_STKSZ));
1160 }
1161 
1162 DEFINE_PER_CPU(u32, debug_idt_ctr);
1163 
1164 void debug_stack_set_zero(void)
1165 {
1166         this_cpu_inc(debug_idt_ctr);
1167         load_current_idt();
1168 }
1169 
1170 void debug_stack_reset(void)
1171 {
1172         if (WARN_ON(!this_cpu_read(debug_idt_ctr)))
1173                 return;
1174         if (this_cpu_dec_return(debug_idt_ctr) == 0)
1175                 load_current_idt();
1176 }
1177 
1178 #else   /* CONFIG_X86_64 */
1179 
1180 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task;
1181 EXPORT_PER_CPU_SYMBOL(current_task);
1182 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1183 EXPORT_PER_CPU_SYMBOL(__preempt_count);
1184 DEFINE_PER_CPU(struct task_struct *, fpu_owner_task);
1185 
1186 #ifdef CONFIG_CC_STACKPROTECTOR
1187 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
1188 #endif
1189 
1190 #endif  /* CONFIG_X86_64 */
1191 
1192 /*
1193  * Clear all 6 debug registers:
1194  */
1195 static void clear_all_debug_regs(void)
1196 {
1197         int i;
1198 
1199         for (i = 0; i < 8; i++) {
1200                 /* Ignore db4, db5 */
1201                 if ((i == 4) || (i == 5))
1202                         continue;
1203 
1204                 set_debugreg(0, i);
1205         }
1206 }
1207 
1208 #ifdef CONFIG_KGDB
1209 /*
1210  * Restore debug regs if using kgdbwait and you have a kernel debugger
1211  * connection established.
1212  */
1213 static void dbg_restore_debug_regs(void)
1214 {
1215         if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break))
1216                 arch_kgdb_ops.correct_hw_break();
1217 }
1218 #else /* ! CONFIG_KGDB */
1219 #define dbg_restore_debug_regs()
1220 #endif /* ! CONFIG_KGDB */
1221 
1222 /*
1223  * cpu_init() initializes state that is per-CPU. Some data is already
1224  * initialized (naturally) in the bootstrap process, such as the GDT
1225  * and IDT. We reload them nevertheless, this function acts as a
1226  * 'CPU state barrier', nothing should get across.
1227  * A lot of state is already set up in PDA init for 64 bit
1228  */
1229 #ifdef CONFIG_X86_64
1230 
1231 void cpu_init(void)
1232 {
1233         struct orig_ist *oist;
1234         struct task_struct *me;
1235         struct tss_struct *t;
1236         unsigned long v;
1237         int cpu;
1238         int i;
1239 
1240         /*
1241          * Load microcode on this cpu if a valid microcode is available.
1242          * This is early microcode loading procedure.
1243          */
1244         load_ucode_ap();
1245 
1246         cpu = stack_smp_processor_id();
1247         t = &per_cpu(init_tss, cpu);
1248         oist = &per_cpu(orig_ist, cpu);
1249 
1250 #ifdef CONFIG_NUMA
1251         if (this_cpu_read(numa_node) == 0 &&
1252             early_cpu_to_node(cpu) != NUMA_NO_NODE)
1253                 set_numa_node(early_cpu_to_node(cpu));
1254 #endif
1255 
1256         me = current;
1257 
1258         if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask))
1259                 panic("CPU#%d already initialized!\n", cpu);
1260 
1261         pr_debug("Initializing CPU#%d\n", cpu);
1262 
1263         clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1264 
1265         /*
1266          * Initialize the per-CPU GDT with the boot GDT,
1267          * and set up the GDT descriptor:
1268          */
1269 
1270         switch_to_new_gdt(cpu);
1271         loadsegment(fs, 0);
1272 
1273         load_current_idt();
1274 
1275         memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
1276         syscall_init();
1277 
1278         wrmsrl(MSR_FS_BASE, 0);
1279         wrmsrl(MSR_KERNEL_GS_BASE, 0);
1280         barrier();
1281 
1282         x86_configure_nx();
1283         enable_x2apic();
1284 
1285         /*
1286          * set up and load the per-CPU TSS
1287          */
1288         if (!oist->ist[0]) {
1289                 char *estacks = per_cpu(exception_stacks, cpu);
1290 
1291                 for (v = 0; v < N_EXCEPTION_STACKS; v++) {
1292                         estacks += exception_stack_sizes[v];
1293                         oist->ist[v] = t->x86_tss.ist[v] =
1294                                         (unsigned long)estacks;
1295                         if (v == DEBUG_STACK-1)
1296                                 per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks;
1297                 }
1298         }
1299 
1300         t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1301 
1302         /*
1303          * <= is required because the CPU will access up to
1304          * 8 bits beyond the end of the IO permission bitmap.
1305          */
1306         for (i = 0; i <= IO_BITMAP_LONGS; i++)
1307                 t->io_bitmap[i] = ~0UL;
1308 
1309         atomic_inc(&init_mm.mm_count);
1310         me->active_mm = &init_mm;
1311         BUG_ON(me->mm);
1312         enter_lazy_tlb(&init_mm, me);
1313 
1314         load_sp0(t, &current->thread);
1315         set_tss_desc(cpu, t);
1316         load_TR_desc();
1317         load_LDT(&init_mm.context);
1318 
1319         clear_all_debug_regs();
1320         dbg_restore_debug_regs();
1321 
1322         fpu_init();
1323 
1324         if (is_uv_system())
1325                 uv_cpu_init();
1326 }
1327 
1328 #else
1329 
1330 void cpu_init(void)
1331 {
1332         int cpu = smp_processor_id();
1333         struct task_struct *curr = current;
1334         struct tss_struct *t = &per_cpu(init_tss, cpu);
1335         struct thread_struct *thread = &curr->thread;
1336 
1337         show_ucode_info_early();
1338 
1339         if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) {
1340                 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
1341                 for (;;)
1342                         local_irq_enable();
1343         }
1344 
1345         printk(KERN_INFO "Initializing CPU#%d\n", cpu);
1346 
1347         if (cpu_has_vme || cpu_has_tsc || cpu_has_de)
1348                 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1349 
1350         load_current_idt();
1351         switch_to_new_gdt(cpu);
1352 
1353         /*
1354          * Set up and load the per-CPU TSS and LDT
1355          */
1356         atomic_inc(&init_mm.mm_count);
1357         curr->active_mm = &init_mm;
1358         BUG_ON(curr->mm);
1359         enter_lazy_tlb(&init_mm, curr);
1360 
1361         load_sp0(t, thread);
1362         set_tss_desc(cpu, t);
1363         load_TR_desc();
1364         load_LDT(&init_mm.context);
1365 
1366         t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1367 
1368 #ifdef CONFIG_DOUBLEFAULT
1369         /* Set up doublefault TSS pointer in the GDT */
1370         __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
1371 #endif
1372 
1373         clear_all_debug_regs();
1374         dbg_restore_debug_regs();
1375 
1376         fpu_init();
1377 }
1378 #endif
1379 
1380 #ifdef CONFIG_X86_DEBUG_STATIC_CPU_HAS
1381 void warn_pre_alternatives(void)
1382 {
1383         WARN(1, "You're using static_cpu_has before alternatives have run!\n");
1384 }
1385 EXPORT_SYMBOL_GPL(warn_pre_alternatives);
1386 #endif
1387 
1388 inline bool __static_cpu_has_safe(u16 bit)
1389 {
1390         return boot_cpu_has(bit);
1391 }
1392 EXPORT_SYMBOL_GPL(__static_cpu_has_safe);
1393 

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