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TOMOYO Linux Cross Reference
Linux/arch/x86/kernel/cpu/common.c

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  1 #include <linux/bootmem.h>
  2 #include <linux/linkage.h>
  3 #include <linux/bitops.h>
  4 #include <linux/kernel.h>
  5 #include <linux/module.h>
  6 #include <linux/percpu.h>
  7 #include <linux/string.h>
  8 #include <linux/ctype.h>
  9 #include <linux/delay.h>
 10 #include <linux/sched.h>
 11 #include <linux/init.h>
 12 #include <linux/kprobes.h>
 13 #include <linux/kgdb.h>
 14 #include <linux/smp.h>
 15 #include <linux/io.h>
 16 #include <linux/syscore_ops.h>
 17 
 18 #include <asm/stackprotector.h>
 19 #include <asm/perf_event.h>
 20 #include <asm/mmu_context.h>
 21 #include <asm/archrandom.h>
 22 #include <asm/hypervisor.h>
 23 #include <asm/processor.h>
 24 #include <asm/tlbflush.h>
 25 #include <asm/debugreg.h>
 26 #include <asm/sections.h>
 27 #include <asm/vsyscall.h>
 28 #include <linux/topology.h>
 29 #include <linux/cpumask.h>
 30 #include <asm/pgtable.h>
 31 #include <linux/atomic.h>
 32 #include <asm/proto.h>
 33 #include <asm/setup.h>
 34 #include <asm/apic.h>
 35 #include <asm/desc.h>
 36 #include <asm/fpu/internal.h>
 37 #include <asm/mtrr.h>
 38 #include <linux/numa.h>
 39 #include <asm/asm.h>
 40 #include <asm/cpu.h>
 41 #include <asm/mce.h>
 42 #include <asm/msr.h>
 43 #include <asm/pat.h>
 44 #include <asm/microcode.h>
 45 #include <asm/microcode_intel.h>
 46 
 47 #ifdef CONFIG_X86_LOCAL_APIC
 48 #include <asm/uv/uv.h>
 49 #endif
 50 
 51 #include "cpu.h"
 52 
 53 /* all of these masks are initialized in setup_cpu_local_masks() */
 54 cpumask_var_t cpu_initialized_mask;
 55 cpumask_var_t cpu_callout_mask;
 56 cpumask_var_t cpu_callin_mask;
 57 
 58 /* representing cpus for which sibling maps can be computed */
 59 cpumask_var_t cpu_sibling_setup_mask;
 60 
 61 /* correctly size the local cpu masks */
 62 void __init setup_cpu_local_masks(void)
 63 {
 64         alloc_bootmem_cpumask_var(&cpu_initialized_mask);
 65         alloc_bootmem_cpumask_var(&cpu_callin_mask);
 66         alloc_bootmem_cpumask_var(&cpu_callout_mask);
 67         alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
 68 }
 69 
 70 static void default_init(struct cpuinfo_x86 *c)
 71 {
 72 #ifdef CONFIG_X86_64
 73         cpu_detect_cache_sizes(c);
 74 #else
 75         /* Not much we can do here... */
 76         /* Check if at least it has cpuid */
 77         if (c->cpuid_level == -1) {
 78                 /* No cpuid. It must be an ancient CPU */
 79                 if (c->x86 == 4)
 80                         strcpy(c->x86_model_id, "486");
 81                 else if (c->x86 == 3)
 82                         strcpy(c->x86_model_id, "386");
 83         }
 84 #endif
 85 }
 86 
 87 static const struct cpu_dev default_cpu = {
 88         .c_init         = default_init,
 89         .c_vendor       = "Unknown",
 90         .c_x86_vendor   = X86_VENDOR_UNKNOWN,
 91 };
 92 
 93 static const struct cpu_dev *this_cpu = &default_cpu;
 94 
 95 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
 96 #ifdef CONFIG_X86_64
 97         /*
 98          * We need valid kernel segments for data and code in long mode too
 99          * IRET will check the segment types  kkeil 2000/10/28
100          * Also sysret mandates a special GDT layout
101          *
102          * TLS descriptors are currently at a different place compared to i386.
103          * Hopefully nobody expects them at a fixed place (Wine?)
104          */
105         [GDT_ENTRY_KERNEL32_CS]         = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
106         [GDT_ENTRY_KERNEL_CS]           = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
107         [GDT_ENTRY_KERNEL_DS]           = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
108         [GDT_ENTRY_DEFAULT_USER32_CS]   = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
109         [GDT_ENTRY_DEFAULT_USER_DS]     = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
110         [GDT_ENTRY_DEFAULT_USER_CS]     = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
111 #else
112         [GDT_ENTRY_KERNEL_CS]           = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
113         [GDT_ENTRY_KERNEL_DS]           = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
114         [GDT_ENTRY_DEFAULT_USER_CS]     = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
115         [GDT_ENTRY_DEFAULT_USER_DS]     = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
116         /*
117          * Segments used for calling PnP BIOS have byte granularity.
118          * They code segments and data segments have fixed 64k limits,
119          * the transfer segment sizes are set at run time.
120          */
121         /* 32-bit code */
122         [GDT_ENTRY_PNPBIOS_CS32]        = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
123         /* 16-bit code */
124         [GDT_ENTRY_PNPBIOS_CS16]        = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
125         /* 16-bit data */
126         [GDT_ENTRY_PNPBIOS_DS]          = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
127         /* 16-bit data */
128         [GDT_ENTRY_PNPBIOS_TS1]         = GDT_ENTRY_INIT(0x0092, 0, 0),
129         /* 16-bit data */
130         [GDT_ENTRY_PNPBIOS_TS2]         = GDT_ENTRY_INIT(0x0092, 0, 0),
131         /*
132          * The APM segments have byte granularity and their bases
133          * are set at run time.  All have 64k limits.
134          */
135         /* 32-bit code */
136         [GDT_ENTRY_APMBIOS_BASE]        = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
137         /* 16-bit code */
138         [GDT_ENTRY_APMBIOS_BASE+1]      = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
139         /* data */
140         [GDT_ENTRY_APMBIOS_BASE+2]      = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
141 
142         [GDT_ENTRY_ESPFIX_SS]           = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
143         [GDT_ENTRY_PERCPU]              = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
144         GDT_STACK_CANARY_INIT
145 #endif
146 } };
147 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
148 
149 static int __init x86_mpx_setup(char *s)
150 {
151         /* require an exact match without trailing characters */
152         if (strlen(s))
153                 return 0;
154 
155         /* do not emit a message if the feature is not present */
156         if (!boot_cpu_has(X86_FEATURE_MPX))
157                 return 1;
158 
159         setup_clear_cpu_cap(X86_FEATURE_MPX);
160         pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n");
161         return 1;
162 }
163 __setup("nompx", x86_mpx_setup);
164 
165 static int __init x86_noinvpcid_setup(char *s)
166 {
167         /* noinvpcid doesn't accept parameters */
168         if (s)
169                 return -EINVAL;
170 
171         /* do not emit a message if the feature is not present */
172         if (!boot_cpu_has(X86_FEATURE_INVPCID))
173                 return 0;
174 
175         setup_clear_cpu_cap(X86_FEATURE_INVPCID);
176         pr_info("noinvpcid: INVPCID feature disabled\n");
177         return 0;
178 }
179 early_param("noinvpcid", x86_noinvpcid_setup);
180 
181 #ifdef CONFIG_X86_32
182 static int cachesize_override = -1;
183 static int disable_x86_serial_nr = 1;
184 
185 static int __init cachesize_setup(char *str)
186 {
187         get_option(&str, &cachesize_override);
188         return 1;
189 }
190 __setup("cachesize=", cachesize_setup);
191 
192 static int __init x86_sep_setup(char *s)
193 {
194         setup_clear_cpu_cap(X86_FEATURE_SEP);
195         return 1;
196 }
197 __setup("nosep", x86_sep_setup);
198 
199 /* Standard macro to see if a specific flag is changeable */
200 static inline int flag_is_changeable_p(u32 flag)
201 {
202         u32 f1, f2;
203 
204         /*
205          * Cyrix and IDT cpus allow disabling of CPUID
206          * so the code below may return different results
207          * when it is executed before and after enabling
208          * the CPUID. Add "volatile" to not allow gcc to
209          * optimize the subsequent calls to this function.
210          */
211         asm volatile ("pushfl           \n\t"
212                       "pushfl           \n\t"
213                       "popl %0          \n\t"
214                       "movl %0, %1      \n\t"
215                       "xorl %2, %0      \n\t"
216                       "pushl %0         \n\t"
217                       "popfl            \n\t"
218                       "pushfl           \n\t"
219                       "popl %0          \n\t"
220                       "popfl            \n\t"
221 
222                       : "=&r" (f1), "=&r" (f2)
223                       : "ir" (flag));
224 
225         return ((f1^f2) & flag) != 0;
226 }
227 
228 /* Probe for the CPUID instruction */
229 int have_cpuid_p(void)
230 {
231         return flag_is_changeable_p(X86_EFLAGS_ID);
232 }
233 
234 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
235 {
236         unsigned long lo, hi;
237 
238         if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
239                 return;
240 
241         /* Disable processor serial number: */
242 
243         rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
244         lo |= 0x200000;
245         wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
246 
247         pr_notice("CPU serial number disabled.\n");
248         clear_cpu_cap(c, X86_FEATURE_PN);
249 
250         /* Disabling the serial number may affect the cpuid level */
251         c->cpuid_level = cpuid_eax(0);
252 }
253 
254 static int __init x86_serial_nr_setup(char *s)
255 {
256         disable_x86_serial_nr = 0;
257         return 1;
258 }
259 __setup("serialnumber", x86_serial_nr_setup);
260 #else
261 static inline int flag_is_changeable_p(u32 flag)
262 {
263         return 1;
264 }
265 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
266 {
267 }
268 #endif
269 
270 static __init int setup_disable_smep(char *arg)
271 {
272         setup_clear_cpu_cap(X86_FEATURE_SMEP);
273         return 1;
274 }
275 __setup("nosmep", setup_disable_smep);
276 
277 static __always_inline void setup_smep(struct cpuinfo_x86 *c)
278 {
279         if (cpu_has(c, X86_FEATURE_SMEP))
280                 cr4_set_bits(X86_CR4_SMEP);
281 }
282 
283 static __init int setup_disable_smap(char *arg)
284 {
285         setup_clear_cpu_cap(X86_FEATURE_SMAP);
286         return 1;
287 }
288 __setup("nosmap", setup_disable_smap);
289 
290 static __always_inline void setup_smap(struct cpuinfo_x86 *c)
291 {
292         unsigned long eflags = native_save_fl();
293 
294         /* This should have been cleared long ago */
295         BUG_ON(eflags & X86_EFLAGS_AC);
296 
297         if (cpu_has(c, X86_FEATURE_SMAP)) {
298 #ifdef CONFIG_X86_SMAP
299                 cr4_set_bits(X86_CR4_SMAP);
300 #else
301                 cr4_clear_bits(X86_CR4_SMAP);
302 #endif
303         }
304 }
305 
306 /*
307  * Protection Keys are not available in 32-bit mode.
308  */
309 static bool pku_disabled;
310 
311 static __always_inline void setup_pku(struct cpuinfo_x86 *c)
312 {
313         /* check the boot processor, plus compile options for PKU: */
314         if (!cpu_feature_enabled(X86_FEATURE_PKU))
315                 return;
316         /* checks the actual processor's cpuid bits: */
317         if (!cpu_has(c, X86_FEATURE_PKU))
318                 return;
319         if (pku_disabled)
320                 return;
321 
322         cr4_set_bits(X86_CR4_PKE);
323         /*
324          * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE
325          * cpuid bit to be set.  We need to ensure that we
326          * update that bit in this CPU's "cpu_info".
327          */
328         get_cpu_cap(c);
329 }
330 
331 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
332 static __init int setup_disable_pku(char *arg)
333 {
334         /*
335          * Do not clear the X86_FEATURE_PKU bit.  All of the
336          * runtime checks are against OSPKE so clearing the
337          * bit does nothing.
338          *
339          * This way, we will see "pku" in cpuinfo, but not
340          * "ospke", which is exactly what we want.  It shows
341          * that the CPU has PKU, but the OS has not enabled it.
342          * This happens to be exactly how a system would look
343          * if we disabled the config option.
344          */
345         pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n");
346         pku_disabled = true;
347         return 1;
348 }
349 __setup("nopku", setup_disable_pku);
350 #endif /* CONFIG_X86_64 */
351 
352 /*
353  * Some CPU features depend on higher CPUID levels, which may not always
354  * be available due to CPUID level capping or broken virtualization
355  * software.  Add those features to this table to auto-disable them.
356  */
357 struct cpuid_dependent_feature {
358         u32 feature;
359         u32 level;
360 };
361 
362 static const struct cpuid_dependent_feature
363 cpuid_dependent_features[] = {
364         { X86_FEATURE_MWAIT,            0x00000005 },
365         { X86_FEATURE_DCA,              0x00000009 },
366         { X86_FEATURE_XSAVE,            0x0000000d },
367         { 0, 0 }
368 };
369 
370 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
371 {
372         const struct cpuid_dependent_feature *df;
373 
374         for (df = cpuid_dependent_features; df->feature; df++) {
375 
376                 if (!cpu_has(c, df->feature))
377                         continue;
378                 /*
379                  * Note: cpuid_level is set to -1 if unavailable, but
380                  * extended_extended_level is set to 0 if unavailable
381                  * and the legitimate extended levels are all negative
382                  * when signed; hence the weird messing around with
383                  * signs here...
384                  */
385                 if (!((s32)df->level < 0 ?
386                      (u32)df->level > (u32)c->extended_cpuid_level :
387                      (s32)df->level > (s32)c->cpuid_level))
388                         continue;
389 
390                 clear_cpu_cap(c, df->feature);
391                 if (!warn)
392                         continue;
393 
394                 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n",
395                         x86_cap_flag(df->feature), df->level);
396         }
397 }
398 
399 /*
400  * Naming convention should be: <Name> [(<Codename>)]
401  * This table only is used unless init_<vendor>() below doesn't set it;
402  * in particular, if CPUID levels 0x80000002..4 are supported, this
403  * isn't used
404  */
405 
406 /* Look up CPU names by table lookup. */
407 static const char *table_lookup_model(struct cpuinfo_x86 *c)
408 {
409 #ifdef CONFIG_X86_32
410         const struct legacy_cpu_model_info *info;
411 
412         if (c->x86_model >= 16)
413                 return NULL;    /* Range check */
414 
415         if (!this_cpu)
416                 return NULL;
417 
418         info = this_cpu->legacy_models;
419 
420         while (info->family) {
421                 if (info->family == c->x86)
422                         return info->model_names[c->x86_model];
423                 info++;
424         }
425 #endif
426         return NULL;            /* Not found */
427 }
428 
429 __u32 cpu_caps_cleared[NCAPINTS];
430 __u32 cpu_caps_set[NCAPINTS];
431 
432 void load_percpu_segment(int cpu)
433 {
434 #ifdef CONFIG_X86_32
435         loadsegment(fs, __KERNEL_PERCPU);
436 #else
437         loadsegment(gs, 0);
438         wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu));
439 #endif
440         load_stack_canary_segment();
441 }
442 
443 /*
444  * Current gdt points %fs at the "master" per-cpu area: after this,
445  * it's on the real one.
446  */
447 void switch_to_new_gdt(int cpu)
448 {
449         struct desc_ptr gdt_descr;
450 
451         gdt_descr.address = (long)get_cpu_gdt_table(cpu);
452         gdt_descr.size = GDT_SIZE - 1;
453         load_gdt(&gdt_descr);
454         /* Reload the per-cpu base */
455 
456         load_percpu_segment(cpu);
457 }
458 
459 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
460 
461 static void get_model_name(struct cpuinfo_x86 *c)
462 {
463         unsigned int *v;
464         char *p, *q, *s;
465 
466         if (c->extended_cpuid_level < 0x80000004)
467                 return;
468 
469         v = (unsigned int *)c->x86_model_id;
470         cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
471         cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
472         cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
473         c->x86_model_id[48] = 0;
474 
475         /* Trim whitespace */
476         p = q = s = &c->x86_model_id[0];
477 
478         while (*p == ' ')
479                 p++;
480 
481         while (*p) {
482                 /* Note the last non-whitespace index */
483                 if (!isspace(*p))
484                         s = q;
485 
486                 *q++ = *p++;
487         }
488 
489         *(s + 1) = '\0';
490 }
491 
492 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
493 {
494         unsigned int n, dummy, ebx, ecx, edx, l2size;
495 
496         n = c->extended_cpuid_level;
497 
498         if (n >= 0x80000005) {
499                 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
500                 c->x86_cache_size = (ecx>>24) + (edx>>24);
501 #ifdef CONFIG_X86_64
502                 /* On K8 L1 TLB is inclusive, so don't count it */
503                 c->x86_tlbsize = 0;
504 #endif
505         }
506 
507         if (n < 0x80000006)     /* Some chips just has a large L1. */
508                 return;
509 
510         cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
511         l2size = ecx >> 16;
512 
513 #ifdef CONFIG_X86_64
514         c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
515 #else
516         /* do processor-specific cache resizing */
517         if (this_cpu->legacy_cache_size)
518                 l2size = this_cpu->legacy_cache_size(c, l2size);
519 
520         /* Allow user to override all this if necessary. */
521         if (cachesize_override != -1)
522                 l2size = cachesize_override;
523 
524         if (l2size == 0)
525                 return;         /* Again, no L2 cache is possible */
526 #endif
527 
528         c->x86_cache_size = l2size;
529 }
530 
531 u16 __read_mostly tlb_lli_4k[NR_INFO];
532 u16 __read_mostly tlb_lli_2m[NR_INFO];
533 u16 __read_mostly tlb_lli_4m[NR_INFO];
534 u16 __read_mostly tlb_lld_4k[NR_INFO];
535 u16 __read_mostly tlb_lld_2m[NR_INFO];
536 u16 __read_mostly tlb_lld_4m[NR_INFO];
537 u16 __read_mostly tlb_lld_1g[NR_INFO];
538 
539 static void cpu_detect_tlb(struct cpuinfo_x86 *c)
540 {
541         if (this_cpu->c_detect_tlb)
542                 this_cpu->c_detect_tlb(c);
543 
544         pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n",
545                 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES],
546                 tlb_lli_4m[ENTRIES]);
547 
548         pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n",
549                 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES],
550                 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]);
551 }
552 
553 void detect_ht(struct cpuinfo_x86 *c)
554 {
555 #ifdef CONFIG_SMP
556         u32 eax, ebx, ecx, edx;
557         int index_msb, core_bits;
558         static bool printed;
559 
560         if (!cpu_has(c, X86_FEATURE_HT))
561                 return;
562 
563         if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
564                 goto out;
565 
566         if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
567                 return;
568 
569         cpuid(1, &eax, &ebx, &ecx, &edx);
570 
571         smp_num_siblings = (ebx & 0xff0000) >> 16;
572 
573         if (smp_num_siblings == 1) {
574                 pr_info_once("CPU0: Hyper-Threading is disabled\n");
575                 goto out;
576         }
577 
578         if (smp_num_siblings <= 1)
579                 goto out;
580 
581         index_msb = get_count_order(smp_num_siblings);
582         c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb);
583 
584         smp_num_siblings = smp_num_siblings / c->x86_max_cores;
585 
586         index_msb = get_count_order(smp_num_siblings);
587 
588         core_bits = get_count_order(c->x86_max_cores);
589 
590         c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) &
591                                        ((1 << core_bits) - 1);
592 
593 out:
594         if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) {
595                 pr_info("CPU: Physical Processor ID: %d\n",
596                         c->phys_proc_id);
597                 pr_info("CPU: Processor Core ID: %d\n",
598                         c->cpu_core_id);
599                 printed = 1;
600         }
601 #endif
602 }
603 
604 static void get_cpu_vendor(struct cpuinfo_x86 *c)
605 {
606         char *v = c->x86_vendor_id;
607         int i;
608 
609         for (i = 0; i < X86_VENDOR_NUM; i++) {
610                 if (!cpu_devs[i])
611                         break;
612 
613                 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
614                     (cpu_devs[i]->c_ident[1] &&
615                      !strcmp(v, cpu_devs[i]->c_ident[1]))) {
616 
617                         this_cpu = cpu_devs[i];
618                         c->x86_vendor = this_cpu->c_x86_vendor;
619                         return;
620                 }
621         }
622 
623         pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \
624                     "CPU: Your system may be unstable.\n", v);
625 
626         c->x86_vendor = X86_VENDOR_UNKNOWN;
627         this_cpu = &default_cpu;
628 }
629 
630 void cpu_detect(struct cpuinfo_x86 *c)
631 {
632         /* Get vendor name */
633         cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
634               (unsigned int *)&c->x86_vendor_id[0],
635               (unsigned int *)&c->x86_vendor_id[8],
636               (unsigned int *)&c->x86_vendor_id[4]);
637 
638         c->x86 = 4;
639         /* Intel-defined flags: level 0x00000001 */
640         if (c->cpuid_level >= 0x00000001) {
641                 u32 junk, tfms, cap0, misc;
642 
643                 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
644                 c->x86          = x86_family(tfms);
645                 c->x86_model    = x86_model(tfms);
646                 c->x86_mask     = x86_stepping(tfms);
647 
648                 if (cap0 & (1<<19)) {
649                         c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
650                         c->x86_cache_alignment = c->x86_clflush_size;
651                 }
652         }
653 }
654 
655 void get_cpu_cap(struct cpuinfo_x86 *c)
656 {
657         u32 eax, ebx, ecx, edx;
658 
659         /* Intel-defined flags: level 0x00000001 */
660         if (c->cpuid_level >= 0x00000001) {
661                 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
662 
663                 c->x86_capability[CPUID_1_ECX] = ecx;
664                 c->x86_capability[CPUID_1_EDX] = edx;
665         }
666 
667         /* Additional Intel-defined flags: level 0x00000007 */
668         if (c->cpuid_level >= 0x00000007) {
669                 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
670 
671                 c->x86_capability[CPUID_7_0_EBX] = ebx;
672 
673                 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006);
674                 c->x86_capability[CPUID_7_ECX] = ecx;
675         }
676 
677         /* Extended state features: level 0x0000000d */
678         if (c->cpuid_level >= 0x0000000d) {
679                 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx);
680 
681                 c->x86_capability[CPUID_D_1_EAX] = eax;
682         }
683 
684         /* Additional Intel-defined flags: level 0x0000000F */
685         if (c->cpuid_level >= 0x0000000F) {
686 
687                 /* QoS sub-leaf, EAX=0Fh, ECX=0 */
688                 cpuid_count(0x0000000F, 0, &eax, &ebx, &ecx, &edx);
689                 c->x86_capability[CPUID_F_0_EDX] = edx;
690 
691                 if (cpu_has(c, X86_FEATURE_CQM_LLC)) {
692                         /* will be overridden if occupancy monitoring exists */
693                         c->x86_cache_max_rmid = ebx;
694 
695                         /* QoS sub-leaf, EAX=0Fh, ECX=1 */
696                         cpuid_count(0x0000000F, 1, &eax, &ebx, &ecx, &edx);
697                         c->x86_capability[CPUID_F_1_EDX] = edx;
698 
699                         if ((cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC)) ||
700                               ((cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL)) ||
701                                (cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)))) {
702                                 c->x86_cache_max_rmid = ecx;
703                                 c->x86_cache_occ_scale = ebx;
704                         }
705                 } else {
706                         c->x86_cache_max_rmid = -1;
707                         c->x86_cache_occ_scale = -1;
708                 }
709         }
710 
711         /* AMD-defined flags: level 0x80000001 */
712         eax = cpuid_eax(0x80000000);
713         c->extended_cpuid_level = eax;
714 
715         if ((eax & 0xffff0000) == 0x80000000) {
716                 if (eax >= 0x80000001) {
717                         cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
718 
719                         c->x86_capability[CPUID_8000_0001_ECX] = ecx;
720                         c->x86_capability[CPUID_8000_0001_EDX] = edx;
721                 }
722         }
723 
724         if (c->extended_cpuid_level >= 0x80000008) {
725                 cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
726 
727                 c->x86_virt_bits = (eax >> 8) & 0xff;
728                 c->x86_phys_bits = eax & 0xff;
729                 c->x86_capability[CPUID_8000_0008_EBX] = ebx;
730         }
731 #ifdef CONFIG_X86_32
732         else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
733                 c->x86_phys_bits = 36;
734 #endif
735 
736         if (c->extended_cpuid_level >= 0x80000007)
737                 c->x86_power = cpuid_edx(0x80000007);
738 
739         if (c->extended_cpuid_level >= 0x8000000a)
740                 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a);
741 
742         init_scattered_cpuid_features(c);
743 }
744 
745 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
746 {
747 #ifdef CONFIG_X86_32
748         int i;
749 
750         /*
751          * First of all, decide if this is a 486 or higher
752          * It's a 486 if we can modify the AC flag
753          */
754         if (flag_is_changeable_p(X86_EFLAGS_AC))
755                 c->x86 = 4;
756         else
757                 c->x86 = 3;
758 
759         for (i = 0; i < X86_VENDOR_NUM; i++)
760                 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
761                         c->x86_vendor_id[0] = 0;
762                         cpu_devs[i]->c_identify(c);
763                         if (c->x86_vendor_id[0]) {
764                                 get_cpu_vendor(c);
765                                 break;
766                         }
767                 }
768 #endif
769 }
770 
771 /*
772  * Do minimum CPU detection early.
773  * Fields really needed: vendor, cpuid_level, family, model, mask,
774  * cache alignment.
775  * The others are not touched to avoid unwanted side effects.
776  *
777  * WARNING: this function is only called on the BP.  Don't add code here
778  * that is supposed to run on all CPUs.
779  */
780 static void __init early_identify_cpu(struct cpuinfo_x86 *c)
781 {
782 #ifdef CONFIG_X86_64
783         c->x86_clflush_size = 64;
784         c->x86_phys_bits = 36;
785         c->x86_virt_bits = 48;
786 #else
787         c->x86_clflush_size = 32;
788         c->x86_phys_bits = 32;
789         c->x86_virt_bits = 32;
790 #endif
791         c->x86_cache_alignment = c->x86_clflush_size;
792 
793         memset(&c->x86_capability, 0, sizeof c->x86_capability);
794         c->extended_cpuid_level = 0;
795 
796         if (!have_cpuid_p())
797                 identify_cpu_without_cpuid(c);
798 
799         /* cyrix could have cpuid enabled via c_identify()*/
800         if (!have_cpuid_p())
801                 return;
802 
803         cpu_detect(c);
804         get_cpu_vendor(c);
805         get_cpu_cap(c);
806 
807         if (this_cpu->c_early_init)
808                 this_cpu->c_early_init(c);
809 
810         c->cpu_index = 0;
811         filter_cpuid_features(c, false);
812 
813         if (this_cpu->c_bsp_init)
814                 this_cpu->c_bsp_init(c);
815 
816         setup_force_cpu_cap(X86_FEATURE_ALWAYS);
817         fpu__init_system(c);
818 }
819 
820 void __init early_cpu_init(void)
821 {
822         const struct cpu_dev *const *cdev;
823         int count = 0;
824 
825 #ifdef CONFIG_PROCESSOR_SELECT
826         pr_info("KERNEL supported cpus:\n");
827 #endif
828 
829         for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
830                 const struct cpu_dev *cpudev = *cdev;
831 
832                 if (count >= X86_VENDOR_NUM)
833                         break;
834                 cpu_devs[count] = cpudev;
835                 count++;
836 
837 #ifdef CONFIG_PROCESSOR_SELECT
838                 {
839                         unsigned int j;
840 
841                         for (j = 0; j < 2; j++) {
842                                 if (!cpudev->c_ident[j])
843                                         continue;
844                                 pr_info("  %s %s\n", cpudev->c_vendor,
845                                         cpudev->c_ident[j]);
846                         }
847                 }
848 #endif
849         }
850         early_identify_cpu(&boot_cpu_data);
851 }
852 
853 /*
854  * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
855  * unfortunately, that's not true in practice because of early VIA
856  * chips and (more importantly) broken virtualizers that are not easy
857  * to detect. In the latter case it doesn't even *fail* reliably, so
858  * probing for it doesn't even work. Disable it completely on 32-bit
859  * unless we can find a reliable way to detect all the broken cases.
860  * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
861  */
862 static void detect_nopl(struct cpuinfo_x86 *c)
863 {
864 #ifdef CONFIG_X86_32
865         clear_cpu_cap(c, X86_FEATURE_NOPL);
866 #else
867         set_cpu_cap(c, X86_FEATURE_NOPL);
868 #endif
869 
870         /*
871          * ESPFIX is a strange bug.  All real CPUs have it.  Paravirt
872          * systems that run Linux at CPL > 0 may or may not have the
873          * issue, but, even if they have the issue, there's absolutely
874          * nothing we can do about it because we can't use the real IRET
875          * instruction.
876          *
877          * NB: For the time being, only 32-bit kernels support
878          * X86_BUG_ESPFIX as such.  64-bit kernels directly choose
879          * whether to apply espfix using paravirt hooks.  If any
880          * non-paravirt system ever shows up that does *not* have the
881          * ESPFIX issue, we can change this.
882          */
883 #ifdef CONFIG_X86_32
884 #ifdef CONFIG_PARAVIRT
885         do {
886                 extern void native_iret(void);
887                 if (pv_cpu_ops.iret == native_iret)
888                         set_cpu_bug(c, X86_BUG_ESPFIX);
889         } while (0);
890 #else
891         set_cpu_bug(c, X86_BUG_ESPFIX);
892 #endif
893 #endif
894 }
895 
896 static void generic_identify(struct cpuinfo_x86 *c)
897 {
898         c->extended_cpuid_level = 0;
899 
900         if (!have_cpuid_p())
901                 identify_cpu_without_cpuid(c);
902 
903         /* cyrix could have cpuid enabled via c_identify()*/
904         if (!have_cpuid_p())
905                 return;
906 
907         cpu_detect(c);
908 
909         get_cpu_vendor(c);
910 
911         get_cpu_cap(c);
912 
913         if (c->cpuid_level >= 0x00000001) {
914                 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
915 #ifdef CONFIG_X86_32
916 # ifdef CONFIG_SMP
917                 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
918 # else
919                 c->apicid = c->initial_apicid;
920 # endif
921 #endif
922                 c->phys_proc_id = c->initial_apicid;
923         }
924 
925         get_model_name(c); /* Default name */
926 
927         detect_nopl(c);
928 }
929 
930 static void x86_init_cache_qos(struct cpuinfo_x86 *c)
931 {
932         /*
933          * The heavy lifting of max_rmid and cache_occ_scale are handled
934          * in get_cpu_cap().  Here we just set the max_rmid for the boot_cpu
935          * in case CQM bits really aren't there in this CPU.
936          */
937         if (c != &boot_cpu_data) {
938                 boot_cpu_data.x86_cache_max_rmid =
939                         min(boot_cpu_data.x86_cache_max_rmid,
940                             c->x86_cache_max_rmid);
941         }
942 }
943 
944 /*
945  * This does the hard work of actually picking apart the CPU stuff...
946  */
947 static void identify_cpu(struct cpuinfo_x86 *c)
948 {
949         int i;
950 
951         c->loops_per_jiffy = loops_per_jiffy;
952         c->x86_cache_size = -1;
953         c->x86_vendor = X86_VENDOR_UNKNOWN;
954         c->x86_model = c->x86_mask = 0; /* So far unknown... */
955         c->x86_vendor_id[0] = '\0'; /* Unset */
956         c->x86_model_id[0] = '\0';  /* Unset */
957         c->x86_max_cores = 1;
958         c->x86_coreid_bits = 0;
959 #ifdef CONFIG_X86_64
960         c->x86_clflush_size = 64;
961         c->x86_phys_bits = 36;
962         c->x86_virt_bits = 48;
963 #else
964         c->cpuid_level = -1;    /* CPUID not detected */
965         c->x86_clflush_size = 32;
966         c->x86_phys_bits = 32;
967         c->x86_virt_bits = 32;
968 #endif
969         c->x86_cache_alignment = c->x86_clflush_size;
970         memset(&c->x86_capability, 0, sizeof c->x86_capability);
971 
972         generic_identify(c);
973 
974         if (this_cpu->c_identify)
975                 this_cpu->c_identify(c);
976 
977         /* Clear/Set all flags overridden by options, after probe */
978         for (i = 0; i < NCAPINTS; i++) {
979                 c->x86_capability[i] &= ~cpu_caps_cleared[i];
980                 c->x86_capability[i] |= cpu_caps_set[i];
981         }
982 
983 #ifdef CONFIG_X86_64
984         c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
985 #endif
986 
987         /*
988          * Vendor-specific initialization.  In this section we
989          * canonicalize the feature flags, meaning if there are
990          * features a certain CPU supports which CPUID doesn't
991          * tell us, CPUID claiming incorrect flags, or other bugs,
992          * we handle them here.
993          *
994          * At the end of this section, c->x86_capability better
995          * indicate the features this CPU genuinely supports!
996          */
997         if (this_cpu->c_init)
998                 this_cpu->c_init(c);
999 
1000         /* Disable the PN if appropriate */
1001         squash_the_stupid_serial_number(c);
1002 
1003         /* Set up SMEP/SMAP */
1004         setup_smep(c);
1005         setup_smap(c);
1006 
1007         /*
1008          * The vendor-specific functions might have changed features.
1009          * Now we do "generic changes."
1010          */
1011 
1012         /* Filter out anything that depends on CPUID levels we don't have */
1013         filter_cpuid_features(c, true);
1014 
1015         /* If the model name is still unset, do table lookup. */
1016         if (!c->x86_model_id[0]) {
1017                 const char *p;
1018                 p = table_lookup_model(c);
1019                 if (p)
1020                         strcpy(c->x86_model_id, p);
1021                 else
1022                         /* Last resort... */
1023                         sprintf(c->x86_model_id, "%02x/%02x",
1024                                 c->x86, c->x86_model);
1025         }
1026 
1027 #ifdef CONFIG_X86_64
1028         detect_ht(c);
1029 #endif
1030 
1031         init_hypervisor(c);
1032         x86_init_rdrand(c);
1033         x86_init_cache_qos(c);
1034         setup_pku(c);
1035 
1036         /*
1037          * Clear/Set all flags overridden by options, need do it
1038          * before following smp all cpus cap AND.
1039          */
1040         for (i = 0; i < NCAPINTS; i++) {
1041                 c->x86_capability[i] &= ~cpu_caps_cleared[i];
1042                 c->x86_capability[i] |= cpu_caps_set[i];
1043         }
1044 
1045         /*
1046          * On SMP, boot_cpu_data holds the common feature set between
1047          * all CPUs; so make sure that we indicate which features are
1048          * common between the CPUs.  The first time this routine gets
1049          * executed, c == &boot_cpu_data.
1050          */
1051         if (c != &boot_cpu_data) {
1052                 /* AND the already accumulated flags with these */
1053                 for (i = 0; i < NCAPINTS; i++)
1054                         boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1055 
1056                 /* OR, i.e. replicate the bug flags */
1057                 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++)
1058                         c->x86_capability[i] |= boot_cpu_data.x86_capability[i];
1059         }
1060 
1061         /* Init Machine Check Exception if available. */
1062         mcheck_cpu_init(c);
1063 
1064         select_idle_routine(c);
1065 
1066 #ifdef CONFIG_NUMA
1067         numa_add_cpu(smp_processor_id());
1068 #endif
1069         /* The boot/hotplug time assigment got cleared, restore it */
1070         c->logical_proc_id = topology_phys_to_logical_pkg(c->phys_proc_id);
1071 }
1072 
1073 /*
1074  * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions
1075  * on 32-bit kernels:
1076  */
1077 #ifdef CONFIG_X86_32
1078 void enable_sep_cpu(void)
1079 {
1080         struct tss_struct *tss;
1081         int cpu;
1082 
1083         cpu = get_cpu();
1084         tss = &per_cpu(cpu_tss, cpu);
1085 
1086         if (!boot_cpu_has(X86_FEATURE_SEP))
1087                 goto out;
1088 
1089         /*
1090          * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field --
1091          * see the big comment in struct x86_hw_tss's definition.
1092          */
1093 
1094         tss->x86_tss.ss1 = __KERNEL_CS;
1095         wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0);
1096 
1097         wrmsr(MSR_IA32_SYSENTER_ESP,
1098               (unsigned long)tss + offsetofend(struct tss_struct, SYSENTER_stack),
1099               0);
1100 
1101         wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0);
1102 
1103 out:
1104         put_cpu();
1105 }
1106 #endif
1107 
1108 void __init identify_boot_cpu(void)
1109 {
1110         identify_cpu(&boot_cpu_data);
1111         init_amd_e400_c1e_mask();
1112 #ifdef CONFIG_X86_32
1113         sysenter_setup();
1114         enable_sep_cpu();
1115 #endif
1116         cpu_detect_tlb(&boot_cpu_data);
1117 }
1118 
1119 void identify_secondary_cpu(struct cpuinfo_x86 *c)
1120 {
1121         BUG_ON(c == &boot_cpu_data);
1122         identify_cpu(c);
1123 #ifdef CONFIG_X86_32
1124         enable_sep_cpu();
1125 #endif
1126         mtrr_ap_init();
1127 }
1128 
1129 struct msr_range {
1130         unsigned        min;
1131         unsigned        max;
1132 };
1133 
1134 static const struct msr_range msr_range_array[] = {
1135         { 0x00000000, 0x00000418},
1136         { 0xc0000000, 0xc000040b},
1137         { 0xc0010000, 0xc0010142},
1138         { 0xc0011000, 0xc001103b},
1139 };
1140 
1141 static void __print_cpu_msr(void)
1142 {
1143         unsigned index_min, index_max;
1144         unsigned index;
1145         u64 val;
1146         int i;
1147 
1148         for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) {
1149                 index_min = msr_range_array[i].min;
1150                 index_max = msr_range_array[i].max;
1151 
1152                 for (index = index_min; index < index_max; index++) {
1153                         if (rdmsrl_safe(index, &val))
1154                                 continue;
1155                         pr_info(" MSR%08x: %016llx\n", index, val);
1156                 }
1157         }
1158 }
1159 
1160 static int show_msr;
1161 
1162 static __init int setup_show_msr(char *arg)
1163 {
1164         int num;
1165 
1166         get_option(&arg, &num);
1167 
1168         if (num > 0)
1169                 show_msr = num;
1170         return 1;
1171 }
1172 __setup("show_msr=", setup_show_msr);
1173 
1174 static __init int setup_noclflush(char *arg)
1175 {
1176         setup_clear_cpu_cap(X86_FEATURE_CLFLUSH);
1177         setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT);
1178         return 1;
1179 }
1180 __setup("noclflush", setup_noclflush);
1181 
1182 void print_cpu_info(struct cpuinfo_x86 *c)
1183 {
1184         const char *vendor = NULL;
1185 
1186         if (c->x86_vendor < X86_VENDOR_NUM) {
1187                 vendor = this_cpu->c_vendor;
1188         } else {
1189                 if (c->cpuid_level >= 0)
1190                         vendor = c->x86_vendor_id;
1191         }
1192 
1193         if (vendor && !strstr(c->x86_model_id, vendor))
1194                 pr_cont("%s ", vendor);
1195 
1196         if (c->x86_model_id[0])
1197                 pr_cont("%s", c->x86_model_id);
1198         else
1199                 pr_cont("%d86", c->x86);
1200 
1201         pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model);
1202 
1203         if (c->x86_mask || c->cpuid_level >= 0)
1204                 pr_cont(", stepping: 0x%x)\n", c->x86_mask);
1205         else
1206                 pr_cont(")\n");
1207 
1208         print_cpu_msr(c);
1209 }
1210 
1211 void print_cpu_msr(struct cpuinfo_x86 *c)
1212 {
1213         if (c->cpu_index < show_msr)
1214                 __print_cpu_msr();
1215 }
1216 
1217 static __init int setup_disablecpuid(char *arg)
1218 {
1219         int bit;
1220 
1221         if (get_option(&arg, &bit) && bit < NCAPINTS*32)
1222                 setup_clear_cpu_cap(bit);
1223         else
1224                 return 0;
1225 
1226         return 1;
1227 }
1228 __setup("clearcpuid=", setup_disablecpuid);
1229 
1230 #ifdef CONFIG_X86_64
1231 struct desc_ptr idt_descr = { NR_VECTORS * 16 - 1, (unsigned long) idt_table };
1232 struct desc_ptr debug_idt_descr = { NR_VECTORS * 16 - 1,
1233                                     (unsigned long) debug_idt_table };
1234 
1235 DEFINE_PER_CPU_FIRST(union irq_stack_union,
1236                      irq_stack_union) __aligned(PAGE_SIZE) __visible;
1237 
1238 /*
1239  * The following percpu variables are hot.  Align current_task to
1240  * cacheline size such that they fall in the same cacheline.
1241  */
1242 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned =
1243         &init_task;
1244 EXPORT_PER_CPU_SYMBOL(current_task);
1245 
1246 DEFINE_PER_CPU(char *, irq_stack_ptr) =
1247         init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64;
1248 
1249 DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1;
1250 
1251 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1252 EXPORT_PER_CPU_SYMBOL(__preempt_count);
1253 
1254 /*
1255  * Special IST stacks which the CPU switches to when it calls
1256  * an IST-marked descriptor entry. Up to 7 stacks (hardware
1257  * limit), all of them are 4K, except the debug stack which
1258  * is 8K.
1259  */
1260 static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = {
1261           [0 ... N_EXCEPTION_STACKS - 1]        = EXCEPTION_STKSZ,
1262           [DEBUG_STACK - 1]                     = DEBUG_STKSZ
1263 };
1264 
1265 static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks
1266         [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]);
1267 
1268 /* May not be marked __init: used by software suspend */
1269 void syscall_init(void)
1270 {
1271         /*
1272          * LSTAR and STAR live in a bit strange symbiosis.
1273          * They both write to the same internal register. STAR allows to
1274          * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
1275          */
1276         wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS);
1277         wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64);
1278 
1279 #ifdef CONFIG_IA32_EMULATION
1280         wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat);
1281         /*
1282          * This only works on Intel CPUs.
1283          * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP.
1284          * This does not cause SYSENTER to jump to the wrong location, because
1285          * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit).
1286          */
1287         wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS);
1288         wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
1289         wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat);
1290 #else
1291         wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret);
1292         wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG);
1293         wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
1294         wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL);
1295 #endif
1296 
1297         /* Flags to clear on syscall */
1298         wrmsrl(MSR_SYSCALL_MASK,
1299                X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|
1300                X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT);
1301 }
1302 
1303 /*
1304  * Copies of the original ist values from the tss are only accessed during
1305  * debugging, no special alignment required.
1306  */
1307 DEFINE_PER_CPU(struct orig_ist, orig_ist);
1308 
1309 static DEFINE_PER_CPU(unsigned long, debug_stack_addr);
1310 DEFINE_PER_CPU(int, debug_stack_usage);
1311 
1312 int is_debug_stack(unsigned long addr)
1313 {
1314         return __this_cpu_read(debug_stack_usage) ||
1315                 (addr <= __this_cpu_read(debug_stack_addr) &&
1316                  addr > (__this_cpu_read(debug_stack_addr) - DEBUG_STKSZ));
1317 }
1318 NOKPROBE_SYMBOL(is_debug_stack);
1319 
1320 DEFINE_PER_CPU(u32, debug_idt_ctr);
1321 
1322 void debug_stack_set_zero(void)
1323 {
1324         this_cpu_inc(debug_idt_ctr);
1325         load_current_idt();
1326 }
1327 NOKPROBE_SYMBOL(debug_stack_set_zero);
1328 
1329 void debug_stack_reset(void)
1330 {
1331         if (WARN_ON(!this_cpu_read(debug_idt_ctr)))
1332                 return;
1333         if (this_cpu_dec_return(debug_idt_ctr) == 0)
1334                 load_current_idt();
1335 }
1336 NOKPROBE_SYMBOL(debug_stack_reset);
1337 
1338 #else   /* CONFIG_X86_64 */
1339 
1340 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task;
1341 EXPORT_PER_CPU_SYMBOL(current_task);
1342 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1343 EXPORT_PER_CPU_SYMBOL(__preempt_count);
1344 
1345 /*
1346  * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find
1347  * the top of the kernel stack.  Use an extra percpu variable to track the
1348  * top of the kernel stack directly.
1349  */
1350 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) =
1351         (unsigned long)&init_thread_union + THREAD_SIZE;
1352 EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack);
1353 
1354 #ifdef CONFIG_CC_STACKPROTECTOR
1355 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
1356 #endif
1357 
1358 #endif  /* CONFIG_X86_64 */
1359 
1360 /*
1361  * Clear all 6 debug registers:
1362  */
1363 static void clear_all_debug_regs(void)
1364 {
1365         int i;
1366 
1367         for (i = 0; i < 8; i++) {
1368                 /* Ignore db4, db5 */
1369                 if ((i == 4) || (i == 5))
1370                         continue;
1371 
1372                 set_debugreg(0, i);
1373         }
1374 }
1375 
1376 #ifdef CONFIG_KGDB
1377 /*
1378  * Restore debug regs if using kgdbwait and you have a kernel debugger
1379  * connection established.
1380  */
1381 static void dbg_restore_debug_regs(void)
1382 {
1383         if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break))
1384                 arch_kgdb_ops.correct_hw_break();
1385 }
1386 #else /* ! CONFIG_KGDB */
1387 #define dbg_restore_debug_regs()
1388 #endif /* ! CONFIG_KGDB */
1389 
1390 static void wait_for_master_cpu(int cpu)
1391 {
1392 #ifdef CONFIG_SMP
1393         /*
1394          * wait for ACK from master CPU before continuing
1395          * with AP initialization
1396          */
1397         WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask));
1398         while (!cpumask_test_cpu(cpu, cpu_callout_mask))
1399                 cpu_relax();
1400 #endif
1401 }
1402 
1403 /*
1404  * cpu_init() initializes state that is per-CPU. Some data is already
1405  * initialized (naturally) in the bootstrap process, such as the GDT
1406  * and IDT. We reload them nevertheless, this function acts as a
1407  * 'CPU state barrier', nothing should get across.
1408  * A lot of state is already set up in PDA init for 64 bit
1409  */
1410 #ifdef CONFIG_X86_64
1411 
1412 void cpu_init(void)
1413 {
1414         struct orig_ist *oist;
1415         struct task_struct *me;
1416         struct tss_struct *t;
1417         unsigned long v;
1418         int cpu = stack_smp_processor_id();
1419         int i;
1420 
1421         wait_for_master_cpu(cpu);
1422 
1423         /*
1424          * Initialize the CR4 shadow before doing anything that could
1425          * try to read it.
1426          */
1427         cr4_init_shadow();
1428 
1429         /*
1430          * Load microcode on this cpu if a valid microcode is available.
1431          * This is early microcode loading procedure.
1432          */
1433         load_ucode_ap();
1434 
1435         t = &per_cpu(cpu_tss, cpu);
1436         oist = &per_cpu(orig_ist, cpu);
1437 
1438 #ifdef CONFIG_NUMA
1439         if (this_cpu_read(numa_node) == 0 &&
1440             early_cpu_to_node(cpu) != NUMA_NO_NODE)
1441                 set_numa_node(early_cpu_to_node(cpu));
1442 #endif
1443 
1444         me = current;
1445 
1446         pr_debug("Initializing CPU#%d\n", cpu);
1447 
1448         cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1449 
1450         /*
1451          * Initialize the per-CPU GDT with the boot GDT,
1452          * and set up the GDT descriptor:
1453          */
1454 
1455         switch_to_new_gdt(cpu);
1456         loadsegment(fs, 0);
1457 
1458         load_current_idt();
1459 
1460         memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
1461         syscall_init();
1462 
1463         wrmsrl(MSR_FS_BASE, 0);
1464         wrmsrl(MSR_KERNEL_GS_BASE, 0);
1465         barrier();
1466 
1467         x86_configure_nx();
1468         x2apic_setup();
1469 
1470         /*
1471          * set up and load the per-CPU TSS
1472          */
1473         if (!oist->ist[0]) {
1474                 char *estacks = per_cpu(exception_stacks, cpu);
1475 
1476                 for (v = 0; v < N_EXCEPTION_STACKS; v++) {
1477                         estacks += exception_stack_sizes[v];
1478                         oist->ist[v] = t->x86_tss.ist[v] =
1479                                         (unsigned long)estacks;
1480                         if (v == DEBUG_STACK-1)
1481                                 per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks;
1482                 }
1483         }
1484 
1485         t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1486 
1487         /*
1488          * <= is required because the CPU will access up to
1489          * 8 bits beyond the end of the IO permission bitmap.
1490          */
1491         for (i = 0; i <= IO_BITMAP_LONGS; i++)
1492                 t->io_bitmap[i] = ~0UL;
1493 
1494         atomic_inc(&init_mm.mm_count);
1495         me->active_mm = &init_mm;
1496         BUG_ON(me->mm);
1497         enter_lazy_tlb(&init_mm, me);
1498 
1499         load_sp0(t, &current->thread);
1500         set_tss_desc(cpu, t);
1501         load_TR_desc();
1502         load_mm_ldt(&init_mm);
1503 
1504         clear_all_debug_regs();
1505         dbg_restore_debug_regs();
1506 
1507         fpu__init_cpu();
1508 
1509         if (is_uv_system())
1510                 uv_cpu_init();
1511 }
1512 
1513 #else
1514 
1515 void cpu_init(void)
1516 {
1517         int cpu = smp_processor_id();
1518         struct task_struct *curr = current;
1519         struct tss_struct *t = &per_cpu(cpu_tss, cpu);
1520         struct thread_struct *thread = &curr->thread;
1521 
1522         wait_for_master_cpu(cpu);
1523 
1524         /*
1525          * Initialize the CR4 shadow before doing anything that could
1526          * try to read it.
1527          */
1528         cr4_init_shadow();
1529 
1530         show_ucode_info_early();
1531 
1532         pr_info("Initializing CPU#%d\n", cpu);
1533 
1534         if (cpu_feature_enabled(X86_FEATURE_VME) ||
1535             cpu_has_tsc ||
1536             boot_cpu_has(X86_FEATURE_DE))
1537                 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1538 
1539         load_current_idt();
1540         switch_to_new_gdt(cpu);
1541 
1542         /*
1543          * Set up and load the per-CPU TSS and LDT
1544          */
1545         atomic_inc(&init_mm.mm_count);
1546         curr->active_mm = &init_mm;
1547         BUG_ON(curr->mm);
1548         enter_lazy_tlb(&init_mm, curr);
1549 
1550         load_sp0(t, thread);
1551         set_tss_desc(cpu, t);
1552         load_TR_desc();
1553         load_mm_ldt(&init_mm);
1554 
1555         t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1556 
1557 #ifdef CONFIG_DOUBLEFAULT
1558         /* Set up doublefault TSS pointer in the GDT */
1559         __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
1560 #endif
1561 
1562         clear_all_debug_regs();
1563         dbg_restore_debug_regs();
1564 
1565         fpu__init_cpu();
1566 }
1567 #endif
1568 
1569 static void bsp_resume(void)
1570 {
1571         if (this_cpu->c_bsp_resume)
1572                 this_cpu->c_bsp_resume(&boot_cpu_data);
1573 }
1574 
1575 static struct syscore_ops cpu_syscore_ops = {
1576         .resume         = bsp_resume,
1577 };
1578 
1579 static int __init init_cpu_syscore(void)
1580 {
1581         register_syscore_ops(&cpu_syscore_ops);
1582         return 0;
1583 }
1584 core_initcall(init_cpu_syscore);
1585 

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