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TOMOYO Linux Cross Reference
Linux/arch/x86/kernel/cpu/intel.c

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  1 #include <linux/init.h>
  2 #include <linux/kernel.h>
  3 
  4 #include <linux/string.h>
  5 #include <linux/bitops.h>
  6 #include <linux/smp.h>
  7 #include <linux/sched.h>
  8 #include <linux/thread_info.h>
  9 #include <linux/module.h>
 10 #include <linux/uaccess.h>
 11 
 12 #include <asm/processor.h>
 13 #include <asm/pgtable.h>
 14 #include <asm/msr.h>
 15 #include <asm/bugs.h>
 16 #include <asm/cpu.h>
 17 
 18 #ifdef CONFIG_X86_64
 19 #include <linux/topology.h>
 20 #endif
 21 
 22 #include "cpu.h"
 23 
 24 #ifdef CONFIG_X86_LOCAL_APIC
 25 #include <asm/mpspec.h>
 26 #include <asm/apic.h>
 27 #endif
 28 
 29 static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
 30 {
 31         u64 misc_enable;
 32 
 33         /* Unmask CPUID levels if masked: */
 34         if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
 35                 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
 36 
 37                 if (misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID) {
 38                         misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID;
 39                         wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
 40                         c->cpuid_level = cpuid_eax(0);
 41                         get_cpu_cap(c);
 42                 }
 43         }
 44 
 45         if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
 46                 (c->x86 == 0x6 && c->x86_model >= 0x0e))
 47                 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
 48 
 49         if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64)) {
 50                 unsigned lower_word;
 51 
 52                 wrmsr(MSR_IA32_UCODE_REV, 0, 0);
 53                 /* Required by the SDM */
 54                 sync_core();
 55                 rdmsr(MSR_IA32_UCODE_REV, lower_word, c->microcode);
 56         }
 57 
 58         /*
 59          * Atom erratum AAE44/AAF40/AAG38/AAH41:
 60          *
 61          * A race condition between speculative fetches and invalidating
 62          * a large page.  This is worked around in microcode, but we
 63          * need the microcode to have already been loaded... so if it is
 64          * not, recommend a BIOS update and disable large pages.
 65          */
 66         if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2 &&
 67             c->microcode < 0x20e) {
 68                 printk(KERN_WARNING "Atom PSE erratum detected, BIOS microcode update recommended\n");
 69                 clear_cpu_cap(c, X86_FEATURE_PSE);
 70         }
 71 
 72 #ifdef CONFIG_X86_64
 73         set_cpu_cap(c, X86_FEATURE_SYSENTER32);
 74 #else
 75         /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
 76         if (c->x86 == 15 && c->x86_cache_alignment == 64)
 77                 c->x86_cache_alignment = 128;
 78 #endif
 79 
 80         /* CPUID workaround for 0F33/0F34 CPU */
 81         if (c->x86 == 0xF && c->x86_model == 0x3
 82             && (c->x86_mask == 0x3 || c->x86_mask == 0x4))
 83                 c->x86_phys_bits = 36;
 84 
 85         /*
 86          * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
 87          * with P/T states and does not stop in deep C-states.
 88          *
 89          * It is also reliable across cores and sockets. (but not across
 90          * cabinets - we turn it off in that case explicitly.)
 91          */
 92         if (c->x86_power & (1 << 8)) {
 93                 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
 94                 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
 95                 if (!check_tsc_unstable())
 96                         sched_clock_stable = 1;
 97         }
 98 
 99         /* Penwell and Cloverview have the TSC which doesn't sleep on S3 */
100         if (c->x86 == 6) {
101                 switch (c->x86_model) {
102                 case 0x27:      /* Penwell */
103                 case 0x35:      /* Cloverview */
104                         set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3);
105                         break;
106                 default:
107                         break;
108                 }
109         }
110 
111         /*
112          * There is a known erratum on Pentium III and Core Solo
113          * and Core Duo CPUs.
114          * " Page with PAT set to WC while associated MTRR is UC
115          *   may consolidate to UC "
116          * Because of this erratum, it is better to stick with
117          * setting WC in MTRR rather than using PAT on these CPUs.
118          *
119          * Enable PAT WC only on P4, Core 2 or later CPUs.
120          */
121         if (c->x86 == 6 && c->x86_model < 15)
122                 clear_cpu_cap(c, X86_FEATURE_PAT);
123 
124 #ifdef CONFIG_KMEMCHECK
125         /*
126          * P4s have a "fast strings" feature which causes single-
127          * stepping REP instructions to only generate a #DB on
128          * cache-line boundaries.
129          *
130          * Ingo Molnar reported a Pentium D (model 6) and a Xeon
131          * (model 2) with the same problem.
132          */
133         if (c->x86 == 15) {
134                 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
135 
136                 if (misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING) {
137                         printk(KERN_INFO "kmemcheck: Disabling fast string operations\n");
138 
139                         misc_enable &= ~MSR_IA32_MISC_ENABLE_FAST_STRING;
140                         wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
141                 }
142         }
143 #endif
144 
145         /*
146          * If fast string is not enabled in IA32_MISC_ENABLE for any reason,
147          * clear the fast string and enhanced fast string CPU capabilities.
148          */
149         if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
150                 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
151                 if (!(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) {
152                         printk(KERN_INFO "Disabled fast string operations\n");
153                         setup_clear_cpu_cap(X86_FEATURE_REP_GOOD);
154                         setup_clear_cpu_cap(X86_FEATURE_ERMS);
155                 }
156         }
157 
158         /*
159          * Intel Quark Core DevMan_001.pdf section 6.4.11
160          * "The operating system also is required to invalidate (i.e., flush)
161          *  the TLB when any changes are made to any of the page table entries.
162          *  The operating system must reload CR3 to cause the TLB to be flushed"
163          *
164          * As a result cpu_has_pge() in arch/x86/include/asm/tlbflush.h should
165          * be false so that __flush_tlb_all() causes CR3 insted of CR4.PGE
166          * to be modified
167          */
168         if (c->x86 == 5 && c->x86_model == 9) {
169                 pr_info("Disabling PGE capability bit\n");
170                 setup_clear_cpu_cap(X86_FEATURE_PGE);
171         }
172 }
173 
174 #ifdef CONFIG_X86_32
175 /*
176  *      Early probe support logic for ppro memory erratum #50
177  *
178  *      This is called before we do cpu ident work
179  */
180 
181 int __cpuinit ppro_with_ram_bug(void)
182 {
183         /* Uses data from early_cpu_detect now */
184         if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
185             boot_cpu_data.x86 == 6 &&
186             boot_cpu_data.x86_model == 1 &&
187             boot_cpu_data.x86_mask < 8) {
188                 printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n");
189                 return 1;
190         }
191         return 0;
192 }
193 
194 static void __cpuinit intel_smp_check(struct cpuinfo_x86 *c)
195 {
196         /* calling is from identify_secondary_cpu() ? */
197         if (!c->cpu_index)
198                 return;
199 
200         /*
201          * Mask B, Pentium, but not Pentium MMX
202          */
203         if (c->x86 == 5 &&
204             c->x86_mask >= 1 && c->x86_mask <= 4 &&
205             c->x86_model <= 3) {
206                 /*
207                  * Remember we have B step Pentia with bugs
208                  */
209                 WARN_ONCE(1, "WARNING: SMP operation may be unreliable"
210                                     "with B stepping processors.\n");
211         }
212 }
213 
214 static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
215 {
216         unsigned long lo, hi;
217 
218 #ifdef CONFIG_X86_F00F_BUG
219         /*
220          * All current models of Pentium and Pentium with MMX technology CPUs
221          * have the F0 0F bug, which lets nonprivileged users lock up the
222          * system. Announce that the fault handler will be checking for it.
223          */
224         clear_cpu_bug(c, X86_BUG_F00F);
225         if (!paravirt_enabled() && c->x86 == 5) {
226                 static int f00f_workaround_enabled;
227 
228                 set_cpu_bug(c, X86_BUG_F00F);
229                 if (!f00f_workaround_enabled) {
230                         printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
231                         f00f_workaround_enabled = 1;
232                 }
233         }
234 #endif
235 
236         /*
237          * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
238          * model 3 mask 3
239          */
240         if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
241                 clear_cpu_cap(c, X86_FEATURE_SEP);
242 
243         /*
244          * P4 Xeon errata 037 workaround.
245          * Hardware prefetcher may cause stale data to be loaded into the cache.
246          */
247         if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
248                 rdmsr(MSR_IA32_MISC_ENABLE, lo, hi);
249                 if ((lo & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE) == 0) {
250                         printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
251                         printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
252                         lo |= MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE;
253                         wrmsr(MSR_IA32_MISC_ENABLE, lo, hi);
254                 }
255         }
256 
257         /*
258          * See if we have a good local APIC by checking for buggy Pentia,
259          * i.e. all B steppings and the C2 stepping of P54C when using their
260          * integrated APIC (see 11AP erratum in "Pentium Processor
261          * Specification Update").
262          */
263         if (cpu_has_apic && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
264             (c->x86_mask < 0x6 || c->x86_mask == 0xb))
265                 set_cpu_cap(c, X86_FEATURE_11AP);
266 
267 
268 #ifdef CONFIG_X86_INTEL_USERCOPY
269         /*
270          * Set up the preferred alignment for movsl bulk memory moves
271          */
272         switch (c->x86) {
273         case 4:         /* 486: untested */
274                 break;
275         case 5:         /* Old Pentia: untested */
276                 break;
277         case 6:         /* PII/PIII only like movsl with 8-byte alignment */
278                 movsl_mask.mask = 7;
279                 break;
280         case 15:        /* P4 is OK down to 8-byte alignment */
281                 movsl_mask.mask = 7;
282                 break;
283         }
284 #endif
285 
286 #ifdef CONFIG_X86_NUMAQ
287         numaq_tsc_disable();
288 #endif
289 
290         intel_smp_check(c);
291 }
292 #else
293 static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
294 {
295 }
296 #endif
297 
298 static void __cpuinit srat_detect_node(struct cpuinfo_x86 *c)
299 {
300 #ifdef CONFIG_NUMA
301         unsigned node;
302         int cpu = smp_processor_id();
303 
304         /* Don't do the funky fallback heuristics the AMD version employs
305            for now. */
306         node = numa_cpu_node(cpu);
307         if (node == NUMA_NO_NODE || !node_online(node)) {
308                 /* reuse the value from init_cpu_to_node() */
309                 node = cpu_to_node(cpu);
310         }
311         numa_set_node(cpu, node);
312 #endif
313 }
314 
315 /*
316  * find out the number of processor cores on the die
317  */
318 static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
319 {
320         unsigned int eax, ebx, ecx, edx;
321 
322         if (c->cpuid_level < 4)
323                 return 1;
324 
325         /* Intel has a non-standard dependency on %ecx for this CPUID level. */
326         cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
327         if (eax & 0x1f)
328                 return (eax >> 26) + 1;
329         else
330                 return 1;
331 }
332 
333 static void __cpuinit detect_vmx_virtcap(struct cpuinfo_x86 *c)
334 {
335         /* Intel VMX MSR indicated features */
336 #define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW    0x00200000
337 #define X86_VMX_FEATURE_PROC_CTLS_VNMI          0x00400000
338 #define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS      0x80000000
339 #define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC    0x00000001
340 #define X86_VMX_FEATURE_PROC_CTLS2_EPT          0x00000002
341 #define X86_VMX_FEATURE_PROC_CTLS2_VPID         0x00000020
342 
343         u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;
344 
345         clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
346         clear_cpu_cap(c, X86_FEATURE_VNMI);
347         clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
348         clear_cpu_cap(c, X86_FEATURE_EPT);
349         clear_cpu_cap(c, X86_FEATURE_VPID);
350 
351         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
352         msr_ctl = vmx_msr_high | vmx_msr_low;
353         if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
354                 set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
355         if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
356                 set_cpu_cap(c, X86_FEATURE_VNMI);
357         if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
358                 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
359                       vmx_msr_low, vmx_msr_high);
360                 msr_ctl2 = vmx_msr_high | vmx_msr_low;
361                 if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
362                     (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
363                         set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
364                 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT)
365                         set_cpu_cap(c, X86_FEATURE_EPT);
366                 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
367                         set_cpu_cap(c, X86_FEATURE_VPID);
368         }
369 }
370 
371 static void __cpuinit init_intel(struct cpuinfo_x86 *c)
372 {
373         unsigned int l2 = 0;
374 
375         early_init_intel(c);
376 
377         intel_workarounds(c);
378 
379         /*
380          * Detect the extended topology information if available. This
381          * will reinitialise the initial_apicid which will be used
382          * in init_intel_cacheinfo()
383          */
384         detect_extended_topology(c);
385 
386         l2 = init_intel_cacheinfo(c);
387         if (c->cpuid_level > 9) {
388                 unsigned eax = cpuid_eax(10);
389                 /* Check for version and the number of counters */
390                 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
391                         set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
392         }
393 
394         if (cpu_has_xmm2)
395                 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
396         if (cpu_has_ds) {
397                 unsigned int l1;
398                 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
399                 if (!(l1 & (1<<11)))
400                         set_cpu_cap(c, X86_FEATURE_BTS);
401                 if (!(l1 & (1<<12)))
402                         set_cpu_cap(c, X86_FEATURE_PEBS);
403         }
404 
405         if (c->x86 == 6 && cpu_has_clflush &&
406             (c->x86_model == 29 || c->x86_model == 46 || c->x86_model == 47))
407                 set_cpu_cap(c, X86_FEATURE_CLFLUSH_MONITOR);
408 
409 #ifdef CONFIG_X86_64
410         if (c->x86 == 15)
411                 c->x86_cache_alignment = c->x86_clflush_size * 2;
412         if (c->x86 == 6)
413                 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
414 #else
415         /*
416          * Names for the Pentium II/Celeron processors
417          * detectable only by also checking the cache size.
418          * Dixon is NOT a Celeron.
419          */
420         if (c->x86 == 6) {
421                 char *p = NULL;
422 
423                 switch (c->x86_model) {
424                 case 5:
425                         if (l2 == 0)
426                                 p = "Celeron (Covington)";
427                         else if (l2 == 256)
428                                 p = "Mobile Pentium II (Dixon)";
429                         break;
430 
431                 case 6:
432                         if (l2 == 128)
433                                 p = "Celeron (Mendocino)";
434                         else if (c->x86_mask == 0 || c->x86_mask == 5)
435                                 p = "Celeron-A";
436                         break;
437 
438                 case 8:
439                         if (l2 == 128)
440                                 p = "Celeron (Coppermine)";
441                         break;
442                 }
443 
444                 if (p)
445                         strcpy(c->x86_model_id, p);
446         }
447 
448         if (c->x86 == 15)
449                 set_cpu_cap(c, X86_FEATURE_P4);
450         if (c->x86 == 6)
451                 set_cpu_cap(c, X86_FEATURE_P3);
452 #endif
453 
454         if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
455                 /*
456                  * let's use the legacy cpuid vector 0x1 and 0x4 for topology
457                  * detection.
458                  */
459                 c->x86_max_cores = intel_num_cpu_cores(c);
460 #ifdef CONFIG_X86_32
461                 detect_ht(c);
462 #endif
463         }
464 
465         /* Work around errata */
466         srat_detect_node(c);
467 
468         if (cpu_has(c, X86_FEATURE_VMX))
469                 detect_vmx_virtcap(c);
470 
471         /*
472          * Initialize MSR_IA32_ENERGY_PERF_BIAS if BIOS did not.
473          * x86_energy_perf_policy(8) is available to change it at run-time
474          */
475         if (cpu_has(c, X86_FEATURE_EPB)) {
476                 u64 epb;
477 
478                 rdmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb);
479                 if ((epb & 0xF) == ENERGY_PERF_BIAS_PERFORMANCE) {
480                         printk_once(KERN_WARNING "ENERGY_PERF_BIAS:"
481                                 " Set to 'normal', was 'performance'\n"
482                                 "ENERGY_PERF_BIAS: View and update with"
483                                 " x86_energy_perf_policy(8)\n");
484                         epb = (epb & ~0xF) | ENERGY_PERF_BIAS_NORMAL;
485                         wrmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb);
486                 }
487         }
488 }
489 
490 #ifdef CONFIG_X86_32
491 static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
492 {
493         /*
494          * Intel PIII Tualatin. This comes in two flavours.
495          * One has 256kb of cache, the other 512. We have no way
496          * to determine which, so we use a boottime override
497          * for the 512kb model, and assume 256 otherwise.
498          */
499         if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
500                 size = 256;
501         return size;
502 }
503 #endif
504 
505 #define TLB_INST_4K     0x01
506 #define TLB_INST_4M     0x02
507 #define TLB_INST_2M_4M  0x03
508 
509 #define TLB_INST_ALL    0x05
510 #define TLB_INST_1G     0x06
511 
512 #define TLB_DATA_4K     0x11
513 #define TLB_DATA_4M     0x12
514 #define TLB_DATA_2M_4M  0x13
515 #define TLB_DATA_4K_4M  0x14
516 
517 #define TLB_DATA_1G     0x16
518 
519 #define TLB_DATA0_4K    0x21
520 #define TLB_DATA0_4M    0x22
521 #define TLB_DATA0_2M_4M 0x23
522 
523 #define STLB_4K         0x41
524 
525 static const struct _tlb_table intel_tlb_table[] __cpuinitconst = {
526         { 0x01, TLB_INST_4K,            32,     " TLB_INST 4 KByte pages, 4-way set associative" },
527         { 0x02, TLB_INST_4M,            2,      " TLB_INST 4 MByte pages, full associative" },
528         { 0x03, TLB_DATA_4K,            64,     " TLB_DATA 4 KByte pages, 4-way set associative" },
529         { 0x04, TLB_DATA_4M,            8,      " TLB_DATA 4 MByte pages, 4-way set associative" },
530         { 0x05, TLB_DATA_4M,            32,     " TLB_DATA 4 MByte pages, 4-way set associative" },
531         { 0x0b, TLB_INST_4M,            4,      " TLB_INST 4 MByte pages, 4-way set associative" },
532         { 0x4f, TLB_INST_4K,            32,     " TLB_INST 4 KByte pages */" },
533         { 0x50, TLB_INST_ALL,           64,     " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
534         { 0x51, TLB_INST_ALL,           128,    " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
535         { 0x52, TLB_INST_ALL,           256,    " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
536         { 0x55, TLB_INST_2M_4M,         7,      " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
537         { 0x56, TLB_DATA0_4M,           16,     " TLB_DATA0 4 MByte pages, 4-way set associative" },
538         { 0x57, TLB_DATA0_4K,           16,     " TLB_DATA0 4 KByte pages, 4-way associative" },
539         { 0x59, TLB_DATA0_4K,           16,     " TLB_DATA0 4 KByte pages, fully associative" },
540         { 0x5a, TLB_DATA0_2M_4M,        32,     " TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative" },
541         { 0x5b, TLB_DATA_4K_4M,         64,     " TLB_DATA 4 KByte and 4 MByte pages" },
542         { 0x5c, TLB_DATA_4K_4M,         128,    " TLB_DATA 4 KByte and 4 MByte pages" },
543         { 0x5d, TLB_DATA_4K_4M,         256,    " TLB_DATA 4 KByte and 4 MByte pages" },
544         { 0xb0, TLB_INST_4K,            128,    " TLB_INST 4 KByte pages, 4-way set associative" },
545         { 0xb1, TLB_INST_2M_4M,         4,      " TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" },
546         { 0xb2, TLB_INST_4K,            64,     " TLB_INST 4KByte pages, 4-way set associative" },
547         { 0xb3, TLB_DATA_4K,            128,    " TLB_DATA 4 KByte pages, 4-way set associative" },
548         { 0xb4, TLB_DATA_4K,            256,    " TLB_DATA 4 KByte pages, 4-way associative" },
549         { 0xba, TLB_DATA_4K,            64,     " TLB_DATA 4 KByte pages, 4-way associative" },
550         { 0xc0, TLB_DATA_4K_4M,         8,      " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" },
551         { 0xca, STLB_4K,                512,    " STLB 4 KByte pages, 4-way associative" },
552         { 0x00, 0, 0 }
553 };
554 
555 static void __cpuinit intel_tlb_lookup(const unsigned char desc)
556 {
557         unsigned char k;
558         if (desc == 0)
559                 return;
560 
561         /* look up this descriptor in the table */
562         for (k = 0; intel_tlb_table[k].descriptor != desc && \
563                         intel_tlb_table[k].descriptor != 0; k++)
564                 ;
565 
566         if (intel_tlb_table[k].tlb_type == 0)
567                 return;
568 
569         switch (intel_tlb_table[k].tlb_type) {
570         case STLB_4K:
571                 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
572                         tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
573                 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
574                         tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
575                 break;
576         case TLB_INST_ALL:
577                 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
578                         tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
579                 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
580                         tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
581                 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
582                         tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
583                 break;
584         case TLB_INST_4K:
585                 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
586                         tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
587                 break;
588         case TLB_INST_4M:
589                 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
590                         tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
591                 break;
592         case TLB_INST_2M_4M:
593                 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
594                         tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
595                 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
596                         tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
597                 break;
598         case TLB_DATA_4K:
599         case TLB_DATA0_4K:
600                 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
601                         tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
602                 break;
603         case TLB_DATA_4M:
604         case TLB_DATA0_4M:
605                 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
606                         tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
607                 break;
608         case TLB_DATA_2M_4M:
609         case TLB_DATA0_2M_4M:
610                 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
611                         tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
612                 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
613                         tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
614                 break;
615         case TLB_DATA_4K_4M:
616                 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
617                         tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
618                 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
619                         tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
620                 break;
621         }
622 }
623 
624 static void __cpuinit intel_tlb_flushall_shift_set(struct cpuinfo_x86 *c)
625 {
626         switch ((c->x86 << 8) + c->x86_model) {
627         case 0x60f: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
628         case 0x616: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */
629         case 0x617: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */
630         case 0x61d: /* six-core 45 nm xeon "Dunnington" */
631                 tlb_flushall_shift = -1;
632                 break;
633         case 0x61a: /* 45 nm nehalem, "Bloomfield" */
634         case 0x61e: /* 45 nm nehalem, "Lynnfield" */
635         case 0x625: /* 32 nm nehalem, "Clarkdale" */
636         case 0x62c: /* 32 nm nehalem, "Gulftown" */
637         case 0x62e: /* 45 nm nehalem-ex, "Beckton" */
638         case 0x62f: /* 32 nm Xeon E7 */
639                 tlb_flushall_shift = 6;
640                 break;
641         case 0x62a: /* SandyBridge */
642         case 0x62d: /* SandyBridge, "Romely-EP" */
643                 tlb_flushall_shift = 5;
644                 break;
645         case 0x63a: /* Ivybridge */
646                 tlb_flushall_shift = 2;
647                 break;
648         default:
649                 tlb_flushall_shift = 6;
650         }
651 }
652 
653 static void __cpuinit intel_detect_tlb(struct cpuinfo_x86 *c)
654 {
655         int i, j, n;
656         unsigned int regs[4];
657         unsigned char *desc = (unsigned char *)regs;
658 
659         if (c->cpuid_level < 2)
660                 return;
661 
662         /* Number of times to iterate */
663         n = cpuid_eax(2) & 0xFF;
664 
665         for (i = 0 ; i < n ; i++) {
666                 cpuid(2, &regs[0], &regs[1], &regs[2], &regs[3]);
667 
668                 /* If bit 31 is set, this is an unknown format */
669                 for (j = 0 ; j < 3 ; j++)
670                         if (regs[j] & (1 << 31))
671                                 regs[j] = 0;
672 
673                 /* Byte 0 is level count, not a descriptor */
674                 for (j = 1 ; j < 16 ; j++)
675                         intel_tlb_lookup(desc[j]);
676         }
677         intel_tlb_flushall_shift_set(c);
678 }
679 
680 static const struct cpu_dev __cpuinitconst intel_cpu_dev = {
681         .c_vendor       = "Intel",
682         .c_ident        = { "GenuineIntel" },
683 #ifdef CONFIG_X86_32
684         .c_models = {
685                 { .vendor = X86_VENDOR_INTEL, .family = 4, .model_names =
686                   {
687                           [0] = "486 DX-25/33",
688                           [1] = "486 DX-50",
689                           [2] = "486 SX",
690                           [3] = "486 DX/2",
691                           [4] = "486 SL",
692                           [5] = "486 SX/2",
693                           [7] = "486 DX/2-WB",
694                           [8] = "486 DX/4",
695                           [9] = "486 DX/4-WB"
696                   }
697                 },
698                 { .vendor = X86_VENDOR_INTEL, .family = 5, .model_names =
699                   {
700                           [0] = "Pentium 60/66 A-step",
701                           [1] = "Pentium 60/66",
702                           [2] = "Pentium 75 - 200",
703                           [3] = "OverDrive PODP5V83",
704                           [4] = "Pentium MMX",
705                           [7] = "Mobile Pentium 75 - 200",
706                           [8] = "Mobile Pentium MMX"
707                   }
708                 },
709                 { .vendor = X86_VENDOR_INTEL, .family = 6, .model_names =
710                   {
711                           [0] = "Pentium Pro A-step",
712                           [1] = "Pentium Pro",
713                           [3] = "Pentium II (Klamath)",
714                           [4] = "Pentium II (Deschutes)",
715                           [5] = "Pentium II (Deschutes)",
716                           [6] = "Mobile Pentium II",
717                           [7] = "Pentium III (Katmai)",
718                           [8] = "Pentium III (Coppermine)",
719                           [10] = "Pentium III (Cascades)",
720                           [11] = "Pentium III (Tualatin)",
721                   }
722                 },
723                 { .vendor = X86_VENDOR_INTEL, .family = 15, .model_names =
724                   {
725                           [0] = "Pentium 4 (Unknown)",
726                           [1] = "Pentium 4 (Willamette)",
727                           [2] = "Pentium 4 (Northwood)",
728                           [4] = "Pentium 4 (Foster)",
729                           [5] = "Pentium 4 (Foster)",
730                   }
731                 },
732         },
733         .c_size_cache   = intel_size_cache,
734 #endif
735         .c_detect_tlb   = intel_detect_tlb,
736         .c_early_init   = early_init_intel,
737         .c_init         = init_intel,
738         .c_x86_vendor   = X86_VENDOR_INTEL,
739 };
740 
741 cpu_dev_register(intel_cpu_dev);
742 
743 

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