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Linux/arch/x86/kernel/cpu/mcheck/mce_amd.c

Version: ~ [ linux-5.4-rc3 ] ~ [ linux-5.3.6 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.79 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.149 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.196 ] ~ [ linux-4.8.17 ] ~ [ linux-4.7.10 ] ~ [ linux-4.6.7 ] ~ [ linux-4.5.7 ] ~ [ linux-4.4.196 ] ~ [ linux-4.3.6 ] ~ [ linux-4.2.8 ] ~ [ linux-4.1.52 ] ~ [ linux-4.0.9 ] ~ [ linux-3.19.8 ] ~ [ linux-3.18.140 ] ~ [ linux-3.17.8 ] ~ [ linux-3.16.75 ] ~ [ linux-3.15.10 ] ~ [ linux-3.14.79 ] ~ [ linux-3.13.11 ] ~ [ linux-3.12.74 ] ~ [ linux-3.11.10 ] ~ [ linux-3.10.108 ] ~ [ linux-3.9.11 ] ~ [ linux-3.8.13 ] ~ [ linux-3.7.10 ] ~ [ linux-3.6.11 ] ~ [ linux-3.5.7 ] ~ [ linux-3.4.113 ] ~ [ linux-3.3.8 ] ~ [ linux-3.2.102 ] ~ [ linux-3.1.10 ] ~ [ linux-3.0.101 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.5 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 /*
  2  *  (c) 2005-2016 Advanced Micro Devices, Inc.
  3  *  Your use of this code is subject to the terms and conditions of the
  4  *  GNU general public license version 2. See "COPYING" or
  5  *  http://www.gnu.org/licenses/gpl.html
  6  *
  7  *  Written by Jacob Shin - AMD, Inc.
  8  *  Maintained by: Borislav Petkov <bp@alien8.de>
  9  *
 10  *  All MC4_MISCi registers are shared between cores on a node.
 11  */
 12 #include <linux/interrupt.h>
 13 #include <linux/notifier.h>
 14 #include <linux/kobject.h>
 15 #include <linux/percpu.h>
 16 #include <linux/errno.h>
 17 #include <linux/sched.h>
 18 #include <linux/sysfs.h>
 19 #include <linux/slab.h>
 20 #include <linux/init.h>
 21 #include <linux/cpu.h>
 22 #include <linux/smp.h>
 23 #include <linux/string.h>
 24 
 25 #include <asm/amd_nb.h>
 26 #include <asm/apic.h>
 27 #include <asm/mce.h>
 28 #include <asm/msr.h>
 29 #include <asm/trace/irq_vectors.h>
 30 
 31 #define NR_BLOCKS         5
 32 #define THRESHOLD_MAX     0xFFF
 33 #define INT_TYPE_APIC     0x00020000
 34 #define MASK_VALID_HI     0x80000000
 35 #define MASK_CNTP_HI      0x40000000
 36 #define MASK_LOCKED_HI    0x20000000
 37 #define MASK_LVTOFF_HI    0x00F00000
 38 #define MASK_COUNT_EN_HI  0x00080000
 39 #define MASK_INT_TYPE_HI  0x00060000
 40 #define MASK_OVERFLOW_HI  0x00010000
 41 #define MASK_ERR_COUNT_HI 0x00000FFF
 42 #define MASK_BLKPTR_LO    0xFF000000
 43 #define MCG_XBLK_ADDR     0xC0000400
 44 
 45 /* Deferred error settings */
 46 #define MSR_CU_DEF_ERR          0xC0000410
 47 #define MASK_DEF_LVTOFF         0x000000F0
 48 #define MASK_DEF_INT_TYPE       0x00000006
 49 #define DEF_LVT_OFF             0x2
 50 #define DEF_INT_TYPE_APIC       0x2
 51 
 52 /* Scalable MCA: */
 53 
 54 /* Threshold LVT offset is at MSR0xC0000410[15:12] */
 55 #define SMCA_THR_LVT_OFF        0xF000
 56 
 57 static bool thresholding_en;
 58 
 59 static const char * const th_names[] = {
 60         "load_store",
 61         "insn_fetch",
 62         "combined_unit",
 63         "decode_unit",
 64         "northbridge",
 65         "execution_unit",
 66 };
 67 
 68 static const char * const smca_umc_block_names[] = {
 69         "dram_ecc",
 70         "misc_umc"
 71 };
 72 
 73 struct smca_bank_name {
 74         const char *name;       /* Short name for sysfs */
 75         const char *long_name;  /* Long name for pretty-printing */
 76 };
 77 
 78 static struct smca_bank_name smca_names[] = {
 79         [SMCA_LS]       = { "load_store",       "Load Store Unit" },
 80         [SMCA_IF]       = { "insn_fetch",       "Instruction Fetch Unit" },
 81         [SMCA_L2_CACHE] = { "l2_cache",         "L2 Cache" },
 82         [SMCA_DE]       = { "decode_unit",      "Decode Unit" },
 83         [SMCA_EX]       = { "execution_unit",   "Execution Unit" },
 84         [SMCA_FP]       = { "floating_point",   "Floating Point Unit" },
 85         [SMCA_L3_CACHE] = { "l3_cache",         "L3 Cache" },
 86         [SMCA_CS]       = { "coherent_slave",   "Coherent Slave" },
 87         [SMCA_PIE]      = { "pie",              "Power, Interrupts, etc." },
 88         [SMCA_UMC]      = { "umc",              "Unified Memory Controller" },
 89         [SMCA_PB]       = { "param_block",      "Parameter Block" },
 90         [SMCA_PSP]      = { "psp",              "Platform Security Processor" },
 91         [SMCA_SMU]      = { "smu",              "System Management Unit" },
 92 };
 93 
 94 const char *smca_get_name(enum smca_bank_types t)
 95 {
 96         if (t >= N_SMCA_BANK_TYPES)
 97                 return NULL;
 98 
 99         return smca_names[t].name;
100 }
101 
102 const char *smca_get_long_name(enum smca_bank_types t)
103 {
104         if (t >= N_SMCA_BANK_TYPES)
105                 return NULL;
106 
107         return smca_names[t].long_name;
108 }
109 EXPORT_SYMBOL_GPL(smca_get_long_name);
110 
111 static struct smca_hwid smca_hwid_mcatypes[] = {
112         /* { bank_type, hwid_mcatype, xec_bitmap } */
113 
114         /* ZN Core (HWID=0xB0) MCA types */
115         { SMCA_LS,       HWID_MCATYPE(0xB0, 0x0), 0x1FFFEF },
116         { SMCA_IF,       HWID_MCATYPE(0xB0, 0x1), 0x3FFF },
117         { SMCA_L2_CACHE, HWID_MCATYPE(0xB0, 0x2), 0xF },
118         { SMCA_DE,       HWID_MCATYPE(0xB0, 0x3), 0x1FF },
119         /* HWID 0xB0 MCATYPE 0x4 is Reserved */
120         { SMCA_EX,       HWID_MCATYPE(0xB0, 0x5), 0x7FF },
121         { SMCA_FP,       HWID_MCATYPE(0xB0, 0x6), 0x7F },
122         { SMCA_L3_CACHE, HWID_MCATYPE(0xB0, 0x7), 0xFF },
123 
124         /* Data Fabric MCA types */
125         { SMCA_CS,       HWID_MCATYPE(0x2E, 0x0), 0x1FF },
126         { SMCA_PIE,      HWID_MCATYPE(0x2E, 0x1), 0xF },
127 
128         /* Unified Memory Controller MCA type */
129         { SMCA_UMC,      HWID_MCATYPE(0x96, 0x0), 0x3F },
130 
131         /* Parameter Block MCA type */
132         { SMCA_PB,       HWID_MCATYPE(0x05, 0x0), 0x1 },
133 
134         /* Platform Security Processor MCA type */
135         { SMCA_PSP,      HWID_MCATYPE(0xFF, 0x0), 0x1 },
136 
137         /* System Management Unit MCA type */
138         { SMCA_SMU,      HWID_MCATYPE(0x01, 0x0), 0x1 },
139 };
140 
141 struct smca_bank smca_banks[MAX_NR_BANKS];
142 EXPORT_SYMBOL_GPL(smca_banks);
143 
144 /*
145  * In SMCA enabled processors, we can have multiple banks for a given IP type.
146  * So to define a unique name for each bank, we use a temp c-string to append
147  * the MCA_IPID[InstanceId] to type's name in get_name().
148  *
149  * InstanceId is 32 bits which is 8 characters. Make sure MAX_MCATYPE_NAME_LEN
150  * is greater than 8 plus 1 (for underscore) plus length of longest type name.
151  */
152 #define MAX_MCATYPE_NAME_LEN    30
153 static char buf_mcatype[MAX_MCATYPE_NAME_LEN];
154 
155 static DEFINE_PER_CPU(struct threshold_bank **, threshold_banks);
156 static DEFINE_PER_CPU(unsigned int, bank_map);  /* see which banks are on */
157 
158 static void amd_threshold_interrupt(void);
159 static void amd_deferred_error_interrupt(void);
160 
161 static void default_deferred_error_interrupt(void)
162 {
163         pr_err("Unexpected deferred interrupt at vector %x\n", DEFERRED_ERROR_VECTOR);
164 }
165 void (*deferred_error_int_vector)(void) = default_deferred_error_interrupt;
166 
167 static void get_smca_bank_info(unsigned int bank)
168 {
169         unsigned int i, hwid_mcatype, cpu = smp_processor_id();
170         struct smca_hwid *s_hwid;
171         u32 high, instance_id;
172 
173         /* Collect bank_info using CPU 0 for now. */
174         if (cpu)
175                 return;
176 
177         if (rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_IPID(bank), &instance_id, &high)) {
178                 pr_warn("Failed to read MCA_IPID for bank %d\n", bank);
179                 return;
180         }
181 
182         hwid_mcatype = HWID_MCATYPE(high & MCI_IPID_HWID,
183                                     (high & MCI_IPID_MCATYPE) >> 16);
184 
185         for (i = 0; i < ARRAY_SIZE(smca_hwid_mcatypes); i++) {
186                 s_hwid = &smca_hwid_mcatypes[i];
187                 if (hwid_mcatype == s_hwid->hwid_mcatype) {
188 
189                         WARN(smca_banks[bank].hwid,
190                              "Bank %s already initialized!\n",
191                              smca_get_name(s_hwid->bank_type));
192 
193                         smca_banks[bank].hwid = s_hwid;
194                         smca_banks[bank].id = instance_id;
195                         break;
196                 }
197         }
198 }
199 
200 struct thresh_restart {
201         struct threshold_block  *b;
202         int                     reset;
203         int                     set_lvt_off;
204         int                     lvt_off;
205         u16                     old_limit;
206 };
207 
208 static inline bool is_shared_bank(int bank)
209 {
210         /*
211          * Scalable MCA provides for only one core to have access to the MSRs of
212          * a shared bank.
213          */
214         if (mce_flags.smca)
215                 return false;
216 
217         /* Bank 4 is for northbridge reporting and is thus shared */
218         return (bank == 4);
219 }
220 
221 static const char *bank4_names(const struct threshold_block *b)
222 {
223         switch (b->address) {
224         /* MSR4_MISC0 */
225         case 0x00000413:
226                 return "dram";
227 
228         case 0xc0000408:
229                 return "ht_links";
230 
231         case 0xc0000409:
232                 return "l3_cache";
233 
234         default:
235                 WARN(1, "Funny MSR: 0x%08x\n", b->address);
236                 return "";
237         }
238 };
239 
240 
241 static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits)
242 {
243         /*
244          * bank 4 supports APIC LVT interrupts implicitly since forever.
245          */
246         if (bank == 4)
247                 return true;
248 
249         /*
250          * IntP: interrupt present; if this bit is set, the thresholding
251          * bank can generate APIC LVT interrupts
252          */
253         return msr_high_bits & BIT(28);
254 }
255 
256 static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi)
257 {
258         int msr = (hi & MASK_LVTOFF_HI) >> 20;
259 
260         if (apic < 0) {
261                 pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt "
262                        "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu,
263                        b->bank, b->block, b->address, hi, lo);
264                 return 0;
265         }
266 
267         if (apic != msr) {
268                 /*
269                  * On SMCA CPUs, LVT offset is programmed at a different MSR, and
270                  * the BIOS provides the value. The original field where LVT offset
271                  * was set is reserved. Return early here:
272                  */
273                 if (mce_flags.smca)
274                         return 0;
275 
276                 pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d "
277                        "for bank %d, block %d (MSR%08X=0x%x%08x)\n",
278                        b->cpu, apic, b->bank, b->block, b->address, hi, lo);
279                 return 0;
280         }
281 
282         return 1;
283 };
284 
285 /* Reprogram MCx_MISC MSR behind this threshold bank. */
286 static void threshold_restart_bank(void *_tr)
287 {
288         struct thresh_restart *tr = _tr;
289         u32 hi, lo;
290 
291         rdmsr(tr->b->address, lo, hi);
292 
293         if (tr->b->threshold_limit < (hi & THRESHOLD_MAX))
294                 tr->reset = 1;  /* limit cannot be lower than err count */
295 
296         if (tr->reset) {                /* reset err count and overflow bit */
297                 hi =
298                     (hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) |
299                     (THRESHOLD_MAX - tr->b->threshold_limit);
300         } else if (tr->old_limit) {     /* change limit w/o reset */
301                 int new_count = (hi & THRESHOLD_MAX) +
302                     (tr->old_limit - tr->b->threshold_limit);
303 
304                 hi = (hi & ~MASK_ERR_COUNT_HI) |
305                     (new_count & THRESHOLD_MAX);
306         }
307 
308         /* clear IntType */
309         hi &= ~MASK_INT_TYPE_HI;
310 
311         if (!tr->b->interrupt_capable)
312                 goto done;
313 
314         if (tr->set_lvt_off) {
315                 if (lvt_off_valid(tr->b, tr->lvt_off, lo, hi)) {
316                         /* set new lvt offset */
317                         hi &= ~MASK_LVTOFF_HI;
318                         hi |= tr->lvt_off << 20;
319                 }
320         }
321 
322         if (tr->b->interrupt_enable)
323                 hi |= INT_TYPE_APIC;
324 
325  done:
326 
327         hi |= MASK_COUNT_EN_HI;
328         wrmsr(tr->b->address, lo, hi);
329 }
330 
331 static void mce_threshold_block_init(struct threshold_block *b, int offset)
332 {
333         struct thresh_restart tr = {
334                 .b                      = b,
335                 .set_lvt_off            = 1,
336                 .lvt_off                = offset,
337         };
338 
339         b->threshold_limit              = THRESHOLD_MAX;
340         threshold_restart_bank(&tr);
341 };
342 
343 static int setup_APIC_mce_threshold(int reserved, int new)
344 {
345         if (reserved < 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR,
346                                               APIC_EILVT_MSG_FIX, 0))
347                 return new;
348 
349         return reserved;
350 }
351 
352 static int setup_APIC_deferred_error(int reserved, int new)
353 {
354         if (reserved < 0 && !setup_APIC_eilvt(new, DEFERRED_ERROR_VECTOR,
355                                               APIC_EILVT_MSG_FIX, 0))
356                 return new;
357 
358         return reserved;
359 }
360 
361 static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c)
362 {
363         u32 low = 0, high = 0;
364         int def_offset = -1, def_new;
365 
366         if (rdmsr_safe(MSR_CU_DEF_ERR, &low, &high))
367                 return;
368 
369         def_new = (low & MASK_DEF_LVTOFF) >> 4;
370         if (!(low & MASK_DEF_LVTOFF)) {
371                 pr_err(FW_BUG "Your BIOS is not setting up LVT offset 0x2 for deferred error IRQs correctly.\n");
372                 def_new = DEF_LVT_OFF;
373                 low = (low & ~MASK_DEF_LVTOFF) | (DEF_LVT_OFF << 4);
374         }
375 
376         def_offset = setup_APIC_deferred_error(def_offset, def_new);
377         if ((def_offset == def_new) &&
378             (deferred_error_int_vector != amd_deferred_error_interrupt))
379                 deferred_error_int_vector = amd_deferred_error_interrupt;
380 
381         low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC;
382         wrmsr(MSR_CU_DEF_ERR, low, high);
383 }
384 
385 static u32 get_block_address(unsigned int cpu, u32 current_addr, u32 low, u32 high,
386                              unsigned int bank, unsigned int block)
387 {
388         u32 addr = 0, offset = 0;
389 
390         if (mce_flags.smca) {
391                 if (!block) {
392                         addr = MSR_AMD64_SMCA_MCx_MISC(bank);
393                 } else {
394                         /*
395                          * For SMCA enabled processors, BLKPTR field of the
396                          * first MISC register (MCx_MISC0) indicates presence of
397                          * additional MISC register set (MISC1-4).
398                          */
399                         u32 low, high;
400 
401                         if (rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high))
402                                 return addr;
403 
404                         if (!(low & MCI_CONFIG_MCAX))
405                                 return addr;
406 
407                         if (!rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high) &&
408                             (low & MASK_BLKPTR_LO))
409                                 addr = MSR_AMD64_SMCA_MCx_MISCy(bank, block - 1);
410                 }
411                 return addr;
412         }
413 
414         /* Fall back to method we used for older processors: */
415         switch (block) {
416         case 0:
417                 addr = msr_ops.misc(bank);
418                 break;
419         case 1:
420                 offset = ((low & MASK_BLKPTR_LO) >> 21);
421                 if (offset)
422                         addr = MCG_XBLK_ADDR + offset;
423                 break;
424         default:
425                 addr = ++current_addr;
426         }
427         return addr;
428 }
429 
430 static int
431 prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr,
432                         int offset, u32 misc_high)
433 {
434         unsigned int cpu = smp_processor_id();
435         u32 smca_low, smca_high, smca_addr;
436         struct threshold_block b;
437         int new;
438 
439         if (!block)
440                 per_cpu(bank_map, cpu) |= (1 << bank);
441 
442         memset(&b, 0, sizeof(b));
443         b.cpu                   = cpu;
444         b.bank                  = bank;
445         b.block                 = block;
446         b.address               = addr;
447         b.interrupt_capable     = lvt_interrupt_supported(bank, misc_high);
448 
449         if (!b.interrupt_capable)
450                 goto done;
451 
452         b.interrupt_enable = 1;
453 
454         if (!mce_flags.smca) {
455                 new = (misc_high & MASK_LVTOFF_HI) >> 20;
456                 goto set_offset;
457         }
458 
459         smca_addr = MSR_AMD64_SMCA_MCx_CONFIG(bank);
460 
461         if (!rdmsr_safe(smca_addr, &smca_low, &smca_high)) {
462                 /*
463                  * OS is required to set the MCAX bit to acknowledge that it is
464                  * now using the new MSR ranges and new registers under each
465                  * bank. It also means that the OS will configure deferred
466                  * errors in the new MCx_CONFIG register. If the bit is not set,
467                  * uncorrectable errors will cause a system panic.
468                  *
469                  * MCA_CONFIG[MCAX] is bit 32 (0 in the high portion of the MSR.)
470                  */
471                 smca_high |= BIT(0);
472 
473                 /*
474                  * SMCA logs Deferred Error information in MCA_DE{STAT,ADDR}
475                  * registers with the option of additionally logging to
476                  * MCA_{STATUS,ADDR} if MCA_CONFIG[LogDeferredInMcaStat] is set.
477                  *
478                  * This bit is usually set by BIOS to retain the old behavior
479                  * for OSes that don't use the new registers. Linux supports the
480                  * new registers so let's disable that additional logging here.
481                  *
482                  * MCA_CONFIG[LogDeferredInMcaStat] is bit 34 (bit 2 in the high
483                  * portion of the MSR).
484                  */
485                 smca_high &= ~BIT(2);
486 
487                 /*
488                  * SMCA sets the Deferred Error Interrupt type per bank.
489                  *
490                  * MCA_CONFIG[DeferredIntTypeSupported] is bit 5, and tells us
491                  * if the DeferredIntType bit field is available.
492                  *
493                  * MCA_CONFIG[DeferredIntType] is bits [38:37] ([6:5] in the
494                  * high portion of the MSR). OS should set this to 0x1 to enable
495                  * APIC based interrupt. First, check that no interrupt has been
496                  * set.
497                  */
498                 if ((smca_low & BIT(5)) && !((smca_high >> 5) & 0x3))
499                         smca_high |= BIT(5);
500 
501                 wrmsr(smca_addr, smca_low, smca_high);
502         }
503 
504         /* Gather LVT offset for thresholding: */
505         if (rdmsr_safe(MSR_CU_DEF_ERR, &smca_low, &smca_high))
506                 goto out;
507 
508         new = (smca_low & SMCA_THR_LVT_OFF) >> 12;
509 
510 set_offset:
511         offset = setup_APIC_mce_threshold(offset, new);
512 
513         if ((offset == new) && (mce_threshold_vector != amd_threshold_interrupt))
514                 mce_threshold_vector = amd_threshold_interrupt;
515 
516 done:
517         mce_threshold_block_init(&b, offset);
518 
519 out:
520         return offset;
521 }
522 
523 /* cpu init entry point, called from mce.c with preempt off */
524 void mce_amd_feature_init(struct cpuinfo_x86 *c)
525 {
526         u32 low = 0, high = 0, address = 0;
527         unsigned int bank, block, cpu = smp_processor_id();
528         int offset = -1;
529 
530         for (bank = 0; bank < mca_cfg.banks; ++bank) {
531                 if (mce_flags.smca)
532                         get_smca_bank_info(bank);
533 
534                 for (block = 0; block < NR_BLOCKS; ++block) {
535                         address = get_block_address(cpu, address, low, high, bank, block);
536                         if (!address)
537                                 break;
538 
539                         if (rdmsr_safe(address, &low, &high))
540                                 break;
541 
542                         if (!(high & MASK_VALID_HI))
543                                 continue;
544 
545                         if (!(high & MASK_CNTP_HI)  ||
546                              (high & MASK_LOCKED_HI))
547                                 continue;
548 
549                         offset = prepare_threshold_block(bank, block, address, offset, high);
550                 }
551         }
552 
553         if (mce_flags.succor)
554                 deferred_error_interrupt_enable(c);
555 }
556 
557 int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr)
558 {
559         u64 dram_base_addr, dram_limit_addr, dram_hole_base;
560         /* We start from the normalized address */
561         u64 ret_addr = norm_addr;
562 
563         u32 tmp;
564 
565         u8 die_id_shift, die_id_mask, socket_id_shift, socket_id_mask;
566         u8 intlv_num_dies, intlv_num_chan, intlv_num_sockets;
567         u8 intlv_addr_sel, intlv_addr_bit;
568         u8 num_intlv_bits, hashed_bit;
569         u8 lgcy_mmio_hole_en, base = 0;
570         u8 cs_mask, cs_id = 0;
571         bool hash_enabled = false;
572 
573         /* Read D18F0x1B4 (DramOffset), check if base 1 is used. */
574         if (amd_df_indirect_read(nid, 0, 0x1B4, umc, &tmp))
575                 goto out_err;
576 
577         /* Remove HiAddrOffset from normalized address, if enabled: */
578         if (tmp & BIT(0)) {
579                 u64 hi_addr_offset = (tmp & GENMASK_ULL(31, 20)) << 8;
580 
581                 if (norm_addr >= hi_addr_offset) {
582                         ret_addr -= hi_addr_offset;
583                         base = 1;
584                 }
585         }
586 
587         /* Read D18F0x110 (DramBaseAddress). */
588         if (amd_df_indirect_read(nid, 0, 0x110 + (8 * base), umc, &tmp))
589                 goto out_err;
590 
591         /* Check if address range is valid. */
592         if (!(tmp & BIT(0))) {
593                 pr_err("%s: Invalid DramBaseAddress range: 0x%x.\n",
594                         __func__, tmp);
595                 goto out_err;
596         }
597 
598         lgcy_mmio_hole_en = tmp & BIT(1);
599         intlv_num_chan    = (tmp >> 4) & 0xF;
600         intlv_addr_sel    = (tmp >> 8) & 0x7;
601         dram_base_addr    = (tmp & GENMASK_ULL(31, 12)) << 16;
602 
603         /* {0, 1, 2, 3} map to address bits {8, 9, 10, 11} respectively */
604         if (intlv_addr_sel > 3) {
605                 pr_err("%s: Invalid interleave address select %d.\n",
606                         __func__, intlv_addr_sel);
607                 goto out_err;
608         }
609 
610         /* Read D18F0x114 (DramLimitAddress). */
611         if (amd_df_indirect_read(nid, 0, 0x114 + (8 * base), umc, &tmp))
612                 goto out_err;
613 
614         intlv_num_sockets = (tmp >> 8) & 0x1;
615         intlv_num_dies    = (tmp >> 10) & 0x3;
616         dram_limit_addr   = ((tmp & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0);
617 
618         intlv_addr_bit = intlv_addr_sel + 8;
619 
620         /* Re-use intlv_num_chan by setting it equal to log2(#channels) */
621         switch (intlv_num_chan) {
622         case 0: intlv_num_chan = 0; break;
623         case 1: intlv_num_chan = 1; break;
624         case 3: intlv_num_chan = 2; break;
625         case 5: intlv_num_chan = 3; break;
626         case 7: intlv_num_chan = 4; break;
627 
628         case 8: intlv_num_chan = 1;
629                 hash_enabled = true;
630                 break;
631         default:
632                 pr_err("%s: Invalid number of interleaved channels %d.\n",
633                         __func__, intlv_num_chan);
634                 goto out_err;
635         }
636 
637         num_intlv_bits = intlv_num_chan;
638 
639         if (intlv_num_dies > 2) {
640                 pr_err("%s: Invalid number of interleaved nodes/dies %d.\n",
641                         __func__, intlv_num_dies);
642                 goto out_err;
643         }
644 
645         num_intlv_bits += intlv_num_dies;
646 
647         /* Add a bit if sockets are interleaved. */
648         num_intlv_bits += intlv_num_sockets;
649 
650         /* Assert num_intlv_bits <= 4 */
651         if (num_intlv_bits > 4) {
652                 pr_err("%s: Invalid interleave bits %d.\n",
653                         __func__, num_intlv_bits);
654                 goto out_err;
655         }
656 
657         if (num_intlv_bits > 0) {
658                 u64 temp_addr_x, temp_addr_i, temp_addr_y;
659                 u8 die_id_bit, sock_id_bit, cs_fabric_id;
660 
661                 /*
662                  * Read FabricBlockInstanceInformation3_CS[BlockFabricID].
663                  * This is the fabric id for this coherent slave. Use
664                  * umc/channel# as instance id of the coherent slave
665                  * for FICAA.
666                  */
667                 if (amd_df_indirect_read(nid, 0, 0x50, umc, &tmp))
668                         goto out_err;
669 
670                 cs_fabric_id = (tmp >> 8) & 0xFF;
671                 die_id_bit   = 0;
672 
673                 /* If interleaved over more than 1 channel: */
674                 if (intlv_num_chan) {
675                         die_id_bit = intlv_num_chan;
676                         cs_mask    = (1 << die_id_bit) - 1;
677                         cs_id      = cs_fabric_id & cs_mask;
678                 }
679 
680                 sock_id_bit = die_id_bit;
681 
682                 /* Read D18F1x208 (SystemFabricIdMask). */
683                 if (intlv_num_dies || intlv_num_sockets)
684                         if (amd_df_indirect_read(nid, 1, 0x208, umc, &tmp))
685                                 goto out_err;
686 
687                 /* If interleaved over more than 1 die. */
688                 if (intlv_num_dies) {
689                         sock_id_bit  = die_id_bit + intlv_num_dies;
690                         die_id_shift = (tmp >> 24) & 0xF;
691                         die_id_mask  = (tmp >> 8) & 0xFF;
692 
693                         cs_id |= ((cs_fabric_id & die_id_mask) >> die_id_shift) << die_id_bit;
694                 }
695 
696                 /* If interleaved over more than 1 socket. */
697                 if (intlv_num_sockets) {
698                         socket_id_shift = (tmp >> 28) & 0xF;
699                         socket_id_mask  = (tmp >> 16) & 0xFF;
700 
701                         cs_id |= ((cs_fabric_id & socket_id_mask) >> socket_id_shift) << sock_id_bit;
702                 }
703 
704                 /*
705                  * The pre-interleaved address consists of XXXXXXIIIYYYYY
706                  * where III is the ID for this CS, and XXXXXXYYYYY are the
707                  * address bits from the post-interleaved address.
708                  * "num_intlv_bits" has been calculated to tell us how many "I"
709                  * bits there are. "intlv_addr_bit" tells us how many "Y" bits
710                  * there are (where "I" starts).
711                  */
712                 temp_addr_y = ret_addr & GENMASK_ULL(intlv_addr_bit-1, 0);
713                 temp_addr_i = (cs_id << intlv_addr_bit);
714                 temp_addr_x = (ret_addr & GENMASK_ULL(63, intlv_addr_bit)) << num_intlv_bits;
715                 ret_addr    = temp_addr_x | temp_addr_i | temp_addr_y;
716         }
717 
718         /* Add dram base address */
719         ret_addr += dram_base_addr;
720 
721         /* If legacy MMIO hole enabled */
722         if (lgcy_mmio_hole_en) {
723                 if (amd_df_indirect_read(nid, 0, 0x104, umc, &tmp))
724                         goto out_err;
725 
726                 dram_hole_base = tmp & GENMASK(31, 24);
727                 if (ret_addr >= dram_hole_base)
728                         ret_addr += (BIT_ULL(32) - dram_hole_base);
729         }
730 
731         if (hash_enabled) {
732                 /* Save some parentheses and grab ls-bit at the end. */
733                 hashed_bit =    (ret_addr >> 12) ^
734                                 (ret_addr >> 18) ^
735                                 (ret_addr >> 21) ^
736                                 (ret_addr >> 30) ^
737                                 cs_id;
738 
739                 hashed_bit &= BIT(0);
740 
741                 if (hashed_bit != ((ret_addr >> intlv_addr_bit) & BIT(0)))
742                         ret_addr ^= BIT(intlv_addr_bit);
743         }
744 
745         /* Is calculated system address is above DRAM limit address? */
746         if (ret_addr > dram_limit_addr)
747                 goto out_err;
748 
749         *sys_addr = ret_addr;
750         return 0;
751 
752 out_err:
753         return -EINVAL;
754 }
755 EXPORT_SYMBOL_GPL(umc_normaddr_to_sysaddr);
756 
757 static void
758 __log_error(unsigned int bank, bool deferred_err, bool threshold_err, u64 misc)
759 {
760         u32 msr_status = msr_ops.status(bank);
761         u32 msr_addr = msr_ops.addr(bank);
762         struct mce m;
763         u64 status;
764 
765         WARN_ON_ONCE(deferred_err && threshold_err);
766 
767         if (deferred_err && mce_flags.smca) {
768                 msr_status = MSR_AMD64_SMCA_MCx_DESTAT(bank);
769                 msr_addr = MSR_AMD64_SMCA_MCx_DEADDR(bank);
770         }
771 
772         rdmsrl(msr_status, status);
773 
774         if (!(status & MCI_STATUS_VAL))
775                 return;
776 
777         mce_setup(&m);
778 
779         m.status = status;
780         m.bank = bank;
781 
782         if (threshold_err)
783                 m.misc = misc;
784 
785         if (m.status & MCI_STATUS_ADDRV) {
786                 rdmsrl(msr_addr, m.addr);
787 
788                 /*
789                  * Extract [55:<lsb>] where lsb is the least significant
790                  * *valid* bit of the address bits.
791                  */
792                 if (mce_flags.smca) {
793                         u8 lsb = (m.addr >> 56) & 0x3f;
794 
795                         m.addr &= GENMASK_ULL(55, lsb);
796                 }
797         }
798 
799         if (mce_flags.smca) {
800                 rdmsrl(MSR_AMD64_SMCA_MCx_IPID(bank), m.ipid);
801 
802                 if (m.status & MCI_STATUS_SYNDV)
803                         rdmsrl(MSR_AMD64_SMCA_MCx_SYND(bank), m.synd);
804         }
805 
806         mce_log(&m);
807 
808         wrmsrl(msr_status, 0);
809 }
810 
811 static inline void __smp_deferred_error_interrupt(void)
812 {
813         inc_irq_stat(irq_deferred_error_count);
814         deferred_error_int_vector();
815 }
816 
817 asmlinkage __visible void smp_deferred_error_interrupt(void)
818 {
819         entering_irq();
820         __smp_deferred_error_interrupt();
821         exiting_ack_irq();
822 }
823 
824 asmlinkage __visible void smp_trace_deferred_error_interrupt(void)
825 {
826         entering_irq();
827         trace_deferred_error_apic_entry(DEFERRED_ERROR_VECTOR);
828         __smp_deferred_error_interrupt();
829         trace_deferred_error_apic_exit(DEFERRED_ERROR_VECTOR);
830         exiting_ack_irq();
831 }
832 
833 /* APIC interrupt handler for deferred errors */
834 static void amd_deferred_error_interrupt(void)
835 {
836         unsigned int bank;
837         u32 msr_status;
838         u64 status;
839 
840         for (bank = 0; bank < mca_cfg.banks; ++bank) {
841                 msr_status = (mce_flags.smca) ? MSR_AMD64_SMCA_MCx_DESTAT(bank)
842                                               : msr_ops.status(bank);
843 
844                 rdmsrl(msr_status, status);
845 
846                 if (!(status & MCI_STATUS_VAL) ||
847                     !(status & MCI_STATUS_DEFERRED))
848                         continue;
849 
850                 __log_error(bank, true, false, 0);
851                 break;
852         }
853 }
854 
855 /*
856  * APIC Interrupt Handler
857  */
858 
859 /*
860  * threshold interrupt handler will service THRESHOLD_APIC_VECTOR.
861  * the interrupt goes off when error_count reaches threshold_limit.
862  * the handler will simply log mcelog w/ software defined bank number.
863  */
864 
865 static void amd_threshold_interrupt(void)
866 {
867         u32 low = 0, high = 0, address = 0;
868         unsigned int bank, block, cpu = smp_processor_id();
869         struct thresh_restart tr;
870 
871         /* assume first bank caused it */
872         for (bank = 0; bank < mca_cfg.banks; ++bank) {
873                 if (!(per_cpu(bank_map, cpu) & (1 << bank)))
874                         continue;
875                 for (block = 0; block < NR_BLOCKS; ++block) {
876                         address = get_block_address(cpu, address, low, high, bank, block);
877                         if (!address)
878                                 break;
879 
880                         if (rdmsr_safe(address, &low, &high))
881                                 break;
882 
883                         if (!(high & MASK_VALID_HI)) {
884                                 if (block)
885                                         continue;
886                                 else
887                                         break;
888                         }
889 
890                         if (!(high & MASK_CNTP_HI)  ||
891                              (high & MASK_LOCKED_HI))
892                                 continue;
893 
894                         /*
895                          * Log the machine check that caused the threshold
896                          * event.
897                          */
898                         if (high & MASK_OVERFLOW_HI)
899                                 goto log;
900                 }
901         }
902         return;
903 
904 log:
905         __log_error(bank, false, true, ((u64)high << 32) | low);
906 
907         /* Reset threshold block after logging error. */
908         memset(&tr, 0, sizeof(tr));
909         tr.b = &per_cpu(threshold_banks, cpu)[bank]->blocks[block];
910         threshold_restart_bank(&tr);
911 }
912 
913 /*
914  * Sysfs Interface
915  */
916 
917 struct threshold_attr {
918         struct attribute attr;
919         ssize_t (*show) (struct threshold_block *, char *);
920         ssize_t (*store) (struct threshold_block *, const char *, size_t count);
921 };
922 
923 #define SHOW_FIELDS(name)                                               \
924 static ssize_t show_ ## name(struct threshold_block *b, char *buf)      \
925 {                                                                       \
926         return sprintf(buf, "%lu\n", (unsigned long) b->name);          \
927 }
928 SHOW_FIELDS(interrupt_enable)
929 SHOW_FIELDS(threshold_limit)
930 
931 static ssize_t
932 store_interrupt_enable(struct threshold_block *b, const char *buf, size_t size)
933 {
934         struct thresh_restart tr;
935         unsigned long new;
936 
937         if (!b->interrupt_capable)
938                 return -EINVAL;
939 
940         if (kstrtoul(buf, 0, &new) < 0)
941                 return -EINVAL;
942 
943         b->interrupt_enable = !!new;
944 
945         memset(&tr, 0, sizeof(tr));
946         tr.b            = b;
947 
948         smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1);
949 
950         return size;
951 }
952 
953 static ssize_t
954 store_threshold_limit(struct threshold_block *b, const char *buf, size_t size)
955 {
956         struct thresh_restart tr;
957         unsigned long new;
958 
959         if (kstrtoul(buf, 0, &new) < 0)
960                 return -EINVAL;
961 
962         if (new > THRESHOLD_MAX)
963                 new = THRESHOLD_MAX;
964         if (new < 1)
965                 new = 1;
966 
967         memset(&tr, 0, sizeof(tr));
968         tr.old_limit = b->threshold_limit;
969         b->threshold_limit = new;
970         tr.b = b;
971 
972         smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1);
973 
974         return size;
975 }
976 
977 static ssize_t show_error_count(struct threshold_block *b, char *buf)
978 {
979         u32 lo, hi;
980 
981         rdmsr_on_cpu(b->cpu, b->address, &lo, &hi);
982 
983         return sprintf(buf, "%u\n", ((hi & THRESHOLD_MAX) -
984                                      (THRESHOLD_MAX - b->threshold_limit)));
985 }
986 
987 static struct threshold_attr error_count = {
988         .attr = {.name = __stringify(error_count), .mode = 0444 },
989         .show = show_error_count,
990 };
991 
992 #define RW_ATTR(val)                                                    \
993 static struct threshold_attr val = {                                    \
994         .attr   = {.name = __stringify(val), .mode = 0644 },            \
995         .show   = show_## val,                                          \
996         .store  = store_## val,                                         \
997 };
998 
999 RW_ATTR(interrupt_enable);
1000 RW_ATTR(threshold_limit);
1001 
1002 static struct attribute *default_attrs[] = {
1003         &threshold_limit.attr,
1004         &error_count.attr,
1005         NULL,   /* possibly interrupt_enable if supported, see below */
1006         NULL,
1007 };
1008 
1009 #define to_block(k)     container_of(k, struct threshold_block, kobj)
1010 #define to_attr(a)      container_of(a, struct threshold_attr, attr)
1011 
1012 static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf)
1013 {
1014         struct threshold_block *b = to_block(kobj);
1015         struct threshold_attr *a = to_attr(attr);
1016         ssize_t ret;
1017 
1018         ret = a->show ? a->show(b, buf) : -EIO;
1019 
1020         return ret;
1021 }
1022 
1023 static ssize_t store(struct kobject *kobj, struct attribute *attr,
1024                      const char *buf, size_t count)
1025 {
1026         struct threshold_block *b = to_block(kobj);
1027         struct threshold_attr *a = to_attr(attr);
1028         ssize_t ret;
1029 
1030         ret = a->store ? a->store(b, buf, count) : -EIO;
1031 
1032         return ret;
1033 }
1034 
1035 static const struct sysfs_ops threshold_ops = {
1036         .show                   = show,
1037         .store                  = store,
1038 };
1039 
1040 static struct kobj_type threshold_ktype = {
1041         .sysfs_ops              = &threshold_ops,
1042         .default_attrs          = default_attrs,
1043 };
1044 
1045 static const char *get_name(unsigned int bank, struct threshold_block *b)
1046 {
1047         unsigned int bank_type;
1048 
1049         if (!mce_flags.smca) {
1050                 if (b && bank == 4)
1051                         return bank4_names(b);
1052 
1053                 return th_names[bank];
1054         }
1055 
1056         if (!smca_banks[bank].hwid)
1057                 return NULL;
1058 
1059         bank_type = smca_banks[bank].hwid->bank_type;
1060 
1061         if (b && bank_type == SMCA_UMC) {
1062                 if (b->block < ARRAY_SIZE(smca_umc_block_names))
1063                         return smca_umc_block_names[b->block];
1064                 return NULL;
1065         }
1066 
1067         snprintf(buf_mcatype, MAX_MCATYPE_NAME_LEN,
1068                  "%s_%x", smca_get_name(bank_type),
1069                           smca_banks[bank].id);
1070         return buf_mcatype;
1071 }
1072 
1073 static int allocate_threshold_blocks(unsigned int cpu, unsigned int bank,
1074                                      unsigned int block, u32 address)
1075 {
1076         struct threshold_block *b = NULL;
1077         u32 low, high;
1078         int err;
1079 
1080         if ((bank >= mca_cfg.banks) || (block >= NR_BLOCKS))
1081                 return 0;
1082 
1083         if (rdmsr_safe_on_cpu(cpu, address, &low, &high))
1084                 return 0;
1085 
1086         if (!(high & MASK_VALID_HI)) {
1087                 if (block)
1088                         goto recurse;
1089                 else
1090                         return 0;
1091         }
1092 
1093         if (!(high & MASK_CNTP_HI)  ||
1094              (high & MASK_LOCKED_HI))
1095                 goto recurse;
1096 
1097         b = kzalloc(sizeof(struct threshold_block), GFP_KERNEL);
1098         if (!b)
1099                 return -ENOMEM;
1100 
1101         b->block                = block;
1102         b->bank                 = bank;
1103         b->cpu                  = cpu;
1104         b->address              = address;
1105         b->interrupt_enable     = 0;
1106         b->interrupt_capable    = lvt_interrupt_supported(bank, high);
1107         b->threshold_limit      = THRESHOLD_MAX;
1108 
1109         if (b->interrupt_capable) {
1110                 threshold_ktype.default_attrs[2] = &interrupt_enable.attr;
1111                 b->interrupt_enable = 1;
1112         } else {
1113                 threshold_ktype.default_attrs[2] = NULL;
1114         }
1115 
1116         INIT_LIST_HEAD(&b->miscj);
1117 
1118         if (per_cpu(threshold_banks, cpu)[bank]->blocks) {
1119                 list_add(&b->miscj,
1120                          &per_cpu(threshold_banks, cpu)[bank]->blocks->miscj);
1121         } else {
1122                 per_cpu(threshold_banks, cpu)[bank]->blocks = b;
1123         }
1124 
1125         err = kobject_init_and_add(&b->kobj, &threshold_ktype,
1126                                    per_cpu(threshold_banks, cpu)[bank]->kobj,
1127                                    get_name(bank, b));
1128         if (err)
1129                 goto out_free;
1130 recurse:
1131         address = get_block_address(cpu, address, low, high, bank, ++block);
1132         if (!address)
1133                 return 0;
1134 
1135         err = allocate_threshold_blocks(cpu, bank, block, address);
1136         if (err)
1137                 goto out_free;
1138 
1139         if (b)
1140                 kobject_uevent(&b->kobj, KOBJ_ADD);
1141 
1142         return err;
1143 
1144 out_free:
1145         if (b) {
1146                 kobject_put(&b->kobj);
1147                 list_del(&b->miscj);
1148                 kfree(b);
1149         }
1150         return err;
1151 }
1152 
1153 static int __threshold_add_blocks(struct threshold_bank *b)
1154 {
1155         struct list_head *head = &b->blocks->miscj;
1156         struct threshold_block *pos = NULL;
1157         struct threshold_block *tmp = NULL;
1158         int err = 0;
1159 
1160         err = kobject_add(&b->blocks->kobj, b->kobj, b->blocks->kobj.name);
1161         if (err)
1162                 return err;
1163 
1164         list_for_each_entry_safe(pos, tmp, head, miscj) {
1165 
1166                 err = kobject_add(&pos->kobj, b->kobj, pos->kobj.name);
1167                 if (err) {
1168                         list_for_each_entry_safe_reverse(pos, tmp, head, miscj)
1169                                 kobject_del(&pos->kobj);
1170 
1171                         return err;
1172                 }
1173         }
1174         return err;
1175 }
1176 
1177 static int threshold_create_bank(unsigned int cpu, unsigned int bank)
1178 {
1179         struct device *dev = per_cpu(mce_device, cpu);
1180         struct amd_northbridge *nb = NULL;
1181         struct threshold_bank *b = NULL;
1182         const char *name = get_name(bank, NULL);
1183         int err = 0;
1184 
1185         if (!dev)
1186                 return -ENODEV;
1187 
1188         if (is_shared_bank(bank)) {
1189                 nb = node_to_amd_nb(amd_get_nb_id(cpu));
1190 
1191                 /* threshold descriptor already initialized on this node? */
1192                 if (nb && nb->bank4) {
1193                         /* yes, use it */
1194                         b = nb->bank4;
1195                         err = kobject_add(b->kobj, &dev->kobj, name);
1196                         if (err)
1197                                 goto out;
1198 
1199                         per_cpu(threshold_banks, cpu)[bank] = b;
1200                         atomic_inc(&b->cpus);
1201 
1202                         err = __threshold_add_blocks(b);
1203 
1204                         goto out;
1205                 }
1206         }
1207 
1208         b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL);
1209         if (!b) {
1210                 err = -ENOMEM;
1211                 goto out;
1212         }
1213 
1214         b->kobj = kobject_create_and_add(name, &dev->kobj);
1215         if (!b->kobj) {
1216                 err = -EINVAL;
1217                 goto out_free;
1218         }
1219 
1220         per_cpu(threshold_banks, cpu)[bank] = b;
1221 
1222         if (is_shared_bank(bank)) {
1223                 atomic_set(&b->cpus, 1);
1224 
1225                 /* nb is already initialized, see above */
1226                 if (nb) {
1227                         WARN_ON(nb->bank4);
1228                         nb->bank4 = b;
1229                 }
1230         }
1231 
1232         err = allocate_threshold_blocks(cpu, bank, 0, msr_ops.misc(bank));
1233         if (!err)
1234                 goto out;
1235 
1236  out_free:
1237         kfree(b);
1238 
1239  out:
1240         return err;
1241 }
1242 
1243 static void deallocate_threshold_block(unsigned int cpu,
1244                                                  unsigned int bank)
1245 {
1246         struct threshold_block *pos = NULL;
1247         struct threshold_block *tmp = NULL;
1248         struct threshold_bank *head = per_cpu(threshold_banks, cpu)[bank];
1249 
1250         if (!head)
1251                 return;
1252 
1253         list_for_each_entry_safe(pos, tmp, &head->blocks->miscj, miscj) {
1254                 kobject_put(&pos->kobj);
1255                 list_del(&pos->miscj);
1256                 kfree(pos);
1257         }
1258 
1259         kfree(per_cpu(threshold_banks, cpu)[bank]->blocks);
1260         per_cpu(threshold_banks, cpu)[bank]->blocks = NULL;
1261 }
1262 
1263 static void __threshold_remove_blocks(struct threshold_bank *b)
1264 {
1265         struct threshold_block *pos = NULL;
1266         struct threshold_block *tmp = NULL;
1267 
1268         kobject_del(b->kobj);
1269 
1270         list_for_each_entry_safe(pos, tmp, &b->blocks->miscj, miscj)
1271                 kobject_del(&pos->kobj);
1272 }
1273 
1274 static void threshold_remove_bank(unsigned int cpu, int bank)
1275 {
1276         struct amd_northbridge *nb;
1277         struct threshold_bank *b;
1278 
1279         b = per_cpu(threshold_banks, cpu)[bank];
1280         if (!b)
1281                 return;
1282 
1283         if (!b->blocks)
1284                 goto free_out;
1285 
1286         if (is_shared_bank(bank)) {
1287                 if (!atomic_dec_and_test(&b->cpus)) {
1288                         __threshold_remove_blocks(b);
1289                         per_cpu(threshold_banks, cpu)[bank] = NULL;
1290                         return;
1291                 } else {
1292                         /*
1293                          * the last CPU on this node using the shared bank is
1294                          * going away, remove that bank now.
1295                          */
1296                         nb = node_to_amd_nb(amd_get_nb_id(cpu));
1297                         nb->bank4 = NULL;
1298                 }
1299         }
1300 
1301         deallocate_threshold_block(cpu, bank);
1302 
1303 free_out:
1304         kobject_del(b->kobj);
1305         kobject_put(b->kobj);
1306         kfree(b);
1307         per_cpu(threshold_banks, cpu)[bank] = NULL;
1308 }
1309 
1310 int mce_threshold_remove_device(unsigned int cpu)
1311 {
1312         unsigned int bank;
1313 
1314         if (!thresholding_en)
1315                 return 0;
1316 
1317         for (bank = 0; bank < mca_cfg.banks; ++bank) {
1318                 if (!(per_cpu(bank_map, cpu) & (1 << bank)))
1319                         continue;
1320                 threshold_remove_bank(cpu, bank);
1321         }
1322         kfree(per_cpu(threshold_banks, cpu));
1323         per_cpu(threshold_banks, cpu) = NULL;
1324         return 0;
1325 }
1326 
1327 /* create dir/files for all valid threshold banks */
1328 int mce_threshold_create_device(unsigned int cpu)
1329 {
1330         unsigned int bank;
1331         struct threshold_bank **bp;
1332         int err = 0;
1333 
1334         if (!thresholding_en)
1335                 return 0;
1336 
1337         bp = per_cpu(threshold_banks, cpu);
1338         if (bp)
1339                 return 0;
1340 
1341         bp = kzalloc(sizeof(struct threshold_bank *) * mca_cfg.banks,
1342                      GFP_KERNEL);
1343         if (!bp)
1344                 return -ENOMEM;
1345 
1346         per_cpu(threshold_banks, cpu) = bp;
1347 
1348         for (bank = 0; bank < mca_cfg.banks; ++bank) {
1349                 if (!(per_cpu(bank_map, cpu) & (1 << bank)))
1350                         continue;
1351                 err = threshold_create_bank(cpu, bank);
1352                 if (err)
1353                         goto err;
1354         }
1355         return err;
1356 err:
1357         mce_threshold_remove_device(cpu);
1358         return err;
1359 }
1360 
1361 static __init int threshold_init_device(void)
1362 {
1363         unsigned lcpu = 0;
1364 
1365         if (mce_threshold_vector == amd_threshold_interrupt)
1366                 thresholding_en = true;
1367 
1368         /* to hit CPUs online before the notifier is up */
1369         for_each_online_cpu(lcpu) {
1370                 int err = mce_threshold_create_device(lcpu);
1371 
1372                 if (err)
1373                         return err;
1374         }
1375 
1376         return 0;
1377 }
1378 /*
1379  * there are 3 funcs which need to be _initcalled in a logic sequence:
1380  * 1. xen_late_init_mcelog
1381  * 2. mcheck_init_device
1382  * 3. threshold_init_device
1383  *
1384  * xen_late_init_mcelog must register xen_mce_chrdev_device before
1385  * native mce_chrdev_device registration if running under xen platform;
1386  *
1387  * mcheck_init_device should be inited before threshold_init_device to
1388  * initialize mce_device, otherwise a NULL ptr dereference will cause panic.
1389  *
1390  * so we use following _initcalls
1391  * 1. device_initcall(xen_late_init_mcelog);
1392  * 2. device_initcall_sync(mcheck_init_device);
1393  * 3. late_initcall(threshold_init_device);
1394  *
1395  * when running under xen, the initcall order is 1,2,3;
1396  * on baremetal, we skip 1 and we do only 2 and 3.
1397  */
1398 late_initcall(threshold_init_device);
1399 

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