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Linux/arch/x86/kernel/cpu/perf_event.c

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  1 /*
  2  * Performance events x86 architecture code
  3  *
  4  *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
  5  *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
  6  *  Copyright (C) 2009 Jaswinder Singh Rajput
  7  *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
  8  *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
  9  *  Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
 10  *  Copyright (C) 2009 Google, Inc., Stephane Eranian
 11  *
 12  *  For licencing details see kernel-base/COPYING
 13  */
 14 
 15 #include <linux/perf_event.h>
 16 #include <linux/capability.h>
 17 #include <linux/notifier.h>
 18 #include <linux/hardirq.h>
 19 #include <linux/kprobes.h>
 20 #include <linux/module.h>
 21 #include <linux/kdebug.h>
 22 #include <linux/sched.h>
 23 #include <linux/uaccess.h>
 24 #include <linux/slab.h>
 25 #include <linux/cpu.h>
 26 #include <linux/bitops.h>
 27 #include <linux/device.h>
 28 
 29 #include <asm/apic.h>
 30 #include <asm/stacktrace.h>
 31 #include <asm/nmi.h>
 32 #include <asm/smp.h>
 33 #include <asm/alternative.h>
 34 #include <asm/mmu_context.h>
 35 #include <asm/tlbflush.h>
 36 #include <asm/timer.h>
 37 #include <asm/desc.h>
 38 #include <asm/ldt.h>
 39 
 40 #include "perf_event.h"
 41 
 42 struct x86_pmu x86_pmu __read_mostly;
 43 
 44 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
 45         .enabled = 1,
 46 };
 47 
 48 struct static_key rdpmc_always_available = STATIC_KEY_INIT_FALSE;
 49 
 50 u64 __read_mostly hw_cache_event_ids
 51                                 [PERF_COUNT_HW_CACHE_MAX]
 52                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 53                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
 54 u64 __read_mostly hw_cache_extra_regs
 55                                 [PERF_COUNT_HW_CACHE_MAX]
 56                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 57                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
 58 
 59 /*
 60  * Propagate event elapsed time into the generic event.
 61  * Can only be executed on the CPU where the event is active.
 62  * Returns the delta events processed.
 63  */
 64 u64 x86_perf_event_update(struct perf_event *event)
 65 {
 66         struct hw_perf_event *hwc = &event->hw;
 67         int shift = 64 - x86_pmu.cntval_bits;
 68         u64 prev_raw_count, new_raw_count;
 69         int idx = hwc->idx;
 70         s64 delta;
 71 
 72         if (idx == INTEL_PMC_IDX_FIXED_BTS)
 73                 return 0;
 74 
 75         /*
 76          * Careful: an NMI might modify the previous event value.
 77          *
 78          * Our tactic to handle this is to first atomically read and
 79          * exchange a new raw count - then add that new-prev delta
 80          * count to the generic event atomically:
 81          */
 82 again:
 83         prev_raw_count = local64_read(&hwc->prev_count);
 84         rdpmcl(hwc->event_base_rdpmc, new_raw_count);
 85 
 86         if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
 87                                         new_raw_count) != prev_raw_count)
 88                 goto again;
 89 
 90         /*
 91          * Now we have the new raw value and have updated the prev
 92          * timestamp already. We can now calculate the elapsed delta
 93          * (event-)time and add that to the generic event.
 94          *
 95          * Careful, not all hw sign-extends above the physical width
 96          * of the count.
 97          */
 98         delta = (new_raw_count << shift) - (prev_raw_count << shift);
 99         delta >>= shift;
100 
101         local64_add(delta, &event->count);
102         local64_sub(delta, &hwc->period_left);
103 
104         return new_raw_count;
105 }
106 
107 /*
108  * Find and validate any extra registers to set up.
109  */
110 static int x86_pmu_extra_regs(u64 config, struct perf_event *event)
111 {
112         struct hw_perf_event_extra *reg;
113         struct extra_reg *er;
114 
115         reg = &event->hw.extra_reg;
116 
117         if (!x86_pmu.extra_regs)
118                 return 0;
119 
120         for (er = x86_pmu.extra_regs; er->msr; er++) {
121                 if (er->event != (config & er->config_mask))
122                         continue;
123                 if (event->attr.config1 & ~er->valid_mask)
124                         return -EINVAL;
125                 /* Check if the extra msrs can be safely accessed*/
126                 if (!er->extra_msr_access)
127                         return -ENXIO;
128 
129                 reg->idx = er->idx;
130                 reg->config = event->attr.config1;
131                 reg->reg = er->msr;
132                 break;
133         }
134         return 0;
135 }
136 
137 static atomic_t active_events;
138 static DEFINE_MUTEX(pmc_reserve_mutex);
139 
140 #ifdef CONFIG_X86_LOCAL_APIC
141 
142 static bool reserve_pmc_hardware(void)
143 {
144         int i;
145 
146         for (i = 0; i < x86_pmu.num_counters; i++) {
147                 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i)))
148                         goto perfctr_fail;
149         }
150 
151         for (i = 0; i < x86_pmu.num_counters; i++) {
152                 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i)))
153                         goto eventsel_fail;
154         }
155 
156         return true;
157 
158 eventsel_fail:
159         for (i--; i >= 0; i--)
160                 release_evntsel_nmi(x86_pmu_config_addr(i));
161 
162         i = x86_pmu.num_counters;
163 
164 perfctr_fail:
165         for (i--; i >= 0; i--)
166                 release_perfctr_nmi(x86_pmu_event_addr(i));
167 
168         return false;
169 }
170 
171 static void release_pmc_hardware(void)
172 {
173         int i;
174 
175         for (i = 0; i < x86_pmu.num_counters; i++) {
176                 release_perfctr_nmi(x86_pmu_event_addr(i));
177                 release_evntsel_nmi(x86_pmu_config_addr(i));
178         }
179 }
180 
181 #else
182 
183 static bool reserve_pmc_hardware(void) { return true; }
184 static void release_pmc_hardware(void) {}
185 
186 #endif
187 
188 static bool check_hw_exists(void)
189 {
190         u64 val, val_fail, val_new= ~0;
191         int i, reg, reg_fail, ret = 0;
192         int bios_fail = 0;
193 
194         /*
195          * Check to see if the BIOS enabled any of the counters, if so
196          * complain and bail.
197          */
198         for (i = 0; i < x86_pmu.num_counters; i++) {
199                 reg = x86_pmu_config_addr(i);
200                 ret = rdmsrl_safe(reg, &val);
201                 if (ret)
202                         goto msr_fail;
203                 if (val & ARCH_PERFMON_EVENTSEL_ENABLE) {
204                         bios_fail = 1;
205                         val_fail = val;
206                         reg_fail = reg;
207                 }
208         }
209 
210         if (x86_pmu.num_counters_fixed) {
211                 reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
212                 ret = rdmsrl_safe(reg, &val);
213                 if (ret)
214                         goto msr_fail;
215                 for (i = 0; i < x86_pmu.num_counters_fixed; i++) {
216                         if (val & (0x03 << i*4)) {
217                                 bios_fail = 1;
218                                 val_fail = val;
219                                 reg_fail = reg;
220                         }
221                 }
222         }
223 
224         /*
225          * Read the current value, change it and read it back to see if it
226          * matches, this is needed to detect certain hardware emulators
227          * (qemu/kvm) that don't trap on the MSR access and always return 0s.
228          */
229         reg = x86_pmu_event_addr(0);
230         if (rdmsrl_safe(reg, &val))
231                 goto msr_fail;
232         val ^= 0xffffUL;
233         ret = wrmsrl_safe(reg, val);
234         ret |= rdmsrl_safe(reg, &val_new);
235         if (ret || val != val_new)
236                 goto msr_fail;
237 
238         /*
239          * We still allow the PMU driver to operate:
240          */
241         if (bios_fail) {
242                 printk(KERN_CONT "Broken BIOS detected, complain to your hardware vendor.\n");
243                 printk(KERN_ERR FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg_fail, val_fail);
244         }
245 
246         return true;
247 
248 msr_fail:
249         printk(KERN_CONT "Broken PMU hardware detected, using software events only.\n");
250         printk("%sFailed to access perfctr msr (MSR %x is %Lx)\n",
251                 boot_cpu_has(X86_FEATURE_HYPERVISOR) ? KERN_INFO : KERN_ERR,
252                 reg, val_new);
253 
254         return false;
255 }
256 
257 static void hw_perf_event_destroy(struct perf_event *event)
258 {
259         if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
260                 release_pmc_hardware();
261                 release_ds_buffers();
262                 mutex_unlock(&pmc_reserve_mutex);
263         }
264 }
265 
266 static inline int x86_pmu_initialized(void)
267 {
268         return x86_pmu.handle_irq != NULL;
269 }
270 
271 static inline int
272 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event)
273 {
274         struct perf_event_attr *attr = &event->attr;
275         unsigned int cache_type, cache_op, cache_result;
276         u64 config, val;
277 
278         config = attr->config;
279 
280         cache_type = (config >>  0) & 0xff;
281         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
282                 return -EINVAL;
283 
284         cache_op = (config >>  8) & 0xff;
285         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
286                 return -EINVAL;
287 
288         cache_result = (config >> 16) & 0xff;
289         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
290                 return -EINVAL;
291 
292         val = hw_cache_event_ids[cache_type][cache_op][cache_result];
293 
294         if (val == 0)
295                 return -ENOENT;
296 
297         if (val == -1)
298                 return -EINVAL;
299 
300         hwc->config |= val;
301         attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result];
302         return x86_pmu_extra_regs(val, event);
303 }
304 
305 int x86_setup_perfctr(struct perf_event *event)
306 {
307         struct perf_event_attr *attr = &event->attr;
308         struct hw_perf_event *hwc = &event->hw;
309         u64 config;
310 
311         if (!is_sampling_event(event)) {
312                 hwc->sample_period = x86_pmu.max_period;
313                 hwc->last_period = hwc->sample_period;
314                 local64_set(&hwc->period_left, hwc->sample_period);
315         }
316 
317         if (attr->type == PERF_TYPE_RAW)
318                 return x86_pmu_extra_regs(event->attr.config, event);
319 
320         if (attr->type == PERF_TYPE_HW_CACHE)
321                 return set_ext_hw_attr(hwc, event);
322 
323         if (attr->config >= x86_pmu.max_events)
324                 return -EINVAL;
325 
326         /*
327          * The generic map:
328          */
329         config = x86_pmu.event_map(attr->config);
330 
331         if (config == 0)
332                 return -ENOENT;
333 
334         if (config == -1LL)
335                 return -EINVAL;
336 
337         /*
338          * Branch tracing:
339          */
340         if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS &&
341             !attr->freq && hwc->sample_period == 1) {
342                 /* BTS is not supported by this architecture. */
343                 if (!x86_pmu.bts_active)
344                         return -EOPNOTSUPP;
345 
346                 /* BTS is currently only allowed for user-mode. */
347                 if (!attr->exclude_kernel)
348                         return -EOPNOTSUPP;
349         }
350 
351         hwc->config |= config;
352 
353         return 0;
354 }
355 
356 /*
357  * check that branch_sample_type is compatible with
358  * settings needed for precise_ip > 1 which implies
359  * using the LBR to capture ALL taken branches at the
360  * priv levels of the measurement
361  */
362 static inline int precise_br_compat(struct perf_event *event)
363 {
364         u64 m = event->attr.branch_sample_type;
365         u64 b = 0;
366 
367         /* must capture all branches */
368         if (!(m & PERF_SAMPLE_BRANCH_ANY))
369                 return 0;
370 
371         m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER;
372 
373         if (!event->attr.exclude_user)
374                 b |= PERF_SAMPLE_BRANCH_USER;
375 
376         if (!event->attr.exclude_kernel)
377                 b |= PERF_SAMPLE_BRANCH_KERNEL;
378 
379         /*
380          * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86
381          */
382 
383         return m == b;
384 }
385 
386 int x86_pmu_hw_config(struct perf_event *event)
387 {
388         if (event->attr.precise_ip) {
389                 int precise = 0;
390 
391                 /* Support for constant skid */
392                 if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) {
393                         precise++;
394 
395                         /* Support for IP fixup */
396                         if (x86_pmu.lbr_nr || x86_pmu.intel_cap.pebs_format >= 2)
397                                 precise++;
398                 }
399 
400                 if (event->attr.precise_ip > precise)
401                         return -EOPNOTSUPP;
402                 /*
403                  * check that PEBS LBR correction does not conflict with
404                  * whatever the user is asking with attr->branch_sample_type
405                  */
406                 if (event->attr.precise_ip > 1 &&
407                     x86_pmu.intel_cap.pebs_format < 2) {
408                         u64 *br_type = &event->attr.branch_sample_type;
409 
410                         if (has_branch_stack(event)) {
411                                 if (!precise_br_compat(event))
412                                         return -EOPNOTSUPP;
413 
414                                 /* branch_sample_type is compatible */
415 
416                         } else {
417                                 /*
418                                  * user did not specify  branch_sample_type
419                                  *
420                                  * For PEBS fixups, we capture all
421                                  * the branches at the priv level of the
422                                  * event.
423                                  */
424                                 *br_type = PERF_SAMPLE_BRANCH_ANY;
425 
426                                 if (!event->attr.exclude_user)
427                                         *br_type |= PERF_SAMPLE_BRANCH_USER;
428 
429                                 if (!event->attr.exclude_kernel)
430                                         *br_type |= PERF_SAMPLE_BRANCH_KERNEL;
431                         }
432                 }
433         }
434 
435         /*
436          * Generate PMC IRQs:
437          * (keep 'enabled' bit clear for now)
438          */
439         event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
440 
441         /*
442          * Count user and OS events unless requested not to
443          */
444         if (!event->attr.exclude_user)
445                 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
446         if (!event->attr.exclude_kernel)
447                 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
448 
449         if (event->attr.type == PERF_TYPE_RAW)
450                 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
451 
452         return x86_setup_perfctr(event);
453 }
454 
455 /*
456  * Setup the hardware configuration for a given attr_type
457  */
458 static int __x86_pmu_event_init(struct perf_event *event)
459 {
460         int err;
461 
462         if (!x86_pmu_initialized())
463                 return -ENODEV;
464 
465         err = 0;
466         if (!atomic_inc_not_zero(&active_events)) {
467                 mutex_lock(&pmc_reserve_mutex);
468                 if (atomic_read(&active_events) == 0) {
469                         if (!reserve_pmc_hardware())
470                                 err = -EBUSY;
471                         else
472                                 reserve_ds_buffers();
473                 }
474                 if (!err)
475                         atomic_inc(&active_events);
476                 mutex_unlock(&pmc_reserve_mutex);
477         }
478         if (err)
479                 return err;
480 
481         event->destroy = hw_perf_event_destroy;
482 
483         event->hw.idx = -1;
484         event->hw.last_cpu = -1;
485         event->hw.last_tag = ~0ULL;
486 
487         /* mark unused */
488         event->hw.extra_reg.idx = EXTRA_REG_NONE;
489         event->hw.branch_reg.idx = EXTRA_REG_NONE;
490 
491         return x86_pmu.hw_config(event);
492 }
493 
494 void x86_pmu_disable_all(void)
495 {
496         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
497         int idx;
498 
499         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
500                 u64 val;
501 
502                 if (!test_bit(idx, cpuc->active_mask))
503                         continue;
504                 rdmsrl(x86_pmu_config_addr(idx), val);
505                 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
506                         continue;
507                 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
508                 wrmsrl(x86_pmu_config_addr(idx), val);
509         }
510 }
511 
512 static void x86_pmu_disable(struct pmu *pmu)
513 {
514         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
515 
516         if (!x86_pmu_initialized())
517                 return;
518 
519         if (!cpuc->enabled)
520                 return;
521 
522         cpuc->n_added = 0;
523         cpuc->enabled = 0;
524         barrier();
525 
526         x86_pmu.disable_all();
527 }
528 
529 void x86_pmu_enable_all(int added)
530 {
531         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
532         int idx;
533 
534         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
535                 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
536 
537                 if (!test_bit(idx, cpuc->active_mask))
538                         continue;
539 
540                 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
541         }
542 }
543 
544 static struct pmu pmu;
545 
546 static inline int is_x86_event(struct perf_event *event)
547 {
548         return event->pmu == &pmu;
549 }
550 
551 /*
552  * Event scheduler state:
553  *
554  * Assign events iterating over all events and counters, beginning
555  * with events with least weights first. Keep the current iterator
556  * state in struct sched_state.
557  */
558 struct sched_state {
559         int     weight;
560         int     event;          /* event index */
561         int     counter;        /* counter index */
562         int     unassigned;     /* number of events to be assigned left */
563         unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
564 };
565 
566 /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */
567 #define SCHED_STATES_MAX        2
568 
569 struct perf_sched {
570         int                     max_weight;
571         int                     max_events;
572         struct perf_event       **events;
573         struct sched_state      state;
574         int                     saved_states;
575         struct sched_state      saved[SCHED_STATES_MAX];
576 };
577 
578 /*
579  * Initialize interator that runs through all events and counters.
580  */
581 static void perf_sched_init(struct perf_sched *sched, struct perf_event **events,
582                             int num, int wmin, int wmax)
583 {
584         int idx;
585 
586         memset(sched, 0, sizeof(*sched));
587         sched->max_events       = num;
588         sched->max_weight       = wmax;
589         sched->events           = events;
590 
591         for (idx = 0; idx < num; idx++) {
592                 if (events[idx]->hw.constraint->weight == wmin)
593                         break;
594         }
595 
596         sched->state.event      = idx;          /* start with min weight */
597         sched->state.weight     = wmin;
598         sched->state.unassigned = num;
599 }
600 
601 static void perf_sched_save_state(struct perf_sched *sched)
602 {
603         if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX))
604                 return;
605 
606         sched->saved[sched->saved_states] = sched->state;
607         sched->saved_states++;
608 }
609 
610 static bool perf_sched_restore_state(struct perf_sched *sched)
611 {
612         if (!sched->saved_states)
613                 return false;
614 
615         sched->saved_states--;
616         sched->state = sched->saved[sched->saved_states];
617 
618         /* continue with next counter: */
619         clear_bit(sched->state.counter++, sched->state.used);
620 
621         return true;
622 }
623 
624 /*
625  * Select a counter for the current event to schedule. Return true on
626  * success.
627  */
628 static bool __perf_sched_find_counter(struct perf_sched *sched)
629 {
630         struct event_constraint *c;
631         int idx;
632 
633         if (!sched->state.unassigned)
634                 return false;
635 
636         if (sched->state.event >= sched->max_events)
637                 return false;
638 
639         c = sched->events[sched->state.event]->hw.constraint;
640         /* Prefer fixed purpose counters */
641         if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) {
642                 idx = INTEL_PMC_IDX_FIXED;
643                 for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) {
644                         if (!__test_and_set_bit(idx, sched->state.used))
645                                 goto done;
646                 }
647         }
648         /* Grab the first unused counter starting with idx */
649         idx = sched->state.counter;
650         for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) {
651                 if (!__test_and_set_bit(idx, sched->state.used))
652                         goto done;
653         }
654 
655         return false;
656 
657 done:
658         sched->state.counter = idx;
659 
660         if (c->overlap)
661                 perf_sched_save_state(sched);
662 
663         return true;
664 }
665 
666 static bool perf_sched_find_counter(struct perf_sched *sched)
667 {
668         while (!__perf_sched_find_counter(sched)) {
669                 if (!perf_sched_restore_state(sched))
670                         return false;
671         }
672 
673         return true;
674 }
675 
676 /*
677  * Go through all unassigned events and find the next one to schedule.
678  * Take events with the least weight first. Return true on success.
679  */
680 static bool perf_sched_next_event(struct perf_sched *sched)
681 {
682         struct event_constraint *c;
683 
684         if (!sched->state.unassigned || !--sched->state.unassigned)
685                 return false;
686 
687         do {
688                 /* next event */
689                 sched->state.event++;
690                 if (sched->state.event >= sched->max_events) {
691                         /* next weight */
692                         sched->state.event = 0;
693                         sched->state.weight++;
694                         if (sched->state.weight > sched->max_weight)
695                                 return false;
696                 }
697                 c = sched->events[sched->state.event]->hw.constraint;
698         } while (c->weight != sched->state.weight);
699 
700         sched->state.counter = 0;       /* start with first counter */
701 
702         return true;
703 }
704 
705 /*
706  * Assign a counter for each event.
707  */
708 int perf_assign_events(struct perf_event **events, int n,
709                         int wmin, int wmax, int *assign)
710 {
711         struct perf_sched sched;
712 
713         perf_sched_init(&sched, events, n, wmin, wmax);
714 
715         do {
716                 if (!perf_sched_find_counter(&sched))
717                         break;  /* failed */
718                 if (assign)
719                         assign[sched.state.event] = sched.state.counter;
720         } while (perf_sched_next_event(&sched));
721 
722         return sched.state.unassigned;
723 }
724 EXPORT_SYMBOL_GPL(perf_assign_events);
725 
726 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
727 {
728         struct event_constraint *c;
729         unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
730         struct perf_event *e;
731         int i, wmin, wmax, num = 0;
732         struct hw_perf_event *hwc;
733 
734         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
735 
736         for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) {
737                 hwc = &cpuc->event_list[i]->hw;
738                 c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]);
739                 hwc->constraint = c;
740 
741                 wmin = min(wmin, c->weight);
742                 wmax = max(wmax, c->weight);
743         }
744 
745         /*
746          * fastpath, try to reuse previous register
747          */
748         for (i = 0; i < n; i++) {
749                 hwc = &cpuc->event_list[i]->hw;
750                 c = hwc->constraint;
751 
752                 /* never assigned */
753                 if (hwc->idx == -1)
754                         break;
755 
756                 /* constraint still honored */
757                 if (!test_bit(hwc->idx, c->idxmsk))
758                         break;
759 
760                 /* not already used */
761                 if (test_bit(hwc->idx, used_mask))
762                         break;
763 
764                 __set_bit(hwc->idx, used_mask);
765                 if (assign)
766                         assign[i] = hwc->idx;
767         }
768 
769         /* slow path */
770         if (i != n)
771                 num = perf_assign_events(cpuc->event_list, n, wmin,
772                                          wmax, assign);
773 
774         /*
775          * Mark the event as committed, so we do not put_constraint()
776          * in case new events are added and fail scheduling.
777          */
778         if (!num && assign) {
779                 for (i = 0; i < n; i++) {
780                         e = cpuc->event_list[i];
781                         e->hw.flags |= PERF_X86_EVENT_COMMITTED;
782                 }
783         }
784         /*
785          * scheduling failed or is just a simulation,
786          * free resources if necessary
787          */
788         if (!assign || num) {
789                 for (i = 0; i < n; i++) {
790                         e = cpuc->event_list[i];
791                         /*
792                          * do not put_constraint() on comitted events,
793                          * because they are good to go
794                          */
795                         if ((e->hw.flags & PERF_X86_EVENT_COMMITTED))
796                                 continue;
797 
798                         if (x86_pmu.put_event_constraints)
799                                 x86_pmu.put_event_constraints(cpuc, e);
800                 }
801         }
802         return num ? -EINVAL : 0;
803 }
804 
805 /*
806  * dogrp: true if must collect siblings events (group)
807  * returns total number of events and error code
808  */
809 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
810 {
811         struct perf_event *event;
812         int n, max_count;
813 
814         max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
815 
816         /* current number of events already accepted */
817         n = cpuc->n_events;
818 
819         if (is_x86_event(leader)) {
820                 if (n >= max_count)
821                         return -EINVAL;
822                 cpuc->event_list[n] = leader;
823                 n++;
824         }
825         if (!dogrp)
826                 return n;
827 
828         list_for_each_entry(event, &leader->sibling_list, group_entry) {
829                 if (!is_x86_event(event) ||
830                     event->state <= PERF_EVENT_STATE_OFF)
831                         continue;
832 
833                 if (n >= max_count)
834                         return -EINVAL;
835 
836                 cpuc->event_list[n] = event;
837                 n++;
838         }
839         return n;
840 }
841 
842 static inline void x86_assign_hw_event(struct perf_event *event,
843                                 struct cpu_hw_events *cpuc, int i)
844 {
845         struct hw_perf_event *hwc = &event->hw;
846 
847         hwc->idx = cpuc->assign[i];
848         hwc->last_cpu = smp_processor_id();
849         hwc->last_tag = ++cpuc->tags[i];
850 
851         if (hwc->idx == INTEL_PMC_IDX_FIXED_BTS) {
852                 hwc->config_base = 0;
853                 hwc->event_base = 0;
854         } else if (hwc->idx >= INTEL_PMC_IDX_FIXED) {
855                 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
856                 hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - INTEL_PMC_IDX_FIXED);
857                 hwc->event_base_rdpmc = (hwc->idx - INTEL_PMC_IDX_FIXED) | 1<<30;
858         } else {
859                 hwc->config_base = x86_pmu_config_addr(hwc->idx);
860                 hwc->event_base  = x86_pmu_event_addr(hwc->idx);
861                 hwc->event_base_rdpmc = x86_pmu_rdpmc_index(hwc->idx);
862         }
863 }
864 
865 static inline int match_prev_assignment(struct hw_perf_event *hwc,
866                                         struct cpu_hw_events *cpuc,
867                                         int i)
868 {
869         return hwc->idx == cpuc->assign[i] &&
870                 hwc->last_cpu == smp_processor_id() &&
871                 hwc->last_tag == cpuc->tags[i];
872 }
873 
874 static void x86_pmu_start(struct perf_event *event, int flags);
875 
876 static void x86_pmu_enable(struct pmu *pmu)
877 {
878         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
879         struct perf_event *event;
880         struct hw_perf_event *hwc;
881         int i, added = cpuc->n_added;
882 
883         if (!x86_pmu_initialized())
884                 return;
885 
886         if (cpuc->enabled)
887                 return;
888 
889         if (cpuc->n_added) {
890                 int n_running = cpuc->n_events - cpuc->n_added;
891                 /*
892                  * apply assignment obtained either from
893                  * hw_perf_group_sched_in() or x86_pmu_enable()
894                  *
895                  * step1: save events moving to new counters
896                  */
897                 for (i = 0; i < n_running; i++) {
898                         event = cpuc->event_list[i];
899                         hwc = &event->hw;
900 
901                         /*
902                          * we can avoid reprogramming counter if:
903                          * - assigned same counter as last time
904                          * - running on same CPU as last time
905                          * - no other event has used the counter since
906                          */
907                         if (hwc->idx == -1 ||
908                             match_prev_assignment(hwc, cpuc, i))
909                                 continue;
910 
911                         /*
912                          * Ensure we don't accidentally enable a stopped
913                          * counter simply because we rescheduled.
914                          */
915                         if (hwc->state & PERF_HES_STOPPED)
916                                 hwc->state |= PERF_HES_ARCH;
917 
918                         x86_pmu_stop(event, PERF_EF_UPDATE);
919                 }
920 
921                 /*
922                  * step2: reprogram moved events into new counters
923                  */
924                 for (i = 0; i < cpuc->n_events; i++) {
925                         event = cpuc->event_list[i];
926                         hwc = &event->hw;
927 
928                         if (!match_prev_assignment(hwc, cpuc, i))
929                                 x86_assign_hw_event(event, cpuc, i);
930                         else if (i < n_running)
931                                 continue;
932 
933                         if (hwc->state & PERF_HES_ARCH)
934                                 continue;
935 
936                         x86_pmu_start(event, PERF_EF_RELOAD);
937                 }
938                 cpuc->n_added = 0;
939                 perf_events_lapic_init();
940         }
941 
942         cpuc->enabled = 1;
943         barrier();
944 
945         x86_pmu.enable_all(added);
946 }
947 
948 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
949 
950 /*
951  * Set the next IRQ period, based on the hwc->period_left value.
952  * To be called with the event disabled in hw:
953  */
954 int x86_perf_event_set_period(struct perf_event *event)
955 {
956         struct hw_perf_event *hwc = &event->hw;
957         s64 left = local64_read(&hwc->period_left);
958         s64 period = hwc->sample_period;
959         int ret = 0, idx = hwc->idx;
960 
961         if (idx == INTEL_PMC_IDX_FIXED_BTS)
962                 return 0;
963 
964         /*
965          * If we are way outside a reasonable range then just skip forward:
966          */
967         if (unlikely(left <= -period)) {
968                 left = period;
969                 local64_set(&hwc->period_left, left);
970                 hwc->last_period = period;
971                 ret = 1;
972         }
973 
974         if (unlikely(left <= 0)) {
975                 left += period;
976                 local64_set(&hwc->period_left, left);
977                 hwc->last_period = period;
978                 ret = 1;
979         }
980         /*
981          * Quirk: certain CPUs dont like it if just 1 hw_event is left:
982          */
983         if (unlikely(left < 2))
984                 left = 2;
985 
986         if (left > x86_pmu.max_period)
987                 left = x86_pmu.max_period;
988 
989         per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
990 
991         /*
992          * The hw event starts counting from this event offset,
993          * mark it to be able to extra future deltas:
994          */
995         local64_set(&hwc->prev_count, (u64)-left);
996 
997         wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
998 
999         /*
1000          * Due to erratum on certan cpu we need
1001          * a second write to be sure the register
1002          * is updated properly
1003          */
1004         if (x86_pmu.perfctr_second_write) {
1005                 wrmsrl(hwc->event_base,
1006                         (u64)(-left) & x86_pmu.cntval_mask);
1007         }
1008 
1009         perf_event_update_userpage(event);
1010 
1011         return ret;
1012 }
1013 
1014 void x86_pmu_enable_event(struct perf_event *event)
1015 {
1016         if (__this_cpu_read(cpu_hw_events.enabled))
1017                 __x86_pmu_enable_event(&event->hw,
1018                                        ARCH_PERFMON_EVENTSEL_ENABLE);
1019 }
1020 
1021 /*
1022  * Add a single event to the PMU.
1023  *
1024  * The event is added to the group of enabled events
1025  * but only if it can be scehduled with existing events.
1026  */
1027 static int x86_pmu_add(struct perf_event *event, int flags)
1028 {
1029         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1030         struct hw_perf_event *hwc;
1031         int assign[X86_PMC_IDX_MAX];
1032         int n, n0, ret;
1033 
1034         hwc = &event->hw;
1035 
1036         perf_pmu_disable(event->pmu);
1037         n0 = cpuc->n_events;
1038         ret = n = collect_events(cpuc, event, false);
1039         if (ret < 0)
1040                 goto out;
1041 
1042         hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
1043         if (!(flags & PERF_EF_START))
1044                 hwc->state |= PERF_HES_ARCH;
1045 
1046         /*
1047          * If group events scheduling transaction was started,
1048          * skip the schedulability test here, it will be performed
1049          * at commit time (->commit_txn) as a whole.
1050          */
1051         if (cpuc->group_flag & PERF_EVENT_TXN)
1052                 goto done_collect;
1053 
1054         ret = x86_pmu.schedule_events(cpuc, n, assign);
1055         if (ret)
1056                 goto out;
1057         /*
1058          * copy new assignment, now we know it is possible
1059          * will be used by hw_perf_enable()
1060          */
1061         memcpy(cpuc->assign, assign, n*sizeof(int));
1062 
1063 done_collect:
1064         /*
1065          * Commit the collect_events() state. See x86_pmu_del() and
1066          * x86_pmu_*_txn().
1067          */
1068         cpuc->n_events = n;
1069         cpuc->n_added += n - n0;
1070         cpuc->n_txn += n - n0;
1071 
1072         ret = 0;
1073 out:
1074         perf_pmu_enable(event->pmu);
1075         return ret;
1076 }
1077 
1078 static void x86_pmu_start(struct perf_event *event, int flags)
1079 {
1080         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1081         int idx = event->hw.idx;
1082 
1083         if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
1084                 return;
1085 
1086         if (WARN_ON_ONCE(idx == -1))
1087                 return;
1088 
1089         if (flags & PERF_EF_RELOAD) {
1090                 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1091                 x86_perf_event_set_period(event);
1092         }
1093 
1094         event->hw.state = 0;
1095 
1096         cpuc->events[idx] = event;
1097         __set_bit(idx, cpuc->active_mask);
1098         __set_bit(idx, cpuc->running);
1099         x86_pmu.enable(event);
1100         perf_event_update_userpage(event);
1101 }
1102 
1103 void perf_event_print_debug(void)
1104 {
1105         u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1106         u64 pebs;
1107         struct cpu_hw_events *cpuc;
1108         unsigned long flags;
1109         int cpu, idx;
1110 
1111         if (!x86_pmu.num_counters)
1112                 return;
1113 
1114         local_irq_save(flags);
1115 
1116         cpu = smp_processor_id();
1117         cpuc = &per_cpu(cpu_hw_events, cpu);
1118 
1119         if (x86_pmu.version >= 2) {
1120                 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1121                 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1122                 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1123                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1124                 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1125 
1126                 pr_info("\n");
1127                 pr_info("CPU#%d: ctrl:       %016llx\n", cpu, ctrl);
1128                 pr_info("CPU#%d: status:     %016llx\n", cpu, status);
1129                 pr_info("CPU#%d: overflow:   %016llx\n", cpu, overflow);
1130                 pr_info("CPU#%d: fixed:      %016llx\n", cpu, fixed);
1131                 pr_info("CPU#%d: pebs:       %016llx\n", cpu, pebs);
1132         }
1133         pr_info("CPU#%d: active:     %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1134 
1135         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1136                 rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl);
1137                 rdmsrl(x86_pmu_event_addr(idx), pmc_count);
1138 
1139                 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1140 
1141                 pr_info("CPU#%d:   gen-PMC%d ctrl:  %016llx\n",
1142                         cpu, idx, pmc_ctrl);
1143                 pr_info("CPU#%d:   gen-PMC%d count: %016llx\n",
1144                         cpu, idx, pmc_count);
1145                 pr_info("CPU#%d:   gen-PMC%d left:  %016llx\n",
1146                         cpu, idx, prev_left);
1147         }
1148         for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1149                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1150 
1151                 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1152                         cpu, idx, pmc_count);
1153         }
1154         local_irq_restore(flags);
1155 }
1156 
1157 void x86_pmu_stop(struct perf_event *event, int flags)
1158 {
1159         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1160         struct hw_perf_event *hwc = &event->hw;
1161 
1162         if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) {
1163                 x86_pmu.disable(event);
1164                 cpuc->events[hwc->idx] = NULL;
1165                 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
1166                 hwc->state |= PERF_HES_STOPPED;
1167         }
1168 
1169         if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
1170                 /*
1171                  * Drain the remaining delta count out of a event
1172                  * that we are disabling:
1173                  */
1174                 x86_perf_event_update(event);
1175                 hwc->state |= PERF_HES_UPTODATE;
1176         }
1177 }
1178 
1179 static void x86_pmu_del(struct perf_event *event, int flags)
1180 {
1181         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1182         int i;
1183 
1184         /*
1185          * event is descheduled
1186          */
1187         event->hw.flags &= ~PERF_X86_EVENT_COMMITTED;
1188 
1189         /*
1190          * If we're called during a txn, we don't need to do anything.
1191          * The events never got scheduled and ->cancel_txn will truncate
1192          * the event_list.
1193          *
1194          * XXX assumes any ->del() called during a TXN will only be on
1195          * an event added during that same TXN.
1196          */
1197         if (cpuc->group_flag & PERF_EVENT_TXN)
1198                 return;
1199 
1200         /*
1201          * Not a TXN, therefore cleanup properly.
1202          */
1203         x86_pmu_stop(event, PERF_EF_UPDATE);
1204 
1205         for (i = 0; i < cpuc->n_events; i++) {
1206                 if (event == cpuc->event_list[i])
1207                         break;
1208         }
1209 
1210         if (WARN_ON_ONCE(i == cpuc->n_events)) /* called ->del() without ->add() ? */
1211                 return;
1212 
1213         /* If we have a newly added event; make sure to decrease n_added. */
1214         if (i >= cpuc->n_events - cpuc->n_added)
1215                 --cpuc->n_added;
1216 
1217         if (x86_pmu.put_event_constraints)
1218                 x86_pmu.put_event_constraints(cpuc, event);
1219 
1220         /* Delete the array entry. */
1221         while (++i < cpuc->n_events)
1222                 cpuc->event_list[i-1] = cpuc->event_list[i];
1223         --cpuc->n_events;
1224 
1225         perf_event_update_userpage(event);
1226 }
1227 
1228 int x86_pmu_handle_irq(struct pt_regs *regs)
1229 {
1230         struct perf_sample_data data;
1231         struct cpu_hw_events *cpuc;
1232         struct perf_event *event;
1233         int idx, handled = 0;
1234         u64 val;
1235 
1236         cpuc = this_cpu_ptr(&cpu_hw_events);
1237 
1238         /*
1239          * Some chipsets need to unmask the LVTPC in a particular spot
1240          * inside the nmi handler.  As a result, the unmasking was pushed
1241          * into all the nmi handlers.
1242          *
1243          * This generic handler doesn't seem to have any issues where the
1244          * unmasking occurs so it was left at the top.
1245          */
1246         apic_write(APIC_LVTPC, APIC_DM_NMI);
1247 
1248         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1249                 if (!test_bit(idx, cpuc->active_mask)) {
1250                         /*
1251                          * Though we deactivated the counter some cpus
1252                          * might still deliver spurious interrupts still
1253                          * in flight. Catch them:
1254                          */
1255                         if (__test_and_clear_bit(idx, cpuc->running))
1256                                 handled++;
1257                         continue;
1258                 }
1259 
1260                 event = cpuc->events[idx];
1261 
1262                 val = x86_perf_event_update(event);
1263                 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1264                         continue;
1265 
1266                 /*
1267                  * event overflow
1268                  */
1269                 handled++;
1270                 perf_sample_data_init(&data, 0, event->hw.last_period);
1271 
1272                 if (!x86_perf_event_set_period(event))
1273                         continue;
1274 
1275                 if (perf_event_overflow(event, &data, regs))
1276                         x86_pmu_stop(event, 0);
1277         }
1278 
1279         if (handled)
1280                 inc_irq_stat(apic_perf_irqs);
1281 
1282         return handled;
1283 }
1284 
1285 void perf_events_lapic_init(void)
1286 {
1287         if (!x86_pmu.apic || !x86_pmu_initialized())
1288                 return;
1289 
1290         /*
1291          * Always use NMI for PMU
1292          */
1293         apic_write(APIC_LVTPC, APIC_DM_NMI);
1294 }
1295 
1296 static int
1297 perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs)
1298 {
1299         u64 start_clock;
1300         u64 finish_clock;
1301         int ret;
1302 
1303         if (!atomic_read(&active_events))
1304                 return NMI_DONE;
1305 
1306         start_clock = sched_clock();
1307         ret = x86_pmu.handle_irq(regs);
1308         finish_clock = sched_clock();
1309 
1310         perf_sample_event_took(finish_clock - start_clock);
1311 
1312         return ret;
1313 }
1314 NOKPROBE_SYMBOL(perf_event_nmi_handler);
1315 
1316 struct event_constraint emptyconstraint;
1317 struct event_constraint unconstrained;
1318 
1319 static int
1320 x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
1321 {
1322         unsigned int cpu = (long)hcpu;
1323         struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1324         int ret = NOTIFY_OK;
1325 
1326         switch (action & ~CPU_TASKS_FROZEN) {
1327         case CPU_UP_PREPARE:
1328                 cpuc->kfree_on_online = NULL;
1329                 if (x86_pmu.cpu_prepare)
1330                         ret = x86_pmu.cpu_prepare(cpu);
1331                 break;
1332 
1333         case CPU_STARTING:
1334                 if (x86_pmu.cpu_starting)
1335                         x86_pmu.cpu_starting(cpu);
1336                 break;
1337 
1338         case CPU_ONLINE:
1339                 kfree(cpuc->kfree_on_online);
1340                 break;
1341 
1342         case CPU_DYING:
1343                 if (x86_pmu.cpu_dying)
1344                         x86_pmu.cpu_dying(cpu);
1345                 break;
1346 
1347         case CPU_UP_CANCELED:
1348         case CPU_DEAD:
1349                 if (x86_pmu.cpu_dead)
1350                         x86_pmu.cpu_dead(cpu);
1351                 break;
1352 
1353         default:
1354                 break;
1355         }
1356 
1357         return ret;
1358 }
1359 
1360 static void __init pmu_check_apic(void)
1361 {
1362         if (cpu_has_apic)
1363                 return;
1364 
1365         x86_pmu.apic = 0;
1366         pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1367         pr_info("no hardware sampling interrupt available.\n");
1368 
1369         /*
1370          * If we have a PMU initialized but no APIC
1371          * interrupts, we cannot sample hardware
1372          * events (user-space has to fall back and
1373          * sample via a hrtimer based software event):
1374          */
1375         pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
1376 
1377 }
1378 
1379 static struct attribute_group x86_pmu_format_group = {
1380         .name = "format",
1381         .attrs = NULL,
1382 };
1383 
1384 /*
1385  * Remove all undefined events (x86_pmu.event_map(id) == 0)
1386  * out of events_attr attributes.
1387  */
1388 static void __init filter_events(struct attribute **attrs)
1389 {
1390         struct device_attribute *d;
1391         struct perf_pmu_events_attr *pmu_attr;
1392         int i, j;
1393 
1394         for (i = 0; attrs[i]; i++) {
1395                 d = (struct device_attribute *)attrs[i];
1396                 pmu_attr = container_of(d, struct perf_pmu_events_attr, attr);
1397                 /* str trumps id */
1398                 if (pmu_attr->event_str)
1399                         continue;
1400                 if (x86_pmu.event_map(i))
1401                         continue;
1402 
1403                 for (j = i; attrs[j]; j++)
1404                         attrs[j] = attrs[j + 1];
1405 
1406                 /* Check the shifted attr. */
1407                 i--;
1408         }
1409 }
1410 
1411 /* Merge two pointer arrays */
1412 static __init struct attribute **merge_attr(struct attribute **a, struct attribute **b)
1413 {
1414         struct attribute **new;
1415         int j, i;
1416 
1417         for (j = 0; a[j]; j++)
1418                 ;
1419         for (i = 0; b[i]; i++)
1420                 j++;
1421         j++;
1422 
1423         new = kmalloc(sizeof(struct attribute *) * j, GFP_KERNEL);
1424         if (!new)
1425                 return NULL;
1426 
1427         j = 0;
1428         for (i = 0; a[i]; i++)
1429                 new[j++] = a[i];
1430         for (i = 0; b[i]; i++)
1431                 new[j++] = b[i];
1432         new[j] = NULL;
1433 
1434         return new;
1435 }
1436 
1437 ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr,
1438                           char *page)
1439 {
1440         struct perf_pmu_events_attr *pmu_attr = \
1441                 container_of(attr, struct perf_pmu_events_attr, attr);
1442         u64 config = x86_pmu.event_map(pmu_attr->id);
1443 
1444         /* string trumps id */
1445         if (pmu_attr->event_str)
1446                 return sprintf(page, "%s", pmu_attr->event_str);
1447 
1448         return x86_pmu.events_sysfs_show(page, config);
1449 }
1450 
1451 EVENT_ATTR(cpu-cycles,                  CPU_CYCLES              );
1452 EVENT_ATTR(instructions,                INSTRUCTIONS            );
1453 EVENT_ATTR(cache-references,            CACHE_REFERENCES        );
1454 EVENT_ATTR(cache-misses,                CACHE_MISSES            );
1455 EVENT_ATTR(branch-instructions,         BRANCH_INSTRUCTIONS     );
1456 EVENT_ATTR(branch-misses,               BRANCH_MISSES           );
1457 EVENT_ATTR(bus-cycles,                  BUS_CYCLES              );
1458 EVENT_ATTR(stalled-cycles-frontend,     STALLED_CYCLES_FRONTEND );
1459 EVENT_ATTR(stalled-cycles-backend,      STALLED_CYCLES_BACKEND  );
1460 EVENT_ATTR(ref-cycles,                  REF_CPU_CYCLES          );
1461 
1462 static struct attribute *empty_attrs;
1463 
1464 static struct attribute *events_attr[] = {
1465         EVENT_PTR(CPU_CYCLES),
1466         EVENT_PTR(INSTRUCTIONS),
1467         EVENT_PTR(CACHE_REFERENCES),
1468         EVENT_PTR(CACHE_MISSES),
1469         EVENT_PTR(BRANCH_INSTRUCTIONS),
1470         EVENT_PTR(BRANCH_MISSES),
1471         EVENT_PTR(BUS_CYCLES),
1472         EVENT_PTR(STALLED_CYCLES_FRONTEND),
1473         EVENT_PTR(STALLED_CYCLES_BACKEND),
1474         EVENT_PTR(REF_CPU_CYCLES),
1475         NULL,
1476 };
1477 
1478 static struct attribute_group x86_pmu_events_group = {
1479         .name = "events",
1480         .attrs = events_attr,
1481 };
1482 
1483 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event)
1484 {
1485         u64 umask  = (config & ARCH_PERFMON_EVENTSEL_UMASK) >> 8;
1486         u64 cmask  = (config & ARCH_PERFMON_EVENTSEL_CMASK) >> 24;
1487         bool edge  = (config & ARCH_PERFMON_EVENTSEL_EDGE);
1488         bool pc    = (config & ARCH_PERFMON_EVENTSEL_PIN_CONTROL);
1489         bool any   = (config & ARCH_PERFMON_EVENTSEL_ANY);
1490         bool inv   = (config & ARCH_PERFMON_EVENTSEL_INV);
1491         ssize_t ret;
1492 
1493         /*
1494         * We have whole page size to spend and just little data
1495         * to write, so we can safely use sprintf.
1496         */
1497         ret = sprintf(page, "event=0x%02llx", event);
1498 
1499         if (umask)
1500                 ret += sprintf(page + ret, ",umask=0x%02llx", umask);
1501 
1502         if (edge)
1503                 ret += sprintf(page + ret, ",edge");
1504 
1505         if (pc)
1506                 ret += sprintf(page + ret, ",pc");
1507 
1508         if (any)
1509                 ret += sprintf(page + ret, ",any");
1510 
1511         if (inv)
1512                 ret += sprintf(page + ret, ",inv");
1513 
1514         if (cmask)
1515                 ret += sprintf(page + ret, ",cmask=0x%02llx", cmask);
1516 
1517         ret += sprintf(page + ret, "\n");
1518 
1519         return ret;
1520 }
1521 
1522 static int __init init_hw_perf_events(void)
1523 {
1524         struct x86_pmu_quirk *quirk;
1525         int err;
1526 
1527         pr_info("Performance Events: ");
1528 
1529         switch (boot_cpu_data.x86_vendor) {
1530         case X86_VENDOR_INTEL:
1531                 err = intel_pmu_init();
1532                 break;
1533         case X86_VENDOR_AMD:
1534                 err = amd_pmu_init();
1535                 break;
1536         default:
1537                 err = -ENOTSUPP;
1538         }
1539         if (err != 0) {
1540                 pr_cont("no PMU driver, software events only.\n");
1541                 return 0;
1542         }
1543 
1544         pmu_check_apic();
1545 
1546         /* sanity check that the hardware exists or is emulated */
1547         if (!check_hw_exists())
1548                 return 0;
1549 
1550         pr_cont("%s PMU driver.\n", x86_pmu.name);
1551 
1552         x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */
1553 
1554         for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next)
1555                 quirk->func();
1556 
1557         if (!x86_pmu.intel_ctrl)
1558                 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
1559 
1560         perf_events_lapic_init();
1561         register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI");
1562 
1563         unconstrained = (struct event_constraint)
1564                 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
1565                                    0, x86_pmu.num_counters, 0, 0);
1566 
1567         x86_pmu_format_group.attrs = x86_pmu.format_attrs;
1568 
1569         if (x86_pmu.event_attrs)
1570                 x86_pmu_events_group.attrs = x86_pmu.event_attrs;
1571 
1572         if (!x86_pmu.events_sysfs_show)
1573                 x86_pmu_events_group.attrs = &empty_attrs;
1574         else
1575                 filter_events(x86_pmu_events_group.attrs);
1576 
1577         if (x86_pmu.cpu_events) {
1578                 struct attribute **tmp;
1579 
1580                 tmp = merge_attr(x86_pmu_events_group.attrs, x86_pmu.cpu_events);
1581                 if (!WARN_ON(!tmp))
1582                         x86_pmu_events_group.attrs = tmp;
1583         }
1584 
1585         pr_info("... version:                %d\n",     x86_pmu.version);
1586         pr_info("... bit width:              %d\n",     x86_pmu.cntval_bits);
1587         pr_info("... generic registers:      %d\n",     x86_pmu.num_counters);
1588         pr_info("... value mask:             %016Lx\n", x86_pmu.cntval_mask);
1589         pr_info("... max period:             %016Lx\n", x86_pmu.max_period);
1590         pr_info("... fixed-purpose events:   %d\n",     x86_pmu.num_counters_fixed);
1591         pr_info("... event mask:             %016Lx\n", x86_pmu.intel_ctrl);
1592 
1593         perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1594         perf_cpu_notifier(x86_pmu_notifier);
1595 
1596         return 0;
1597 }
1598 early_initcall(init_hw_perf_events);
1599 
1600 static inline void x86_pmu_read(struct perf_event *event)
1601 {
1602         x86_perf_event_update(event);
1603 }
1604 
1605 /*
1606  * Start group events scheduling transaction
1607  * Set the flag to make pmu::enable() not perform the
1608  * schedulability test, it will be performed at commit time
1609  */
1610 static void x86_pmu_start_txn(struct pmu *pmu)
1611 {
1612         perf_pmu_disable(pmu);
1613         __this_cpu_or(cpu_hw_events.group_flag, PERF_EVENT_TXN);
1614         __this_cpu_write(cpu_hw_events.n_txn, 0);
1615 }
1616 
1617 /*
1618  * Stop group events scheduling transaction
1619  * Clear the flag and pmu::enable() will perform the
1620  * schedulability test.
1621  */
1622 static void x86_pmu_cancel_txn(struct pmu *pmu)
1623 {
1624         __this_cpu_and(cpu_hw_events.group_flag, ~PERF_EVENT_TXN);
1625         /*
1626          * Truncate collected array by the number of events added in this
1627          * transaction. See x86_pmu_add() and x86_pmu_*_txn().
1628          */
1629         __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn));
1630         __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn));
1631         perf_pmu_enable(pmu);
1632 }
1633 
1634 /*
1635  * Commit group events scheduling transaction
1636  * Perform the group schedulability test as a whole
1637  * Return 0 if success
1638  *
1639  * Does not cancel the transaction on failure; expects the caller to do this.
1640  */
1641 static int x86_pmu_commit_txn(struct pmu *pmu)
1642 {
1643         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1644         int assign[X86_PMC_IDX_MAX];
1645         int n, ret;
1646 
1647         n = cpuc->n_events;
1648 
1649         if (!x86_pmu_initialized())
1650                 return -EAGAIN;
1651 
1652         ret = x86_pmu.schedule_events(cpuc, n, assign);
1653         if (ret)
1654                 return ret;
1655 
1656         /*
1657          * copy new assignment, now we know it is possible
1658          * will be used by hw_perf_enable()
1659          */
1660         memcpy(cpuc->assign, assign, n*sizeof(int));
1661 
1662         cpuc->group_flag &= ~PERF_EVENT_TXN;
1663         perf_pmu_enable(pmu);
1664         return 0;
1665 }
1666 /*
1667  * a fake_cpuc is used to validate event groups. Due to
1668  * the extra reg logic, we need to also allocate a fake
1669  * per_core and per_cpu structure. Otherwise, group events
1670  * using extra reg may conflict without the kernel being
1671  * able to catch this when the last event gets added to
1672  * the group.
1673  */
1674 static void free_fake_cpuc(struct cpu_hw_events *cpuc)
1675 {
1676         kfree(cpuc->shared_regs);
1677         kfree(cpuc);
1678 }
1679 
1680 static struct cpu_hw_events *allocate_fake_cpuc(void)
1681 {
1682         struct cpu_hw_events *cpuc;
1683         int cpu = raw_smp_processor_id();
1684 
1685         cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL);
1686         if (!cpuc)
1687                 return ERR_PTR(-ENOMEM);
1688 
1689         /* only needed, if we have extra_regs */
1690         if (x86_pmu.extra_regs) {
1691                 cpuc->shared_regs = allocate_shared_regs(cpu);
1692                 if (!cpuc->shared_regs)
1693                         goto error;
1694         }
1695         cpuc->is_fake = 1;
1696         return cpuc;
1697 error:
1698         free_fake_cpuc(cpuc);
1699         return ERR_PTR(-ENOMEM);
1700 }
1701 
1702 /*
1703  * validate that we can schedule this event
1704  */
1705 static int validate_event(struct perf_event *event)
1706 {
1707         struct cpu_hw_events *fake_cpuc;
1708         struct event_constraint *c;
1709         int ret = 0;
1710 
1711         fake_cpuc = allocate_fake_cpuc();
1712         if (IS_ERR(fake_cpuc))
1713                 return PTR_ERR(fake_cpuc);
1714 
1715         c = x86_pmu.get_event_constraints(fake_cpuc, event);
1716 
1717         if (!c || !c->weight)
1718                 ret = -EINVAL;
1719 
1720         if (x86_pmu.put_event_constraints)
1721                 x86_pmu.put_event_constraints(fake_cpuc, event);
1722 
1723         free_fake_cpuc(fake_cpuc);
1724 
1725         return ret;
1726 }
1727 
1728 /*
1729  * validate a single event group
1730  *
1731  * validation include:
1732  *      - check events are compatible which each other
1733  *      - events do not compete for the same counter
1734  *      - number of events <= number of counters
1735  *
1736  * validation ensures the group can be loaded onto the
1737  * PMU if it was the only group available.
1738  */
1739 static int validate_group(struct perf_event *event)
1740 {
1741         struct perf_event *leader = event->group_leader;
1742         struct cpu_hw_events *fake_cpuc;
1743         int ret = -EINVAL, n;
1744 
1745         fake_cpuc = allocate_fake_cpuc();
1746         if (IS_ERR(fake_cpuc))
1747                 return PTR_ERR(fake_cpuc);
1748         /*
1749          * the event is not yet connected with its
1750          * siblings therefore we must first collect
1751          * existing siblings, then add the new event
1752          * before we can simulate the scheduling
1753          */
1754         n = collect_events(fake_cpuc, leader, true);
1755         if (n < 0)
1756                 goto out;
1757 
1758         fake_cpuc->n_events = n;
1759         n = collect_events(fake_cpuc, event, false);
1760         if (n < 0)
1761                 goto out;
1762 
1763         fake_cpuc->n_events = n;
1764 
1765         ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
1766 
1767 out:
1768         free_fake_cpuc(fake_cpuc);
1769         return ret;
1770 }
1771 
1772 static int x86_pmu_event_init(struct perf_event *event)
1773 {
1774         struct pmu *tmp;
1775         int err;
1776 
1777         switch (event->attr.type) {
1778         case PERF_TYPE_RAW:
1779         case PERF_TYPE_HARDWARE:
1780         case PERF_TYPE_HW_CACHE:
1781                 break;
1782 
1783         default:
1784                 return -ENOENT;
1785         }
1786 
1787         err = __x86_pmu_event_init(event);
1788         if (!err) {
1789                 /*
1790                  * we temporarily connect event to its pmu
1791                  * such that validate_group() can classify
1792                  * it as an x86 event using is_x86_event()
1793                  */
1794                 tmp = event->pmu;
1795                 event->pmu = &pmu;
1796 
1797                 if (event->group_leader != event)
1798                         err = validate_group(event);
1799                 else
1800                         err = validate_event(event);
1801 
1802                 event->pmu = tmp;
1803         }
1804         if (err) {
1805                 if (event->destroy)
1806                         event->destroy(event);
1807         }
1808 
1809         if (ACCESS_ONCE(x86_pmu.attr_rdpmc))
1810                 event->hw.flags |= PERF_X86_EVENT_RDPMC_ALLOWED;
1811 
1812         return err;
1813 }
1814 
1815 static void refresh_pce(void *ignored)
1816 {
1817         if (current->mm)
1818                 load_mm_cr4(current->mm);
1819 }
1820 
1821 static void x86_pmu_event_mapped(struct perf_event *event)
1822 {
1823         if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
1824                 return;
1825 
1826         if (atomic_inc_return(&current->mm->context.perf_rdpmc_allowed) == 1)
1827                 on_each_cpu_mask(mm_cpumask(current->mm), refresh_pce, NULL, 1);
1828 }
1829 
1830 static void x86_pmu_event_unmapped(struct perf_event *event)
1831 {
1832         if (!current->mm)
1833                 return;
1834 
1835         if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
1836                 return;
1837 
1838         if (atomic_dec_and_test(&current->mm->context.perf_rdpmc_allowed))
1839                 on_each_cpu_mask(mm_cpumask(current->mm), refresh_pce, NULL, 1);
1840 }
1841 
1842 static int x86_pmu_event_idx(struct perf_event *event)
1843 {
1844         int idx = event->hw.idx;
1845 
1846         if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
1847                 return 0;
1848 
1849         if (x86_pmu.num_counters_fixed && idx >= INTEL_PMC_IDX_FIXED) {
1850                 idx -= INTEL_PMC_IDX_FIXED;
1851                 idx |= 1 << 30;
1852         }
1853 
1854         return idx + 1;
1855 }
1856 
1857 static ssize_t get_attr_rdpmc(struct device *cdev,
1858                               struct device_attribute *attr,
1859                               char *buf)
1860 {
1861         return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc);
1862 }
1863 
1864 static ssize_t set_attr_rdpmc(struct device *cdev,
1865                               struct device_attribute *attr,
1866                               const char *buf, size_t count)
1867 {
1868         unsigned long val;
1869         ssize_t ret;
1870 
1871         ret = kstrtoul(buf, 0, &val);
1872         if (ret)
1873                 return ret;
1874 
1875         if (val > 2)
1876                 return -EINVAL;
1877 
1878         if (x86_pmu.attr_rdpmc_broken)
1879                 return -ENOTSUPP;
1880 
1881         if ((val == 2) != (x86_pmu.attr_rdpmc == 2)) {
1882                 /*
1883                  * Changing into or out of always available, aka
1884                  * perf-event-bypassing mode.  This path is extremely slow,
1885                  * but only root can trigger it, so it's okay.
1886                  */
1887                 if (val == 2)
1888                         static_key_slow_inc(&rdpmc_always_available);
1889                 else
1890                         static_key_slow_dec(&rdpmc_always_available);
1891                 on_each_cpu(refresh_pce, NULL, 1);
1892         }
1893 
1894         x86_pmu.attr_rdpmc = val;
1895 
1896         return count;
1897 }
1898 
1899 static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc);
1900 
1901 static struct attribute *x86_pmu_attrs[] = {
1902         &dev_attr_rdpmc.attr,
1903         NULL,
1904 };
1905 
1906 static struct attribute_group x86_pmu_attr_group = {
1907         .attrs = x86_pmu_attrs,
1908 };
1909 
1910 static const struct attribute_group *x86_pmu_attr_groups[] = {
1911         &x86_pmu_attr_group,
1912         &x86_pmu_format_group,
1913         &x86_pmu_events_group,
1914         NULL,
1915 };
1916 
1917 static void x86_pmu_flush_branch_stack(void)
1918 {
1919         if (x86_pmu.flush_branch_stack)
1920                 x86_pmu.flush_branch_stack();
1921 }
1922 
1923 void perf_check_microcode(void)
1924 {
1925         if (x86_pmu.check_microcode)
1926                 x86_pmu.check_microcode();
1927 }
1928 EXPORT_SYMBOL_GPL(perf_check_microcode);
1929 
1930 static struct pmu pmu = {
1931         .pmu_enable             = x86_pmu_enable,
1932         .pmu_disable            = x86_pmu_disable,
1933 
1934         .attr_groups            = x86_pmu_attr_groups,
1935 
1936         .event_init             = x86_pmu_event_init,
1937 
1938         .event_mapped           = x86_pmu_event_mapped,
1939         .event_unmapped         = x86_pmu_event_unmapped,
1940 
1941         .add                    = x86_pmu_add,
1942         .del                    = x86_pmu_del,
1943         .start                  = x86_pmu_start,
1944         .stop                   = x86_pmu_stop,
1945         .read                   = x86_pmu_read,
1946 
1947         .start_txn              = x86_pmu_start_txn,
1948         .cancel_txn             = x86_pmu_cancel_txn,
1949         .commit_txn             = x86_pmu_commit_txn,
1950 
1951         .event_idx              = x86_pmu_event_idx,
1952         .flush_branch_stack     = x86_pmu_flush_branch_stack,
1953 };
1954 
1955 void arch_perf_update_userpage(struct perf_event *event,
1956                                struct perf_event_mmap_page *userpg, u64 now)
1957 {
1958         struct cyc2ns_data *data;
1959 
1960         userpg->cap_user_time = 0;
1961         userpg->cap_user_time_zero = 0;
1962         userpg->cap_user_rdpmc =
1963                 !!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED);
1964         userpg->pmc_width = x86_pmu.cntval_bits;
1965 
1966         if (!sched_clock_stable())
1967                 return;
1968 
1969         data = cyc2ns_read_begin();
1970 
1971         userpg->cap_user_time = 1;
1972         userpg->time_mult = data->cyc2ns_mul;
1973         userpg->time_shift = data->cyc2ns_shift;
1974         userpg->time_offset = data->cyc2ns_offset - now;
1975 
1976         userpg->cap_user_time_zero = 1;
1977         userpg->time_zero = data->cyc2ns_offset;
1978 
1979         cyc2ns_read_end(data);
1980 }
1981 
1982 /*
1983  * callchain support
1984  */
1985 
1986 static int backtrace_stack(void *data, char *name)
1987 {
1988         return 0;
1989 }
1990 
1991 static void backtrace_address(void *data, unsigned long addr, int reliable)
1992 {
1993         struct perf_callchain_entry *entry = data;
1994 
1995         perf_callchain_store(entry, addr);
1996 }
1997 
1998 static const struct stacktrace_ops backtrace_ops = {
1999         .stack                  = backtrace_stack,
2000         .address                = backtrace_address,
2001         .walk_stack             = print_context_stack_bp,
2002 };
2003 
2004 void
2005 perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
2006 {
2007         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2008                 /* TODO: We don't support guest os callchain now */
2009                 return;
2010         }
2011 
2012         perf_callchain_store(entry, regs->ip);
2013 
2014         dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry);
2015 }
2016 
2017 static inline int
2018 valid_user_frame(const void __user *fp, unsigned long size)
2019 {
2020         return (__range_not_ok(fp, size, TASK_SIZE) == 0);
2021 }
2022 
2023 static unsigned long get_segment_base(unsigned int segment)
2024 {
2025         struct desc_struct *desc;
2026         int idx = segment >> 3;
2027 
2028         if ((segment & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2029                 if (idx > LDT_ENTRIES)
2030                         return 0;
2031 
2032                 if (idx > current->active_mm->context.size)
2033                         return 0;
2034 
2035                 desc = current->active_mm->context.ldt;
2036         } else {
2037                 if (idx > GDT_ENTRIES)
2038                         return 0;
2039 
2040                 desc = raw_cpu_ptr(gdt_page.gdt);
2041         }
2042 
2043         return get_desc_base(desc + idx);
2044 }
2045 
2046 #ifdef CONFIG_COMPAT
2047 
2048 #include <asm/compat.h>
2049 
2050 static inline int
2051 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
2052 {
2053         /* 32-bit process in 64-bit kernel. */
2054         unsigned long ss_base, cs_base;
2055         struct stack_frame_ia32 frame;
2056         const void __user *fp;
2057 
2058         if (!test_thread_flag(TIF_IA32))
2059                 return 0;
2060 
2061         cs_base = get_segment_base(regs->cs);
2062         ss_base = get_segment_base(regs->ss);
2063 
2064         fp = compat_ptr(ss_base + regs->bp);
2065         while (entry->nr < PERF_MAX_STACK_DEPTH) {
2066                 unsigned long bytes;
2067                 frame.next_frame     = 0;
2068                 frame.return_address = 0;
2069 
2070                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
2071                 if (bytes != 0)
2072                         break;
2073 
2074                 if (!valid_user_frame(fp, sizeof(frame)))
2075                         break;
2076 
2077                 perf_callchain_store(entry, cs_base + frame.return_address);
2078                 fp = compat_ptr(ss_base + frame.next_frame);
2079         }
2080         return 1;
2081 }
2082 #else
2083 static inline int
2084 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
2085 {
2086     return 0;
2087 }
2088 #endif
2089 
2090 void
2091 perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
2092 {
2093         struct stack_frame frame;
2094         const void __user *fp;
2095 
2096         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2097                 /* TODO: We don't support guest os callchain now */
2098                 return;
2099         }
2100 
2101         /*
2102          * We don't know what to do with VM86 stacks.. ignore them for now.
2103          */
2104         if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM))
2105                 return;
2106 
2107         fp = (void __user *)regs->bp;
2108 
2109         perf_callchain_store(entry, regs->ip);
2110 
2111         if (!current->mm)
2112                 return;
2113 
2114         if (perf_callchain_user32(regs, entry))
2115                 return;
2116 
2117         while (entry->nr < PERF_MAX_STACK_DEPTH) {
2118                 unsigned long bytes;
2119                 frame.next_frame             = NULL;
2120                 frame.return_address = 0;
2121 
2122                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
2123                 if (bytes != 0)
2124                         break;
2125 
2126                 if (!valid_user_frame(fp, sizeof(frame)))
2127                         break;
2128 
2129                 perf_callchain_store(entry, frame.return_address);
2130                 fp = frame.next_frame;
2131         }
2132 }
2133 
2134 /*
2135  * Deal with code segment offsets for the various execution modes:
2136  *
2137  *   VM86 - the good olde 16 bit days, where the linear address is
2138  *          20 bits and we use regs->ip + 0x10 * regs->cs.
2139  *
2140  *   IA32 - Where we need to look at GDT/LDT segment descriptor tables
2141  *          to figure out what the 32bit base address is.
2142  *
2143  *    X32 - has TIF_X32 set, but is running in x86_64
2144  *
2145  * X86_64 - CS,DS,SS,ES are all zero based.
2146  */
2147 static unsigned long code_segment_base(struct pt_regs *regs)
2148 {
2149         /*
2150          * If we are in VM86 mode, add the segment offset to convert to a
2151          * linear address.
2152          */
2153         if (regs->flags & X86_VM_MASK)
2154                 return 0x10 * regs->cs;
2155 
2156         /*
2157          * For IA32 we look at the GDT/LDT segment base to convert the
2158          * effective IP to a linear address.
2159          */
2160 #ifdef CONFIG_X86_32
2161         if (user_mode(regs) && regs->cs != __USER_CS)
2162                 return get_segment_base(regs->cs);
2163 #else
2164         if (test_thread_flag(TIF_IA32)) {
2165                 if (user_mode(regs) && regs->cs != __USER32_CS)
2166                         return get_segment_base(regs->cs);
2167         }
2168 #endif
2169         return 0;
2170 }
2171 
2172 unsigned long perf_instruction_pointer(struct pt_regs *regs)
2173 {
2174         if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
2175                 return perf_guest_cbs->get_guest_ip();
2176 
2177         return regs->ip + code_segment_base(regs);
2178 }
2179 
2180 unsigned long perf_misc_flags(struct pt_regs *regs)
2181 {
2182         int misc = 0;
2183 
2184         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2185                 if (perf_guest_cbs->is_user_mode())
2186                         misc |= PERF_RECORD_MISC_GUEST_USER;
2187                 else
2188                         misc |= PERF_RECORD_MISC_GUEST_KERNEL;
2189         } else {
2190                 if (user_mode(regs))
2191                         misc |= PERF_RECORD_MISC_USER;
2192                 else
2193                         misc |= PERF_RECORD_MISC_KERNEL;
2194         }
2195 
2196         if (regs->flags & PERF_EFLAGS_EXACT)
2197                 misc |= PERF_RECORD_MISC_EXACT_IP;
2198 
2199         return misc;
2200 }
2201 
2202 void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
2203 {
2204         cap->version            = x86_pmu.version;
2205         cap->num_counters_gp    = x86_pmu.num_counters;
2206         cap->num_counters_fixed = x86_pmu.num_counters_fixed;
2207         cap->bit_width_gp       = x86_pmu.cntval_bits;
2208         cap->bit_width_fixed    = x86_pmu.cntval_bits;
2209         cap->events_mask        = (unsigned int)x86_pmu.events_maskl;
2210         cap->events_mask_len    = x86_pmu.events_mask_len;
2211 }
2212 EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability);
2213 

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