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TOMOYO Linux Cross Reference
Linux/arch/x86/kernel/cpu/perf_event_intel_ds.c

Version: ~ [ linux-5.5-rc7 ] ~ [ linux-5.4.13 ] ~ [ linux-5.3.18 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.97 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.166 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.210 ] ~ [ linux-4.8.17 ] ~ [ linux-4.7.10 ] ~ [ linux-4.6.7 ] ~ [ linux-4.5.7 ] ~ [ linux-4.4.210 ] ~ [ linux-4.3.6 ] ~ [ linux-4.2.8 ] ~ [ linux-4.1.52 ] ~ [ linux-4.0.9 ] ~ [ linux-3.19.8 ] ~ [ linux-3.18.140 ] ~ [ linux-3.17.8 ] ~ [ linux-3.16.81 ] ~ [ linux-3.15.10 ] ~ [ linux-3.14.79 ] ~ [ linux-3.13.11 ] ~ [ linux-3.12.74 ] ~ [ linux-3.11.10 ] ~ [ linux-3.10.108 ] ~ [ linux-3.9.11 ] ~ [ linux-3.8.13 ] ~ [ linux-3.7.10 ] ~ [ linux-3.6.11 ] ~ [ linux-3.5.7 ] ~ [ linux-3.4.113 ] ~ [ linux-3.3.8 ] ~ [ linux-3.2.102 ] ~ [ linux-3.1.10 ] ~ [ linux-3.0.101 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.5 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 #include <linux/bitops.h>
  2 #include <linux/types.h>
  3 #include <linux/slab.h>
  4 
  5 #include <asm/perf_event.h>
  6 #include <asm/insn.h>
  7 
  8 #include "perf_event.h"
  9 
 10 /* The size of a BTS record in bytes: */
 11 #define BTS_RECORD_SIZE         24
 12 
 13 #define BTS_BUFFER_SIZE         (PAGE_SIZE << 4)
 14 #define PEBS_BUFFER_SIZE        PAGE_SIZE
 15 
 16 /*
 17  * pebs_record_32 for p4 and core not supported
 18 
 19 struct pebs_record_32 {
 20         u32 flags, ip;
 21         u32 ax, bc, cx, dx;
 22         u32 si, di, bp, sp;
 23 };
 24 
 25  */
 26 
 27 union intel_x86_pebs_dse {
 28         u64 val;
 29         struct {
 30                 unsigned int ld_dse:4;
 31                 unsigned int ld_stlb_miss:1;
 32                 unsigned int ld_locked:1;
 33                 unsigned int ld_reserved:26;
 34         };
 35         struct {
 36                 unsigned int st_l1d_hit:1;
 37                 unsigned int st_reserved1:3;
 38                 unsigned int st_stlb_miss:1;
 39                 unsigned int st_locked:1;
 40                 unsigned int st_reserved2:26;
 41         };
 42 };
 43 
 44 
 45 /*
 46  * Map PEBS Load Latency Data Source encodings to generic
 47  * memory data source information
 48  */
 49 #define P(a, b) PERF_MEM_S(a, b)
 50 #define OP_LH (P(OP, LOAD) | P(LVL, HIT))
 51 #define SNOOP_NONE_MISS (P(SNOOP, NONE) | P(SNOOP, MISS))
 52 
 53 /* Version for Sandy Bridge and later */
 54 static u64 pebs_data_source[] = {
 55         P(OP, LOAD) | P(LVL, MISS) | P(LVL, L3) | P(SNOOP, NA),/* 0x00:ukn L3 */
 56         OP_LH | P(LVL, L1)  | P(SNOOP, NONE),   /* 0x01: L1 local */
 57         OP_LH | P(LVL, LFB) | P(SNOOP, NONE),   /* 0x02: LFB hit */
 58         OP_LH | P(LVL, L2)  | P(SNOOP, NONE),   /* 0x03: L2 hit */
 59         OP_LH | P(LVL, L3)  | P(SNOOP, NONE),   /* 0x04: L3 hit */
 60         OP_LH | P(LVL, L3)  | P(SNOOP, MISS),   /* 0x05: L3 hit, snoop miss */
 61         OP_LH | P(LVL, L3)  | P(SNOOP, HIT),    /* 0x06: L3 hit, snoop hit */
 62         OP_LH | P(LVL, L3)  | P(SNOOP, HITM),   /* 0x07: L3 hit, snoop hitm */
 63         OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HIT),  /* 0x08: L3 miss snoop hit */
 64         OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HITM), /* 0x09: L3 miss snoop hitm*/
 65         OP_LH | P(LVL, LOC_RAM)  | P(SNOOP, HIT),  /* 0x0a: L3 miss, shared */
 66         OP_LH | P(LVL, REM_RAM1) | P(SNOOP, HIT),  /* 0x0b: L3 miss, shared */
 67         OP_LH | P(LVL, LOC_RAM)  | SNOOP_NONE_MISS,/* 0x0c: L3 miss, excl */
 68         OP_LH | P(LVL, REM_RAM1) | SNOOP_NONE_MISS,/* 0x0d: L3 miss, excl */
 69         OP_LH | P(LVL, IO)  | P(SNOOP, NONE), /* 0x0e: I/O */
 70         OP_LH | P(LVL, UNC) | P(SNOOP, NONE), /* 0x0f: uncached */
 71 };
 72 
 73 /* Patch up minor differences in the bits */
 74 void __init intel_pmu_pebs_data_source_nhm(void)
 75 {
 76         pebs_data_source[0x05] = OP_LH | P(LVL, L3)  | P(SNOOP, HIT);
 77         pebs_data_source[0x06] = OP_LH | P(LVL, L3)  | P(SNOOP, HITM);
 78         pebs_data_source[0x07] = OP_LH | P(LVL, L3)  | P(SNOOP, HITM);
 79 }
 80 
 81 static u64 precise_store_data(u64 status)
 82 {
 83         union intel_x86_pebs_dse dse;
 84         u64 val = P(OP, STORE) | P(SNOOP, NA) | P(LVL, L1) | P(TLB, L2);
 85 
 86         dse.val = status;
 87 
 88         /*
 89          * bit 4: TLB access
 90          * 1 = stored missed 2nd level TLB
 91          *
 92          * so it either hit the walker or the OS
 93          * otherwise hit 2nd level TLB
 94          */
 95         if (dse.st_stlb_miss)
 96                 val |= P(TLB, MISS);
 97         else
 98                 val |= P(TLB, HIT);
 99 
100         /*
101          * bit 0: hit L1 data cache
102          * if not set, then all we know is that
103          * it missed L1D
104          */
105         if (dse.st_l1d_hit)
106                 val |= P(LVL, HIT);
107         else
108                 val |= P(LVL, MISS);
109 
110         /*
111          * bit 5: Locked prefix
112          */
113         if (dse.st_locked)
114                 val |= P(LOCK, LOCKED);
115 
116         return val;
117 }
118 
119 static u64 precise_store_data_hsw(u64 status)
120 {
121         union perf_mem_data_src dse;
122 
123         dse.val = 0;
124         dse.mem_op = PERF_MEM_OP_STORE;
125         dse.mem_lvl = PERF_MEM_LVL_NA;
126         if (status & 1)
127                 dse.mem_lvl = PERF_MEM_LVL_L1;
128         /* Nothing else supported. Sorry. */
129         return dse.val;
130 }
131 
132 static u64 load_latency_data(u64 status)
133 {
134         union intel_x86_pebs_dse dse;
135         u64 val;
136         int model = boot_cpu_data.x86_model;
137         int fam = boot_cpu_data.x86;
138 
139         dse.val = status;
140 
141         /*
142          * use the mapping table for bit 0-3
143          */
144         val = pebs_data_source[dse.ld_dse];
145 
146         /*
147          * Nehalem models do not support TLB, Lock infos
148          */
149         if (fam == 0x6 && (model == 26 || model == 30
150             || model == 31 || model == 46)) {
151                 val |= P(TLB, NA) | P(LOCK, NA);
152                 return val;
153         }
154         /*
155          * bit 4: TLB access
156          * 0 = did not miss 2nd level TLB
157          * 1 = missed 2nd level TLB
158          */
159         if (dse.ld_stlb_miss)
160                 val |= P(TLB, MISS) | P(TLB, L2);
161         else
162                 val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2);
163 
164         /*
165          * bit 5: locked prefix
166          */
167         if (dse.ld_locked)
168                 val |= P(LOCK, LOCKED);
169 
170         return val;
171 }
172 
173 struct pebs_record_core {
174         u64 flags, ip;
175         u64 ax, bx, cx, dx;
176         u64 si, di, bp, sp;
177         u64 r8,  r9,  r10, r11;
178         u64 r12, r13, r14, r15;
179 };
180 
181 struct pebs_record_nhm {
182         u64 flags, ip;
183         u64 ax, bx, cx, dx;
184         u64 si, di, bp, sp;
185         u64 r8,  r9,  r10, r11;
186         u64 r12, r13, r14, r15;
187         u64 status, dla, dse, lat;
188 };
189 
190 /*
191  * Same as pebs_record_nhm, with two additional fields.
192  */
193 struct pebs_record_hsw {
194         struct pebs_record_nhm nhm;
195         /*
196          * Real IP of the event. In the Intel documentation this
197          * is called eventingrip.
198          */
199         u64 real_ip;
200         /*
201          * TSX tuning information field: abort cycles and abort flags.
202          */
203         u64 tsx_tuning;
204 };
205 
206 void init_debug_store_on_cpu(int cpu)
207 {
208         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
209 
210         if (!ds)
211                 return;
212 
213         wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA,
214                      (u32)((u64)(unsigned long)ds),
215                      (u32)((u64)(unsigned long)ds >> 32));
216 }
217 
218 void fini_debug_store_on_cpu(int cpu)
219 {
220         if (!per_cpu(cpu_hw_events, cpu).ds)
221                 return;
222 
223         wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0);
224 }
225 
226 static int alloc_pebs_buffer(int cpu)
227 {
228         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
229         int node = cpu_to_node(cpu);
230         int max, thresh = 1; /* always use a single PEBS record */
231         void *buffer;
232 
233         if (!x86_pmu.pebs)
234                 return 0;
235 
236         buffer = kzalloc_node(x86_pmu.pebs_buffer_size, GFP_KERNEL, node);
237         if (unlikely(!buffer))
238                 return -ENOMEM;
239 
240         max = x86_pmu.pebs_buffer_size / x86_pmu.pebs_record_size;
241 
242         ds->pebs_buffer_base = (u64)(unsigned long)buffer;
243         ds->pebs_index = ds->pebs_buffer_base;
244         ds->pebs_absolute_maximum = ds->pebs_buffer_base +
245                 max * x86_pmu.pebs_record_size;
246 
247         ds->pebs_interrupt_threshold = ds->pebs_buffer_base +
248                 thresh * x86_pmu.pebs_record_size;
249 
250         return 0;
251 }
252 
253 static void release_pebs_buffer(int cpu)
254 {
255         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
256 
257         if (!ds || !x86_pmu.pebs)
258                 return;
259 
260         kfree((void *)(unsigned long)ds->pebs_buffer_base);
261         ds->pebs_buffer_base = 0;
262 }
263 
264 static int alloc_bts_buffer(int cpu)
265 {
266         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
267         int node = cpu_to_node(cpu);
268         int max, thresh;
269         void *buffer;
270 
271         if (!x86_pmu.bts)
272                 return 0;
273 
274         buffer = kzalloc_node(BTS_BUFFER_SIZE, GFP_KERNEL, node);
275         if (unlikely(!buffer))
276                 return -ENOMEM;
277 
278         max = BTS_BUFFER_SIZE / BTS_RECORD_SIZE;
279         thresh = max / 16;
280 
281         ds->bts_buffer_base = (u64)(unsigned long)buffer;
282         ds->bts_index = ds->bts_buffer_base;
283         ds->bts_absolute_maximum = ds->bts_buffer_base +
284                 max * BTS_RECORD_SIZE;
285         ds->bts_interrupt_threshold = ds->bts_absolute_maximum -
286                 thresh * BTS_RECORD_SIZE;
287 
288         return 0;
289 }
290 
291 static void release_bts_buffer(int cpu)
292 {
293         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
294 
295         if (!ds || !x86_pmu.bts)
296                 return;
297 
298         kfree((void *)(unsigned long)ds->bts_buffer_base);
299         ds->bts_buffer_base = 0;
300 }
301 
302 static int alloc_ds_buffer(int cpu)
303 {
304         int node = cpu_to_node(cpu);
305         struct debug_store *ds;
306 
307         ds = kzalloc_node(sizeof(*ds), GFP_KERNEL, node);
308         if (unlikely(!ds))
309                 return -ENOMEM;
310 
311         per_cpu(cpu_hw_events, cpu).ds = ds;
312 
313         return 0;
314 }
315 
316 static void release_ds_buffer(int cpu)
317 {
318         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
319 
320         if (!ds)
321                 return;
322 
323         per_cpu(cpu_hw_events, cpu).ds = NULL;
324         kfree(ds);
325 }
326 
327 void release_ds_buffers(void)
328 {
329         int cpu;
330 
331         if (!x86_pmu.bts && !x86_pmu.pebs)
332                 return;
333 
334         get_online_cpus();
335         for_each_online_cpu(cpu)
336                 fini_debug_store_on_cpu(cpu);
337 
338         for_each_possible_cpu(cpu) {
339                 release_pebs_buffer(cpu);
340                 release_bts_buffer(cpu);
341                 release_ds_buffer(cpu);
342         }
343         put_online_cpus();
344 }
345 
346 void reserve_ds_buffers(void)
347 {
348         int bts_err = 0, pebs_err = 0;
349         int cpu;
350 
351         x86_pmu.bts_active = 0;
352         x86_pmu.pebs_active = 0;
353 
354         if (!x86_pmu.bts && !x86_pmu.pebs)
355                 return;
356 
357         if (!x86_pmu.bts)
358                 bts_err = 1;
359 
360         if (!x86_pmu.pebs)
361                 pebs_err = 1;
362 
363         get_online_cpus();
364 
365         for_each_possible_cpu(cpu) {
366                 if (alloc_ds_buffer(cpu)) {
367                         bts_err = 1;
368                         pebs_err = 1;
369                 }
370 
371                 if (!bts_err && alloc_bts_buffer(cpu))
372                         bts_err = 1;
373 
374                 if (!pebs_err && alloc_pebs_buffer(cpu))
375                         pebs_err = 1;
376 
377                 if (bts_err && pebs_err)
378                         break;
379         }
380 
381         if (bts_err) {
382                 for_each_possible_cpu(cpu)
383                         release_bts_buffer(cpu);
384         }
385 
386         if (pebs_err) {
387                 for_each_possible_cpu(cpu)
388                         release_pebs_buffer(cpu);
389         }
390 
391         if (bts_err && pebs_err) {
392                 for_each_possible_cpu(cpu)
393                         release_ds_buffer(cpu);
394         } else {
395                 if (x86_pmu.bts && !bts_err)
396                         x86_pmu.bts_active = 1;
397 
398                 if (x86_pmu.pebs && !pebs_err)
399                         x86_pmu.pebs_active = 1;
400 
401                 for_each_online_cpu(cpu)
402                         init_debug_store_on_cpu(cpu);
403         }
404 
405         put_online_cpus();
406 }
407 
408 /*
409  * BTS
410  */
411 
412 struct event_constraint bts_constraint =
413         EVENT_CONSTRAINT(0, 1ULL << INTEL_PMC_IDX_FIXED_BTS, 0);
414 
415 void intel_pmu_enable_bts(u64 config)
416 {
417         unsigned long debugctlmsr;
418 
419         debugctlmsr = get_debugctlmsr();
420 
421         debugctlmsr |= DEBUGCTLMSR_TR;
422         debugctlmsr |= DEBUGCTLMSR_BTS;
423         debugctlmsr |= DEBUGCTLMSR_BTINT;
424 
425         if (!(config & ARCH_PERFMON_EVENTSEL_OS))
426                 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_OS;
427 
428         if (!(config & ARCH_PERFMON_EVENTSEL_USR))
429                 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_USR;
430 
431         update_debugctlmsr(debugctlmsr);
432 }
433 
434 void intel_pmu_disable_bts(void)
435 {
436         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
437         unsigned long debugctlmsr;
438 
439         if (!cpuc->ds)
440                 return;
441 
442         debugctlmsr = get_debugctlmsr();
443 
444         debugctlmsr &=
445                 ~(DEBUGCTLMSR_TR | DEBUGCTLMSR_BTS | DEBUGCTLMSR_BTINT |
446                   DEBUGCTLMSR_BTS_OFF_OS | DEBUGCTLMSR_BTS_OFF_USR);
447 
448         update_debugctlmsr(debugctlmsr);
449 }
450 
451 int intel_pmu_drain_bts_buffer(void)
452 {
453         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
454         struct debug_store *ds = cpuc->ds;
455         struct bts_record {
456                 u64     from;
457                 u64     to;
458                 u64     flags;
459         };
460         struct perf_event *event = cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
461         struct bts_record *at, *top;
462         struct perf_output_handle handle;
463         struct perf_event_header header;
464         struct perf_sample_data data;
465         struct pt_regs regs;
466 
467         if (!event)
468                 return 0;
469 
470         if (!x86_pmu.bts_active)
471                 return 0;
472 
473         at  = (struct bts_record *)(unsigned long)ds->bts_buffer_base;
474         top = (struct bts_record *)(unsigned long)ds->bts_index;
475 
476         if (top <= at)
477                 return 0;
478 
479         memset(&regs, 0, sizeof(regs));
480 
481         ds->bts_index = ds->bts_buffer_base;
482 
483         perf_sample_data_init(&data, 0, event->hw.last_period);
484 
485         /*
486          * Prepare a generic sample, i.e. fill in the invariant fields.
487          * We will overwrite the from and to address before we output
488          * the sample.
489          */
490         perf_prepare_sample(&header, &data, event, &regs);
491 
492         if (perf_output_begin(&handle, event, header.size * (top - at)))
493                 return 1;
494 
495         for (; at < top; at++) {
496                 data.ip         = at->from;
497                 data.addr       = at->to;
498 
499                 perf_output_sample(&handle, &header, &data, event);
500         }
501 
502         perf_output_end(&handle);
503 
504         /* There's new data available. */
505         event->hw.interrupts++;
506         event->pending_kill = POLL_IN;
507         return 1;
508 }
509 
510 /*
511  * PEBS
512  */
513 struct event_constraint intel_core2_pebs_event_constraints[] = {
514         INTEL_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
515         INTEL_UEVENT_CONSTRAINT(0xfec1, 0x1), /* X87_OPS_RETIRED.ANY */
516         INTEL_UEVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */
517         INTEL_UEVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */
518         INTEL_EVENT_CONSTRAINT(0xcb, 0x1),    /* MEM_LOAD_RETIRED.* */
519         EVENT_CONSTRAINT_END
520 };
521 
522 struct event_constraint intel_atom_pebs_event_constraints[] = {
523         INTEL_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
524         INTEL_UEVENT_CONSTRAINT(0x00c5, 0x1), /* MISPREDICTED_BRANCH_RETIRED */
525         INTEL_EVENT_CONSTRAINT(0xcb, 0x1),    /* MEM_LOAD_RETIRED.* */
526         EVENT_CONSTRAINT_END
527 };
528 
529 struct event_constraint intel_slm_pebs_event_constraints[] = {
530         INTEL_UEVENT_CONSTRAINT(0x0103, 0x1), /* REHABQ.LD_BLOCK_ST_FORWARD_PS */
531         INTEL_UEVENT_CONSTRAINT(0x0803, 0x1), /* REHABQ.LD_SPLITS_PS */
532         INTEL_UEVENT_CONSTRAINT(0x0204, 0x1), /* MEM_UOPS_RETIRED.L2_HIT_LOADS_PS */
533         INTEL_UEVENT_CONSTRAINT(0x0404, 0x1), /* MEM_UOPS_RETIRED.L2_MISS_LOADS_PS */
534         INTEL_UEVENT_CONSTRAINT(0x0804, 0x1), /* MEM_UOPS_RETIRED.DTLB_MISS_LOADS_PS */
535         INTEL_UEVENT_CONSTRAINT(0x2004, 0x1), /* MEM_UOPS_RETIRED.HITM_PS */
536         INTEL_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY_PS */
537         INTEL_UEVENT_CONSTRAINT(0x00c4, 0x1), /* BR_INST_RETIRED.ALL_BRANCHES_PS */
538         INTEL_UEVENT_CONSTRAINT(0x7ec4, 0x1), /* BR_INST_RETIRED.JCC_PS */
539         INTEL_UEVENT_CONSTRAINT(0xbfc4, 0x1), /* BR_INST_RETIRED.FAR_BRANCH_PS */
540         INTEL_UEVENT_CONSTRAINT(0xebc4, 0x1), /* BR_INST_RETIRED.NON_RETURN_IND_PS */
541         INTEL_UEVENT_CONSTRAINT(0xf7c4, 0x1), /* BR_INST_RETIRED.RETURN_PS */
542         INTEL_UEVENT_CONSTRAINT(0xf9c4, 0x1), /* BR_INST_RETIRED.CALL_PS */
543         INTEL_UEVENT_CONSTRAINT(0xfbc4, 0x1), /* BR_INST_RETIRED.IND_CALL_PS */
544         INTEL_UEVENT_CONSTRAINT(0xfdc4, 0x1), /* BR_INST_RETIRED.REL_CALL_PS */
545         INTEL_UEVENT_CONSTRAINT(0xfec4, 0x1), /* BR_INST_RETIRED.TAKEN_JCC_PS */
546         INTEL_UEVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_MISP_RETIRED.ALL_BRANCHES_PS */
547         INTEL_UEVENT_CONSTRAINT(0x7ec5, 0x1), /* BR_INST_MISP_RETIRED.JCC_PS */
548         INTEL_UEVENT_CONSTRAINT(0xebc5, 0x1), /* BR_INST_MISP_RETIRED.NON_RETURN_IND_PS */
549         INTEL_UEVENT_CONSTRAINT(0xf7c5, 0x1), /* BR_INST_MISP_RETIRED.RETURN_PS */
550         INTEL_UEVENT_CONSTRAINT(0xfbc5, 0x1), /* BR_INST_MISP_RETIRED.IND_CALL_PS */
551         INTEL_UEVENT_CONSTRAINT(0xfec5, 0x1), /* BR_INST_MISP_RETIRED.TAKEN_JCC_PS */
552         EVENT_CONSTRAINT_END
553 };
554 
555 struct event_constraint intel_nehalem_pebs_event_constraints[] = {
556         INTEL_PLD_CONSTRAINT(0x100b, 0xf),      /* MEM_INST_RETIRED.* */
557         INTEL_EVENT_CONSTRAINT(0x0f, 0xf),    /* MEM_UNCORE_RETIRED.* */
558         INTEL_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
559         INTEL_EVENT_CONSTRAINT(0xc0, 0xf),    /* INST_RETIRED.ANY */
560         INTEL_EVENT_CONSTRAINT(0xc2, 0xf),    /* UOPS_RETIRED.* */
561         INTEL_EVENT_CONSTRAINT(0xc4, 0xf),    /* BR_INST_RETIRED.* */
562         INTEL_UEVENT_CONSTRAINT(0x02c5, 0xf), /* BR_MISP_RETIRED.NEAR_CALL */
563         INTEL_EVENT_CONSTRAINT(0xc7, 0xf),    /* SSEX_UOPS_RETIRED.* */
564         INTEL_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
565         INTEL_EVENT_CONSTRAINT(0xcb, 0xf),    /* MEM_LOAD_RETIRED.* */
566         INTEL_EVENT_CONSTRAINT(0xf7, 0xf),    /* FP_ASSIST.* */
567         EVENT_CONSTRAINT_END
568 };
569 
570 struct event_constraint intel_westmere_pebs_event_constraints[] = {
571         INTEL_PLD_CONSTRAINT(0x100b, 0xf),      /* MEM_INST_RETIRED.* */
572         INTEL_EVENT_CONSTRAINT(0x0f, 0xf),    /* MEM_UNCORE_RETIRED.* */
573         INTEL_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
574         INTEL_EVENT_CONSTRAINT(0xc0, 0xf),    /* INSTR_RETIRED.* */
575         INTEL_EVENT_CONSTRAINT(0xc2, 0xf),    /* UOPS_RETIRED.* */
576         INTEL_EVENT_CONSTRAINT(0xc4, 0xf),    /* BR_INST_RETIRED.* */
577         INTEL_EVENT_CONSTRAINT(0xc5, 0xf),    /* BR_MISP_RETIRED.* */
578         INTEL_EVENT_CONSTRAINT(0xc7, 0xf),    /* SSEX_UOPS_RETIRED.* */
579         INTEL_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
580         INTEL_EVENT_CONSTRAINT(0xcb, 0xf),    /* MEM_LOAD_RETIRED.* */
581         INTEL_EVENT_CONSTRAINT(0xf7, 0xf),    /* FP_ASSIST.* */
582         EVENT_CONSTRAINT_END
583 };
584 
585 struct event_constraint intel_snb_pebs_event_constraints[] = {
586         INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
587         INTEL_UEVENT_CONSTRAINT(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
588         INTEL_UEVENT_CONSTRAINT(0x02c2, 0xf), /* UOPS_RETIRED.RETIRE_SLOTS */
589         INTEL_EVENT_CONSTRAINT(0xc4, 0xf),    /* BR_INST_RETIRED.* */
590         INTEL_EVENT_CONSTRAINT(0xc5, 0xf),    /* BR_MISP_RETIRED.* */
591         INTEL_PLD_CONSTRAINT(0x01cd, 0x8),    /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
592         INTEL_PST_CONSTRAINT(0x02cd, 0x8),    /* MEM_TRANS_RETIRED.PRECISE_STORES */
593         INTEL_EVENT_CONSTRAINT(0xd0, 0xf),    /* MEM_UOP_RETIRED.* */
594         INTEL_EVENT_CONSTRAINT(0xd1, 0xf),    /* MEM_LOAD_UOPS_RETIRED.* */
595         INTEL_EVENT_CONSTRAINT(0xd2, 0xf),    /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
596         INTEL_EVENT_CONSTRAINT(0xd3, 0xf),    /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
597         INTEL_UEVENT_CONSTRAINT(0x02d4, 0xf), /* MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS */
598         EVENT_CONSTRAINT_END
599 };
600 
601 struct event_constraint intel_ivb_pebs_event_constraints[] = {
602         INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
603         INTEL_UEVENT_CONSTRAINT(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
604         INTEL_UEVENT_CONSTRAINT(0x02c2, 0xf), /* UOPS_RETIRED.RETIRE_SLOTS */
605         INTEL_EVENT_CONSTRAINT(0xc4, 0xf),    /* BR_INST_RETIRED.* */
606         INTEL_EVENT_CONSTRAINT(0xc5, 0xf),    /* BR_MISP_RETIRED.* */
607         INTEL_PLD_CONSTRAINT(0x01cd, 0x8),    /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
608         INTEL_PST_CONSTRAINT(0x02cd, 0x8),    /* MEM_TRANS_RETIRED.PRECISE_STORES */
609         INTEL_EVENT_CONSTRAINT(0xd0, 0xf),    /* MEM_UOP_RETIRED.* */
610         INTEL_EVENT_CONSTRAINT(0xd1, 0xf),    /* MEM_LOAD_UOPS_RETIRED.* */
611         INTEL_EVENT_CONSTRAINT(0xd2, 0xf),    /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
612         INTEL_EVENT_CONSTRAINT(0xd3, 0xf),    /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
613         EVENT_CONSTRAINT_END
614 };
615 
616 struct event_constraint intel_hsw_pebs_event_constraints[] = {
617         INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
618         INTEL_PST_HSW_CONSTRAINT(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
619         INTEL_UEVENT_CONSTRAINT(0x02c2, 0xf), /* UOPS_RETIRED.RETIRE_SLOTS */
620         INTEL_EVENT_CONSTRAINT(0xc4, 0xf),    /* BR_INST_RETIRED.* */
621         INTEL_UEVENT_CONSTRAINT(0x01c5, 0xf), /* BR_MISP_RETIRED.CONDITIONAL */
622         INTEL_UEVENT_CONSTRAINT(0x04c5, 0xf), /* BR_MISP_RETIRED.ALL_BRANCHES */
623         INTEL_UEVENT_CONSTRAINT(0x20c5, 0xf), /* BR_MISP_RETIRED.NEAR_TAKEN */
624         INTEL_PLD_CONSTRAINT(0x01cd, 0x8),    /* MEM_TRANS_RETIRED.* */
625         /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
626         INTEL_UEVENT_CONSTRAINT(0x11d0, 0xf),
627         /* MEM_UOPS_RETIRED.STLB_MISS_STORES */
628         INTEL_UEVENT_CONSTRAINT(0x12d0, 0xf),
629         INTEL_UEVENT_CONSTRAINT(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
630         INTEL_UEVENT_CONSTRAINT(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */
631         /* MEM_UOPS_RETIRED.SPLIT_STORES */
632         INTEL_UEVENT_CONSTRAINT(0x42d0, 0xf),
633         INTEL_UEVENT_CONSTRAINT(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */
634         INTEL_PST_HSW_CONSTRAINT(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */
635         INTEL_UEVENT_CONSTRAINT(0x01d1, 0xf), /* MEM_LOAD_UOPS_RETIRED.L1_HIT */
636         INTEL_UEVENT_CONSTRAINT(0x02d1, 0xf), /* MEM_LOAD_UOPS_RETIRED.L2_HIT */
637         INTEL_UEVENT_CONSTRAINT(0x04d1, 0xf), /* MEM_LOAD_UOPS_RETIRED.L3_HIT */
638         /* MEM_LOAD_UOPS_RETIRED.HIT_LFB */
639         INTEL_UEVENT_CONSTRAINT(0x40d1, 0xf),
640         /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS */
641         INTEL_UEVENT_CONSTRAINT(0x01d2, 0xf),
642         /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT */
643         INTEL_UEVENT_CONSTRAINT(0x02d2, 0xf),
644         /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM */
645         INTEL_UEVENT_CONSTRAINT(0x01d3, 0xf),
646         INTEL_UEVENT_CONSTRAINT(0x04c8, 0xf), /* HLE_RETIRED.Abort */
647         INTEL_UEVENT_CONSTRAINT(0x04c9, 0xf), /* RTM_RETIRED.Abort */
648 
649         EVENT_CONSTRAINT_END
650 };
651 
652 struct event_constraint *intel_pebs_constraints(struct perf_event *event)
653 {
654         struct event_constraint *c;
655 
656         if (!event->attr.precise_ip)
657                 return NULL;
658 
659         if (x86_pmu.pebs_constraints) {
660                 for_each_event_constraint(c, x86_pmu.pebs_constraints) {
661                         if ((event->hw.config & c->cmask) == c->code) {
662                                 event->hw.flags |= c->flags;
663                                 return c;
664                         }
665                 }
666         }
667 
668         return &emptyconstraint;
669 }
670 
671 void intel_pmu_pebs_enable(struct perf_event *event)
672 {
673         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
674         struct hw_perf_event *hwc = &event->hw;
675 
676         hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT;
677 
678         cpuc->pebs_enabled |= 1ULL << hwc->idx;
679 
680         if (event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT)
681                 cpuc->pebs_enabled |= 1ULL << (hwc->idx + 32);
682         else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
683                 cpuc->pebs_enabled |= 1ULL << 63;
684 }
685 
686 void intel_pmu_pebs_disable(struct perf_event *event)
687 {
688         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
689         struct hw_perf_event *hwc = &event->hw;
690 
691         cpuc->pebs_enabled &= ~(1ULL << hwc->idx);
692 
693         if (event->hw.constraint->flags & PERF_X86_EVENT_PEBS_LDLAT)
694                 cpuc->pebs_enabled &= ~(1ULL << (hwc->idx + 32));
695         else if (event->hw.constraint->flags & PERF_X86_EVENT_PEBS_ST)
696                 cpuc->pebs_enabled &= ~(1ULL << 63);
697 
698         if (cpuc->enabled)
699                 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
700 
701         hwc->config |= ARCH_PERFMON_EVENTSEL_INT;
702 }
703 
704 void intel_pmu_pebs_enable_all(void)
705 {
706         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
707 
708         if (cpuc->pebs_enabled)
709                 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
710 }
711 
712 void intel_pmu_pebs_disable_all(void)
713 {
714         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
715 
716         if (cpuc->pebs_enabled)
717                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
718 }
719 
720 static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs)
721 {
722         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
723         unsigned long from = cpuc->lbr_entries[0].from;
724         unsigned long old_to, to = cpuc->lbr_entries[0].to;
725         unsigned long ip = regs->ip;
726         int is_64bit = 0;
727 
728         /*
729          * We don't need to fixup if the PEBS assist is fault like
730          */
731         if (!x86_pmu.intel_cap.pebs_trap)
732                 return 1;
733 
734         /*
735          * No LBR entry, no basic block, no rewinding
736          */
737         if (!cpuc->lbr_stack.nr || !from || !to)
738                 return 0;
739 
740         /*
741          * Basic blocks should never cross user/kernel boundaries
742          */
743         if (kernel_ip(ip) != kernel_ip(to))
744                 return 0;
745 
746         /*
747          * unsigned math, either ip is before the start (impossible) or
748          * the basic block is larger than 1 page (sanity)
749          */
750         if ((ip - to) > PAGE_SIZE)
751                 return 0;
752 
753         /*
754          * We sampled a branch insn, rewind using the LBR stack
755          */
756         if (ip == to) {
757                 set_linear_ip(regs, from);
758                 return 1;
759         }
760 
761         do {
762                 struct insn insn;
763                 u8 buf[MAX_INSN_SIZE];
764                 void *kaddr;
765 
766                 old_to = to;
767                 if (!kernel_ip(ip)) {
768                         int bytes, size = MAX_INSN_SIZE;
769 
770                         bytes = copy_from_user_nmi(buf, (void __user *)to, size);
771                         if (bytes != size)
772                                 return 0;
773 
774                         kaddr = buf;
775                 } else
776                         kaddr = (void *)to;
777 
778 #ifdef CONFIG_X86_64
779                 is_64bit = kernel_ip(to) || !test_thread_flag(TIF_IA32);
780 #endif
781                 insn_init(&insn, kaddr, is_64bit);
782                 insn_get_length(&insn);
783                 to += insn.length;
784         } while (to < ip);
785 
786         if (to == ip) {
787                 set_linear_ip(regs, old_to);
788                 return 1;
789         }
790 
791         /*
792          * Even though we decoded the basic block, the instruction stream
793          * never matched the given IP, either the TO or the IP got corrupted.
794          */
795         return 0;
796 }
797 
798 static void __intel_pmu_pebs_event(struct perf_event *event,
799                                    struct pt_regs *iregs, void *__pebs)
800 {
801         /*
802          * We cast to pebs_record_nhm to get the load latency data
803          * if extra_reg MSR_PEBS_LD_LAT_THRESHOLD used
804          */
805         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
806         struct pebs_record_nhm *pebs = __pebs;
807         struct pebs_record_hsw *pebs_hsw = __pebs;
808         struct perf_sample_data data;
809         struct pt_regs regs;
810         u64 sample_type;
811         int fll, fst;
812 
813         if (!intel_pmu_save_and_restart(event))
814                 return;
815 
816         fll = event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT;
817         fst = event->hw.flags & (PERF_X86_EVENT_PEBS_ST |
818                                  PERF_X86_EVENT_PEBS_ST_HSW);
819 
820         perf_sample_data_init(&data, 0, event->hw.last_period);
821 
822         data.period = event->hw.last_period;
823         sample_type = event->attr.sample_type;
824 
825         /*
826          * if PEBS-LL or PreciseStore
827          */
828         if (fll || fst) {
829                 /*
830                  * Use latency for weight (only avail with PEBS-LL)
831                  */
832                 if (fll && (sample_type & PERF_SAMPLE_WEIGHT))
833                         data.weight = pebs->lat;
834 
835                 /*
836                  * data.data_src encodes the data source
837                  */
838                 if (sample_type & PERF_SAMPLE_DATA_SRC) {
839                         if (fll)
840                                 data.data_src.val = load_latency_data(pebs->dse);
841                         else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW)
842                                 data.data_src.val =
843                                         precise_store_data_hsw(pebs->dse);
844                         else
845                                 data.data_src.val = precise_store_data(pebs->dse);
846                 }
847         }
848 
849         /*
850          * We use the interrupt regs as a base because the PEBS record
851          * does not contain a full regs set, specifically it seems to
852          * lack segment descriptors, which get used by things like
853          * user_mode().
854          *
855          * In the simple case fix up only the IP and BP,SP regs, for
856          * PERF_SAMPLE_IP and PERF_SAMPLE_CALLCHAIN to function properly.
857          * A possible PERF_SAMPLE_REGS will have to transfer all regs.
858          */
859         regs = *iregs;
860         regs.flags = pebs->flags;
861         set_linear_ip(&regs, pebs->ip);
862         regs.bp = pebs->bp;
863         regs.sp = pebs->sp;
864 
865         if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format >= 2) {
866                 regs.ip = pebs_hsw->real_ip;
867                 regs.flags |= PERF_EFLAGS_EXACT;
868         } else if (event->attr.precise_ip > 1 && intel_pmu_pebs_fixup_ip(&regs))
869                 regs.flags |= PERF_EFLAGS_EXACT;
870         else
871                 regs.flags &= ~PERF_EFLAGS_EXACT;
872 
873         if ((event->attr.sample_type & PERF_SAMPLE_ADDR) &&
874                 x86_pmu.intel_cap.pebs_format >= 1)
875                 data.addr = pebs->dla;
876 
877         if (has_branch_stack(event))
878                 data.br_stack = &cpuc->lbr_stack;
879 
880         if (perf_event_overflow(event, &data, &regs))
881                 x86_pmu_stop(event, 0);
882 }
883 
884 static void intel_pmu_drain_pebs_core(struct pt_regs *iregs)
885 {
886         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
887         struct debug_store *ds = cpuc->ds;
888         struct perf_event *event = cpuc->events[0]; /* PMC0 only */
889         struct pebs_record_core *at, *top;
890         int n;
891 
892         if (!x86_pmu.pebs_active)
893                 return;
894 
895         at  = (struct pebs_record_core *)(unsigned long)ds->pebs_buffer_base;
896         top = (struct pebs_record_core *)(unsigned long)ds->pebs_index;
897 
898         /*
899          * Whatever else happens, drain the thing
900          */
901         ds->pebs_index = ds->pebs_buffer_base;
902 
903         if (!test_bit(0, cpuc->active_mask))
904                 return;
905 
906         WARN_ON_ONCE(!event);
907 
908         if (!event->attr.precise_ip)
909                 return;
910 
911         n = top - at;
912         if (n <= 0)
913                 return;
914 
915         /*
916          * Should not happen, we program the threshold at 1 and do not
917          * set a reset value.
918          */
919         WARN_ONCE(n > 1, "bad leftover pebs %d\n", n);
920         at += n - 1;
921 
922         __intel_pmu_pebs_event(event, iregs, at);
923 }
924 
925 static void __intel_pmu_drain_pebs_nhm(struct pt_regs *iregs, void *at,
926                                         void *top)
927 {
928         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
929         struct debug_store *ds = cpuc->ds;
930         struct perf_event *event = NULL;
931         u64 status = 0;
932         int bit;
933 
934         ds->pebs_index = ds->pebs_buffer_base;
935 
936         for (; at < top; at += x86_pmu.pebs_record_size) {
937                 struct pebs_record_nhm *p = at;
938 
939                 for_each_set_bit(bit, (unsigned long *)&p->status,
940                                  x86_pmu.max_pebs_events) {
941                         event = cpuc->events[bit];
942                         if (!test_bit(bit, cpuc->active_mask))
943                                 continue;
944 
945                         WARN_ON_ONCE(!event);
946 
947                         if (!event->attr.precise_ip)
948                                 continue;
949 
950                         if (__test_and_set_bit(bit, (unsigned long *)&status))
951                                 continue;
952 
953                         break;
954                 }
955 
956                 if (!event || bit >= x86_pmu.max_pebs_events)
957                         continue;
958 
959                 __intel_pmu_pebs_event(event, iregs, at);
960         }
961 }
962 
963 static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
964 {
965         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
966         struct debug_store *ds = cpuc->ds;
967         struct pebs_record_nhm *at, *top;
968         int n;
969 
970         if (!x86_pmu.pebs_active)
971                 return;
972 
973         at  = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base;
974         top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index;
975 
976         ds->pebs_index = ds->pebs_buffer_base;
977 
978         n = top - at;
979         if (n <= 0)
980                 return;
981 
982         /*
983          * Should not happen, we program the threshold at 1 and do not
984          * set a reset value.
985          */
986         WARN_ONCE(n > x86_pmu.max_pebs_events,
987                   "Unexpected number of pebs records %d\n", n);
988 
989         return __intel_pmu_drain_pebs_nhm(iregs, at, top);
990 }
991 
992 static void intel_pmu_drain_pebs_hsw(struct pt_regs *iregs)
993 {
994         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
995         struct debug_store *ds = cpuc->ds;
996         struct pebs_record_hsw *at, *top;
997         int n;
998 
999         if (!x86_pmu.pebs_active)
1000                 return;
1001 
1002         at  = (struct pebs_record_hsw *)(unsigned long)ds->pebs_buffer_base;
1003         top = (struct pebs_record_hsw *)(unsigned long)ds->pebs_index;
1004 
1005         n = top - at;
1006         if (n <= 0)
1007                 return;
1008         /*
1009          * Should not happen, we program the threshold at 1 and do not
1010          * set a reset value.
1011          */
1012         WARN_ONCE(n > x86_pmu.max_pebs_events,
1013                   "Unexpected number of pebs records %d\n", n);
1014 
1015         return __intel_pmu_drain_pebs_nhm(iregs, at, top);
1016 }
1017 
1018 /*
1019  * BTS, PEBS probe and setup
1020  */
1021 
1022 void intel_ds_init(void)
1023 {
1024         /*
1025          * No support for 32bit formats
1026          */
1027         if (!boot_cpu_has(X86_FEATURE_DTES64))
1028                 return;
1029 
1030         x86_pmu.bts  = boot_cpu_has(X86_FEATURE_BTS);
1031         x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS);
1032         x86_pmu.pebs_buffer_size = PEBS_BUFFER_SIZE;
1033         if (x86_pmu.pebs) {
1034                 char pebs_type = x86_pmu.intel_cap.pebs_trap ?  '+' : '-';
1035                 int format = x86_pmu.intel_cap.pebs_format;
1036 
1037                 switch (format) {
1038                 case 0:
1039                         printk(KERN_CONT "PEBS fmt0%c, ", pebs_type);
1040                         x86_pmu.pebs_record_size = sizeof(struct pebs_record_core);
1041                         /*
1042                          * Using >PAGE_SIZE buffers makes the WRMSR to
1043                          * PERF_GLOBAL_CTRL in intel_pmu_enable_all()
1044                          * mysteriously hang on Core2.
1045                          *
1046                          * As a workaround, we don't do this.
1047                          */
1048                         x86_pmu.pebs_buffer_size = PAGE_SIZE;
1049                         x86_pmu.drain_pebs = intel_pmu_drain_pebs_core;
1050                         break;
1051 
1052                 case 1:
1053                         printk(KERN_CONT "PEBS fmt1%c, ", pebs_type);
1054                         x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm);
1055                         x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1056                         break;
1057 
1058                 case 2:
1059                         pr_cont("PEBS fmt2%c, ", pebs_type);
1060                         x86_pmu.pebs_record_size = sizeof(struct pebs_record_hsw);
1061                         x86_pmu.drain_pebs = intel_pmu_drain_pebs_hsw;
1062                         break;
1063 
1064                 default:
1065                         printk(KERN_CONT "no PEBS fmt%d%c, ", format, pebs_type);
1066                         x86_pmu.pebs = 0;
1067                 }
1068         }
1069 }
1070 
1071 void perf_restore_debug_store(void)
1072 {
1073         struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
1074 
1075         if (!x86_pmu.bts && !x86_pmu.pebs)
1076                 return;
1077 
1078         wrmsrl(MSR_IA32_DS_AREA, (unsigned long)ds);
1079 }
1080 

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