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TOMOYO Linux Cross Reference
Linux/arch/x86/kernel/early-quirks.c

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  1 // SPDX-License-Identifier: GPL-2.0
  2 /* Various workarounds for chipset bugs.
  3    This code runs very early and can't use the regular PCI subsystem
  4    The entries are keyed to PCI bridges which usually identify chipsets
  5    uniquely.
  6    This is only for whole classes of chipsets with specific problems which
  7    need early invasive action (e.g. before the timers are initialized).
  8    Most PCI device specific workarounds can be done later and should be
  9    in standard PCI quirks
 10    Mainboard specific bugs should be handled by DMI entries.
 11    CPU specific bugs in setup.c */
 12 
 13 #include <linux/pci.h>
 14 #include <linux/acpi.h>
 15 #include <linux/delay.h>
 16 #include <linux/pci_ids.h>
 17 #include <linux/bcma/bcma.h>
 18 #include <linux/bcma/bcma_regs.h>
 19 #include <linux/platform_data/x86/apple.h>
 20 #include <drm/i915_drm.h>
 21 #include <asm/pci-direct.h>
 22 #include <asm/dma.h>
 23 #include <asm/io_apic.h>
 24 #include <asm/apic.h>
 25 #include <asm/hpet.h>
 26 #include <asm/iommu.h>
 27 #include <asm/gart.h>
 28 #include <asm/irq_remapping.h>
 29 #include <asm/early_ioremap.h>
 30 
 31 static void __init fix_hypertransport_config(int num, int slot, int func)
 32 {
 33         u32 htcfg;
 34         /*
 35          * we found a hypertransport bus
 36          * make sure that we are broadcasting
 37          * interrupts to all cpus on the ht bus
 38          * if we're using extended apic ids
 39          */
 40         htcfg = read_pci_config(num, slot, func, 0x68);
 41         if (htcfg & (1 << 18)) {
 42                 printk(KERN_INFO "Detected use of extended apic ids "
 43                                  "on hypertransport bus\n");
 44                 if ((htcfg & (1 << 17)) == 0) {
 45                         printk(KERN_INFO "Enabling hypertransport extended "
 46                                          "apic interrupt broadcast\n");
 47                         printk(KERN_INFO "Note this is a bios bug, "
 48                                          "please contact your hw vendor\n");
 49                         htcfg |= (1 << 17);
 50                         write_pci_config(num, slot, func, 0x68, htcfg);
 51                 }
 52         }
 53 
 54 
 55 }
 56 
 57 static void __init via_bugs(int  num, int slot, int func)
 58 {
 59 #ifdef CONFIG_GART_IOMMU
 60         if ((max_pfn > MAX_DMA32_PFN ||  force_iommu) &&
 61             !gart_iommu_aperture_allowed) {
 62                 printk(KERN_INFO
 63                        "Looks like a VIA chipset. Disabling IOMMU."
 64                        " Override with iommu=allowed\n");
 65                 gart_iommu_aperture_disabled = 1;
 66         }
 67 #endif
 68 }
 69 
 70 #ifdef CONFIG_ACPI
 71 #ifdef CONFIG_X86_IO_APIC
 72 
 73 static int __init nvidia_hpet_check(struct acpi_table_header *header)
 74 {
 75         return 0;
 76 }
 77 #endif /* CONFIG_X86_IO_APIC */
 78 #endif /* CONFIG_ACPI */
 79 
 80 static void __init nvidia_bugs(int num, int slot, int func)
 81 {
 82 #ifdef CONFIG_ACPI
 83 #ifdef CONFIG_X86_IO_APIC
 84         /*
 85          * Only applies to Nvidia root ports (bus 0) and not to
 86          * Nvidia graphics cards with PCI ports on secondary buses.
 87          */
 88         if (num)
 89                 return;
 90 
 91         /*
 92          * All timer overrides on Nvidia are
 93          * wrong unless HPET is enabled.
 94          * Unfortunately that's not true on many Asus boards.
 95          * We don't know yet how to detect this automatically, but
 96          * at least allow a command line override.
 97          */
 98         if (acpi_use_timer_override)
 99                 return;
100 
101         if (acpi_table_parse(ACPI_SIG_HPET, nvidia_hpet_check)) {
102                 acpi_skip_timer_override = 1;
103                 printk(KERN_INFO "Nvidia board "
104                        "detected. Ignoring ACPI "
105                        "timer override.\n");
106                 printk(KERN_INFO "If you got timer trouble "
107                         "try acpi_use_timer_override\n");
108         }
109 #endif
110 #endif
111         /* RED-PEN skip them on mptables too? */
112 
113 }
114 
115 #if defined(CONFIG_ACPI) && defined(CONFIG_X86_IO_APIC)
116 static u32 __init ati_ixp4x0_rev(int num, int slot, int func)
117 {
118         u32 d;
119         u8  b;
120 
121         b = read_pci_config_byte(num, slot, func, 0xac);
122         b &= ~(1<<5);
123         write_pci_config_byte(num, slot, func, 0xac, b);
124 
125         d = read_pci_config(num, slot, func, 0x70);
126         d |= 1<<8;
127         write_pci_config(num, slot, func, 0x70, d);
128 
129         d = read_pci_config(num, slot, func, 0x8);
130         d &= 0xff;
131         return d;
132 }
133 
134 static void __init ati_bugs(int num, int slot, int func)
135 {
136         u32 d;
137         u8  b;
138 
139         if (acpi_use_timer_override)
140                 return;
141 
142         d = ati_ixp4x0_rev(num, slot, func);
143         if (d  < 0x82)
144                 acpi_skip_timer_override = 1;
145         else {
146                 /* check for IRQ0 interrupt swap */
147                 outb(0x72, 0xcd6); b = inb(0xcd7);
148                 if (!(b & 0x2))
149                         acpi_skip_timer_override = 1;
150         }
151 
152         if (acpi_skip_timer_override) {
153                 printk(KERN_INFO "SB4X0 revision 0x%x\n", d);
154                 printk(KERN_INFO "Ignoring ACPI timer override.\n");
155                 printk(KERN_INFO "If you got timer trouble "
156                        "try acpi_use_timer_override\n");
157         }
158 }
159 
160 static u32 __init ati_sbx00_rev(int num, int slot, int func)
161 {
162         u32 d;
163 
164         d = read_pci_config(num, slot, func, 0x8);
165         d &= 0xff;
166 
167         return d;
168 }
169 
170 static void __init ati_bugs_contd(int num, int slot, int func)
171 {
172         u32 d, rev;
173 
174         rev = ati_sbx00_rev(num, slot, func);
175         if (rev >= 0x40)
176                 acpi_fix_pin2_polarity = 1;
177 
178         /*
179          * SB600: revisions 0x11, 0x12, 0x13, 0x14, ...
180          * SB700: revisions 0x39, 0x3a, ...
181          * SB800: revisions 0x40, 0x41, ...
182          */
183         if (rev >= 0x39)
184                 return;
185 
186         if (acpi_use_timer_override)
187                 return;
188 
189         /* check for IRQ0 interrupt swap */
190         d = read_pci_config(num, slot, func, 0x64);
191         if (!(d & (1<<14)))
192                 acpi_skip_timer_override = 1;
193 
194         if (acpi_skip_timer_override) {
195                 printk(KERN_INFO "SB600 revision 0x%x\n", rev);
196                 printk(KERN_INFO "Ignoring ACPI timer override.\n");
197                 printk(KERN_INFO "If you got timer trouble "
198                        "try acpi_use_timer_override\n");
199         }
200 }
201 #else
202 static void __init ati_bugs(int num, int slot, int func)
203 {
204 }
205 
206 static void __init ati_bugs_contd(int num, int slot, int func)
207 {
208 }
209 #endif
210 
211 static void __init intel_remapping_check(int num, int slot, int func)
212 {
213         u8 revision;
214         u16 device;
215 
216         device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID);
217         revision = read_pci_config_byte(num, slot, func, PCI_REVISION_ID);
218 
219         /*
220          * Revision <= 13 of all triggering devices id in this quirk
221          * have a problem draining interrupts when irq remapping is
222          * enabled, and should be flagged as broken. Additionally
223          * revision 0x22 of device id 0x3405 has this problem.
224          */
225         if (revision <= 0x13)
226                 set_irq_remapping_broken();
227         else if (device == 0x3405 && revision == 0x22)
228                 set_irq_remapping_broken();
229 }
230 
231 /*
232  * Systems with Intel graphics controllers set aside memory exclusively
233  * for gfx driver use.  This memory is not marked in the E820 as reserved
234  * or as RAM, and so is subject to overlap from E820 manipulation later
235  * in the boot process.  On some systems, MMIO space is allocated on top,
236  * despite the efforts of the "RAM buffer" approach, which simply rounds
237  * memory boundaries up to 64M to try to catch space that may decode
238  * as RAM and so is not suitable for MMIO.
239  */
240 
241 #define KB(x)   ((x) * 1024UL)
242 #define MB(x)   (KB (KB (x)))
243 
244 static resource_size_t __init i830_tseg_size(void)
245 {
246         u8 esmramc = read_pci_config_byte(0, 0, 0, I830_ESMRAMC);
247 
248         if (!(esmramc & TSEG_ENABLE))
249                 return 0;
250 
251         if (esmramc & I830_TSEG_SIZE_1M)
252                 return MB(1);
253         else
254                 return KB(512);
255 }
256 
257 static resource_size_t __init i845_tseg_size(void)
258 {
259         u8 esmramc = read_pci_config_byte(0, 0, 0, I845_ESMRAMC);
260         u8 tseg_size = esmramc & I845_TSEG_SIZE_MASK;
261 
262         if (!(esmramc & TSEG_ENABLE))
263                 return 0;
264 
265         switch (tseg_size) {
266         case I845_TSEG_SIZE_512K:       return KB(512);
267         case I845_TSEG_SIZE_1M:         return MB(1);
268         default:
269                 WARN(1, "Unknown ESMRAMC value: %x!\n", esmramc);
270         }
271         return 0;
272 }
273 
274 static resource_size_t __init i85x_tseg_size(void)
275 {
276         u8 esmramc = read_pci_config_byte(0, 0, 0, I85X_ESMRAMC);
277 
278         if (!(esmramc & TSEG_ENABLE))
279                 return 0;
280 
281         return MB(1);
282 }
283 
284 static resource_size_t __init i830_mem_size(void)
285 {
286         return read_pci_config_byte(0, 0, 0, I830_DRB3) * MB(32);
287 }
288 
289 static resource_size_t __init i85x_mem_size(void)
290 {
291         return read_pci_config_byte(0, 0, 1, I85X_DRB3) * MB(32);
292 }
293 
294 /*
295  * On 830/845/85x the stolen memory base isn't available in any
296  * register. We need to calculate it as TOM-TSEG_SIZE-stolen_size.
297  */
298 static resource_size_t __init i830_stolen_base(int num, int slot, int func,
299                                                resource_size_t stolen_size)
300 {
301         return i830_mem_size() - i830_tseg_size() - stolen_size;
302 }
303 
304 static resource_size_t __init i845_stolen_base(int num, int slot, int func,
305                                                resource_size_t stolen_size)
306 {
307         return i830_mem_size() - i845_tseg_size() - stolen_size;
308 }
309 
310 static resource_size_t __init i85x_stolen_base(int num, int slot, int func,
311                                                resource_size_t stolen_size)
312 {
313         return i85x_mem_size() - i85x_tseg_size() - stolen_size;
314 }
315 
316 static resource_size_t __init i865_stolen_base(int num, int slot, int func,
317                                                resource_size_t stolen_size)
318 {
319         u16 toud = 0;
320 
321         toud = read_pci_config_16(0, 0, 0, I865_TOUD);
322 
323         return toud * KB(64) + i845_tseg_size();
324 }
325 
326 static resource_size_t __init gen3_stolen_base(int num, int slot, int func,
327                                                resource_size_t stolen_size)
328 {
329         u32 bsm;
330 
331         /* Almost universally we can find the Graphics Base of Stolen Memory
332          * at register BSM (0x5c) in the igfx configuration space. On a few
333          * (desktop) machines this is also mirrored in the bridge device at
334          * different locations, or in the MCHBAR.
335          */
336         bsm = read_pci_config(num, slot, func, INTEL_BSM);
337 
338         return bsm & INTEL_BSM_MASK;
339 }
340 
341 static resource_size_t __init gen11_stolen_base(int num, int slot, int func,
342                                                 resource_size_t stolen_size)
343 {
344         u64 bsm;
345 
346         bsm = read_pci_config(num, slot, func, INTEL_GEN11_BSM_DW0);
347         bsm &= INTEL_BSM_MASK;
348         bsm |= (u64)read_pci_config(num, slot, func, INTEL_GEN11_BSM_DW1) << 32;
349 
350         return bsm;
351 }
352 
353 static resource_size_t __init i830_stolen_size(int num, int slot, int func)
354 {
355         u16 gmch_ctrl;
356         u16 gms;
357 
358         gmch_ctrl = read_pci_config_16(0, 0, 0, I830_GMCH_CTRL);
359         gms = gmch_ctrl & I830_GMCH_GMS_MASK;
360 
361         switch (gms) {
362         case I830_GMCH_GMS_STOLEN_512:  return KB(512);
363         case I830_GMCH_GMS_STOLEN_1024: return MB(1);
364         case I830_GMCH_GMS_STOLEN_8192: return MB(8);
365         /* local memory isn't part of the normal address space */
366         case I830_GMCH_GMS_LOCAL:       return 0;
367         default:
368                 WARN(1, "Unknown GMCH_CTRL value: %x!\n", gmch_ctrl);
369         }
370 
371         return 0;
372 }
373 
374 static resource_size_t __init gen3_stolen_size(int num, int slot, int func)
375 {
376         u16 gmch_ctrl;
377         u16 gms;
378 
379         gmch_ctrl = read_pci_config_16(0, 0, 0, I830_GMCH_CTRL);
380         gms = gmch_ctrl & I855_GMCH_GMS_MASK;
381 
382         switch (gms) {
383         case I855_GMCH_GMS_STOLEN_1M:   return MB(1);
384         case I855_GMCH_GMS_STOLEN_4M:   return MB(4);
385         case I855_GMCH_GMS_STOLEN_8M:   return MB(8);
386         case I855_GMCH_GMS_STOLEN_16M:  return MB(16);
387         case I855_GMCH_GMS_STOLEN_32M:  return MB(32);
388         case I915_GMCH_GMS_STOLEN_48M:  return MB(48);
389         case I915_GMCH_GMS_STOLEN_64M:  return MB(64);
390         case G33_GMCH_GMS_STOLEN_128M:  return MB(128);
391         case G33_GMCH_GMS_STOLEN_256M:  return MB(256);
392         case INTEL_GMCH_GMS_STOLEN_96M: return MB(96);
393         case INTEL_GMCH_GMS_STOLEN_160M:return MB(160);
394         case INTEL_GMCH_GMS_STOLEN_224M:return MB(224);
395         case INTEL_GMCH_GMS_STOLEN_352M:return MB(352);
396         default:
397                 WARN(1, "Unknown GMCH_CTRL value: %x!\n", gmch_ctrl);
398         }
399 
400         return 0;
401 }
402 
403 static resource_size_t __init gen6_stolen_size(int num, int slot, int func)
404 {
405         u16 gmch_ctrl;
406         u16 gms;
407 
408         gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
409         gms = (gmch_ctrl >> SNB_GMCH_GMS_SHIFT) & SNB_GMCH_GMS_MASK;
410 
411         return gms * MB(32);
412 }
413 
414 static resource_size_t __init gen8_stolen_size(int num, int slot, int func)
415 {
416         u16 gmch_ctrl;
417         u16 gms;
418 
419         gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
420         gms = (gmch_ctrl >> BDW_GMCH_GMS_SHIFT) & BDW_GMCH_GMS_MASK;
421 
422         return gms * MB(32);
423 }
424 
425 static resource_size_t __init chv_stolen_size(int num, int slot, int func)
426 {
427         u16 gmch_ctrl;
428         u16 gms;
429 
430         gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
431         gms = (gmch_ctrl >> SNB_GMCH_GMS_SHIFT) & SNB_GMCH_GMS_MASK;
432 
433         /*
434          * 0x0  to 0x10: 32MB increments starting at 0MB
435          * 0x11 to 0x16: 4MB increments starting at 8MB
436          * 0x17 to 0x1d: 4MB increments start at 36MB
437          */
438         if (gms < 0x11)
439                 return gms * MB(32);
440         else if (gms < 0x17)
441                 return (gms - 0x11) * MB(4) + MB(8);
442         else
443                 return (gms - 0x17) * MB(4) + MB(36);
444 }
445 
446 static resource_size_t __init gen9_stolen_size(int num, int slot, int func)
447 {
448         u16 gmch_ctrl;
449         u16 gms;
450 
451         gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
452         gms = (gmch_ctrl >> BDW_GMCH_GMS_SHIFT) & BDW_GMCH_GMS_MASK;
453 
454         /* 0x0  to 0xef: 32MB increments starting at 0MB */
455         /* 0xf0 to 0xfe: 4MB increments starting at 4MB */
456         if (gms < 0xf0)
457                 return gms * MB(32);
458         else
459                 return (gms - 0xf0) * MB(4) + MB(4);
460 }
461 
462 struct intel_early_ops {
463         resource_size_t (*stolen_size)(int num, int slot, int func);
464         resource_size_t (*stolen_base)(int num, int slot, int func,
465                                        resource_size_t size);
466 };
467 
468 static const struct intel_early_ops i830_early_ops __initconst = {
469         .stolen_base = i830_stolen_base,
470         .stolen_size = i830_stolen_size,
471 };
472 
473 static const struct intel_early_ops i845_early_ops __initconst = {
474         .stolen_base = i845_stolen_base,
475         .stolen_size = i830_stolen_size,
476 };
477 
478 static const struct intel_early_ops i85x_early_ops __initconst = {
479         .stolen_base = i85x_stolen_base,
480         .stolen_size = gen3_stolen_size,
481 };
482 
483 static const struct intel_early_ops i865_early_ops __initconst = {
484         .stolen_base = i865_stolen_base,
485         .stolen_size = gen3_stolen_size,
486 };
487 
488 static const struct intel_early_ops gen3_early_ops __initconst = {
489         .stolen_base = gen3_stolen_base,
490         .stolen_size = gen3_stolen_size,
491 };
492 
493 static const struct intel_early_ops gen6_early_ops __initconst = {
494         .stolen_base = gen3_stolen_base,
495         .stolen_size = gen6_stolen_size,
496 };
497 
498 static const struct intel_early_ops gen8_early_ops __initconst = {
499         .stolen_base = gen3_stolen_base,
500         .stolen_size = gen8_stolen_size,
501 };
502 
503 static const struct intel_early_ops gen9_early_ops __initconst = {
504         .stolen_base = gen3_stolen_base,
505         .stolen_size = gen9_stolen_size,
506 };
507 
508 static const struct intel_early_ops chv_early_ops __initconst = {
509         .stolen_base = gen3_stolen_base,
510         .stolen_size = chv_stolen_size,
511 };
512 
513 static const struct intel_early_ops gen11_early_ops __initconst = {
514         .stolen_base = gen11_stolen_base,
515         .stolen_size = gen9_stolen_size,
516 };
517 
518 static const struct pci_device_id intel_early_ids[] __initconst = {
519         INTEL_I830_IDS(&i830_early_ops),
520         INTEL_I845G_IDS(&i845_early_ops),
521         INTEL_I85X_IDS(&i85x_early_ops),
522         INTEL_I865G_IDS(&i865_early_ops),
523         INTEL_I915G_IDS(&gen3_early_ops),
524         INTEL_I915GM_IDS(&gen3_early_ops),
525         INTEL_I945G_IDS(&gen3_early_ops),
526         INTEL_I945GM_IDS(&gen3_early_ops),
527         INTEL_VLV_IDS(&gen6_early_ops),
528         INTEL_PINEVIEW_IDS(&gen3_early_ops),
529         INTEL_I965G_IDS(&gen3_early_ops),
530         INTEL_G33_IDS(&gen3_early_ops),
531         INTEL_I965GM_IDS(&gen3_early_ops),
532         INTEL_GM45_IDS(&gen3_early_ops),
533         INTEL_G45_IDS(&gen3_early_ops),
534         INTEL_IRONLAKE_D_IDS(&gen3_early_ops),
535         INTEL_IRONLAKE_M_IDS(&gen3_early_ops),
536         INTEL_SNB_D_IDS(&gen6_early_ops),
537         INTEL_SNB_M_IDS(&gen6_early_ops),
538         INTEL_IVB_M_IDS(&gen6_early_ops),
539         INTEL_IVB_D_IDS(&gen6_early_ops),
540         INTEL_HSW_IDS(&gen6_early_ops),
541         INTEL_BDW_IDS(&gen8_early_ops),
542         INTEL_CHV_IDS(&chv_early_ops),
543         INTEL_SKL_IDS(&gen9_early_ops),
544         INTEL_BXT_IDS(&gen9_early_ops),
545         INTEL_KBL_IDS(&gen9_early_ops),
546         INTEL_CFL_IDS(&gen9_early_ops),
547         INTEL_GLK_IDS(&gen9_early_ops),
548         INTEL_CNL_IDS(&gen9_early_ops),
549         INTEL_ICL_11_IDS(&gen11_early_ops),
550 };
551 
552 struct resource intel_graphics_stolen_res __ro_after_init = DEFINE_RES_MEM(0, 0);
553 EXPORT_SYMBOL(intel_graphics_stolen_res);
554 
555 static void __init
556 intel_graphics_stolen(int num, int slot, int func,
557                       const struct intel_early_ops *early_ops)
558 {
559         resource_size_t base, size;
560         resource_size_t end;
561 
562         size = early_ops->stolen_size(num, slot, func);
563         base = early_ops->stolen_base(num, slot, func, size);
564 
565         if (!size || !base)
566                 return;
567 
568         end = base + size - 1;
569 
570         intel_graphics_stolen_res.start = base;
571         intel_graphics_stolen_res.end = end;
572 
573         printk(KERN_INFO "Reserving Intel graphics memory at %pR\n",
574                &intel_graphics_stolen_res);
575 
576         /* Mark this space as reserved */
577         e820__range_add(base, size, E820_TYPE_RESERVED);
578         e820__update_table(e820_table);
579 }
580 
581 static void __init intel_graphics_quirks(int num, int slot, int func)
582 {
583         const struct intel_early_ops *early_ops;
584         u16 device;
585         int i;
586 
587         device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID);
588 
589         for (i = 0; i < ARRAY_SIZE(intel_early_ids); i++) {
590                 kernel_ulong_t driver_data = intel_early_ids[i].driver_data;
591 
592                 if (intel_early_ids[i].device != device)
593                         continue;
594 
595                 early_ops = (typeof(early_ops))driver_data;
596 
597                 intel_graphics_stolen(num, slot, func, early_ops);
598 
599                 return;
600         }
601 }
602 
603 static void __init force_disable_hpet(int num, int slot, int func)
604 {
605 #ifdef CONFIG_HPET_TIMER
606         boot_hpet_disable = true;
607         pr_info("x86/hpet: Will disable the HPET for this platform because it's not reliable\n");
608 #endif
609 }
610 
611 #define BCM4331_MMIO_SIZE       16384
612 #define BCM4331_PM_CAP          0x40
613 #define bcma_aread32(reg)       ioread32(mmio + 1 * BCMA_CORE_SIZE + reg)
614 #define bcma_awrite32(reg, val) iowrite32(val, mmio + 1 * BCMA_CORE_SIZE + reg)
615 
616 static void __init apple_airport_reset(int bus, int slot, int func)
617 {
618         void __iomem *mmio;
619         u16 pmcsr;
620         u64 addr;
621         int i;
622 
623         if (!x86_apple_machine)
624                 return;
625 
626         /* Card may have been put into PCI_D3hot by grub quirk */
627         pmcsr = read_pci_config_16(bus, slot, func, BCM4331_PM_CAP + PCI_PM_CTRL);
628 
629         if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) {
630                 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
631                 write_pci_config_16(bus, slot, func, BCM4331_PM_CAP + PCI_PM_CTRL, pmcsr);
632                 mdelay(10);
633 
634                 pmcsr = read_pci_config_16(bus, slot, func, BCM4331_PM_CAP + PCI_PM_CTRL);
635                 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) {
636                         pr_err("pci 0000:%02x:%02x.%d: Cannot power up Apple AirPort card\n",
637                                bus, slot, func);
638                         return;
639                 }
640         }
641 
642         addr  =      read_pci_config(bus, slot, func, PCI_BASE_ADDRESS_0);
643         addr |= (u64)read_pci_config(bus, slot, func, PCI_BASE_ADDRESS_1) << 32;
644         addr &= PCI_BASE_ADDRESS_MEM_MASK;
645 
646         mmio = early_ioremap(addr, BCM4331_MMIO_SIZE);
647         if (!mmio) {
648                 pr_err("pci 0000:%02x:%02x.%d: Cannot iomap Apple AirPort card\n",
649                        bus, slot, func);
650                 return;
651         }
652 
653         pr_info("Resetting Apple AirPort card (left enabled by EFI)\n");
654 
655         for (i = 0; bcma_aread32(BCMA_RESET_ST) && i < 30; i++)
656                 udelay(10);
657 
658         bcma_awrite32(BCMA_RESET_CTL, BCMA_RESET_CTL_RESET);
659         bcma_aread32(BCMA_RESET_CTL);
660         udelay(1);
661 
662         bcma_awrite32(BCMA_RESET_CTL, 0);
663         bcma_aread32(BCMA_RESET_CTL);
664         udelay(10);
665 
666         early_iounmap(mmio, BCM4331_MMIO_SIZE);
667 }
668 
669 #define QFLAG_APPLY_ONCE        0x1
670 #define QFLAG_APPLIED           0x2
671 #define QFLAG_DONE              (QFLAG_APPLY_ONCE|QFLAG_APPLIED)
672 struct chipset {
673         u32 vendor;
674         u32 device;
675         u32 class;
676         u32 class_mask;
677         u32 flags;
678         void (*f)(int num, int slot, int func);
679 };
680 
681 static struct chipset early_qrk[] __initdata = {
682         { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
683           PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, nvidia_bugs },
684         { PCI_VENDOR_ID_VIA, PCI_ANY_ID,
685           PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, via_bugs },
686         { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB,
687           PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, fix_hypertransport_config },
688         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS,
689           PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs },
690         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
691           PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs_contd },
692         { PCI_VENDOR_ID_INTEL, 0x3403, PCI_CLASS_BRIDGE_HOST,
693           PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check },
694         { PCI_VENDOR_ID_INTEL, 0x3405, PCI_CLASS_BRIDGE_HOST,
695           PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check },
696         { PCI_VENDOR_ID_INTEL, 0x3406, PCI_CLASS_BRIDGE_HOST,
697           PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check },
698         { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA, PCI_ANY_ID,
699           QFLAG_APPLY_ONCE, intel_graphics_quirks },
700         /*
701          * HPET on the current version of the Baytrail platform has accuracy
702          * problems: it will halt in deep idle state - so we disable it.
703          *
704          * More details can be found in section 18.10.1.3 of the datasheet:
705          *
706          *    http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/atom-z8000-datasheet-vol-1.pdf
707          */
708         { PCI_VENDOR_ID_INTEL, 0x0f00,
709                 PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, force_disable_hpet},
710         { PCI_VENDOR_ID_BROADCOM, 0x4331,
711           PCI_CLASS_NETWORK_OTHER, PCI_ANY_ID, 0, apple_airport_reset},
712         {}
713 };
714 
715 static void __init early_pci_scan_bus(int bus);
716 
717 /**
718  * check_dev_quirk - apply early quirks to a given PCI device
719  * @num: bus number
720  * @slot: slot number
721  * @func: PCI function
722  *
723  * Check the vendor & device ID against the early quirks table.
724  *
725  * If the device is single function, let early_pci_scan_bus() know so we don't
726  * poke at this device again.
727  */
728 static int __init check_dev_quirk(int num, int slot, int func)
729 {
730         u16 class;
731         u16 vendor;
732         u16 device;
733         u8 type;
734         u8 sec;
735         int i;
736 
737         class = read_pci_config_16(num, slot, func, PCI_CLASS_DEVICE);
738 
739         if (class == 0xffff)
740                 return -1; /* no class, treat as single function */
741 
742         vendor = read_pci_config_16(num, slot, func, PCI_VENDOR_ID);
743 
744         device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID);
745 
746         for (i = 0; early_qrk[i].f != NULL; i++) {
747                 if (((early_qrk[i].vendor == PCI_ANY_ID) ||
748                         (early_qrk[i].vendor == vendor)) &&
749                         ((early_qrk[i].device == PCI_ANY_ID) ||
750                         (early_qrk[i].device == device)) &&
751                         (!((early_qrk[i].class ^ class) &
752                             early_qrk[i].class_mask))) {
753                                 if ((early_qrk[i].flags &
754                                      QFLAG_DONE) != QFLAG_DONE)
755                                         early_qrk[i].f(num, slot, func);
756                                 early_qrk[i].flags |= QFLAG_APPLIED;
757                         }
758         }
759 
760         type = read_pci_config_byte(num, slot, func,
761                                     PCI_HEADER_TYPE);
762 
763         if ((type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) {
764                 sec = read_pci_config_byte(num, slot, func, PCI_SECONDARY_BUS);
765                 if (sec > num)
766                         early_pci_scan_bus(sec);
767         }
768 
769         if (!(type & 0x80))
770                 return -1;
771 
772         return 0;
773 }
774 
775 static void __init early_pci_scan_bus(int bus)
776 {
777         int slot, func;
778 
779         /* Poor man's PCI discovery */
780         for (slot = 0; slot < 32; slot++)
781                 for (func = 0; func < 8; func++) {
782                         /* Only probe function 0 on single fn devices */
783                         if (check_dev_quirk(bus, slot, func))
784                                 break;
785                 }
786 }
787 
788 void __init early_quirks(void)
789 {
790         if (!early_pci_allowed())
791                 return;
792 
793         early_pci_scan_bus(0);
794 }
795 

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